linux/drivers/gpio/gpio-tegra.c
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   1/*
   2 * arch/arm/mach-tegra/gpio.c
   3 *
   4 * Copyright (c) 2010 Google, Inc
   5 *
   6 * Author:
   7 *      Erik Gilling <konkers@google.com>
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/irq.h>
  22#include <linux/interrupt.h>
  23#include <linux/io.h>
  24#include <linux/gpio.h>
  25#include <linux/of_device.h>
  26#include <linux/platform_device.h>
  27#include <linux/module.h>
  28#include <linux/irqdomain.h>
  29#include <linux/pinctrl/consumer.h>
  30
  31#include <asm/mach/irq.h>
  32
  33#include <mach/iomap.h>
  34#include <mach/suspend.h>
  35
  36#define GPIO_BANK(x)            ((x) >> 5)
  37#define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  38#define GPIO_BIT(x)             ((x) & 0x7)
  39
  40#define GPIO_REG(x)             (GPIO_BANK(x) * tegra_gpio_bank_stride + \
  41                                        GPIO_PORT(x) * 4)
  42
  43#define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  44#define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  45#define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  46#define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  47#define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  48#define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  49#define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  50#define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  51
  52#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
  53#define GPIO_MSK_OE(x)          (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
  54#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
  55#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
  56#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
  57#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
  58
  59#define GPIO_INT_LVL_MASK               0x010101
  60#define GPIO_INT_LVL_EDGE_RISING        0x000101
  61#define GPIO_INT_LVL_EDGE_FALLING       0x000100
  62#define GPIO_INT_LVL_EDGE_BOTH          0x010100
  63#define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  64#define GPIO_INT_LVL_LEVEL_LOW          0x000000
  65
  66struct tegra_gpio_bank {
  67        int bank;
  68        int irq;
  69        spinlock_t lvl_lock[4];
  70#ifdef CONFIG_PM
  71        u32 cnf[4];
  72        u32 out[4];
  73        u32 oe[4];
  74        u32 int_enb[4];
  75        u32 int_lvl[4];
  76#endif
  77};
  78
  79static struct irq_domain *irq_domain;
  80static void __iomem *regs;
  81static u32 tegra_gpio_bank_count;
  82static u32 tegra_gpio_bank_stride;
  83static u32 tegra_gpio_upper_offset;
  84static struct tegra_gpio_bank *tegra_gpio_banks;
  85
  86static inline void tegra_gpio_writel(u32 val, u32 reg)
  87{
  88        __raw_writel(val, regs + reg);
  89}
  90
  91static inline u32 tegra_gpio_readl(u32 reg)
  92{
  93        return __raw_readl(regs + reg);
  94}
  95
  96static int tegra_gpio_compose(int bank, int port, int bit)
  97{
  98        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  99}
 100
 101static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 102{
 103        u32 val;
 104
 105        val = 0x100 << GPIO_BIT(gpio);
 106        if (value)
 107                val |= 1 << GPIO_BIT(gpio);
 108        tegra_gpio_writel(val, reg);
 109}
 110
 111static void tegra_gpio_enable(int gpio)
 112{
 113        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 114}
 115EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 116
 117static void tegra_gpio_disable(int gpio)
 118{
 119        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 120}
 121EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 122
 123int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
 124{
 125        return pinctrl_request_gpio(offset);
 126}
 127
 128void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
 129{
 130        pinctrl_free_gpio(offset);
 131        tegra_gpio_disable(offset);
 132}
 133
 134static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 135{
 136        tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 137}
 138
 139static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 140{
 141        return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 142}
 143
 144static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 145{
 146        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 147        tegra_gpio_enable(offset);
 148        return 0;
 149}
 150
 151static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 152                                        int value)
 153{
 154        tegra_gpio_set(chip, offset, value);
 155        tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 156        tegra_gpio_enable(offset);
 157        return 0;
 158}
 159
 160static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 161{
 162        return irq_find_mapping(irq_domain, offset);
 163}
 164
 165static struct gpio_chip tegra_gpio_chip = {
 166        .label                  = "tegra-gpio",
 167        .request                = tegra_gpio_request,
 168        .free                   = tegra_gpio_free,
 169        .direction_input        = tegra_gpio_direction_input,
 170        .get                    = tegra_gpio_get,
 171        .direction_output       = tegra_gpio_direction_output,
 172        .set                    = tegra_gpio_set,
 173        .to_irq                 = tegra_gpio_to_irq,
 174        .base                   = 0,
 175};
 176
 177static void tegra_gpio_irq_ack(struct irq_data *d)
 178{
 179        int gpio = d->hwirq;
 180
 181        tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 182}
 183
 184static void tegra_gpio_irq_mask(struct irq_data *d)
 185{
 186        int gpio = d->hwirq;
 187
 188        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 189}
 190
 191static void tegra_gpio_irq_unmask(struct irq_data *d)
 192{
 193        int gpio = d->hwirq;
 194
 195        tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 196}
 197
 198static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 199{
 200        int gpio = d->hwirq;
 201        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 202        int port = GPIO_PORT(gpio);
 203        int lvl_type;
 204        int val;
 205        unsigned long flags;
 206
 207        switch (type & IRQ_TYPE_SENSE_MASK) {
 208        case IRQ_TYPE_EDGE_RISING:
 209                lvl_type = GPIO_INT_LVL_EDGE_RISING;
 210                break;
 211
 212        case IRQ_TYPE_EDGE_FALLING:
 213                lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 214                break;
 215
 216        case IRQ_TYPE_EDGE_BOTH:
 217                lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 218                break;
 219
 220        case IRQ_TYPE_LEVEL_HIGH:
 221                lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 222                break;
 223
 224        case IRQ_TYPE_LEVEL_LOW:
 225                lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 226                break;
 227
 228        default:
 229                return -EINVAL;
 230        }
 231
 232        spin_lock_irqsave(&bank->lvl_lock[port], flags);
 233
 234        val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 235        val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 236        val |= lvl_type << GPIO_BIT(gpio);
 237        tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
 238
 239        spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 240
 241        tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
 242        tegra_gpio_enable(gpio);
 243
 244        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 245                __irq_set_handler_locked(d->irq, handle_level_irq);
 246        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 247                __irq_set_handler_locked(d->irq, handle_edge_irq);
 248
 249        return 0;
 250}
 251
 252static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 253{
 254        struct tegra_gpio_bank *bank;
 255        int port;
 256        int pin;
 257        int unmasked = 0;
 258        struct irq_chip *chip = irq_desc_get_chip(desc);
 259
 260        chained_irq_enter(chip, desc);
 261
 262        bank = irq_get_handler_data(irq);
 263
 264        for (port = 0; port < 4; port++) {
 265                int gpio = tegra_gpio_compose(bank->bank, port, 0);
 266                unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
 267                        tegra_gpio_readl(GPIO_INT_ENB(gpio));
 268                u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 269
 270                for_each_set_bit(pin, &sta, 8) {
 271                        tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
 272
 273                        /* if gpio is edge triggered, clear condition
 274                         * before executing the hander so that we don't
 275                         * miss edges
 276                         */
 277                        if (lvl & (0x100 << pin)) {
 278                                unmasked = 1;
 279                                chained_irq_exit(chip, desc);
 280                        }
 281
 282                        generic_handle_irq(gpio_to_irq(gpio + pin));
 283                }
 284        }
 285
 286        if (!unmasked)
 287                chained_irq_exit(chip, desc);
 288
 289}
 290
 291#ifdef CONFIG_PM
 292void tegra_gpio_resume(void)
 293{
 294        unsigned long flags;
 295        int b;
 296        int p;
 297
 298        local_irq_save(flags);
 299
 300        for (b = 0; b < tegra_gpio_bank_count; b++) {
 301                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 302
 303                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 304                        unsigned int gpio = (b<<5) | (p<<3);
 305                        tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
 306                        tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
 307                        tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
 308                        tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 309                        tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 310                }
 311        }
 312
 313        local_irq_restore(flags);
 314}
 315
 316void tegra_gpio_suspend(void)
 317{
 318        unsigned long flags;
 319        int b;
 320        int p;
 321
 322        local_irq_save(flags);
 323        for (b = 0; b < tegra_gpio_bank_count; b++) {
 324                struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 325
 326                for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 327                        unsigned int gpio = (b<<5) | (p<<3);
 328                        bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
 329                        bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
 330                        bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
 331                        bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
 332                        bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
 333                }
 334        }
 335        local_irq_restore(flags);
 336}
 337
 338static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 339{
 340        struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 341        return irq_set_irq_wake(bank->irq, enable);
 342}
 343#endif
 344
 345static struct irq_chip tegra_gpio_irq_chip = {
 346        .name           = "GPIO",
 347        .irq_ack        = tegra_gpio_irq_ack,
 348        .irq_mask       = tegra_gpio_irq_mask,
 349        .irq_unmask     = tegra_gpio_irq_unmask,
 350        .irq_set_type   = tegra_gpio_irq_set_type,
 351#ifdef CONFIG_PM
 352        .irq_set_wake   = tegra_gpio_wake_enable,
 353#endif
 354};
 355
 356struct tegra_gpio_soc_config {
 357        u32 bank_stride;
 358        u32 upper_offset;
 359};
 360
 361static struct tegra_gpio_soc_config tegra20_gpio_config = {
 362        .bank_stride = 0x80,
 363        .upper_offset = 0x800,
 364};
 365
 366static struct tegra_gpio_soc_config tegra30_gpio_config = {
 367        .bank_stride = 0x100,
 368        .upper_offset = 0x80,
 369};
 370
 371static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
 372        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
 373        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
 374        { },
 375};
 376
 377/* This lock class tells lockdep that GPIO irqs are in a different
 378 * category than their parents, so it won't report false recursion.
 379 */
 380static struct lock_class_key gpio_lock_class;
 381
 382static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 383{
 384        const struct of_device_id *match;
 385        struct tegra_gpio_soc_config *config;
 386        int irq_base;
 387        struct resource *res;
 388        struct tegra_gpio_bank *bank;
 389        int gpio;
 390        int i;
 391        int j;
 392
 393        match = of_match_device(tegra_gpio_of_match, &pdev->dev);
 394        if (match)
 395                config = (struct tegra_gpio_soc_config *)match->data;
 396        else
 397                config = &tegra20_gpio_config;
 398
 399        tegra_gpio_bank_stride = config->bank_stride;
 400        tegra_gpio_upper_offset = config->upper_offset;
 401
 402        for (;;) {
 403                res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
 404                if (!res)
 405                        break;
 406                tegra_gpio_bank_count++;
 407        }
 408        if (!tegra_gpio_bank_count) {
 409                dev_err(&pdev->dev, "Missing IRQ resource\n");
 410                return -ENODEV;
 411        }
 412
 413        tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
 414
 415        tegra_gpio_banks = devm_kzalloc(&pdev->dev,
 416                        tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
 417                        GFP_KERNEL);
 418        if (!tegra_gpio_banks) {
 419                dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
 420                return -ENODEV;
 421        }
 422
 423        irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0);
 424        if (irq_base < 0) {
 425                dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n");
 426                return -ENODEV;
 427        }
 428        irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
 429                                           tegra_gpio_chip.ngpio, irq_base, 0,
 430                                           &irq_domain_simple_ops, NULL);
 431
 432        for (i = 0; i < tegra_gpio_bank_count; i++) {
 433                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
 434                if (!res) {
 435                        dev_err(&pdev->dev, "Missing IRQ resource\n");
 436                        return -ENODEV;
 437                }
 438
 439                bank = &tegra_gpio_banks[i];
 440                bank->bank = i;
 441                bank->irq = res->start;
 442        }
 443
 444        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 445        if (!res) {
 446                dev_err(&pdev->dev, "Missing MEM resource\n");
 447                return -ENODEV;
 448        }
 449
 450        regs = devm_request_and_ioremap(&pdev->dev, res);
 451        if (!regs) {
 452                dev_err(&pdev->dev, "Couldn't ioremap regs\n");
 453                return -ENODEV;
 454        }
 455
 456        for (i = 0; i < tegra_gpio_bank_count; i++) {
 457                for (j = 0; j < 4; j++) {
 458                        int gpio = tegra_gpio_compose(i, j, 0);
 459                        tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
 460                }
 461        }
 462
 463#ifdef CONFIG_OF_GPIO
 464        tegra_gpio_chip.of_node = pdev->dev.of_node;
 465#endif
 466
 467        gpiochip_add(&tegra_gpio_chip);
 468
 469        for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
 470                int irq = irq_find_mapping(irq_domain, gpio);
 471                /* No validity check; all Tegra GPIOs are valid IRQs */
 472
 473                bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 474
 475                irq_set_lockdep_class(irq, &gpio_lock_class);
 476                irq_set_chip_data(irq, bank);
 477                irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 478                                         handle_simple_irq);
 479                set_irq_flags(irq, IRQF_VALID);
 480        }
 481
 482        for (i = 0; i < tegra_gpio_bank_count; i++) {
 483                bank = &tegra_gpio_banks[i];
 484
 485                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 486                irq_set_handler_data(bank->irq, bank);
 487
 488                for (j = 0; j < 4; j++)
 489                        spin_lock_init(&bank->lvl_lock[j]);
 490        }
 491
 492        return 0;
 493}
 494
 495static struct platform_driver tegra_gpio_driver = {
 496        .driver         = {
 497                .name   = "tegra-gpio",
 498                .owner  = THIS_MODULE,
 499                .of_match_table = tegra_gpio_of_match,
 500        },
 501        .probe          = tegra_gpio_probe,
 502};
 503
 504static int __init tegra_gpio_init(void)
 505{
 506        return platform_driver_register(&tegra_gpio_driver);
 507}
 508postcore_initcall(tegra_gpio_init);
 509
 510#ifdef  CONFIG_DEBUG_FS
 511
 512#include <linux/debugfs.h>
 513#include <linux/seq_file.h>
 514
 515static int dbg_gpio_show(struct seq_file *s, void *unused)
 516{
 517        int i;
 518        int j;
 519
 520        for (i = 0; i < tegra_gpio_bank_count; i++) {
 521                for (j = 0; j < 4; j++) {
 522                        int gpio = tegra_gpio_compose(i, j, 0);
 523                        seq_printf(s,
 524                                "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 525                                i, j,
 526                                tegra_gpio_readl(GPIO_CNF(gpio)),
 527                                tegra_gpio_readl(GPIO_OE(gpio)),
 528                                tegra_gpio_readl(GPIO_OUT(gpio)),
 529                                tegra_gpio_readl(GPIO_IN(gpio)),
 530                                tegra_gpio_readl(GPIO_INT_STA(gpio)),
 531                                tegra_gpio_readl(GPIO_INT_ENB(gpio)),
 532                                tegra_gpio_readl(GPIO_INT_LVL(gpio)));
 533                }
 534        }
 535        return 0;
 536}
 537
 538static int dbg_gpio_open(struct inode *inode, struct file *file)
 539{
 540        return single_open(file, dbg_gpio_show, &inode->i_private);
 541}
 542
 543static const struct file_operations debug_fops = {
 544        .open           = dbg_gpio_open,
 545        .read           = seq_read,
 546        .llseek         = seq_lseek,
 547        .release        = single_release,
 548};
 549
 550static int __init tegra_gpio_debuginit(void)
 551{
 552        (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 553                                        NULL, NULL, &debug_fops);
 554        return 0;
 555}
 556late_initcall(tegra_gpio_debuginit);
 557#endif
 558
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