linux/drivers/gpio/gpio-ml-ioh.c
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   1/*
   2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; version 2 of the License.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16 */
  17#include <linux/module.h>
  18#include <linux/kernel.h>
  19#include <linux/slab.h>
  20#include <linux/pci.h>
  21#include <linux/gpio.h>
  22#include <linux/interrupt.h>
  23#include <linux/irq.h>
  24
  25#define IOH_EDGE_FALLING        0
  26#define IOH_EDGE_RISING         BIT(0)
  27#define IOH_LEVEL_L             BIT(1)
  28#define IOH_LEVEL_H             (BIT(0) | BIT(1))
  29#define IOH_EDGE_BOTH           BIT(2)
  30#define IOH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
  31
  32#define IOH_IRQ_BASE            0
  33
  34#define PCI_VENDOR_ID_ROHM             0x10DB
  35
  36struct ioh_reg_comn {
  37        u32     ien;
  38        u32     istatus;
  39        u32     idisp;
  40        u32     iclr;
  41        u32     imask;
  42        u32     imaskclr;
  43        u32     po;
  44        u32     pi;
  45        u32     pm;
  46        u32     im_0;
  47        u32     im_1;
  48        u32     reserved;
  49};
  50
  51struct ioh_regs {
  52        struct ioh_reg_comn regs[8];
  53        u32 reserve1[16];
  54        u32 ioh_sel_reg[4];
  55        u32 reserve2[11];
  56        u32 srst;
  57};
  58
  59/**
  60 * struct ioh_gpio_reg_data - The register store data.
  61 * @ien_reg     To store contents of interrupt enable register.
  62 * @imask_reg:  To store contents of interrupt mask regist
  63 * @po_reg:     To store contents of PO register.
  64 * @pm_reg:     To store contents of PM register.
  65 * @im0_reg:    To store contents of interrupt mode regist0
  66 * @im1_reg:    To store contents of interrupt mode regist1
  67 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
  68 */
  69struct ioh_gpio_reg_data {
  70        u32 ien_reg;
  71        u32 imask_reg;
  72        u32 po_reg;
  73        u32 pm_reg;
  74        u32 im0_reg;
  75        u32 im1_reg;
  76        u32 use_sel_reg;
  77};
  78
  79/**
  80 * struct ioh_gpio - GPIO private data structure.
  81 * @base:                       PCI base address of Memory mapped I/O register.
  82 * @reg:                        Memory mapped IOH GPIO register list.
  83 * @dev:                        Pointer to device structure.
  84 * @gpio:                       Data for GPIO infrastructure.
  85 * @ioh_gpio_reg:               Memory mapped Register data is saved here
  86 *                              when suspend.
  87 * @gpio_use_sel:               Save GPIO_USE_SEL1~4 register for PM
  88 * @ch:                         Indicate GPIO channel
  89 * @irq_base:           Save base of IRQ number for interrupt
  90 * @spinlock:           Used for register access protection in
  91 *                              interrupt context ioh_irq_type and PM;
  92 */
  93struct ioh_gpio {
  94        void __iomem *base;
  95        struct ioh_regs __iomem *reg;
  96        struct device *dev;
  97        struct gpio_chip gpio;
  98        struct ioh_gpio_reg_data ioh_gpio_reg;
  99        u32 gpio_use_sel;
 100        struct mutex lock;
 101        int ch;
 102        int irq_base;
 103        spinlock_t spinlock;
 104};
 105
 106static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
 107
 108static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
 109{
 110        u32 reg_val;
 111        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
 112
 113        mutex_lock(&chip->lock);
 114        reg_val = ioread32(&chip->reg->regs[chip->ch].po);
 115        if (val)
 116                reg_val |= (1 << nr);
 117        else
 118                reg_val &= ~(1 << nr);
 119
 120        iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
 121        mutex_unlock(&chip->lock);
 122}
 123
 124static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
 125{
 126        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
 127
 128        return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
 129}
 130
 131static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 132                                     int val)
 133{
 134        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
 135        u32 pm;
 136        u32 reg_val;
 137
 138        mutex_lock(&chip->lock);
 139        pm = ioread32(&chip->reg->regs[chip->ch].pm) &
 140                                        ((1 << num_ports[chip->ch]) - 1);
 141        pm |= (1 << nr);
 142        iowrite32(pm, &chip->reg->regs[chip->ch].pm);
 143
 144        reg_val = ioread32(&chip->reg->regs[chip->ch].po);
 145        if (val)
 146                reg_val |= (1 << nr);
 147        else
 148                reg_val &= ~(1 << nr);
 149        iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
 150
 151        mutex_unlock(&chip->lock);
 152
 153        return 0;
 154}
 155
 156static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 157{
 158        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
 159        u32 pm;
 160
 161        mutex_lock(&chip->lock);
 162        pm = ioread32(&chip->reg->regs[chip->ch].pm) &
 163                                ((1 << num_ports[chip->ch]) - 1);
 164        pm &= ~(1 << nr);
 165        iowrite32(pm, &chip->reg->regs[chip->ch].pm);
 166        mutex_unlock(&chip->lock);
 167
 168        return 0;
 169}
 170
 171#ifdef CONFIG_PM
 172/*
 173 * Save register configuration and disable interrupts.
 174 */
 175static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
 176{
 177        int i;
 178
 179        for (i = 0; i < 8; i ++, chip++) {
 180                chip->ioh_gpio_reg.po_reg =
 181                                        ioread32(&chip->reg->regs[chip->ch].po);
 182                chip->ioh_gpio_reg.pm_reg =
 183                                        ioread32(&chip->reg->regs[chip->ch].pm);
 184                chip->ioh_gpio_reg.ien_reg =
 185                                       ioread32(&chip->reg->regs[chip->ch].ien);
 186                chip->ioh_gpio_reg.imask_reg =
 187                                     ioread32(&chip->reg->regs[chip->ch].imask);
 188                chip->ioh_gpio_reg.im0_reg =
 189                                      ioread32(&chip->reg->regs[chip->ch].im_0);
 190                chip->ioh_gpio_reg.im1_reg =
 191                                      ioread32(&chip->reg->regs[chip->ch].im_1);
 192                if (i < 4)
 193                        chip->ioh_gpio_reg.use_sel_reg =
 194                                           ioread32(&chip->reg->ioh_sel_reg[i]);
 195        }
 196}
 197
 198/*
 199 * This function restores the register configuration of the GPIO device.
 200 */
 201static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
 202{
 203        int i;
 204
 205        for (i = 0; i < 8; i ++, chip++) {
 206                iowrite32(chip->ioh_gpio_reg.po_reg,
 207                          &chip->reg->regs[chip->ch].po);
 208                iowrite32(chip->ioh_gpio_reg.pm_reg,
 209                          &chip->reg->regs[chip->ch].pm);
 210                iowrite32(chip->ioh_gpio_reg.ien_reg,
 211                          &chip->reg->regs[chip->ch].ien);
 212                iowrite32(chip->ioh_gpio_reg.imask_reg,
 213                          &chip->reg->regs[chip->ch].imask);
 214                iowrite32(chip->ioh_gpio_reg.im0_reg,
 215                          &chip->reg->regs[chip->ch].im_0);
 216                iowrite32(chip->ioh_gpio_reg.im1_reg,
 217                          &chip->reg->regs[chip->ch].im_1);
 218                if (i < 4)
 219                        iowrite32(chip->ioh_gpio_reg.use_sel_reg,
 220                                  &chip->reg->ioh_sel_reg[i]);
 221        }
 222}
 223#endif
 224
 225static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
 226{
 227        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
 228        return chip->irq_base + offset;
 229}
 230
 231static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
 232{
 233        struct gpio_chip *gpio = &chip->gpio;
 234
 235        gpio->label = dev_name(chip->dev);
 236        gpio->owner = THIS_MODULE;
 237        gpio->direction_input = ioh_gpio_direction_input;
 238        gpio->get = ioh_gpio_get;
 239        gpio->direction_output = ioh_gpio_direction_output;
 240        gpio->set = ioh_gpio_set;
 241        gpio->dbg_show = NULL;
 242        gpio->base = -1;
 243        gpio->ngpio = num_port;
 244        gpio->can_sleep = 0;
 245        gpio->to_irq = ioh_gpio_to_irq;
 246}
 247
 248static int ioh_irq_type(struct irq_data *d, unsigned int type)
 249{
 250        u32 im;
 251        void __iomem *im_reg;
 252        u32 ien;
 253        u32 im_pos;
 254        int ch;
 255        unsigned long flags;
 256        u32 val;
 257        int irq = d->irq;
 258        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 259        struct ioh_gpio *chip = gc->private;
 260
 261        ch = irq - chip->irq_base;
 262        if (irq <= chip->irq_base + 7) {
 263                im_reg = &chip->reg->regs[chip->ch].im_0;
 264                im_pos = ch;
 265        } else {
 266                im_reg = &chip->reg->regs[chip->ch].im_1;
 267                im_pos = ch - 8;
 268        }
 269        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
 270                __func__, irq, type, ch, im_pos, type);
 271
 272        spin_lock_irqsave(&chip->spinlock, flags);
 273
 274        switch (type) {
 275        case IRQ_TYPE_EDGE_RISING:
 276                val = IOH_EDGE_RISING;
 277                break;
 278        case IRQ_TYPE_EDGE_FALLING:
 279                val = IOH_EDGE_FALLING;
 280                break;
 281        case IRQ_TYPE_EDGE_BOTH:
 282                val = IOH_EDGE_BOTH;
 283                break;
 284        case IRQ_TYPE_LEVEL_HIGH:
 285                val = IOH_LEVEL_H;
 286                break;
 287        case IRQ_TYPE_LEVEL_LOW:
 288                val = IOH_LEVEL_L;
 289                break;
 290        case IRQ_TYPE_PROBE:
 291                goto end;
 292        default:
 293                dev_warn(chip->dev, "%s: unknown type(%dd)",
 294                        __func__, type);
 295                goto end;
 296        }
 297
 298        /* Set interrupt mode */
 299        im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
 300        iowrite32(im | (val << (im_pos * 4)), im_reg);
 301
 302        /* iclr */
 303        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
 304
 305        /* IMASKCLR */
 306        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
 307
 308        /* Enable interrupt */
 309        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 310        iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
 311end:
 312        spin_unlock_irqrestore(&chip->spinlock, flags);
 313
 314        return 0;
 315}
 316
 317static void ioh_irq_unmask(struct irq_data *d)
 318{
 319        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 320        struct ioh_gpio *chip = gc->private;
 321
 322        iowrite32(1 << (d->irq - chip->irq_base),
 323                  &chip->reg->regs[chip->ch].imaskclr);
 324}
 325
 326static void ioh_irq_mask(struct irq_data *d)
 327{
 328        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 329        struct ioh_gpio *chip = gc->private;
 330
 331        iowrite32(1 << (d->irq - chip->irq_base),
 332                  &chip->reg->regs[chip->ch].imask);
 333}
 334
 335static void ioh_irq_disable(struct irq_data *d)
 336{
 337        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 338        struct ioh_gpio *chip = gc->private;
 339        unsigned long flags;
 340        u32 ien;
 341
 342        spin_lock_irqsave(&chip->spinlock, flags);
 343        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 344        ien &= ~(1 << (d->irq - chip->irq_base));
 345        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
 346        spin_unlock_irqrestore(&chip->spinlock, flags);
 347}
 348
 349static void ioh_irq_enable(struct irq_data *d)
 350{
 351        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 352        struct ioh_gpio *chip = gc->private;
 353        unsigned long flags;
 354        u32 ien;
 355
 356        spin_lock_irqsave(&chip->spinlock, flags);
 357        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 358        ien |= 1 << (d->irq - chip->irq_base);
 359        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
 360        spin_unlock_irqrestore(&chip->spinlock, flags);
 361}
 362
 363static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
 364{
 365        struct ioh_gpio *chip = dev_id;
 366        u32 reg_val;
 367        int i, j;
 368        int ret = IRQ_NONE;
 369
 370        for (i = 0; i < 8; i++, chip++) {
 371                reg_val = ioread32(&chip->reg->regs[i].istatus);
 372                for (j = 0; j < num_ports[i]; j++) {
 373                        if (reg_val & BIT(j)) {
 374                                dev_dbg(chip->dev,
 375                                        "%s:[%d]:irq=%d status=0x%x\n",
 376                                        __func__, j, irq, reg_val);
 377                                iowrite32(BIT(j),
 378                                          &chip->reg->regs[chip->ch].iclr);
 379                                generic_handle_irq(chip->irq_base + j);
 380                                ret = IRQ_HANDLED;
 381                        }
 382                }
 383        }
 384        return ret;
 385}
 386
 387static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
 388                                unsigned int irq_start, unsigned int num)
 389{
 390        struct irq_chip_generic *gc;
 391        struct irq_chip_type *ct;
 392
 393        gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
 394                                    handle_simple_irq);
 395        gc->private = chip;
 396        ct = gc->chip_types;
 397
 398        ct->chip.irq_mask = ioh_irq_mask;
 399        ct->chip.irq_unmask = ioh_irq_unmask;
 400        ct->chip.irq_set_type = ioh_irq_type;
 401        ct->chip.irq_disable = ioh_irq_disable;
 402        ct->chip.irq_enable = ioh_irq_enable;
 403
 404        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 405                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 406}
 407
 408static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
 409                                    const struct pci_device_id *id)
 410{
 411        int ret;
 412        int i, j;
 413        struct ioh_gpio *chip;
 414        void __iomem *base;
 415        void *chip_save;
 416        int irq_base;
 417
 418        ret = pci_enable_device(pdev);
 419        if (ret) {
 420                dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
 421                goto err_pci_enable;
 422        }
 423
 424        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 425        if (ret) {
 426                dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
 427                goto err_request_regions;
 428        }
 429
 430        base = pci_iomap(pdev, 1, 0);
 431        if (!base) {
 432                dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
 433                ret = -ENOMEM;
 434                goto err_iomap;
 435        }
 436
 437        chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
 438        if (chip_save == NULL) {
 439                dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
 440                ret = -ENOMEM;
 441                goto err_kzalloc;
 442        }
 443
 444        chip = chip_save;
 445        for (i = 0; i < 8; i++, chip++) {
 446                chip->dev = &pdev->dev;
 447                chip->base = base;
 448                chip->reg = chip->base;
 449                chip->ch = i;
 450                mutex_init(&chip->lock);
 451                spin_lock_init(&chip->spinlock);
 452                ioh_gpio_setup(chip, num_ports[i]);
 453                ret = gpiochip_add(&chip->gpio);
 454                if (ret) {
 455                        dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
 456                        goto err_gpiochip_add;
 457                }
 458        }
 459
 460        chip = chip_save;
 461        for (j = 0; j < 8; j++, chip++) {
 462                irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
 463                                           NUMA_NO_NODE);
 464                if (irq_base < 0) {
 465                        dev_warn(&pdev->dev,
 466                                "ml_ioh_gpio: Failed to get IRQ base num\n");
 467                        chip->irq_base = -1;
 468                        goto err_irq_alloc_descs;
 469                }
 470                chip->irq_base = irq_base;
 471                ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
 472        }
 473
 474        chip = chip_save;
 475        ret = request_irq(pdev->irq, ioh_gpio_handler,
 476                             IRQF_SHARED, KBUILD_MODNAME, chip);
 477        if (ret != 0) {
 478                dev_err(&pdev->dev,
 479                        "%s request_irq failed\n", __func__);
 480                goto err_request_irq;
 481        }
 482
 483        pci_set_drvdata(pdev, chip);
 484
 485        return 0;
 486
 487err_request_irq:
 488        chip = chip_save;
 489err_irq_alloc_descs:
 490        while (--j >= 0) {
 491                chip--;
 492                irq_free_descs(chip->irq_base, num_ports[j]);
 493        }
 494
 495        chip = chip_save;
 496err_gpiochip_add:
 497        while (--i >= 0) {
 498                chip--;
 499                ret = gpiochip_remove(&chip->gpio);
 500                if (ret)
 501                        dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
 502        }
 503        kfree(chip_save);
 504
 505err_kzalloc:
 506        pci_iounmap(pdev, base);
 507
 508err_iomap:
 509        pci_release_regions(pdev);
 510
 511err_request_regions:
 512        pci_disable_device(pdev);
 513
 514err_pci_enable:
 515
 516        dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
 517        return ret;
 518}
 519
 520static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
 521{
 522        int err;
 523        int i;
 524        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 525        void *chip_save;
 526
 527        chip_save = chip;
 528
 529        free_irq(pdev->irq, chip);
 530
 531        for (i = 0; i < 8; i++, chip++) {
 532                irq_free_descs(chip->irq_base, num_ports[i]);
 533                err = gpiochip_remove(&chip->gpio);
 534                if (err)
 535                        dev_err(&pdev->dev, "Failed gpiochip_remove\n");
 536        }
 537
 538        chip = chip_save;
 539        pci_iounmap(pdev, chip->base);
 540        pci_release_regions(pdev);
 541        pci_disable_device(pdev);
 542        kfree(chip);
 543}
 544
 545#ifdef CONFIG_PM
 546static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 547{
 548        s32 ret;
 549        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 550        unsigned long flags;
 551
 552        spin_lock_irqsave(&chip->spinlock, flags);
 553        ioh_gpio_save_reg_conf(chip);
 554        spin_unlock_irqrestore(&chip->spinlock, flags);
 555
 556        ret = pci_save_state(pdev);
 557        if (ret) {
 558                dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
 559                return ret;
 560        }
 561        pci_disable_device(pdev);
 562        pci_set_power_state(pdev, PCI_D0);
 563        ret = pci_enable_wake(pdev, PCI_D0, 1);
 564        if (ret)
 565                dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
 566
 567        return 0;
 568}
 569
 570static int ioh_gpio_resume(struct pci_dev *pdev)
 571{
 572        s32 ret;
 573        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 574        unsigned long flags;
 575
 576        ret = pci_enable_wake(pdev, PCI_D0, 0);
 577
 578        pci_set_power_state(pdev, PCI_D0);
 579        ret = pci_enable_device(pdev);
 580        if (ret) {
 581                dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
 582                return ret;
 583        }
 584        pci_restore_state(pdev);
 585
 586        spin_lock_irqsave(&chip->spinlock, flags);
 587        iowrite32(0x01, &chip->reg->srst);
 588        iowrite32(0x00, &chip->reg->srst);
 589        ioh_gpio_restore_reg_conf(chip);
 590        spin_unlock_irqrestore(&chip->spinlock, flags);
 591
 592        return 0;
 593}
 594#else
 595#define ioh_gpio_suspend NULL
 596#define ioh_gpio_resume NULL
 597#endif
 598
 599static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
 600        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
 601        { 0, }
 602};
 603MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
 604
 605static struct pci_driver ioh_gpio_driver = {
 606        .name = "ml_ioh_gpio",
 607        .id_table = ioh_gpio_pcidev_id,
 608        .probe = ioh_gpio_probe,
 609        .remove = __devexit_p(ioh_gpio_remove),
 610        .suspend = ioh_gpio_suspend,
 611        .resume = ioh_gpio_resume
 612};
 613
 614module_pci_driver(ioh_gpio_driver);
 615
 616MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
 617MODULE_LICENSE("GPL");
 618
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