linux/drivers/ata/sata_svw.c
<<
>>
Prefs
   1/*
   2 *  sata_svw.c - ServerWorks / Apple K2 SATA
   3 *
   4 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
   5 *                 Jeff Garzik <jgarzik@pobox.com>
   6 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7 *                  on emails.
   8 *
   9 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  10 *
  11 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  12 *
  13 *  This driver probably works with non-Apple versions of the
  14 *  Broadcom chipset...
  15 *
  16 *
  17 *  This program is free software; you can redistribute it and/or modify
  18 *  it under the terms of the GNU General Public License as published by
  19 *  the Free Software Foundation; either version 2, or (at your option)
  20 *  any later version.
  21 *
  22 *  This program is distributed in the hope that it will be useful,
  23 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 *  GNU General Public License for more details.
  26 *
  27 *  You should have received a copy of the GNU General Public License
  28 *  along with this program; see the file COPYING.  If not, write to
  29 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  30 *
  31 *
  32 *  libata documentation is available via 'make {ps|pdf}docs',
  33 *  as Documentation/DocBook/libata.*
  34 *
  35 *  Hardware documentation available under NDA.
  36 *
  37 */
  38
  39#include <linux/kernel.h>
  40#include <linux/module.h>
  41#include <linux/pci.h>
  42#include <linux/init.h>
  43#include <linux/blkdev.h>
  44#include <linux/delay.h>
  45#include <linux/interrupt.h>
  46#include <linux/device.h>
  47#include <scsi/scsi_host.h>
  48#include <scsi/scsi_cmnd.h>
  49#include <scsi/scsi.h>
  50#include <linux/libata.h>
  51
  52#ifdef CONFIG_PPC_OF
  53#include <asm/prom.h>
  54#include <asm/pci-bridge.h>
  55#endif /* CONFIG_PPC_OF */
  56
  57#define DRV_NAME        "sata_svw"
  58#define DRV_VERSION     "2.3"
  59
  60enum {
  61        /* ap->flags bits */
  62        K2_FLAG_SATA_8_PORTS            = (1 << 24),
  63        K2_FLAG_NO_ATAPI_DMA            = (1 << 25),
  64        K2_FLAG_BAR_POS_3                       = (1 << 26),
  65
  66        /* Taskfile registers offsets */
  67        K2_SATA_TF_CMD_OFFSET           = 0x00,
  68        K2_SATA_TF_DATA_OFFSET          = 0x00,
  69        K2_SATA_TF_ERROR_OFFSET         = 0x04,
  70        K2_SATA_TF_NSECT_OFFSET         = 0x08,
  71        K2_SATA_TF_LBAL_OFFSET          = 0x0c,
  72        K2_SATA_TF_LBAM_OFFSET          = 0x10,
  73        K2_SATA_TF_LBAH_OFFSET          = 0x14,
  74        K2_SATA_TF_DEVICE_OFFSET        = 0x18,
  75        K2_SATA_TF_CMDSTAT_OFFSET       = 0x1c,
  76        K2_SATA_TF_CTL_OFFSET           = 0x20,
  77
  78        /* DMA base */
  79        K2_SATA_DMA_CMD_OFFSET          = 0x30,
  80
  81        /* SCRs base */
  82        K2_SATA_SCR_STATUS_OFFSET       = 0x40,
  83        K2_SATA_SCR_ERROR_OFFSET        = 0x44,
  84        K2_SATA_SCR_CONTROL_OFFSET      = 0x48,
  85
  86        /* Others */
  87        K2_SATA_SICR1_OFFSET            = 0x80,
  88        K2_SATA_SICR2_OFFSET            = 0x84,
  89        K2_SATA_SIM_OFFSET              = 0x88,
  90
  91        /* Port stride */
  92        K2_SATA_PORT_OFFSET             = 0x100,
  93
  94        chip_svw4                       = 0,
  95        chip_svw8                       = 1,
  96        chip_svw42                      = 2,    /* bar 3 */
  97        chip_svw43                      = 3,    /* bar 5 */
  98};
  99
 100static u8 k2_stat_check_status(struct ata_port *ap);
 101
 102
 103static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
 104{
 105        u8 cmnd = qc->scsicmd->cmnd[0];
 106
 107        if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
 108                return -1;      /* ATAPI DMA not supported */
 109        else {
 110                switch (cmnd) {
 111                case READ_10:
 112                case READ_12:
 113                case READ_16:
 114                case WRITE_10:
 115                case WRITE_12:
 116                case WRITE_16:
 117                        return 0;
 118
 119                default:
 120                        return -1;
 121                }
 122
 123        }
 124}
 125
 126static int k2_sata_scr_read(struct ata_link *link,
 127                            unsigned int sc_reg, u32 *val)
 128{
 129        if (sc_reg > SCR_CONTROL)
 130                return -EINVAL;
 131        *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
 132        return 0;
 133}
 134
 135
 136static int k2_sata_scr_write(struct ata_link *link,
 137                             unsigned int sc_reg, u32 val)
 138{
 139        if (sc_reg > SCR_CONTROL)
 140                return -EINVAL;
 141        writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
 142        return 0;
 143}
 144
 145
 146static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 147{
 148        struct ata_ioports *ioaddr = &ap->ioaddr;
 149        unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 150
 151        if (tf->ctl != ap->last_ctl) {
 152                writeb(tf->ctl, ioaddr->ctl_addr);
 153                ap->last_ctl = tf->ctl;
 154                ata_wait_idle(ap);
 155        }
 156        if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 157                writew(tf->feature | (((u16)tf->hob_feature) << 8),
 158                       ioaddr->feature_addr);
 159                writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
 160                       ioaddr->nsect_addr);
 161                writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
 162                       ioaddr->lbal_addr);
 163                writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
 164                       ioaddr->lbam_addr);
 165                writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
 166                       ioaddr->lbah_addr);
 167        } else if (is_addr) {
 168                writew(tf->feature, ioaddr->feature_addr);
 169                writew(tf->nsect, ioaddr->nsect_addr);
 170                writew(tf->lbal, ioaddr->lbal_addr);
 171                writew(tf->lbam, ioaddr->lbam_addr);
 172                writew(tf->lbah, ioaddr->lbah_addr);
 173        }
 174
 175        if (tf->flags & ATA_TFLAG_DEVICE)
 176                writeb(tf->device, ioaddr->device_addr);
 177
 178        ata_wait_idle(ap);
 179}
 180
 181
 182static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 183{
 184        struct ata_ioports *ioaddr = &ap->ioaddr;
 185        u16 nsect, lbal, lbam, lbah, feature;
 186
 187        tf->command = k2_stat_check_status(ap);
 188        tf->device = readw(ioaddr->device_addr);
 189        feature = readw(ioaddr->error_addr);
 190        nsect = readw(ioaddr->nsect_addr);
 191        lbal = readw(ioaddr->lbal_addr);
 192        lbam = readw(ioaddr->lbam_addr);
 193        lbah = readw(ioaddr->lbah_addr);
 194
 195        tf->feature = feature;
 196        tf->nsect = nsect;
 197        tf->lbal = lbal;
 198        tf->lbam = lbam;
 199        tf->lbah = lbah;
 200
 201        if (tf->flags & ATA_TFLAG_LBA48) {
 202                tf->hob_feature = feature >> 8;
 203                tf->hob_nsect = nsect >> 8;
 204                tf->hob_lbal = lbal >> 8;
 205                tf->hob_lbam = lbam >> 8;
 206                tf->hob_lbah = lbah >> 8;
 207        }
 208}
 209
 210/**
 211 *      k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 212 *      @qc: Info associated with this ATA transaction.
 213 *
 214 *      LOCKING:
 215 *      spin_lock_irqsave(host lock)
 216 */
 217
 218static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
 219{
 220        struct ata_port *ap = qc->ap;
 221        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 222        u8 dmactl;
 223        void __iomem *mmio = ap->ioaddr.bmdma_addr;
 224
 225        /* load PRD table addr. */
 226        mb();   /* make sure PRD table writes are visible to controller */
 227        writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
 228
 229        /* specify data direction, triple-check start bit is clear */
 230        dmactl = readb(mmio + ATA_DMA_CMD);
 231        dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
 232        if (!rw)
 233                dmactl |= ATA_DMA_WR;
 234        writeb(dmactl, mmio + ATA_DMA_CMD);
 235
 236        /* issue r/w command if this is not a ATA DMA command*/
 237        if (qc->tf.protocol != ATA_PROT_DMA)
 238                ap->ops->sff_exec_command(ap, &qc->tf);
 239}
 240
 241/**
 242 *      k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 243 *      @qc: Info associated with this ATA transaction.
 244 *
 245 *      LOCKING:
 246 *      spin_lock_irqsave(host lock)
 247 */
 248
 249static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
 250{
 251        struct ata_port *ap = qc->ap;
 252        void __iomem *mmio = ap->ioaddr.bmdma_addr;
 253        u8 dmactl;
 254
 255        /* start host DMA transaction */
 256        dmactl = readb(mmio + ATA_DMA_CMD);
 257        writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
 258        /* This works around possible data corruption.
 259
 260           On certain SATA controllers that can be seen when the r/w
 261           command is given to the controller before the host DMA is
 262           started.
 263
 264           On a Read command, the controller would initiate the
 265           command to the drive even before it sees the DMA
 266           start. When there are very fast drives connected to the
 267           controller, or when the data request hits in the drive
 268           cache, there is the possibility that the drive returns a
 269           part or all of the requested data to the controller before
 270           the DMA start is issued.  In this case, the controller
 271           would become confused as to what to do with the data.  In
 272           the worst case when all the data is returned back to the
 273           controller, the controller could hang. In other cases it
 274           could return partial data returning in data
 275           corruption. This problem has been seen in PPC systems and
 276           can also appear on an system with very fast disks, where
 277           the SATA controller is sitting behind a number of bridges,
 278           and hence there is significant latency between the r/w
 279           command and the start command. */
 280        /* issue r/w command if the access is to ATA */
 281        if (qc->tf.protocol == ATA_PROT_DMA)
 282                ap->ops->sff_exec_command(ap, &qc->tf);
 283}
 284
 285
 286static u8 k2_stat_check_status(struct ata_port *ap)
 287{
 288        return readl(ap->ioaddr.status_addr);
 289}
 290
 291#ifdef CONFIG_PPC_OF
 292/*
 293 * k2_sata_proc_info
 294 * inout : decides on the direction of the dataflow and the meaning of the
 295 *         variables
 296 * buffer: If inout==FALSE data is being written to it else read from it
 297 * *start: If inout==FALSE start of the valid data in the buffer
 298 * offset: If inout==FALSE offset from the beginning of the imaginary file
 299 *         from which we start writing into the buffer
 300 * length: If inout==FALSE max number of bytes to be written into the buffer
 301 *         else number of bytes in the buffer
 302 */
 303static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
 304                             off_t offset, int count, int inout)
 305{
 306        struct ata_port *ap;
 307        struct device_node *np;
 308        int len, index;
 309
 310        /* Find  the ata_port */
 311        ap = ata_shost_to_port(shost);
 312        if (ap == NULL)
 313                return 0;
 314
 315        /* Find the OF node for the PCI device proper */
 316        np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
 317        if (np == NULL)
 318                return 0;
 319
 320        /* Match it to a port node */
 321        index = (ap == ap->host->ports[0]) ? 0 : 1;
 322        for (np = np->child; np != NULL; np = np->sibling) {
 323                const u32 *reg = of_get_property(np, "reg", NULL);
 324                if (!reg)
 325                        continue;
 326                if (index == *reg)
 327                        break;
 328        }
 329        if (np == NULL)
 330                return 0;
 331
 332        len = sprintf(page, "devspec: %s\n", np->full_name);
 333
 334        return len;
 335}
 336#endif /* CONFIG_PPC_OF */
 337
 338
 339static struct scsi_host_template k2_sata_sht = {
 340        ATA_BMDMA_SHT(DRV_NAME),
 341#ifdef CONFIG_PPC_OF
 342        .proc_info              = k2_sata_proc_info,
 343#endif
 344};
 345
 346
 347static struct ata_port_operations k2_sata_ops = {
 348        .inherits               = &ata_bmdma_port_ops,
 349        .sff_tf_load            = k2_sata_tf_load,
 350        .sff_tf_read            = k2_sata_tf_read,
 351        .sff_check_status       = k2_stat_check_status,
 352        .check_atapi_dma        = k2_sata_check_atapi_dma,
 353        .bmdma_setup            = k2_bmdma_setup_mmio,
 354        .bmdma_start            = k2_bmdma_start_mmio,
 355        .scr_read               = k2_sata_scr_read,
 356        .scr_write              = k2_sata_scr_write,
 357};
 358
 359static const struct ata_port_info k2_port_info[] = {
 360        /* chip_svw4 */
 361        {
 362                .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
 363                .pio_mask       = ATA_PIO4,
 364                .mwdma_mask     = ATA_MWDMA2,
 365                .udma_mask      = ATA_UDMA6,
 366                .port_ops       = &k2_sata_ops,
 367        },
 368        /* chip_svw8 */
 369        {
 370                .flags          = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
 371                                  K2_FLAG_SATA_8_PORTS,
 372                .pio_mask       = ATA_PIO4,
 373                .mwdma_mask     = ATA_MWDMA2,
 374                .udma_mask      = ATA_UDMA6,
 375                .port_ops       = &k2_sata_ops,
 376        },
 377        /* chip_svw42 */
 378        {
 379                .flags          = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
 380                .pio_mask       = ATA_PIO4,
 381                .mwdma_mask     = ATA_MWDMA2,
 382                .udma_mask      = ATA_UDMA6,
 383                .port_ops       = &k2_sata_ops,
 384        },
 385        /* chip_svw43 */
 386        {
 387                .flags          = ATA_FLAG_SATA,
 388                .pio_mask       = ATA_PIO4,
 389                .mwdma_mask     = ATA_MWDMA2,
 390                .udma_mask      = ATA_UDMA6,
 391                .port_ops       = &k2_sata_ops,
 392        },
 393};
 394
 395static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
 396{
 397        port->cmd_addr          = base + K2_SATA_TF_CMD_OFFSET;
 398        port->data_addr         = base + K2_SATA_TF_DATA_OFFSET;
 399        port->feature_addr      =
 400        port->error_addr        = base + K2_SATA_TF_ERROR_OFFSET;
 401        port->nsect_addr        = base + K2_SATA_TF_NSECT_OFFSET;
 402        port->lbal_addr         = base + K2_SATA_TF_LBAL_OFFSET;
 403        port->lbam_addr         = base + K2_SATA_TF_LBAM_OFFSET;
 404        port->lbah_addr         = base + K2_SATA_TF_LBAH_OFFSET;
 405        port->device_addr       = base + K2_SATA_TF_DEVICE_OFFSET;
 406        port->command_addr      =
 407        port->status_addr       = base + K2_SATA_TF_CMDSTAT_OFFSET;
 408        port->altstatus_addr    =
 409        port->ctl_addr          = base + K2_SATA_TF_CTL_OFFSET;
 410        port->bmdma_addr        = base + K2_SATA_DMA_CMD_OFFSET;
 411        port->scr_addr          = base + K2_SATA_SCR_STATUS_OFFSET;
 412}
 413
 414
 415static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 416{
 417        const struct ata_port_info *ppi[] =
 418                { &k2_port_info[ent->driver_data], NULL };
 419        struct ata_host *host;
 420        void __iomem *mmio_base;
 421        int n_ports, i, rc, bar_pos;
 422
 423        ata_print_version_once(&pdev->dev, DRV_VERSION);
 424
 425        /* allocate host */
 426        n_ports = 4;
 427        if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
 428                n_ports = 8;
 429
 430        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 431        if (!host)
 432                return -ENOMEM;
 433
 434        bar_pos = 5;
 435        if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
 436                bar_pos = 3;
 437        /*
 438         * If this driver happens to only be useful on Apple's K2, then
 439         * we should check that here as it has a normal Serverworks ID
 440         */
 441        rc = pcim_enable_device(pdev);
 442        if (rc)
 443                return rc;
 444
 445        /*
 446         * Check if we have resources mapped at all (second function may
 447         * have been disabled by firmware)
 448         */
 449        if (pci_resource_len(pdev, bar_pos) == 0) {
 450                /* In IDE mode we need to pin the device to ensure that
 451                        pcim_release does not clear the busmaster bit in config
 452                        space, clearing causes busmaster DMA to fail on
 453                        ports 3 & 4 */
 454                pcim_pin_device(pdev);
 455                return -ENODEV;
 456        }
 457
 458        /* Request and iomap PCI regions */
 459        rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
 460        if (rc == -EBUSY)
 461                pcim_pin_device(pdev);
 462        if (rc)
 463                return rc;
 464        host->iomap = pcim_iomap_table(pdev);
 465        mmio_base = host->iomap[bar_pos];
 466
 467        /* different controllers have different number of ports - currently 4 or 8 */
 468        /* All ports are on the same function. Multi-function device is no
 469         * longer available. This should not be seen in any system. */
 470        for (i = 0; i < host->n_ports; i++) {
 471                struct ata_port *ap = host->ports[i];
 472                unsigned int offset = i * K2_SATA_PORT_OFFSET;
 473
 474                k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
 475
 476                ata_port_pbar_desc(ap, 5, -1, "mmio");
 477                ata_port_pbar_desc(ap, 5, offset, "port");
 478        }
 479
 480        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 481        if (rc)
 482                return rc;
 483        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 484        if (rc)
 485                return rc;
 486
 487        /* Clear a magic bit in SCR1 according to Darwin, those help
 488         * some funky seagate drives (though so far, those were already
 489         * set by the firmware on the machines I had access to)
 490         */
 491        writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
 492               mmio_base + K2_SATA_SICR1_OFFSET);
 493
 494        /* Clear SATA error & interrupts we don't use */
 495        writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
 496        writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
 497
 498        pci_set_master(pdev);
 499        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 500                                 IRQF_SHARED, &k2_sata_sht);
 501}
 502
 503/* 0x240 is device ID for Apple K2 device
 504 * 0x241 is device ID for Serverworks Frodo4
 505 * 0x242 is device ID for Serverworks Frodo8
 506 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 507 * controller
 508 * */
 509static const struct pci_device_id k2_sata_pci_tbl[] = {
 510        { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
 511        { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
 512        { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
 513        { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
 514        { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
 515        { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
 516        { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
 517
 518        { }
 519};
 520
 521static struct pci_driver k2_sata_pci_driver = {
 522        .name                   = DRV_NAME,
 523        .id_table               = k2_sata_pci_tbl,
 524        .probe                  = k2_sata_init_one,
 525        .remove                 = ata_pci_remove_one,
 526};
 527
 528module_pci_driver(k2_sata_pci_driver);
 529
 530MODULE_AUTHOR("Benjamin Herrenschmidt");
 531MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
 532MODULE_LICENSE("GPL");
 533MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
 534MODULE_VERSION(DRV_VERSION);
 535
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.