linux/drivers/ata/sata_dwc_460ex.c
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   1/*
   2 * drivers/ata/sata_dwc_460ex.c
   3 *
   4 * Synopsys DesignWare Cores (DWC) SATA host driver
   5 *
   6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
   7 *
   8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
   9 * Copyright 2008 DENX Software Engineering
  10 *
  11 * Based on versions provided by AMCC and Synopsys which are:
  12 *          Copyright 2006 Applied Micro Circuits Corporation
  13 *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
  14 *
  15 * This program is free software; you can redistribute  it and/or modify it
  16 * under  the terms of  the GNU General  Public License as published by the
  17 * Free Software Foundation;  either version 2 of the  License, or (at your
  18 * option) any later version.
  19 */
  20
  21#ifdef CONFIG_SATA_DWC_DEBUG
  22#define DEBUG
  23#endif
  24
  25#ifdef CONFIG_SATA_DWC_VDEBUG
  26#define VERBOSE_DEBUG
  27#define DEBUG_NCQ
  28#endif
  29
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/init.h>
  33#include <linux/device.h>
  34#include <linux/of_platform.h>
  35#include <linux/platform_device.h>
  36#include <linux/libata.h>
  37#include <linux/slab.h>
  38#include "libata.h"
  39
  40#include <scsi/scsi_host.h>
  41#include <scsi/scsi_cmnd.h>
  42
  43/* These two are defined in "libata.h" */
  44#undef  DRV_NAME
  45#undef  DRV_VERSION
  46#define DRV_NAME        "sata-dwc"
  47#define DRV_VERSION     "1.3"
  48
  49/* SATA DMA driver Globals */
  50#define DMA_NUM_CHANS           1
  51#define DMA_NUM_CHAN_REGS       8
  52
  53/* SATA DMA Register definitions */
  54#define AHB_DMA_BRST_DFLT       64      /* 16 data items burst length*/
  55
  56struct dmareg {
  57        u32 low;                /* Low bits 0-31 */
  58        u32 high;               /* High bits 32-63 */
  59};
  60
  61/* DMA Per Channel registers */
  62struct dma_chan_regs {
  63        struct dmareg sar;      /* Source Address */
  64        struct dmareg dar;      /* Destination address */
  65        struct dmareg llp;      /* Linked List Pointer */
  66        struct dmareg ctl;      /* Control */
  67        struct dmareg sstat;    /* Source Status not implemented in core */
  68        struct dmareg dstat;    /* Destination Status not implemented in core*/
  69        struct dmareg sstatar;  /* Source Status Address not impl in core */
  70        struct dmareg dstatar;  /* Destination Status Address not implemente */
  71        struct dmareg cfg;      /* Config */
  72        struct dmareg sgr;      /* Source Gather */
  73        struct dmareg dsr;      /* Destination Scatter */
  74};
  75
  76/* Generic Interrupt Registers */
  77struct dma_interrupt_regs {
  78        struct dmareg tfr;      /* Transfer Interrupt */
  79        struct dmareg block;    /* Block Interrupt */
  80        struct dmareg srctran;  /* Source Transfer Interrupt */
  81        struct dmareg dsttran;  /* Dest Transfer Interrupt */
  82        struct dmareg error;    /* Error */
  83};
  84
  85struct ahb_dma_regs {
  86        struct dma_chan_regs    chan_regs[DMA_NUM_CHAN_REGS];
  87        struct dma_interrupt_regs interrupt_raw;        /* Raw Interrupt */
  88        struct dma_interrupt_regs interrupt_status;     /* Interrupt Status */
  89        struct dma_interrupt_regs interrupt_mask;       /* Interrupt Mask */
  90        struct dma_interrupt_regs interrupt_clear;      /* Interrupt Clear */
  91        struct dmareg           statusInt;      /* Interrupt combined*/
  92        struct dmareg           rq_srcreg;      /* Src Trans Req */
  93        struct dmareg           rq_dstreg;      /* Dst Trans Req */
  94        struct dmareg           rq_sgl_srcreg;  /* Sngl Src Trans Req*/
  95        struct dmareg           rq_sgl_dstreg;  /* Sngl Dst Trans Req*/
  96        struct dmareg           rq_lst_srcreg;  /* Last Src Trans Req*/
  97        struct dmareg           rq_lst_dstreg;  /* Last Dst Trans Req*/
  98        struct dmareg           dma_cfg;                /* DMA Config */
  99        struct dmareg           dma_chan_en;            /* DMA Channel Enable*/
 100        struct dmareg           dma_id;                 /* DMA ID */
 101        struct dmareg           dma_test;               /* DMA Test */
 102        struct dmareg           res1;                   /* reserved */
 103        struct dmareg           res2;                   /* reserved */
 104        /*
 105         * DMA Comp Params
 106         * Param 6 = dma_param[0], Param 5 = dma_param[1],
 107         * Param 4 = dma_param[2] ...
 108         */
 109        struct dmareg           dma_params[6];
 110};
 111
 112/* Data structure for linked list item */
 113struct lli {
 114        u32             sar;            /* Source Address */
 115        u32             dar;            /* Destination address */
 116        u32             llp;            /* Linked List Pointer */
 117        struct dmareg   ctl;            /* Control */
 118        struct dmareg   dstat;          /* Destination Status */
 119};
 120
 121enum {
 122        SATA_DWC_DMAC_LLI_SZ =  (sizeof(struct lli)),
 123        SATA_DWC_DMAC_LLI_NUM = 256,
 124        SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
 125                                        SATA_DWC_DMAC_LLI_NUM),
 126        SATA_DWC_DMAC_TWIDTH_BYTES = 4,
 127        SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
 128                                                SATA_DWC_DMAC_TWIDTH_BYTES),
 129};
 130
 131/* DMA Register Operation Bits */
 132enum {
 133        DMA_EN  =               0x00000001, /* Enable AHB DMA */
 134        DMA_CTL_LLP_SRCEN =     0x10000000, /* Blk chain enable Src */
 135        DMA_CTL_LLP_DSTEN =     0x08000000, /* Blk chain enable Dst */
 136};
 137
 138#define DMA_CTL_BLK_TS(size)    ((size) & 0x000000FFF)  /* Blk Transfer size */
 139#define DMA_CHANNEL(ch)         (0x00000001 << (ch))    /* Select channel */
 140        /* Enable channel */
 141#define DMA_ENABLE_CHAN(ch)     ((0x00000001 << (ch)) |                 \
 142                                 ((0x000000001 << (ch)) << 8))
 143        /* Disable channel */
 144#define DMA_DISABLE_CHAN(ch)    (0x00000000 | ((0x000000001 << (ch)) << 8))
 145        /* Transfer Type & Flow Controller */
 146#define DMA_CTL_TTFC(type)      (((type) & 0x7) << 20)
 147#define DMA_CTL_SMS(num)        (((num) & 0x3) << 25) /* Src Master Select */
 148#define DMA_CTL_DMS(num)        (((num) & 0x3) << 23)/* Dst Master Select */
 149        /* Src Burst Transaction Length */
 150#define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
 151        /* Dst Burst Transaction Length */
 152#define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
 153        /* Source Transfer Width */
 154#define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
 155        /* Destination Transfer Width */
 156#define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
 157
 158/* Assign HW handshaking interface (x) to destination / source peripheral */
 159#define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
 160#define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
 161#define DMA_CFG_HW_CH_PRIOR(int_num) (((int_num) & 0xF) << 5)
 162#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
 163
 164/*
 165 * This define is used to set block chaining disabled in the control low
 166 * register.  It is already in little endian format so it can be &'d dirctly.
 167 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
 168 */
 169enum {
 170        DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
 171        DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
 172        DMA_CTL_TTFC_M2P_PER =  0x00000003, /* Mem to per, peripheral cntr */
 173        DMA_CTL_SINC_INC =      0x00000000, /* Source Address Increment */
 174        DMA_CTL_SINC_DEC =      0x00000200,
 175        DMA_CTL_SINC_NOCHANGE = 0x00000400,
 176        DMA_CTL_DINC_INC =      0x00000000, /* Destination Address Increment */
 177        DMA_CTL_DINC_DEC =      0x00000080,
 178        DMA_CTL_DINC_NOCHANGE = 0x00000100,
 179        DMA_CTL_INT_EN =        0x00000001, /* Interrupt Enable */
 180
 181/* Channel Configuration Register high bits */
 182        DMA_CFG_FCMOD_REQ =     0x00000001, /* Flow Control - request based */
 183        DMA_CFG_PROTCTL =       (0x00000003 << 2),/* Protection Control */
 184
 185/* Channel Configuration Register low bits */
 186        DMA_CFG_RELD_DST =      0x80000000, /* Reload Dest / Src Addr */
 187        DMA_CFG_RELD_SRC =      0x40000000,
 188        DMA_CFG_HS_SELSRC =     0x00000800, /* Software handshake Src/ Dest */
 189        DMA_CFG_HS_SELDST =     0x00000400,
 190        DMA_CFG_FIFOEMPTY =     (0x00000001 << 9), /* FIFO Empty bit */
 191
 192/* Channel Linked List Pointer Register */
 193        DMA_LLP_AHBMASTER1 =    0,      /* List Master Select */
 194        DMA_LLP_AHBMASTER2 =    1,
 195
 196        SATA_DWC_MAX_PORTS = 1,
 197
 198        SATA_DWC_SCR_OFFSET = 0x24,
 199        SATA_DWC_REG_OFFSET = 0x64,
 200};
 201
 202/* DWC SATA Registers */
 203struct sata_dwc_regs {
 204        u32 fptagr;             /* 1st party DMA tag */
 205        u32 fpbor;              /* 1st party DMA buffer offset */
 206        u32 fptcr;              /* 1st party DMA Xfr count */
 207        u32 dmacr;              /* DMA Control */
 208        u32 dbtsr;              /* DMA Burst Transac size */
 209        u32 intpr;              /* Interrupt Pending */
 210        u32 intmr;              /* Interrupt Mask */
 211        u32 errmr;              /* Error Mask */
 212        u32 llcr;               /* Link Layer Control */
 213        u32 phycr;              /* PHY Control */
 214        u32 physr;              /* PHY Status */
 215        u32 rxbistpd;           /* Recvd BIST pattern def register */
 216        u32 rxbistpd1;          /* Recvd BIST data dword1 */
 217        u32 rxbistpd2;          /* Recvd BIST pattern data dword2 */
 218        u32 txbistpd;           /* Trans BIST pattern def register */
 219        u32 txbistpd1;          /* Trans BIST data dword1 */
 220        u32 txbistpd2;          /* Trans BIST data dword2 */
 221        u32 bistcr;             /* BIST Control Register */
 222        u32 bistfctr;           /* BIST FIS Count Register */
 223        u32 bistsr;             /* BIST Status Register */
 224        u32 bistdecr;           /* BIST Dword Error count register */
 225        u32 res[15];            /* Reserved locations */
 226        u32 testr;              /* Test Register */
 227        u32 versionr;           /* Version Register */
 228        u32 idr;                /* ID Register */
 229        u32 unimpl[192];        /* Unimplemented */
 230        u32 dmadr[256]; /* FIFO Locations in DMA Mode */
 231};
 232
 233enum {
 234        SCR_SCONTROL_DET_ENABLE =       0x00000001,
 235        SCR_SSTATUS_DET_PRESENT =       0x00000001,
 236        SCR_SERROR_DIAG_X       =       0x04000000,
 237/* DWC SATA Register Operations */
 238        SATA_DWC_TXFIFO_DEPTH   =       0x01FF,
 239        SATA_DWC_RXFIFO_DEPTH   =       0x01FF,
 240        SATA_DWC_DMACR_TMOD_TXCHEN =    0x00000004,
 241        SATA_DWC_DMACR_TXCHEN   = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
 242        SATA_DWC_DMACR_RXCHEN   = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
 243        SATA_DWC_DMACR_TXRXCH_CLEAR =   SATA_DWC_DMACR_TMOD_TXCHEN,
 244        SATA_DWC_INTPR_DMAT     =       0x00000001,
 245        SATA_DWC_INTPR_NEWFP    =       0x00000002,
 246        SATA_DWC_INTPR_PMABRT   =       0x00000004,
 247        SATA_DWC_INTPR_ERR      =       0x00000008,
 248        SATA_DWC_INTPR_NEWBIST  =       0x00000010,
 249        SATA_DWC_INTPR_IPF      =       0x10000000,
 250        SATA_DWC_INTMR_DMATM    =       0x00000001,
 251        SATA_DWC_INTMR_NEWFPM   =       0x00000002,
 252        SATA_DWC_INTMR_PMABRTM  =       0x00000004,
 253        SATA_DWC_INTMR_ERRM     =       0x00000008,
 254        SATA_DWC_INTMR_NEWBISTM =       0x00000010,
 255        SATA_DWC_LLCR_SCRAMEN   =       0x00000001,
 256        SATA_DWC_LLCR_DESCRAMEN =       0x00000002,
 257        SATA_DWC_LLCR_RPDEN     =       0x00000004,
 258/* This is all error bits, zero's are reserved fields. */
 259        SATA_DWC_SERROR_ERR_BITS =      0x0FFF0F03
 260};
 261
 262#define SATA_DWC_SCR0_SPD_GET(v)        (((v) >> 4) & 0x0000000F)
 263#define SATA_DWC_DMACR_TX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
 264                                                 SATA_DWC_DMACR_TMOD_TXCHEN)
 265#define SATA_DWC_DMACR_RX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
 266                                                 SATA_DWC_DMACR_TMOD_TXCHEN)
 267#define SATA_DWC_DBTSR_MWR(size)        (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
 268#define SATA_DWC_DBTSR_MRD(size)        ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
 269                                                 << 16)
 270struct sata_dwc_device {
 271        struct device           *dev;           /* generic device struct */
 272        struct ata_probe_ent    *pe;            /* ptr to probe-ent */
 273        struct ata_host         *host;
 274        u8                      *reg_base;
 275        struct sata_dwc_regs    *sata_dwc_regs; /* DW Synopsys SATA specific */
 276        int                     irq_dma;
 277};
 278
 279#define SATA_DWC_QCMD_MAX       32
 280
 281struct sata_dwc_device_port {
 282        struct sata_dwc_device  *hsdev;
 283        int                     cmd_issued[SATA_DWC_QCMD_MAX];
 284        struct lli              *llit[SATA_DWC_QCMD_MAX];  /* DMA LLI table */
 285        dma_addr_t              llit_dma[SATA_DWC_QCMD_MAX];
 286        u32                     dma_chan[SATA_DWC_QCMD_MAX];
 287        int                     dma_pending[SATA_DWC_QCMD_MAX];
 288};
 289
 290/*
 291 * Commonly used DWC SATA driver Macros
 292 */
 293#define HSDEV_FROM_HOST(host)  ((struct sata_dwc_device *)\
 294                                        (host)->private_data)
 295#define HSDEV_FROM_AP(ap)  ((struct sata_dwc_device *)\
 296                                        (ap)->host->private_data)
 297#define HSDEVP_FROM_AP(ap)   ((struct sata_dwc_device_port *)\
 298                                        (ap)->private_data)
 299#define HSDEV_FROM_QC(qc)       ((struct sata_dwc_device *)\
 300                                        (qc)->ap->host->private_data)
 301#define HSDEV_FROM_HSDEVP(p)    ((struct sata_dwc_device *)\
 302                                                (hsdevp)->hsdev)
 303
 304enum {
 305        SATA_DWC_CMD_ISSUED_NOT         = 0,
 306        SATA_DWC_CMD_ISSUED_PEND        = 1,
 307        SATA_DWC_CMD_ISSUED_EXEC        = 2,
 308        SATA_DWC_CMD_ISSUED_NODATA      = 3,
 309
 310        SATA_DWC_DMA_PENDING_NONE       = 0,
 311        SATA_DWC_DMA_PENDING_TX         = 1,
 312        SATA_DWC_DMA_PENDING_RX         = 2,
 313};
 314
 315struct sata_dwc_host_priv {
 316        void    __iomem  *scr_addr_sstatus;
 317        u32     sata_dwc_sactive_issued ;
 318        u32     sata_dwc_sactive_queued ;
 319        u32     dma_interrupt_count;
 320        struct  ahb_dma_regs    *sata_dma_regs;
 321        struct  device  *dwc_dev;
 322        int     dma_channel;
 323};
 324struct sata_dwc_host_priv host_pvt;
 325/*
 326 * Prototypes
 327 */
 328static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
 329static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
 330                                u32 check_status);
 331static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
 332static void sata_dwc_port_stop(struct ata_port *ap);
 333static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
 334static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
 335static void dma_dwc_exit(struct sata_dwc_device *hsdev);
 336static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
 337                              struct lli *lli, dma_addr_t dma_lli,
 338                              void __iomem *addr, int dir);
 339static void dma_dwc_xfer_start(int dma_ch);
 340
 341static const char *get_prot_descript(u8 protocol)
 342{
 343        switch ((enum ata_tf_protocols)protocol) {
 344        case ATA_PROT_NODATA:
 345                return "ATA no data";
 346        case ATA_PROT_PIO:
 347                return "ATA PIO";
 348        case ATA_PROT_DMA:
 349                return "ATA DMA";
 350        case ATA_PROT_NCQ:
 351                return "ATA NCQ";
 352        case ATAPI_PROT_NODATA:
 353                return "ATAPI no data";
 354        case ATAPI_PROT_PIO:
 355                return "ATAPI PIO";
 356        case ATAPI_PROT_DMA:
 357                return "ATAPI DMA";
 358        default:
 359                return "unknown";
 360        }
 361}
 362
 363static const char *get_dma_dir_descript(int dma_dir)
 364{
 365        switch ((enum dma_data_direction)dma_dir) {
 366        case DMA_BIDIRECTIONAL:
 367                return "bidirectional";
 368        case DMA_TO_DEVICE:
 369                return "to device";
 370        case DMA_FROM_DEVICE:
 371                return "from device";
 372        default:
 373                return "none";
 374        }
 375}
 376
 377static void sata_dwc_tf_dump(struct ata_taskfile *tf)
 378{
 379        dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
 380                "0x%lx device: %x\n", tf->command,
 381                get_prot_descript(tf->protocol), tf->flags, tf->device);
 382        dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
 383                "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
 384                 tf->lbam, tf->lbah);
 385        dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
 386                "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
 387                tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
 388                tf->hob_lbah);
 389}
 390
 391/*
 392 * Function: get_burst_length_encode
 393 * arguments: datalength: length in bytes of data
 394 * returns value to be programmed in register corresponding to data length
 395 * This value is effectively the log(base 2) of the length
 396 */
 397static  int get_burst_length_encode(int datalength)
 398{
 399        int items = datalength >> 2;    /* div by 4 to get lword count */
 400
 401        if (items >= 64)
 402                return 5;
 403
 404        if (items >= 32)
 405                return 4;
 406
 407        if (items >= 16)
 408                return 3;
 409
 410        if (items >= 8)
 411                return 2;
 412
 413        if (items >= 4)
 414                return 1;
 415
 416        return 0;
 417}
 418
 419static  void clear_chan_interrupts(int c)
 420{
 421        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
 422                 DMA_CHANNEL(c));
 423        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
 424                 DMA_CHANNEL(c));
 425        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
 426                 DMA_CHANNEL(c));
 427        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
 428                 DMA_CHANNEL(c));
 429        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
 430                 DMA_CHANNEL(c));
 431}
 432
 433/*
 434 * Function: dma_request_channel
 435 * arguments: None
 436 * returns channel number if available else -1
 437 * This function assigns the next available DMA channel from the list to the
 438 * requester
 439 */
 440static int dma_request_channel(void)
 441{
 442        /* Check if the channel is not currently in use */
 443        if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &
 444                DMA_CHANNEL(host_pvt.dma_channel)))
 445                return host_pvt.dma_channel;
 446        dev_err(host_pvt.dwc_dev, "%s Channel %d is currently in use\n",
 447                __func__, host_pvt.dma_channel);
 448        return -1;
 449}
 450
 451/*
 452 * Function: dma_dwc_interrupt
 453 * arguments: irq, dev_id, pt_regs
 454 * returns channel number if available else -1
 455 * Interrupt Handler for DW AHB SATA DMA
 456 */
 457static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
 458{
 459        int chan;
 460        u32 tfr_reg, err_reg;
 461        unsigned long flags;
 462        struct sata_dwc_device *hsdev =
 463                (struct sata_dwc_device *)hsdev_instance;
 464        struct ata_host *host = (struct ata_host *)hsdev->host;
 465        struct ata_port *ap;
 466        struct sata_dwc_device_port *hsdevp;
 467        u8 tag = 0;
 468        unsigned int port = 0;
 469
 470        spin_lock_irqsave(&host->lock, flags);
 471        ap = host->ports[port];
 472        hsdevp = HSDEVP_FROM_AP(ap);
 473        tag = ap->link.active_tag;
 474
 475        tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
 476                        .low));
 477        err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
 478                        .low));
 479
 480        dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
 481                tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
 482
 483        chan = host_pvt.dma_channel;
 484        if (chan >= 0) {
 485                /* Check for end-of-transfer interrupt. */
 486                if (tfr_reg & DMA_CHANNEL(chan)) {
 487                        /*
 488                         * Each DMA command produces 2 interrupts.  Only
 489                         * complete the command after both interrupts have been
 490                         * seen. (See sata_dwc_isr())
 491                         */
 492                        host_pvt.dma_interrupt_count++;
 493                        sata_dwc_clear_dmacr(hsdevp, tag);
 494
 495                        if (hsdevp->dma_pending[tag] ==
 496                            SATA_DWC_DMA_PENDING_NONE) {
 497                                dev_err(ap->dev, "DMA not pending eot=0x%08x "
 498                                        "err=0x%08x tag=0x%02x pending=%d\n",
 499                                        tfr_reg, err_reg, tag,
 500                                        hsdevp->dma_pending[tag]);
 501                        }
 502
 503                        if ((host_pvt.dma_interrupt_count % 2) == 0)
 504                                sata_dwc_dma_xfer_complete(ap, 1);
 505
 506                        /* Clear the interrupt */
 507                        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
 508                                .tfr.low),
 509                                 DMA_CHANNEL(chan));
 510                }
 511
 512                /* Check for error interrupt. */
 513                if (err_reg & DMA_CHANNEL(chan)) {
 514                        /* TODO Need error handler ! */
 515                        dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
 516                                err_reg);
 517
 518                        /* Clear the interrupt. */
 519                        out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
 520                                .error.low),
 521                                 DMA_CHANNEL(chan));
 522                }
 523        }
 524        spin_unlock_irqrestore(&host->lock, flags);
 525        return IRQ_HANDLED;
 526}
 527
 528/*
 529 * Function: dma_request_interrupts
 530 * arguments: hsdev
 531 * returns status
 532 * This function registers ISR for a particular DMA channel interrupt
 533 */
 534static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
 535{
 536        int retval = 0;
 537        int chan = host_pvt.dma_channel;
 538
 539        if (chan >= 0) {
 540                /* Unmask error interrupt */
 541                out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
 542                         DMA_ENABLE_CHAN(chan));
 543
 544                /* Unmask end-of-transfer interrupt */
 545                out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
 546                         DMA_ENABLE_CHAN(chan));
 547        }
 548
 549        retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
 550        if (retval) {
 551                dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
 552                __func__, irq);
 553                return -ENODEV;
 554        }
 555
 556        /* Mark this interrupt as requested */
 557        hsdev->irq_dma = irq;
 558        return 0;
 559}
 560
 561/*
 562 * Function: map_sg_to_lli
 563 * The Synopsis driver has a comment proposing that better performance
 564 * is possible by only enabling interrupts on the last item in the linked list.
 565 * However, it seems that could be a problem if an error happened on one of the
 566 * first items.  The transfer would halt, but no error interrupt would occur.
 567 * Currently this function sets interrupts enabled for each linked list item:
 568 * DMA_CTL_INT_EN.
 569 */
 570static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
 571                        struct lli *lli, dma_addr_t dma_lli,
 572                        void __iomem *dmadr_addr, int dir)
 573{
 574        int i, idx = 0;
 575        int fis_len = 0;
 576        dma_addr_t next_llp;
 577        int bl;
 578        int sms_val, dms_val;
 579
 580        sms_val = 0;
 581        dms_val = 1 + host_pvt.dma_channel;
 582        dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
 583                " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
 584                (u32)dmadr_addr);
 585
 586        bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
 587
 588        for (i = 0; i < num_elems; i++, sg++) {
 589                u32 addr, offset;
 590                u32 sg_len, len;
 591
 592                addr = (u32) sg_dma_address(sg);
 593                sg_len = sg_dma_len(sg);
 594
 595                dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
 596                        "=%d\n", __func__, i, addr, sg_len);
 597
 598                while (sg_len) {
 599                        if (idx >= SATA_DWC_DMAC_LLI_NUM) {
 600                                /* The LLI table is not large enough. */
 601                                dev_err(host_pvt.dwc_dev, "LLI table overrun "
 602                                "(idx=%d)\n", idx);
 603                                break;
 604                        }
 605                        len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
 606                                SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
 607
 608                        offset = addr & 0xffff;
 609                        if ((offset + sg_len) > 0x10000)
 610                                len = 0x10000 - offset;
 611
 612                        /*
 613                         * Make sure a LLI block is not created that will span
 614                         * 8K max FIS boundary.  If the block spans such a FIS
 615                         * boundary, there is a chance that a DMA burst will
 616                         * cross that boundary -- this results in an error in
 617                         * the host controller.
 618                         */
 619                        if (fis_len + len > 8192) {
 620                                dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
 621                                        "%d(0x%x) len=%d(0x%x)\n", fis_len,
 622                                         fis_len, len, len);
 623                                len = 8192 - fis_len;
 624                                fis_len = 0;
 625                        } else {
 626                                fis_len += len;
 627                        }
 628                        if (fis_len == 8192)
 629                                fis_len = 0;
 630
 631                        /*
 632                         * Set DMA addresses and lower half of control register
 633                         * based on direction.
 634                         */
 635                        if (dir == DMA_FROM_DEVICE) {
 636                                lli[idx].dar = cpu_to_le32(addr);
 637                                lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
 638
 639                                lli[idx].ctl.low = cpu_to_le32(
 640                                        DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
 641                                        DMA_CTL_SMS(sms_val) |
 642                                        DMA_CTL_DMS(dms_val) |
 643                                        DMA_CTL_SRC_MSIZE(bl) |
 644                                        DMA_CTL_DST_MSIZE(bl) |
 645                                        DMA_CTL_SINC_NOCHANGE |
 646                                        DMA_CTL_SRC_TRWID(2) |
 647                                        DMA_CTL_DST_TRWID(2) |
 648                                        DMA_CTL_INT_EN |
 649                                        DMA_CTL_LLP_SRCEN |
 650                                        DMA_CTL_LLP_DSTEN);
 651                        } else {        /* DMA_TO_DEVICE */
 652                                lli[idx].sar = cpu_to_le32(addr);
 653                                lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
 654
 655                                lli[idx].ctl.low = cpu_to_le32(
 656                                        DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
 657                                        DMA_CTL_SMS(dms_val) |
 658                                        DMA_CTL_DMS(sms_val) |
 659                                        DMA_CTL_SRC_MSIZE(bl) |
 660                                        DMA_CTL_DST_MSIZE(bl) |
 661                                        DMA_CTL_DINC_NOCHANGE |
 662                                        DMA_CTL_SRC_TRWID(2) |
 663                                        DMA_CTL_DST_TRWID(2) |
 664                                        DMA_CTL_INT_EN |
 665                                        DMA_CTL_LLP_SRCEN |
 666                                        DMA_CTL_LLP_DSTEN);
 667                        }
 668
 669                        dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
 670                                "0x%08x val: 0x%08x\n", __func__,
 671                                len, DMA_CTL_BLK_TS(len / 4));
 672
 673                        /* Program the LLI CTL high register */
 674                        lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
 675                                                (len / 4));
 676
 677                        /* Program the next pointer.  The next pointer must be
 678                         * the physical address, not the virtual address.
 679                         */
 680                        next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
 681                                                        lli)));
 682
 683                        /* The last 2 bits encode the list master select. */
 684                        next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
 685
 686                        lli[idx].llp = cpu_to_le32(next_llp);
 687                        idx++;
 688                        sg_len -= len;
 689                        addr += len;
 690                }
 691        }
 692
 693        /*
 694         * The last next ptr has to be zero and the last control low register
 695         * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
 696         * and destination enable) set back to 0 (disabled.) This is what tells
 697         * the core that this is the last item in the linked list.
 698         */
 699        if (idx) {
 700                lli[idx-1].llp = 0x00000000;
 701                lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
 702
 703                /* Flush cache to memory */
 704                dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
 705                               DMA_BIDIRECTIONAL);
 706        }
 707
 708        return idx;
 709}
 710
 711/*
 712 * Function: dma_dwc_xfer_start
 713 * arguments: Channel number
 714 * Return : None
 715 * Enables the DMA channel
 716 */
 717static void dma_dwc_xfer_start(int dma_ch)
 718{
 719        /* Enable the DMA channel */
 720        out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
 721                 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
 722                 DMA_ENABLE_CHAN(dma_ch));
 723}
 724
 725static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
 726                              struct lli *lli, dma_addr_t dma_lli,
 727                              void __iomem *addr, int dir)
 728{
 729        int dma_ch;
 730        int num_lli;
 731        /* Acquire DMA channel */
 732        dma_ch = dma_request_channel();
 733        if (dma_ch == -1) {
 734                dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
 735                         __func__);
 736                return -EAGAIN;
 737        }
 738
 739        /* Convert SG list to linked list of items (LLIs) for AHB DMA */
 740        num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
 741
 742        dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
 743                " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
 744                 lli, (u32)dma_lli, addr, num_lli);
 745
 746        clear_chan_interrupts(dma_ch);
 747
 748        /* Program the CFG register. */
 749        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
 750                 DMA_CFG_HW_HS_SRC(dma_ch) | DMA_CFG_HW_HS_DEST(dma_ch) |
 751                 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
 752        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low),
 753                 DMA_CFG_HW_CH_PRIOR(dma_ch));
 754
 755        /* Program the address of the linked list */
 756        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
 757                 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
 758
 759        /* Program the CTL register with src enable / dst enable */
 760        out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
 761                 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
 762        return dma_ch;
 763}
 764
 765/*
 766 * Function: dma_dwc_exit
 767 * arguments: None
 768 * returns status
 769 * This function exits the SATA DMA driver
 770 */
 771static void dma_dwc_exit(struct sata_dwc_device *hsdev)
 772{
 773        dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
 774        if (host_pvt.sata_dma_regs) {
 775                iounmap(host_pvt.sata_dma_regs);
 776                host_pvt.sata_dma_regs = NULL;
 777        }
 778
 779        if (hsdev->irq_dma) {
 780                free_irq(hsdev->irq_dma, hsdev);
 781                hsdev->irq_dma = 0;
 782        }
 783}
 784
 785/*
 786 * Function: dma_dwc_init
 787 * arguments: hsdev
 788 * returns status
 789 * This function initializes the SATA DMA driver
 790 */
 791static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
 792{
 793        int err;
 794
 795        err = dma_request_interrupts(hsdev, irq);
 796        if (err) {
 797                dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
 798                        " %d\n", __func__, err);
 799                goto error_out;
 800        }
 801
 802        /* Enabe DMA */
 803        out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
 804
 805        dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
 806        dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
 807                sata_dma_regs);
 808
 809        return 0;
 810
 811error_out:
 812        dma_dwc_exit(hsdev);
 813
 814        return err;
 815}
 816
 817static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
 818{
 819        if (scr > SCR_NOTIFICATION) {
 820                dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
 821                        __func__, scr);
 822                return -EINVAL;
 823        }
 824
 825        *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
 826        dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
 827                __func__, link->ap->print_id, scr, *val);
 828
 829        return 0;
 830}
 831
 832static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
 833{
 834        dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
 835                __func__, link->ap->print_id, scr, val);
 836        if (scr > SCR_NOTIFICATION) {
 837                dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
 838                         __func__, scr);
 839                return -EINVAL;
 840        }
 841        out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
 842
 843        return 0;
 844}
 845
 846static u32 core_scr_read(unsigned int scr)
 847{
 848        return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
 849                        (scr * 4));
 850}
 851
 852static void core_scr_write(unsigned int scr, u32 val)
 853{
 854        out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
 855                val);
 856}
 857
 858static void clear_serror(void)
 859{
 860        u32 val;
 861        val = core_scr_read(SCR_ERROR);
 862        core_scr_write(SCR_ERROR, val);
 863
 864}
 865
 866static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
 867{
 868        out_le32(&hsdev->sata_dwc_regs->intpr,
 869                 in_le32(&hsdev->sata_dwc_regs->intpr));
 870}
 871
 872static u32 qcmd_tag_to_mask(u8 tag)
 873{
 874        return 0x00000001 << (tag & 0x1f);
 875}
 876
 877/* See ahci.c */
 878static void sata_dwc_error_intr(struct ata_port *ap,
 879                                struct sata_dwc_device *hsdev, uint intpr)
 880{
 881        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
 882        struct ata_eh_info *ehi = &ap->link.eh_info;
 883        unsigned int err_mask = 0, action = 0;
 884        struct ata_queued_cmd *qc;
 885        u32 serror;
 886        u8 status, tag;
 887        u32 err_reg;
 888
 889        ata_ehi_clear_desc(ehi);
 890
 891        serror = core_scr_read(SCR_ERROR);
 892        status = ap->ops->sff_check_status(ap);
 893
 894        err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
 895                        low));
 896        tag = ap->link.active_tag;
 897
 898        dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
 899                "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
 900                __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
 901                hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
 902
 903        /* Clear error register and interrupt bit */
 904        clear_serror();
 905        clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
 906
 907        /* This is the only error happening now.  TODO check for exact error */
 908
 909        err_mask |= AC_ERR_HOST_BUS;
 910        action |= ATA_EH_RESET;
 911
 912        /* Pass this on to EH */
 913        ehi->serror |= serror;
 914        ehi->action |= action;
 915
 916        qc = ata_qc_from_tag(ap, tag);
 917        if (qc)
 918                qc->err_mask |= err_mask;
 919        else
 920                ehi->err_mask |= err_mask;
 921
 922        ata_port_abort(ap);
 923}
 924
 925/*
 926 * Function : sata_dwc_isr
 927 * arguments : irq, void *dev_instance, struct pt_regs *regs
 928 * Return value : irqreturn_t - status of IRQ
 929 * This Interrupt handler called via port ops registered function.
 930 * .irq_handler = sata_dwc_isr
 931 */
 932static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
 933{
 934        struct ata_host *host = (struct ata_host *)dev_instance;
 935        struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
 936        struct ata_port *ap;
 937        struct ata_queued_cmd *qc;
 938        unsigned long flags;
 939        u8 status, tag;
 940        int handled, num_processed, port = 0;
 941        uint intpr, sactive, sactive2, tag_mask;
 942        struct sata_dwc_device_port *hsdevp;
 943        host_pvt.sata_dwc_sactive_issued = 0;
 944
 945        spin_lock_irqsave(&host->lock, flags);
 946
 947        /* Read the interrupt register */
 948        intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
 949
 950        ap = host->ports[port];
 951        hsdevp = HSDEVP_FROM_AP(ap);
 952
 953        dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
 954                ap->link.active_tag);
 955
 956        /* Check for error interrupt */
 957        if (intpr & SATA_DWC_INTPR_ERR) {
 958                sata_dwc_error_intr(ap, hsdev, intpr);
 959                handled = 1;
 960                goto DONE;
 961        }
 962
 963        /* Check for DMA SETUP FIS (FP DMA) interrupt */
 964        if (intpr & SATA_DWC_INTPR_NEWFP) {
 965                clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
 966
 967                tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
 968                dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
 969                if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
 970                        dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
 971
 972                host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
 973
 974                qc = ata_qc_from_tag(ap, tag);
 975                /*
 976                 * Start FP DMA for NCQ command.  At this point the tag is the
 977                 * active tag.  It is the tag that matches the command about to
 978                 * be completed.
 979                 */
 980                qc->ap->link.active_tag = tag;
 981                sata_dwc_bmdma_start_by_tag(qc, tag);
 982
 983                handled = 1;
 984                goto DONE;
 985        }
 986        sactive = core_scr_read(SCR_ACTIVE);
 987        tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
 988
 989        /* If no sactive issued and tag_mask is zero then this is not NCQ */
 990        if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
 991                if (ap->link.active_tag == ATA_TAG_POISON)
 992                        tag = 0;
 993                else
 994                        tag = ap->link.active_tag;
 995                qc = ata_qc_from_tag(ap, tag);
 996
 997                /* DEV interrupt w/ no active qc? */
 998                if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
 999                        dev_err(ap->dev, "%s interrupt with no active qc "
1000                                "qc=%p\n", __func__, qc);
1001                        ap->ops->sff_check_status(ap);
1002                        handled = 1;
1003                        goto DONE;
1004                }
1005                status = ap->ops->sff_check_status(ap);
1006
1007                qc->ap->link.active_tag = tag;
1008                hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1009
1010                if (status & ATA_ERR) {
1011                        dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1012                        sata_dwc_qc_complete(ap, qc, 1);
1013                        handled = 1;
1014                        goto DONE;
1015                }
1016
1017                dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
1018                        __func__, get_prot_descript(qc->tf.protocol));
1019DRVSTILLBUSY:
1020                if (ata_is_dma(qc->tf.protocol)) {
1021                        /*
1022                         * Each DMA transaction produces 2 interrupts. The DMAC
1023                         * transfer complete interrupt and the SATA controller
1024                         * operation done interrupt. The command should be
1025                         * completed only after both interrupts are seen.
1026                         */
1027                        host_pvt.dma_interrupt_count++;
1028                        if (hsdevp->dma_pending[tag] == \
1029                                        SATA_DWC_DMA_PENDING_NONE) {
1030                                dev_err(ap->dev, "%s: DMA not pending "
1031                                        "intpr=0x%08x status=0x%08x pending"
1032                                        "=%d\n", __func__, intpr, status,
1033                                        hsdevp->dma_pending[tag]);
1034                        }
1035
1036                        if ((host_pvt.dma_interrupt_count % 2) == 0)
1037                                sata_dwc_dma_xfer_complete(ap, 1);
1038                } else if (ata_is_pio(qc->tf.protocol)) {
1039                        ata_sff_hsm_move(ap, qc, status, 0);
1040                        handled = 1;
1041                        goto DONE;
1042                } else {
1043                        if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1044                                goto DRVSTILLBUSY;
1045                }
1046
1047                handled = 1;
1048                goto DONE;
1049        }
1050
1051        /*
1052         * This is a NCQ command. At this point we need to figure out for which
1053         * tags we have gotten a completion interrupt.  One interrupt may serve
1054         * as completion for more than one operation when commands are queued
1055         * (NCQ).  We need to process each completed command.
1056         */
1057
1058         /* process completed commands */
1059        sactive = core_scr_read(SCR_ACTIVE);
1060        tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1061
1062        if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1063                                                        tag_mask > 1) {
1064                dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x  sactive_issued=0x%08x"
1065                        "tag_mask=0x%08x\n", __func__, sactive,
1066                        host_pvt.sata_dwc_sactive_issued, tag_mask);
1067        }
1068
1069        if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1070                                        (host_pvt.sata_dwc_sactive_issued)) {
1071                dev_warn(ap->dev, "Bad tag mask?  sactive=0x%08x "
1072                         "(host_pvt.sata_dwc_sactive_issued)=0x%08x  tag_mask"
1073                         "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1074                          tag_mask);
1075        }
1076
1077        /* read just to clear ... not bad if currently still busy */
1078        status = ap->ops->sff_check_status(ap);
1079        dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1080
1081        tag = 0;
1082        num_processed = 0;
1083        while (tag_mask) {
1084                num_processed++;
1085                while (!(tag_mask & 0x00000001)) {
1086                        tag++;
1087                        tag_mask <<= 1;
1088                }
1089
1090                tag_mask &= (~0x00000001);
1091                qc = ata_qc_from_tag(ap, tag);
1092
1093                /* To be picked up by completion functions */
1094                qc->ap->link.active_tag = tag;
1095                hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1096
1097                /* Let libata/scsi layers handle error */
1098                if (status & ATA_ERR) {
1099                        dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1100                                status);
1101                        sata_dwc_qc_complete(ap, qc, 1);
1102                        handled = 1;
1103                        goto DONE;
1104                }
1105
1106                /* Process completed command */
1107                dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1108                        get_prot_descript(qc->tf.protocol));
1109                if (ata_is_dma(qc->tf.protocol)) {
1110                        host_pvt.dma_interrupt_count++;
1111                        if (hsdevp->dma_pending[tag] == \
1112                                        SATA_DWC_DMA_PENDING_NONE)
1113                                dev_warn(ap->dev, "%s: DMA not pending?\n",
1114                                        __func__);
1115                        if ((host_pvt.dma_interrupt_count % 2) == 0)
1116                                sata_dwc_dma_xfer_complete(ap, 1);
1117                } else {
1118                        if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1119                                goto STILLBUSY;
1120                }
1121                continue;
1122
1123STILLBUSY:
1124                ap->stats.idle_irq++;
1125                dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1126                        ap->print_id);
1127        } /* while tag_mask */
1128
1129        /*
1130         * Check to see if any commands completed while we were processing our
1131         * initial set of completed commands (read status clears interrupts,
1132         * so we might miss a completed command interrupt if one came in while
1133         * we were processing --we read status as part of processing a completed
1134         * command).
1135         */
1136        sactive2 = core_scr_read(SCR_ACTIVE);
1137        if (sactive2 != sactive) {
1138                dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1139                        "=0x%x\n", sactive, sactive2);
1140        }
1141        handled = 1;
1142
1143DONE:
1144        spin_unlock_irqrestore(&host->lock, flags);
1145        return IRQ_RETVAL(handled);
1146}
1147
1148static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1149{
1150        struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1151
1152        if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1153                out_le32(&(hsdev->sata_dwc_regs->dmacr),
1154                         SATA_DWC_DMACR_RX_CLEAR(
1155                                 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1156        } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1157                out_le32(&(hsdev->sata_dwc_regs->dmacr),
1158                         SATA_DWC_DMACR_TX_CLEAR(
1159                                 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1160        } else {
1161                /*
1162                 * This should not happen, it indicates the driver is out of
1163                 * sync.  If it does happen, clear dmacr anyway.
1164                 */
1165                dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1166                        "TX DMA not pending tag=0x%02x pending=%d"
1167                        " dmacr: 0x%08x\n", __func__, tag,
1168                        hsdevp->dma_pending[tag],
1169                        in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1170                out_le32(&(hsdev->sata_dwc_regs->dmacr),
1171                        SATA_DWC_DMACR_TXRXCH_CLEAR);
1172        }
1173}
1174
1175static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1176{
1177        struct ata_queued_cmd *qc;
1178        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1179        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1180        u8 tag = 0;
1181
1182        tag = ap->link.active_tag;
1183        qc = ata_qc_from_tag(ap, tag);
1184        if (!qc) {
1185                dev_err(ap->dev, "failed to get qc");
1186                return;
1187        }
1188
1189#ifdef DEBUG_NCQ
1190        if (tag > 0) {
1191                dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1192                         "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1193                         get_dma_dir_descript(qc->dma_dir),
1194                         get_prot_descript(qc->tf.protocol),
1195                         in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1196        }
1197#endif
1198
1199        if (ata_is_dma(qc->tf.protocol)) {
1200                if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1201                        dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1202                                "pending dmacr: 0x%08x\n", __func__,
1203                                in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1204                }
1205
1206                hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1207                sata_dwc_qc_complete(ap, qc, check_status);
1208                ap->link.active_tag = ATA_TAG_POISON;
1209        } else {
1210                sata_dwc_qc_complete(ap, qc, check_status);
1211        }
1212}
1213
1214static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1215                                u32 check_status)
1216{
1217        u8 status = 0;
1218        u32 mask = 0x0;
1219        u8 tag = qc->tag;
1220        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1221        host_pvt.sata_dwc_sactive_queued = 0;
1222        dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1223
1224        if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1225                dev_err(ap->dev, "TX DMA PENDING\n");
1226        else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1227                dev_err(ap->dev, "RX DMA PENDING\n");
1228        dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1229                " protocol=%d\n", qc->tf.command, status, ap->print_id,
1230                 qc->tf.protocol);
1231
1232        /* clear active bit */
1233        mask = (~(qcmd_tag_to_mask(tag)));
1234        host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1235                                                & mask;
1236        host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1237                                                & mask;
1238        ata_qc_complete(qc);
1239        return 0;
1240}
1241
1242static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1243{
1244        /* Enable selective interrupts by setting the interrupt maskregister*/
1245        out_le32(&hsdev->sata_dwc_regs->intmr,
1246                 SATA_DWC_INTMR_ERRM |
1247                 SATA_DWC_INTMR_NEWFPM |
1248                 SATA_DWC_INTMR_PMABRTM |
1249                 SATA_DWC_INTMR_DMATM);
1250        /*
1251         * Unmask the error bits that should trigger an error interrupt by
1252         * setting the error mask register.
1253         */
1254        out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1255
1256        dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1257                 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1258                in_le32(&hsdev->sata_dwc_regs->errmr));
1259}
1260
1261static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1262{
1263        port->cmd_addr = (void *)base + 0x00;
1264        port->data_addr = (void *)base + 0x00;
1265
1266        port->error_addr = (void *)base + 0x04;
1267        port->feature_addr = (void *)base + 0x04;
1268
1269        port->nsect_addr = (void *)base + 0x08;
1270
1271        port->lbal_addr = (void *)base + 0x0c;
1272        port->lbam_addr = (void *)base + 0x10;
1273        port->lbah_addr = (void *)base + 0x14;
1274
1275        port->device_addr = (void *)base + 0x18;
1276        port->command_addr = (void *)base + 0x1c;
1277        port->status_addr = (void *)base + 0x1c;
1278
1279        port->altstatus_addr = (void *)base + 0x20;
1280        port->ctl_addr = (void *)base + 0x20;
1281}
1282
1283/*
1284 * Function : sata_dwc_port_start
1285 * arguments : struct ata_ioports *port
1286 * Return value : returns 0 if success, error code otherwise
1287 * This function allocates the scatter gather LLI table for AHB DMA
1288 */
1289static int sata_dwc_port_start(struct ata_port *ap)
1290{
1291        int err = 0;
1292        struct sata_dwc_device *hsdev;
1293        struct sata_dwc_device_port *hsdevp = NULL;
1294        struct device *pdev;
1295        int i;
1296
1297        hsdev = HSDEV_FROM_AP(ap);
1298
1299        dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1300
1301        hsdev->host = ap->host;
1302        pdev = ap->host->dev;
1303        if (!pdev) {
1304                dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1305                err = -ENODEV;
1306                goto CLEANUP;
1307        }
1308
1309        /* Allocate Port Struct */
1310        hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1311        if (!hsdevp) {
1312                dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1313                err = -ENOMEM;
1314                goto CLEANUP;
1315        }
1316        hsdevp->hsdev = hsdev;
1317
1318        for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1319                hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1320
1321        ap->bmdma_prd = 0;      /* set these so libata doesn't use them */
1322        ap->bmdma_prd_dma = 0;
1323
1324        /*
1325         * DMA - Assign scatter gather LLI table. We can't use the libata
1326         * version since it's PRD is IDE PCI specific.
1327         */
1328        for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1329                hsdevp->llit[i] = dma_alloc_coherent(pdev,
1330                                                     SATA_DWC_DMAC_LLI_TBL_SZ,
1331                                                     &(hsdevp->llit_dma[i]),
1332                                                     GFP_ATOMIC);
1333                if (!hsdevp->llit[i]) {
1334                        dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1335                                 __func__);
1336                        err = -ENOMEM;
1337                        goto CLEANUP_ALLOC;
1338                }
1339        }
1340
1341        if (ap->port_no == 0)  {
1342                dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1343                        __func__);
1344                out_le32(&hsdev->sata_dwc_regs->dmacr,
1345                         SATA_DWC_DMACR_TXRXCH_CLEAR);
1346
1347                dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1348                         __func__);
1349                out_le32(&hsdev->sata_dwc_regs->dbtsr,
1350                         (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1351                          SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1352        }
1353
1354        /* Clear any error bits before libata starts issuing commands */
1355        clear_serror();
1356        ap->private_data = hsdevp;
1357        dev_dbg(ap->dev, "%s: done\n", __func__);
1358        return 0;
1359
1360CLEANUP_ALLOC:
1361        kfree(hsdevp);
1362CLEANUP:
1363        dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
1364        return err;
1365}
1366
1367static void sata_dwc_port_stop(struct ata_port *ap)
1368{
1369        int i;
1370        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1371        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1372
1373        dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1374
1375        if (hsdevp && hsdev) {
1376                /* deallocate LLI table */
1377                for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1378                        dma_free_coherent(ap->host->dev,
1379                                          SATA_DWC_DMAC_LLI_TBL_SZ,
1380                                         hsdevp->llit[i], hsdevp->llit_dma[i]);
1381                }
1382
1383                kfree(hsdevp);
1384        }
1385        ap->private_data = NULL;
1386}
1387
1388/*
1389 * Function : sata_dwc_exec_command_by_tag
1390 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1391 * Return value : None
1392 * This function keeps track of individual command tag ids and calls
1393 * ata_exec_command in libata
1394 */
1395static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1396                                         struct ata_taskfile *tf,
1397                                         u8 tag, u32 cmd_issued)
1398{
1399        unsigned long flags;
1400        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1401
1402        dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1403                ata_get_cmd_descript(tf->command), tag);
1404
1405        spin_lock_irqsave(&ap->host->lock, flags);
1406        hsdevp->cmd_issued[tag] = cmd_issued;
1407        spin_unlock_irqrestore(&ap->host->lock, flags);
1408        /*
1409         * Clear SError before executing a new command.
1410         * sata_dwc_scr_write and read can not be used here. Clearing the PM
1411         * managed SError register for the disk needs to be done before the
1412         * task file is loaded.
1413         */
1414        clear_serror();
1415        ata_sff_exec_command(ap, tf);
1416}
1417
1418static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1419{
1420        sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1421                                     SATA_DWC_CMD_ISSUED_PEND);
1422}
1423
1424static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1425{
1426        u8 tag = qc->tag;
1427
1428        if (ata_is_ncq(qc->tf.protocol)) {
1429                dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1430                        __func__, qc->ap->link.sactive, tag);
1431        } else {
1432                tag = 0;
1433        }
1434        sata_dwc_bmdma_setup_by_tag(qc, tag);
1435}
1436
1437static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1438{
1439        int start_dma;
1440        u32 reg, dma_chan;
1441        struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1442        struct ata_port *ap = qc->ap;
1443        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1444        int dir = qc->dma_dir;
1445        dma_chan = hsdevp->dma_chan[tag];
1446
1447        if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1448                start_dma = 1;
1449                if (dir == DMA_TO_DEVICE)
1450                        hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1451                else
1452                        hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1453        } else {
1454                dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1455                        "(tag=%d) DMA NOT started\n", __func__,
1456                        hsdevp->cmd_issued[tag], tag);
1457                start_dma = 0;
1458        }
1459
1460        dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1461                "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1462                get_dma_dir_descript(qc->dma_dir), start_dma);
1463        sata_dwc_tf_dump(&(qc->tf));
1464
1465        if (start_dma) {
1466                reg = core_scr_read(SCR_ERROR);
1467                if (reg & SATA_DWC_SERROR_ERR_BITS) {
1468                        dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1469                                __func__, reg);
1470                }
1471
1472                if (dir == DMA_TO_DEVICE)
1473                        out_le32(&hsdev->sata_dwc_regs->dmacr,
1474                                SATA_DWC_DMACR_TXCHEN);
1475                else
1476                        out_le32(&hsdev->sata_dwc_regs->dmacr,
1477                                SATA_DWC_DMACR_RXCHEN);
1478
1479                /* Enable AHB DMA transfer on the specified channel */
1480                dma_dwc_xfer_start(dma_chan);
1481        }
1482}
1483
1484static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1485{
1486        u8 tag = qc->tag;
1487
1488        if (ata_is_ncq(qc->tf.protocol)) {
1489                dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1490                        __func__, qc->ap->link.sactive, tag);
1491        } else {
1492                tag = 0;
1493        }
1494        dev_dbg(qc->ap->dev, "%s\n", __func__);
1495        sata_dwc_bmdma_start_by_tag(qc, tag);
1496}
1497
1498/*
1499 * Function : sata_dwc_qc_prep_by_tag
1500 * arguments : ata_queued_cmd *qc, u8 tag
1501 * Return value : None
1502 * qc_prep for a particular queued command based on tag
1503 */
1504static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1505{
1506        struct scatterlist *sg = qc->sg;
1507        struct ata_port *ap = qc->ap;
1508        int dma_chan;
1509        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1510        struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1511
1512        dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1513                __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
1514                 qc->n_elem);
1515
1516        dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1517                                      hsdevp->llit_dma[tag],
1518                                      (void *__iomem)(&hsdev->sata_dwc_regs->\
1519                                      dmadr), qc->dma_dir);
1520        if (dma_chan < 0) {
1521                dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1522                        __func__, dma_chan);
1523                return;
1524        }
1525        hsdevp->dma_chan[tag] = dma_chan;
1526}
1527
1528static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1529{
1530        u32 sactive;
1531        u8 tag = qc->tag;
1532        struct ata_port *ap = qc->ap;
1533
1534#ifdef DEBUG_NCQ
1535        if (qc->tag > 0 || ap->link.sactive > 1)
1536                dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1537                         "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1538                         __func__, ap->print_id, qc->tf.command,
1539                         ata_get_cmd_descript(qc->tf.command),
1540                         qc->tag, get_prot_descript(qc->tf.protocol),
1541                         ap->link.active_tag, ap->link.sactive);
1542#endif
1543
1544        if (!ata_is_ncq(qc->tf.protocol))
1545                tag = 0;
1546        sata_dwc_qc_prep_by_tag(qc, tag);
1547
1548        if (ata_is_ncq(qc->tf.protocol)) {
1549                sactive = core_scr_read(SCR_ACTIVE);
1550                sactive |= (0x00000001 << tag);
1551                core_scr_write(SCR_ACTIVE, sactive);
1552
1553                dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1554                        "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1555                        sactive);
1556
1557                ap->ops->sff_tf_load(ap, &qc->tf);
1558                sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1559                                             SATA_DWC_CMD_ISSUED_PEND);
1560        } else {
1561                ata_sff_qc_issue(qc);
1562        }
1563        return 0;
1564}
1565
1566/*
1567 * Function : sata_dwc_qc_prep
1568 * arguments : ata_queued_cmd *qc
1569 * Return value : None
1570 * qc_prep for a particular queued command
1571 */
1572
1573static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1574{
1575        if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1576                return;
1577
1578#ifdef DEBUG_NCQ
1579        if (qc->tag > 0)
1580                dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1581                         __func__, qc->tag, qc->ap->link.active_tag);
1582
1583        return ;
1584#endif
1585}
1586
1587static void sata_dwc_error_handler(struct ata_port *ap)
1588{
1589        ata_sff_error_handler(ap);
1590}
1591
1592int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1593                        unsigned long deadline)
1594{
1595        struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1596        int ret;
1597
1598        ret = sata_sff_hardreset(link, class, deadline);
1599
1600        sata_dwc_enable_interrupts(hsdev);
1601
1602        /* Reconfigure the DMA control register */
1603        out_le32(&hsdev->sata_dwc_regs->dmacr,
1604                 SATA_DWC_DMACR_TXRXCH_CLEAR);
1605
1606        /* Reconfigure the DMA Burst Transaction Size register */
1607        out_le32(&hsdev->sata_dwc_regs->dbtsr,
1608                 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1609                 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1610
1611        return ret;
1612}
1613
1614/*
1615 * scsi mid-layer and libata interface structures
1616 */
1617static struct scsi_host_template sata_dwc_sht = {
1618        ATA_NCQ_SHT(DRV_NAME),
1619        /*
1620         * test-only: Currently this driver doesn't handle NCQ
1621         * correctly. We enable NCQ but set the queue depth to a
1622         * max of 1. This will get fixed in in a future release.
1623         */
1624        .sg_tablesize           = LIBATA_MAX_PRD,
1625        .can_queue              = ATA_DEF_QUEUE,        /* ATA_MAX_QUEUE */
1626        .dma_boundary           = ATA_DMA_BOUNDARY,
1627};
1628
1629static struct ata_port_operations sata_dwc_ops = {
1630        .inherits               = &ata_sff_port_ops,
1631
1632        .error_handler          = sata_dwc_error_handler,
1633        .hardreset              = sata_dwc_hardreset,
1634
1635        .qc_prep                = sata_dwc_qc_prep,
1636        .qc_issue               = sata_dwc_qc_issue,
1637
1638        .scr_read               = sata_dwc_scr_read,
1639        .scr_write              = sata_dwc_scr_write,
1640
1641        .port_start             = sata_dwc_port_start,
1642        .port_stop              = sata_dwc_port_stop,
1643
1644        .bmdma_setup            = sata_dwc_bmdma_setup,
1645        .bmdma_start            = sata_dwc_bmdma_start,
1646};
1647
1648static const struct ata_port_info sata_dwc_port_info[] = {
1649        {
1650                .flags          = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1651                .pio_mask       = ATA_PIO4,
1652                .udma_mask      = ATA_UDMA6,
1653                .port_ops       = &sata_dwc_ops,
1654        },
1655};
1656
1657static int sata_dwc_probe(struct platform_device *ofdev)
1658{
1659        struct sata_dwc_device *hsdev;
1660        u32 idr, versionr;
1661        char *ver = (char *)&versionr;
1662        u8 *base = NULL;
1663        int err = 0;
1664        int irq, rc;
1665        struct ata_host *host;
1666        struct ata_port_info pi = sata_dwc_port_info[0];
1667        const struct ata_port_info *ppi[] = { &pi, NULL };
1668        struct device_node *np = ofdev->dev.of_node;
1669        u32 dma_chan;
1670
1671        /* Allocate DWC SATA device */
1672        hsdev = kzalloc(sizeof(*hsdev), GFP_KERNEL);
1673        if (hsdev == NULL) {
1674                dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1675                err = -ENOMEM;
1676                goto error;
1677        }
1678
1679        if (of_property_read_u32(np, "dma-channel", &dma_chan)) {
1680                dev_warn(&ofdev->dev, "no dma-channel property set."
1681                         " Use channel 0\n");
1682                dma_chan = 0;
1683        }
1684        host_pvt.dma_channel = dma_chan;
1685
1686        /* Ioremap SATA registers */
1687        base = of_iomap(ofdev->dev.of_node, 0);
1688        if (!base) {
1689                dev_err(&ofdev->dev, "ioremap failed for SATA register"
1690                        " address\n");
1691                err = -ENODEV;
1692                goto error_kmalloc;
1693        }
1694        hsdev->reg_base = base;
1695        dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1696
1697        /* Synopsys DWC SATA specific Registers */
1698        hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1699
1700        /* Allocate and fill host */
1701        host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1702        if (!host) {
1703                dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1704                err = -ENOMEM;
1705                goto error_iomap;
1706        }
1707
1708        host->private_data = hsdev;
1709
1710        /* Setup port */
1711        host->ports[0]->ioaddr.cmd_addr = base;
1712        host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1713        host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1714        sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1715
1716        /* Read the ID and Version Registers */
1717        idr = in_le32(&hsdev->sata_dwc_regs->idr);
1718        versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1719        dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1720                   idr, ver[0], ver[1], ver[2]);
1721
1722        /* Get SATA DMA interrupt number */
1723        irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1724        if (irq == NO_IRQ) {
1725                dev_err(&ofdev->dev, "no SATA DMA irq\n");
1726                err = -ENODEV;
1727                goto error_out;
1728        }
1729
1730        /* Get physical SATA DMA register base address */
1731        host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1732        if (!(host_pvt.sata_dma_regs)) {
1733                dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1734                        " address\n");
1735                err = -ENODEV;
1736                goto error_out;
1737        }
1738
1739        /* Save dev for later use in dev_xxx() routines */
1740        host_pvt.dwc_dev = &ofdev->dev;
1741
1742        /* Initialize AHB DMAC */
1743        dma_dwc_init(hsdev, irq);
1744
1745        /* Enable SATA Interrupts */
1746        sata_dwc_enable_interrupts(hsdev);
1747
1748        /* Get SATA interrupt number */
1749        irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1750        if (irq == NO_IRQ) {
1751                dev_err(&ofdev->dev, "no SATA DMA irq\n");
1752                err = -ENODEV;
1753                goto error_out;
1754        }
1755
1756        /*
1757         * Now, register with libATA core, this will also initiate the
1758         * device discovery process, invoking our port_start() handler &
1759         * error_handler() to execute a dummy Softreset EH session
1760         */
1761        rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1762
1763        if (rc != 0)
1764                dev_err(&ofdev->dev, "failed to activate host");
1765
1766        dev_set_drvdata(&ofdev->dev, host);
1767        return 0;
1768
1769error_out:
1770        /* Free SATA DMA resources */
1771        dma_dwc_exit(hsdev);
1772
1773error_iomap:
1774        iounmap(base);
1775error_kmalloc:
1776        kfree(hsdev);
1777error:
1778        return err;
1779}
1780
1781static int sata_dwc_remove(struct platform_device *ofdev)
1782{
1783        struct device *dev = &ofdev->dev;
1784        struct ata_host *host = dev_get_drvdata(dev);
1785        struct sata_dwc_device *hsdev = host->private_data;
1786
1787        ata_host_detach(host);
1788        dev_set_drvdata(dev, NULL);
1789
1790        /* Free SATA DMA resources */
1791        dma_dwc_exit(hsdev);
1792
1793        iounmap(hsdev->reg_base);
1794        kfree(hsdev);
1795        kfree(host);
1796        dev_dbg(&ofdev->dev, "done\n");
1797        return 0;
1798}
1799
1800static const struct of_device_id sata_dwc_match[] = {
1801        { .compatible = "amcc,sata-460ex", },
1802        {}
1803};
1804MODULE_DEVICE_TABLE(of, sata_dwc_match);
1805
1806static struct platform_driver sata_dwc_driver = {
1807        .driver = {
1808                .name = DRV_NAME,
1809                .owner = THIS_MODULE,
1810                .of_match_table = sata_dwc_match,
1811        },
1812        .probe = sata_dwc_probe,
1813        .remove = sata_dwc_remove,
1814};
1815
1816module_platform_driver(sata_dwc_driver);
1817
1818MODULE_LICENSE("GPL");
1819MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1820MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1821MODULE_VERSION(DRV_VERSION);
1822
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