linux/drivers/ata/pata_pdc2027x.c
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   1/*
   2 *  Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
   3 *
   4 *  This program is free software; you can redistribute it and/or
   5 *  modify it under the terms of the GNU General Public License
   6 *  as published by the Free Software Foundation; either version
   7 *  2 of the License, or (at your option) any later version.
   8 *
   9 *  Ported to libata by:
  10 *  Albert Lee <albertcc@tw.ibm.com> IBM Corporation
  11 *
  12 *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  13 *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14 *
  15 *  Author: Frank Tiernan (frankt@promise.com)
  16 *  Released under terms of General Public License
  17 *
  18 *
  19 *  libata documentation is available via 'make {ps|pdf}docs',
  20 *  as Documentation/DocBook/libata.*
  21 *
  22 *  Hardware information only available under NDA.
  23 *
  24 */
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/pci.h>
  28#include <linux/init.h>
  29#include <linux/blkdev.h>
  30#include <linux/delay.h>
  31#include <linux/device.h>
  32#include <scsi/scsi.h>
  33#include <scsi/scsi_host.h>
  34#include <scsi/scsi_cmnd.h>
  35#include <linux/libata.h>
  36
  37#define DRV_NAME        "pata_pdc2027x"
  38#define DRV_VERSION     "1.0"
  39#undef PDC_DEBUG
  40
  41#ifdef PDC_DEBUG
  42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
  43#else
  44#define PDPRINTK(fmt, args...)
  45#endif
  46
  47enum {
  48        PDC_MMIO_BAR            = 5,
  49
  50        PDC_UDMA_100            = 0,
  51        PDC_UDMA_133            = 1,
  52
  53        PDC_100_MHZ             = 100000000,
  54        PDC_133_MHZ             = 133333333,
  55
  56        PDC_SYS_CTL             = 0x1100,
  57        PDC_ATA_CTL             = 0x1104,
  58        PDC_GLOBAL_CTL          = 0x1108,
  59        PDC_CTCR0               = 0x110C,
  60        PDC_CTCR1               = 0x1110,
  61        PDC_BYTE_COUNT          = 0x1120,
  62        PDC_PLL_CTL             = 0x1202,
  63};
  64
  65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  66static int pdc2027x_reinit_one(struct pci_dev *pdev);
  67static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
  68static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
  69static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
  70static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
  71static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
  72static int pdc2027x_cable_detect(struct ata_port *ap);
  73static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
  74
  75/*
  76 * ATA Timing Tables based on 133MHz controller clock.
  77 * These tables are only used when the controller is in 133MHz clock.
  78 * If the controller is in 100MHz clock, the ASIC hardware will
  79 * set the timing registers automatically when "set feature" command
  80 * is issued to the device. However, if the controller clock is 133MHz,
  81 * the following tables must be used.
  82 */
  83static struct pdc2027x_pio_timing {
  84        u8 value0, value1, value2;
  85} pdc2027x_pio_timing_tbl [] = {
  86        { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
  87        { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
  88        { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
  89        { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
  90        { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
  91};
  92
  93static struct pdc2027x_mdma_timing {
  94        u8 value0, value1;
  95} pdc2027x_mdma_timing_tbl [] = {
  96        { 0xdf, 0x5f }, /* MDMA mode 0 */
  97        { 0x6b, 0x27 }, /* MDMA mode 1 */
  98        { 0x69, 0x25 }, /* MDMA mode 2 */
  99};
 100
 101static struct pdc2027x_udma_timing {
 102        u8 value0, value1, value2;
 103} pdc2027x_udma_timing_tbl [] = {
 104        { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
 105        { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
 106        { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
 107        { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
 108        { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
 109        { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
 110        { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
 111};
 112
 113static const struct pci_device_id pdc2027x_pci_tbl[] = {
 114        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
 115        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
 116        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
 117        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
 118        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
 119        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
 120        { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
 121
 122        { }     /* terminate list */
 123};
 124
 125static struct pci_driver pdc2027x_pci_driver = {
 126        .name                   = DRV_NAME,
 127        .id_table               = pdc2027x_pci_tbl,
 128        .probe                  = pdc2027x_init_one,
 129        .remove                 = ata_pci_remove_one,
 130#ifdef CONFIG_PM
 131        .suspend                = ata_pci_device_suspend,
 132        .resume                 = pdc2027x_reinit_one,
 133#endif
 134};
 135
 136static struct scsi_host_template pdc2027x_sht = {
 137        ATA_BMDMA_SHT(DRV_NAME),
 138};
 139
 140static struct ata_port_operations pdc2027x_pata100_ops = {
 141        .inherits               = &ata_bmdma_port_ops,
 142        .check_atapi_dma        = pdc2027x_check_atapi_dma,
 143        .cable_detect           = pdc2027x_cable_detect,
 144        .prereset               = pdc2027x_prereset,
 145};
 146
 147static struct ata_port_operations pdc2027x_pata133_ops = {
 148        .inherits               = &pdc2027x_pata100_ops,
 149        .mode_filter            = pdc2027x_mode_filter,
 150        .set_piomode            = pdc2027x_set_piomode,
 151        .set_dmamode            = pdc2027x_set_dmamode,
 152        .set_mode               = pdc2027x_set_mode,
 153};
 154
 155static struct ata_port_info pdc2027x_port_info[] = {
 156        /* PDC_UDMA_100 */
 157        {
 158                .flags          = ATA_FLAG_SLAVE_POSS,
 159                .pio_mask       = ATA_PIO4,
 160                .mwdma_mask     = ATA_MWDMA2,
 161                .udma_mask      = ATA_UDMA5,
 162                .port_ops       = &pdc2027x_pata100_ops,
 163        },
 164        /* PDC_UDMA_133 */
 165        {
 166                .flags          = ATA_FLAG_SLAVE_POSS,
 167                .pio_mask       = ATA_PIO4,
 168                .mwdma_mask     = ATA_MWDMA2,
 169                .udma_mask      = ATA_UDMA6,
 170                .port_ops       = &pdc2027x_pata133_ops,
 171        },
 172};
 173
 174MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
 175MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
 176MODULE_LICENSE("GPL");
 177MODULE_VERSION(DRV_VERSION);
 178MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
 179
 180/**
 181 *      port_mmio - Get the MMIO address of PDC2027x extended registers
 182 *      @ap: Port
 183 *      @offset: offset from mmio base
 184 */
 185static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
 186{
 187        return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
 188}
 189
 190/**
 191 *      dev_mmio - Get the MMIO address of PDC2027x extended registers
 192 *      @ap: Port
 193 *      @adev: device
 194 *      @offset: offset from mmio base
 195 */
 196static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
 197{
 198        u8 adj = (adev->devno) ? 0x08 : 0x00;
 199        return port_mmio(ap, offset) + adj;
 200}
 201
 202/**
 203 *      pdc2027x_pata_cable_detect - Probe host controller cable detect info
 204 *      @ap: Port for which cable detect info is desired
 205 *
 206 *      Read 80c cable indicator from Promise extended register.
 207 *      This register is latched when the system is reset.
 208 *
 209 *      LOCKING:
 210 *      None (inherited from caller).
 211 */
 212static int pdc2027x_cable_detect(struct ata_port *ap)
 213{
 214        u32 cgcr;
 215
 216        /* check cable detect results */
 217        cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
 218        if (cgcr & (1 << 26))
 219                goto cbl40;
 220
 221        PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
 222
 223        return ATA_CBL_PATA80;
 224cbl40:
 225        printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
 226        return ATA_CBL_PATA40;
 227}
 228
 229/**
 230 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
 231 * @ap: Port to check
 232 */
 233static inline int pdc2027x_port_enabled(struct ata_port *ap)
 234{
 235        return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
 236}
 237
 238/**
 239 *      pdc2027x_prereset - prereset for PATA host controller
 240 *      @link: Target link
 241 *      @deadline: deadline jiffies for the operation
 242 *
 243 *      Probeinit including cable detection.
 244 *
 245 *      LOCKING:
 246 *      None (inherited from caller).
 247 */
 248
 249static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
 250{
 251        /* Check whether port enabled */
 252        if (!pdc2027x_port_enabled(link->ap))
 253                return -ENOENT;
 254        return ata_sff_prereset(link, deadline);
 255}
 256
 257/**
 258 *      pdc2720x_mode_filter    -       mode selection filter
 259 *      @adev: ATA device
 260 *      @mask: list of modes proposed
 261 *
 262 *      Block UDMA on devices that cause trouble with this controller.
 263 */
 264
 265static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
 266{
 267        unsigned char model_num[ATA_ID_PROD_LEN + 1];
 268        struct ata_device *pair = ata_dev_pair(adev);
 269
 270        if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
 271                return mask;
 272
 273        /* Check for slave of a Maxtor at UDMA6 */
 274        ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
 275                          ATA_ID_PROD_LEN + 1);
 276        /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
 277        if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
 278                mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
 279
 280        return mask;
 281}
 282
 283/**
 284 *      pdc2027x_set_piomode - Initialize host controller PATA PIO timings
 285 *      @ap: Port to configure
 286 *      @adev: um
 287 *
 288 *      Set PIO mode for device.
 289 *
 290 *      LOCKING:
 291 *      None (inherited from caller).
 292 */
 293
 294static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 295{
 296        unsigned int pio = adev->pio_mode - XFER_PIO_0;
 297        u32 ctcr0, ctcr1;
 298
 299        PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
 300
 301        /* Sanity check */
 302        if (pio > 4) {
 303                printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
 304                return;
 305
 306        }
 307
 308        /* Set the PIO timing registers using value table for 133MHz */
 309        PDPRINTK("Set pio regs... \n");
 310
 311        ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 312        ctcr0 &= 0xffff0000;
 313        ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
 314                (pdc2027x_pio_timing_tbl[pio].value1 << 8);
 315        iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 316
 317        ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 318        ctcr1 &= 0x00ffffff;
 319        ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
 320        iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 321
 322        PDPRINTK("Set pio regs done\n");
 323
 324        PDPRINTK("Set to pio mode[%u] \n", pio);
 325}
 326
 327/**
 328 *      pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
 329 *      @ap: Port to configure
 330 *      @adev: um
 331 *
 332 *      Set UDMA mode for device.
 333 *
 334 *      LOCKING:
 335 *      None (inherited from caller).
 336 */
 337static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 338{
 339        unsigned int dma_mode = adev->dma_mode;
 340        u32 ctcr0, ctcr1;
 341
 342        if ((dma_mode >= XFER_UDMA_0) &&
 343           (dma_mode <= XFER_UDMA_6)) {
 344                /* Set the UDMA timing registers with value table for 133MHz */
 345                unsigned int udma_mode = dma_mode & 0x07;
 346
 347                if (dma_mode == XFER_UDMA_2) {
 348                        /*
 349                         * Turn off tHOLD.
 350                         * If tHOLD is '1', the hardware will add half clock for data hold time.
 351                         * This code segment seems to be no effect. tHOLD will be overwritten below.
 352                         */
 353                        ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 354                        iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
 355                }
 356
 357                PDPRINTK("Set udma regs... \n");
 358
 359                ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
 360                ctcr1 &= 0xff000000;
 361                ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
 362                        (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
 363                        (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
 364                iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
 365
 366                PDPRINTK("Set udma regs done\n");
 367
 368                PDPRINTK("Set to udma mode[%u] \n", udma_mode);
 369
 370        } else  if ((dma_mode >= XFER_MW_DMA_0) &&
 371                   (dma_mode <= XFER_MW_DMA_2)) {
 372                /* Set the MDMA timing registers with value table for 133MHz */
 373                unsigned int mdma_mode = dma_mode & 0x07;
 374
 375                PDPRINTK("Set mdma regs... \n");
 376                ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
 377
 378                ctcr0 &= 0x0000ffff;
 379                ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
 380                        (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
 381
 382                iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
 383                PDPRINTK("Set mdma regs done\n");
 384
 385                PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
 386        } else {
 387                printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
 388        }
 389}
 390
 391/**
 392 *      pdc2027x_set_mode - Set the timing registers back to correct values.
 393 *      @link: link to configure
 394 *      @r_failed: Returned device for failure
 395 *
 396 *      The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
 397 *      automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
 398 *      This function overwrites the possibly incorrect values set by the hardware to be correct.
 399 */
 400static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
 401{
 402        struct ata_port *ap = link->ap;
 403        struct ata_device *dev;
 404        int rc;
 405
 406        rc = ata_do_set_mode(link, r_failed);
 407        if (rc < 0)
 408                return rc;
 409
 410        ata_for_each_dev(dev, link, ENABLED) {
 411                pdc2027x_set_piomode(ap, dev);
 412
 413                /*
 414                 * Enable prefetch if the device support PIO only.
 415                 */
 416                if (dev->xfer_shift == ATA_SHIFT_PIO) {
 417                        u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
 418                        ctcr1 |= (1 << 25);
 419                        iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
 420
 421                        PDPRINTK("Turn on prefetch\n");
 422                } else {
 423                        pdc2027x_set_dmamode(ap, dev);
 424                }
 425        }
 426        return 0;
 427}
 428
 429/**
 430 *      pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
 431 *      @qc: Metadata associated with taskfile to check
 432 *
 433 *      LOCKING:
 434 *      None (inherited from caller).
 435 *
 436 *      RETURNS: 0 when ATAPI DMA can be used
 437 *               1 otherwise
 438 */
 439static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
 440{
 441        struct scsi_cmnd *cmd = qc->scsicmd;
 442        u8 *scsicmd = cmd->cmnd;
 443        int rc = 1; /* atapi dma off by default */
 444
 445        /*
 446         * This workaround is from Promise's GPL driver.
 447         * If ATAPI DMA is used for commands not in the
 448         * following white list, say MODE_SENSE and REQUEST_SENSE,
 449         * pdc2027x might hit the irq lost problem.
 450         */
 451        switch (scsicmd[0]) {
 452        case READ_10:
 453        case WRITE_10:
 454        case READ_12:
 455        case WRITE_12:
 456        case READ_6:
 457        case WRITE_6:
 458        case 0xad: /* READ_DVD_STRUCTURE */
 459        case 0xbe: /* READ_CD */
 460                /* ATAPI DMA is ok */
 461                rc = 0;
 462                break;
 463        default:
 464                ;
 465        }
 466
 467        return rc;
 468}
 469
 470/**
 471 * pdc_read_counter - Read the ctr counter
 472 * @host: target ATA host
 473 */
 474
 475static long pdc_read_counter(struct ata_host *host)
 476{
 477        void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 478        long counter;
 479        int retry = 1;
 480        u32 bccrl, bccrh, bccrlv, bccrhv;
 481
 482retry:
 483        bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
 484        bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 485
 486        /* Read the counter values again for verification */
 487        bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
 488        bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
 489
 490        counter = (bccrh << 15) | bccrl;
 491
 492        PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
 493        PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
 494
 495        /*
 496         * The 30-bit decreasing counter are read by 2 pieces.
 497         * Incorrect value may be read when both bccrh and bccrl are changing.
 498         * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
 499         */
 500        if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
 501                retry--;
 502                PDPRINTK("rereading counter\n");
 503                goto retry;
 504        }
 505
 506        return counter;
 507}
 508
 509/**
 510 * adjust_pll - Adjust the PLL input clock in Hz.
 511 *
 512 * @pdc_controller: controller specific information
 513 * @host: target ATA host
 514 * @pll_clock: The input of PLL in HZ
 515 */
 516static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
 517{
 518        void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 519        u16 pll_ctl;
 520        long pll_clock_khz = pll_clock / 1000;
 521        long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
 522        long ratio = pout_required / pll_clock_khz;
 523        int F, R;
 524
 525        /* Sanity check */
 526        if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
 527                printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
 528                return;
 529        }
 530
 531#ifdef PDC_DEBUG
 532        PDPRINTK("pout_required is %ld\n", pout_required);
 533
 534        /* Show the current clock value of PLL control register
 535         * (maybe already configured by the firmware)
 536         */
 537        pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 538
 539        PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 540#endif
 541
 542        /*
 543         * Calculate the ratio of F, R and OD
 544         * POUT = (F + 2) / (( R + 2) * NO)
 545         */
 546        if (ratio < 8600L) { /* 8.6x */
 547                /* Using NO = 0x01, R = 0x0D */
 548                R = 0x0d;
 549        } else if (ratio < 12900L) { /* 12.9x */
 550                /* Using NO = 0x01, R = 0x08 */
 551                R = 0x08;
 552        } else if (ratio < 16100L) { /* 16.1x */
 553                /* Using NO = 0x01, R = 0x06 */
 554                R = 0x06;
 555        } else if (ratio < 64000L) { /* 64x */
 556                R = 0x00;
 557        } else {
 558                /* Invalid ratio */
 559                printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
 560                return;
 561        }
 562
 563        F = (ratio * (R+2)) / 1000 - 2;
 564
 565        if (unlikely(F < 0 || F > 127)) {
 566                /* Invalid F */
 567                printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
 568                return;
 569        }
 570
 571        PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
 572
 573        pll_ctl = (R << 8) | F;
 574
 575        PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
 576
 577        iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
 578        ioread16(mmio_base + PDC_PLL_CTL); /* flush */
 579
 580        /* Wait the PLL circuit to be stable */
 581        mdelay(30);
 582
 583#ifdef PDC_DEBUG
 584        /*
 585         *  Show the current clock value of PLL control register
 586         * (maybe configured by the firmware)
 587         */
 588        pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
 589
 590        PDPRINTK("pll_ctl[%X]\n", pll_ctl);
 591#endif
 592
 593        return;
 594}
 595
 596/**
 597 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 598 * @host: target ATA host
 599 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
 600 *     Half of the PCI clock.
 601 */
 602static long pdc_detect_pll_input_clock(struct ata_host *host)
 603{
 604        void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
 605        u32 scr;
 606        long start_count, end_count;
 607        struct timeval start_time, end_time;
 608        long pll_clock, usec_elapsed;
 609
 610        /* Start the test mode */
 611        scr = ioread32(mmio_base + PDC_SYS_CTL);
 612        PDPRINTK("scr[%X]\n", scr);
 613        iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
 614        ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 615
 616        /* Read current counter value */
 617        start_count = pdc_read_counter(host);
 618        do_gettimeofday(&start_time);
 619
 620        /* Let the counter run for 100 ms. */
 621        mdelay(100);
 622
 623        /* Read the counter values again */
 624        end_count = pdc_read_counter(host);
 625        do_gettimeofday(&end_time);
 626
 627        /* Stop the test mode */
 628        scr = ioread32(mmio_base + PDC_SYS_CTL);
 629        PDPRINTK("scr[%X]\n", scr);
 630        iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
 631        ioread32(mmio_base + PDC_SYS_CTL); /* flush */
 632
 633        /* calculate the input clock in Hz */
 634        usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
 635                (end_time.tv_usec - start_time.tv_usec);
 636
 637        pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
 638                (100000000 / usec_elapsed);
 639
 640        PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
 641        PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
 642
 643        return pll_clock;
 644}
 645
 646/**
 647 * pdc_hardware_init - Initialize the hardware.
 648 * @host: target ATA host
 649 * @board_idx: board identifier
 650 */
 651static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
 652{
 653        long pll_clock;
 654
 655        /*
 656         * Detect PLL input clock rate.
 657         * On some system, where PCI bus is running at non-standard clock rate.
 658         * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
 659         * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
 660         */
 661        pll_clock = pdc_detect_pll_input_clock(host);
 662
 663        dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
 664
 665        /* Adjust PLL control register */
 666        pdc_adjust_pll(host, pll_clock, board_idx);
 667
 668        return 0;
 669}
 670
 671/**
 672 * pdc_ata_setup_port - setup the mmio address
 673 * @port: ata ioports to setup
 674 * @base: base address
 675 */
 676static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 677{
 678        port->cmd_addr          =
 679        port->data_addr         = base;
 680        port->feature_addr      =
 681        port->error_addr        = base + 0x05;
 682        port->nsect_addr        = base + 0x0a;
 683        port->lbal_addr         = base + 0x0f;
 684        port->lbam_addr         = base + 0x10;
 685        port->lbah_addr         = base + 0x15;
 686        port->device_addr       = base + 0x1a;
 687        port->command_addr      =
 688        port->status_addr       = base + 0x1f;
 689        port->altstatus_addr    =
 690        port->ctl_addr          = base + 0x81a;
 691}
 692
 693/**
 694 * pdc2027x_init_one - PCI probe function
 695 * Called when an instance of PCI adapter is inserted.
 696 * This function checks whether the hardware is supported,
 697 * initialize hardware and register an instance of ata_host to
 698 * libata.  (implements struct pci_driver.probe() )
 699 *
 700 * @pdev: instance of pci_dev found
 701 * @ent:  matching entry in the id_tbl[]
 702 */
 703static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 704{
 705        static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
 706        static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
 707        unsigned int board_idx = (unsigned int) ent->driver_data;
 708        const struct ata_port_info *ppi[] =
 709                { &pdc2027x_port_info[board_idx], NULL };
 710        struct ata_host *host;
 711        void __iomem *mmio_base;
 712        int i, rc;
 713
 714        ata_print_version_once(&pdev->dev, DRV_VERSION);
 715
 716        /* alloc host */
 717        host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
 718        if (!host)
 719                return -ENOMEM;
 720
 721        /* acquire resources and fill host */
 722        rc = pcim_enable_device(pdev);
 723        if (rc)
 724                return rc;
 725
 726        rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
 727        if (rc)
 728                return rc;
 729        host->iomap = pcim_iomap_table(pdev);
 730
 731        rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 732        if (rc)
 733                return rc;
 734
 735        rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 736        if (rc)
 737                return rc;
 738
 739        mmio_base = host->iomap[PDC_MMIO_BAR];
 740
 741        for (i = 0; i < 2; i++) {
 742                struct ata_port *ap = host->ports[i];
 743
 744                pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
 745                ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
 746
 747                ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
 748                ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
 749        }
 750
 751        //pci_enable_intx(pdev);
 752
 753        /* initialize adapter */
 754        if (pdc_hardware_init(host, board_idx) != 0)
 755                return -EIO;
 756
 757        pci_set_master(pdev);
 758        return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 759                                 IRQF_SHARED, &pdc2027x_sht);
 760}
 761
 762#ifdef CONFIG_PM
 763static int pdc2027x_reinit_one(struct pci_dev *pdev)
 764{
 765        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 766        unsigned int board_idx;
 767        int rc;
 768
 769        rc = ata_pci_device_do_resume(pdev);
 770        if (rc)
 771                return rc;
 772
 773        if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
 774            pdev->device == PCI_DEVICE_ID_PROMISE_20270)
 775                board_idx = PDC_UDMA_100;
 776        else
 777                board_idx = PDC_UDMA_133;
 778
 779        if (pdc_hardware_init(host, board_idx))
 780                return -EIO;
 781
 782        ata_host_resume(host);
 783        return 0;
 784}
 785#endif
 786
 787module_pci_driver(pdc2027x_pci_driver);
 788
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