1config ARM 2 bool 3 default y 4 select ARCH_HAVE_CUSTOM_GPIO_H 5 select HAVE_AOUT 6 select HAVE_DMA_API_DEBUG 7 select HAVE_IDE if PCI || ISA || PCMCIA 8 select HAVE_DMA_ATTRS 9 select HAVE_DMA_CONTIGUOUS if MMU 10 select HAVE_MEMBLOCK 11 select RTC_LIB 12 select SYS_SUPPORTS_APM_EMULATION 13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 17 select HAVE_ARCH_KGDB 18 select HAVE_ARCH_TRACEHOOK 19 select HAVE_KPROBES if !XIP_KERNEL 20 select HAVE_KRETPROBES if (HAVE_KPROBES) 21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 26 select HAVE_GENERIC_DMA_COHERENT 27 select HAVE_KERNEL_GZIP 28 select HAVE_KERNEL_LZO 29 select HAVE_KERNEL_LZMA 30 select HAVE_KERNEL_XZ 31 select HAVE_IRQ_WORK 32 select HAVE_PERF_EVENTS 33 select PERF_USE_VMALLOC 34 select HAVE_REGS_AND_STACK_ACCESS_API 35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 36 select HAVE_C_RECORDMCOUNT 37 select HAVE_GENERIC_HARDIRQS 38 select HARDIRQS_SW_RESEND 39 select GENERIC_IRQ_PROBE 40 select GENERIC_IRQ_SHOW 41 select ARCH_WANT_IPC_PARSE_VERSION 42 select HARDIRQS_SW_RESEND 43 select CPU_PM if (SUSPEND || CPU_IDLE) 44 select GENERIC_PCI_IOMAP 45 select HAVE_BPF_JIT 46 select GENERIC_SMP_IDLE_THREAD 47 select KTIME_SCALAR 48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 49 select GENERIC_STRNCPY_FROM_USER 50 select GENERIC_STRNLEN_USER 51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN 52 help 53 The ARM series is a line of low-power-consumption RISC chip designs 54 licensed by ARM Ltd and targeted at embedded applications and 55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 56 manufactured, but legacy ARM-based PC hardware remains popular in 57 Europe. There is an ARM Linux project with a web page at 58 <http://www.arm.linux.org.uk/>. 59 60config ARM_HAS_SG_CHAIN 61 bool 62 63config NEED_SG_DMA_LENGTH 64 bool 65 66config ARM_DMA_USE_IOMMU 67 select NEED_SG_DMA_LENGTH 68 select ARM_HAS_SG_CHAIN 69 bool 70 71config HAVE_PWM 72 bool 73 74config MIGHT_HAVE_PCI 75 bool 76 77config SYS_SUPPORTS_APM_EMULATION 78 bool 79 80config GENERIC_GPIO 81 bool 82 83config HAVE_TCM 84 bool 85 select GENERIC_ALLOCATOR 86 87config HAVE_PROC_CPU 88 bool 89 90config NO_IOPORT 91 bool 92 93config EISA 94 bool 95 ---help--- 96 The Extended Industry Standard Architecture (EISA) bus was 97 developed as an open alternative to the IBM MicroChannel bus. 98 99 The EISA bus provided some of the features of the IBM MicroChannel 100 bus while maintaining backward compatibility with cards made for 101 the older ISA bus. The EISA bus saw limited use between 1988 and 102 1995 when it was made obsolete by the PCI bus. 103 104 Say Y here if you are building a kernel for an EISA-based machine. 105 106 Otherwise, say N. 107 108config SBUS 109 bool 110 111config STACKTRACE_SUPPORT 112 bool 113 default y 114 115config HAVE_LATENCYTOP_SUPPORT 116 bool 117 depends on !SMP 118 default y 119 120config LOCKDEP_SUPPORT 121 bool 122 default y 123 124config TRACE_IRQFLAGS_SUPPORT 125 bool 126 default y 127 128config RWSEM_GENERIC_SPINLOCK 129 bool 130 default y 131 132config RWSEM_XCHGADD_ALGORITHM 133 bool 134 135config ARCH_HAS_ILOG2_U32 136 bool 137 138config ARCH_HAS_ILOG2_U64 139 bool 140 141config ARCH_HAS_CPUFREQ 142 bool 143 help 144 Internal node to signify that the ARCH has CPUFREQ support 145 and that the relevant menu configurations are displayed for 146 it. 147 148config GENERIC_HWEIGHT 149 bool 150 default y 151 152config GENERIC_CALIBRATE_DELAY 153 bool 154 default y 155 156config ARCH_MAY_HAVE_PC_FDC 157 bool 158 159config ZONE_DMA 160 bool 161 162config NEED_DMA_MAP_STATE 163 def_bool y 164 165config ARCH_HAS_DMA_SET_COHERENT_MASK 166 bool 167 168config GENERIC_ISA_DMA 169 bool 170 171config FIQ 172 bool 173 174config NEED_RET_TO_USER 175 bool 176 177config ARCH_MTD_XIP 178 bool 179 180config VECTORS_BASE 181 hex 182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 183 default DRAM_BASE if REMAP_VECTORS_TO_RAM 184 default 0x00000000 185 help 186 The base address of exception vectors. 187 188config ARM_PATCH_PHYS_VIRT 189 bool "Patch physical to virtual translations at runtime" if EMBEDDED 190 default y 191 depends on !XIP_KERNEL && MMU 192 depends on !ARCH_REALVIEW || !SPARSEMEM 193 help 194 Patch phys-to-virt and virt-to-phys translation functions at 195 boot and module load time according to the position of the 196 kernel in system memory. 197 198 This can only be used with non-XIP MMU kernels where the base 199 of physical memory is at a 16MB boundary. 200 201 Only disable this option if you know that you do not require 202 this feature (eg, building a kernel for a single machine) and 203 you need to shrink the kernel to the minimal size. 204 205config NEED_MACH_IO_H 206 bool 207 help 208 Select this when mach/io.h is required to provide special 209 definitions for this platform. The need for mach/io.h should 210 be avoided when possible. 211 212config NEED_MACH_MEMORY_H 213 bool 214 help 215 Select this when mach/memory.h is required to provide special 216 definitions for this platform. The need for mach/memory.h should 217 be avoided when possible. 218 219config PHYS_OFFSET 220 hex "Physical address of main memory" if MMU 221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 222 default DRAM_BASE if !MMU 223 help 224 Please provide the physical address corresponding to the 225 location of main memory in your system. 226 227config GENERIC_BUG 228 def_bool y 229 depends on BUG 230 231source "init/Kconfig" 232 233source "kernel/Kconfig.freezer" 234 235menu "System Type" 236 237config MMU 238 bool "MMU-based Paged Memory Management Support" 239 default y 240 help 241 Select if you want MMU-based virtualised addressing space 242 support by paged memory management. If unsure, say 'Y'. 243 244# 245# The "ARM system type" choice list is ordered alphabetically by option 246# text. Please add new entries in the option alphabetic order. 247# 248choice 249 prompt "ARM system type" 250 default ARCH_VERSATILE 251 252config ARCH_SOCFPGA 253 bool "Altera SOCFPGA family" 254 select ARCH_WANT_OPTIONAL_GPIOLIB 255 select ARM_AMBA 256 select ARM_GIC 257 select CACHE_L2X0 258 select CLKDEV_LOOKUP 259 select COMMON_CLK 260 select CPU_V7 261 select DW_APB_TIMER 262 select DW_APB_TIMER_OF 263 select GENERIC_CLOCKEVENTS 264 select GPIO_PL061 if GPIOLIB 265 select HAVE_ARM_SCU 266 select SPARSE_IRQ 267 select USE_OF 268 help 269 This enables support for Altera SOCFPGA Cyclone V platform 270 271config ARCH_INTEGRATOR 272 bool "ARM Ltd. Integrator family" 273 select ARM_AMBA 274 select ARCH_HAS_CPUFREQ 275 select COMMON_CLK 276 select CLK_VERSATILE 277 select HAVE_TCM 278 select ICST 279 select GENERIC_CLOCKEVENTS 280 select PLAT_VERSATILE 281 select PLAT_VERSATILE_FPGA_IRQ 282 select NEED_MACH_IO_H 283 select NEED_MACH_MEMORY_H 284 select SPARSE_IRQ 285 select MULTI_IRQ_HANDLER 286 help 287 Support for ARM's Integrator platform. 288 289config ARCH_REALVIEW 290 bool "ARM Ltd. RealView family" 291 select ARM_AMBA 292 select CLKDEV_LOOKUP 293 select HAVE_MACH_CLKDEV 294 select ICST 295 select GENERIC_CLOCKEVENTS 296 select ARCH_WANT_OPTIONAL_GPIOLIB 297 select PLAT_VERSATILE 298 select PLAT_VERSATILE_CLOCK 299 select PLAT_VERSATILE_CLCD 300 select ARM_TIMER_SP804 301 select GPIO_PL061 if GPIOLIB 302 select NEED_MACH_MEMORY_H 303 help 304 This enables support for ARM Ltd RealView boards. 305 306config ARCH_VERSATILE 307 bool "ARM Ltd. Versatile family" 308 select ARM_AMBA 309 select ARM_VIC 310 select CLKDEV_LOOKUP 311 select HAVE_MACH_CLKDEV 312 select ICST 313 select GENERIC_CLOCKEVENTS 314 select ARCH_WANT_OPTIONAL_GPIOLIB 315 select NEED_MACH_IO_H if PCI 316 select PLAT_VERSATILE 317 select PLAT_VERSATILE_CLOCK 318 select PLAT_VERSATILE_CLCD 319 select PLAT_VERSATILE_FPGA_IRQ 320 select ARM_TIMER_SP804 321 help 322 This enables support for ARM Ltd Versatile board. 323 324config ARCH_VEXPRESS 325 bool "ARM Ltd. Versatile Express family" 326 select ARCH_WANT_OPTIONAL_GPIOLIB 327 select ARM_AMBA 328 select ARM_TIMER_SP804 329 select CLKDEV_LOOKUP 330 select COMMON_CLK 331 select GENERIC_CLOCKEVENTS 332 select HAVE_CLK 333 select HAVE_PATA_PLATFORM 334 select ICST 335 select NO_IOPORT 336 select PLAT_VERSATILE 337 select PLAT_VERSATILE_CLCD 338 select REGULATOR_FIXED_VOLTAGE if REGULATOR 339 help 340 This enables support for the ARM Ltd Versatile Express boards. 341 342config ARCH_AT91 343 bool "Atmel AT91" 344 select ARCH_REQUIRE_GPIOLIB 345 select HAVE_CLK 346 select CLKDEV_LOOKUP 347 select IRQ_DOMAIN 348 select NEED_MACH_IO_H if PCCARD 349 help 350 This enables support for systems based on Atmel 351 AT91RM9200 and AT91SAM9* processors. 352 353config ARCH_BCMRING 354 bool "Broadcom BCMRING" 355 depends on MMU 356 select CPU_V6 357 select ARM_AMBA 358 select ARM_TIMER_SP804 359 select CLKDEV_LOOKUP 360 select GENERIC_CLOCKEVENTS 361 select ARCH_WANT_OPTIONAL_GPIOLIB 362 help 363 Support for Broadcom's BCMRing platform. 364 365config ARCH_HIGHBANK 366 bool "Calxeda Highbank-based" 367 select ARCH_WANT_OPTIONAL_GPIOLIB 368 select ARM_AMBA 369 select ARM_GIC 370 select ARM_TIMER_SP804 371 select CACHE_L2X0 372 select CLKDEV_LOOKUP 373 select COMMON_CLK 374 select CPU_V7 375 select GENERIC_CLOCKEVENTS 376 select HAVE_ARM_SCU 377 select HAVE_SMP 378 select SPARSE_IRQ 379 select USE_OF 380 help 381 Support for the Calxeda Highbank SoC based boards. 382 383config ARCH_CLPS711X 384 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 385 select CPU_ARM720T 386 select ARCH_USES_GETTIMEOFFSET 387 select NEED_MACH_MEMORY_H 388 help 389 Support for Cirrus Logic 711x/721x/731x based boards. 390 391config ARCH_CNS3XXX 392 bool "Cavium Networks CNS3XXX family" 393 select CPU_V6K 394 select GENERIC_CLOCKEVENTS 395 select ARM_GIC 396 select MIGHT_HAVE_CACHE_L2X0 397 select MIGHT_HAVE_PCI 398 select PCI_DOMAINS if PCI 399 help 400 Support for Cavium Networks CNS3XXX platform. 401 402config ARCH_GEMINI 403 bool "Cortina Systems Gemini" 404 select CPU_FA526 405 select ARCH_REQUIRE_GPIOLIB 406 select ARCH_USES_GETTIMEOFFSET 407 help 408 Support for the Cortina Systems Gemini family SoCs 409 410config ARCH_PRIMA2 411 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 412 select CPU_V7 413 select NO_IOPORT 414 select ARCH_REQUIRE_GPIOLIB 415 select GENERIC_CLOCKEVENTS 416 select CLKDEV_LOOKUP 417 select GENERIC_IRQ_CHIP 418 select MIGHT_HAVE_CACHE_L2X0 419 select PINCTRL 420 select PINCTRL_SIRF 421 select USE_OF 422 select ZONE_DMA 423 help 424 Support for CSR SiRFSoC ARM Cortex A9 Platform 425 426config ARCH_EBSA110 427 bool "EBSA-110" 428 select CPU_SA110 429 select ISA 430 select NO_IOPORT 431 select ARCH_USES_GETTIMEOFFSET 432 select NEED_MACH_IO_H 433 select NEED_MACH_MEMORY_H 434 help 435 This is an evaluation board for the StrongARM processor available 436 from Digital. It has limited hardware on-board, including an 437 Ethernet interface, two PCMCIA sockets, two serial ports and a 438 parallel port. 439 440config ARCH_EP93XX 441 bool "EP93xx-based" 442 select CPU_ARM920T 443 select ARM_AMBA 444 select ARM_VIC 445 select CLKDEV_LOOKUP 446 select ARCH_REQUIRE_GPIOLIB 447 select ARCH_HAS_HOLES_MEMORYMODEL 448 select ARCH_USES_GETTIMEOFFSET 449 select NEED_MACH_MEMORY_H 450 help 451 This enables support for the Cirrus EP93xx series of CPUs. 452 453config ARCH_FOOTBRIDGE 454 bool "FootBridge" 455 select CPU_SA110 456 select FOOTBRIDGE 457 select GENERIC_CLOCKEVENTS 458 select HAVE_IDE 459 select NEED_MACH_IO_H 460 select NEED_MACH_MEMORY_H 461 help 462 Support for systems based on the DC21285 companion chip 463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 464 465config ARCH_MXC 466 bool "Freescale MXC/iMX-based" 467 select GENERIC_CLOCKEVENTS 468 select ARCH_REQUIRE_GPIOLIB 469 select CLKDEV_LOOKUP 470 select CLKSRC_MMIO 471 select GENERIC_IRQ_CHIP 472 select MULTI_IRQ_HANDLER 473 select SPARSE_IRQ 474 select USE_OF 475 help 476 Support for Freescale MXC/iMX-based family of processors 477 478config ARCH_MXS 479 bool "Freescale MXS-based" 480 select GENERIC_CLOCKEVENTS 481 select ARCH_REQUIRE_GPIOLIB 482 select CLKDEV_LOOKUP 483 select CLKSRC_MMIO 484 select COMMON_CLK 485 select HAVE_CLK_PREPARE 486 select PINCTRL 487 select USE_OF 488 help 489 Support for Freescale MXS-based family of processors 490 491config ARCH_NETX 492 bool "Hilscher NetX based" 493 select CLKSRC_MMIO 494 select CPU_ARM926T 495 select ARM_VIC 496 select GENERIC_CLOCKEVENTS 497 help 498 This enables support for systems based on the Hilscher NetX Soc 499 500config ARCH_H720X 501 bool "Hynix HMS720x-based" 502 select CPU_ARM720T 503 select ISA_DMA_API 504 select ARCH_USES_GETTIMEOFFSET 505 help 506 This enables support for systems based on the Hynix HMS720x 507 508config ARCH_IOP13XX 509 bool "IOP13xx-based" 510 depends on MMU 511 select CPU_XSC3 512 select PLAT_IOP 513 select PCI 514 select ARCH_SUPPORTS_MSI 515 select VMSPLIT_1G 516 select NEED_MACH_IO_H 517 select NEED_MACH_MEMORY_H 518 select NEED_RET_TO_USER 519 help 520 Support for Intel's IOP13XX (XScale) family of processors. 521 522config ARCH_IOP32X 523 bool "IOP32x-based" 524 depends on MMU 525 select CPU_XSCALE 526 select NEED_MACH_IO_H 527 select NEED_RET_TO_USER 528 select PLAT_IOP 529 select PCI 530 select ARCH_REQUIRE_GPIOLIB 531 help 532 Support for Intel's 80219 and IOP32X (XScale) family of 533 processors. 534 535config ARCH_IOP33X 536 bool "IOP33x-based" 537 depends on MMU 538 select CPU_XSCALE 539 select NEED_MACH_IO_H 540 select NEED_RET_TO_USER 541 select PLAT_IOP 542 select PCI 543 select ARCH_REQUIRE_GPIOLIB 544 help 545 Support for Intel's IOP33X (XScale) family of processors. 546 547config ARCH_IXP4XX 548 bool "IXP4xx-based" 549 depends on MMU 550 select ARCH_HAS_DMA_SET_COHERENT_MASK 551 select CLKSRC_MMIO 552 select CPU_XSCALE 553 select ARCH_REQUIRE_GPIOLIB 554 select GENERIC_CLOCKEVENTS 555 select MIGHT_HAVE_PCI 556 select NEED_MACH_IO_H 557 select DMABOUNCE if PCI 558 help 559 Support for Intel's IXP4XX (XScale) family of processors. 560 561config ARCH_MVEBU 562 bool "Marvell SOCs with Device Tree support" 563 select GENERIC_CLOCKEVENTS 564 select MULTI_IRQ_HANDLER 565 select SPARSE_IRQ 566 select CLKSRC_MMIO 567 select GENERIC_IRQ_CHIP 568 select IRQ_DOMAIN 569 select COMMON_CLK 570 help 571 Support for the Marvell SoC Family with device tree support 572 573config ARCH_DOVE 574 bool "Marvell Dove" 575 select CPU_V7 576 select PCI 577 select ARCH_REQUIRE_GPIOLIB 578 select GENERIC_CLOCKEVENTS 579 select NEED_MACH_IO_H 580 select PLAT_ORION 581 help 582 Support for the Marvell Dove SoC 88AP510 583 584config ARCH_KIRKWOOD 585 bool "Marvell Kirkwood" 586 select CPU_FEROCEON 587 select PCI 588 select ARCH_REQUIRE_GPIOLIB 589 select GENERIC_CLOCKEVENTS 590 select NEED_MACH_IO_H 591 select PLAT_ORION 592 help 593 Support for the following Marvell Kirkwood series SoCs: 594 88F6180, 88F6192 and 88F6281. 595 596config ARCH_LPC32XX 597 bool "NXP LPC32XX" 598 select CLKSRC_MMIO 599 select CPU_ARM926T 600 select ARCH_REQUIRE_GPIOLIB 601 select HAVE_IDE 602 select ARM_AMBA 603 select USB_ARCH_HAS_OHCI 604 select CLKDEV_LOOKUP 605 select GENERIC_CLOCKEVENTS 606 select USE_OF 607 select HAVE_PWM 608 help 609 Support for the NXP LPC32XX family of processors 610 611config ARCH_MV78XX0 612 bool "Marvell MV78xx0" 613 select CPU_FEROCEON 614 select PCI 615 select ARCH_REQUIRE_GPIOLIB 616 select GENERIC_CLOCKEVENTS 617 select NEED_MACH_IO_H 618 select PLAT_ORION 619 help 620 Support for the following Marvell MV78xx0 series SoCs: 621 MV781x0, MV782x0. 622 623config ARCH_ORION5X 624 bool "Marvell Orion" 625 depends on MMU 626 select CPU_FEROCEON 627 select PCI 628 select ARCH_REQUIRE_GPIOLIB 629 select GENERIC_CLOCKEVENTS 630 select NEED_MACH_IO_H 631 select PLAT_ORION 632 help 633 Support for the following Marvell Orion 5x series SoCs: 634 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 635 Orion-2 (5281), Orion-1-90 (6183). 636 637config ARCH_MMP 638 bool "Marvell PXA168/910/MMP2" 639 depends on MMU 640 select ARCH_REQUIRE_GPIOLIB 641 select CLKDEV_LOOKUP 642 select GENERIC_CLOCKEVENTS 643 select GPIO_PXA 644 select IRQ_DOMAIN 645 select PLAT_PXA 646 select SPARSE_IRQ 647 select GENERIC_ALLOCATOR 648 help 649 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 650 651config ARCH_KS8695 652 bool "Micrel/Kendin KS8695" 653 select CPU_ARM922T 654 select ARCH_REQUIRE_GPIOLIB 655 select ARCH_USES_GETTIMEOFFSET 656 select NEED_MACH_MEMORY_H 657 help 658 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 659 System-on-Chip devices. 660 661config ARCH_W90X900 662 bool "Nuvoton W90X900 CPU" 663 select CPU_ARM926T 664 select ARCH_REQUIRE_GPIOLIB 665 select CLKDEV_LOOKUP 666 select CLKSRC_MMIO 667 select GENERIC_CLOCKEVENTS 668 help 669 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 670 At present, the w90x900 has been renamed nuc900, regarding 671 the ARM series product line, you can login the following 672 link address to know more. 673 674 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 675 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 676 677config ARCH_TEGRA 678 bool "NVIDIA Tegra" 679 select CLKDEV_LOOKUP 680 select CLKSRC_MMIO 681 select GENERIC_CLOCKEVENTS 682 select GENERIC_GPIO 683 select HAVE_CLK 684 select HAVE_SMP 685 select MIGHT_HAVE_CACHE_L2X0 686 select NEED_MACH_IO_H if PCI 687 select ARCH_HAS_CPUFREQ 688 select USE_OF 689 help 690 This enables support for NVIDIA Tegra based systems (Tegra APX, 691 Tegra 6xx and Tegra 2 series). 692 693config ARCH_PICOXCELL 694 bool "Picochip picoXcell" 695 select ARCH_REQUIRE_GPIOLIB 696 select ARM_PATCH_PHYS_VIRT 697 select ARM_VIC 698 select CPU_V6K 699 select DW_APB_TIMER 700 select DW_APB_TIMER_OF 701 select GENERIC_CLOCKEVENTS 702 select GENERIC_GPIO 703 select HAVE_TCM 704 select NO_IOPORT 705 select SPARSE_IRQ 706 select USE_OF 707 help 708 This enables support for systems based on the Picochip picoXcell 709 family of Femtocell devices. The picoxcell support requires device tree 710 for all boards. 711 712config ARCH_PNX4008 713 bool "Philips Nexperia PNX4008 Mobile" 714 select CPU_ARM926T 715 select CLKDEV_LOOKUP 716 select ARCH_USES_GETTIMEOFFSET 717 help 718 This enables support for Philips PNX4008 mobile platform. 719 720config ARCH_PXA 721 bool "PXA2xx/PXA3xx-based" 722 depends on MMU 723 select ARCH_MTD_XIP 724 select ARCH_HAS_CPUFREQ 725 select CLKDEV_LOOKUP 726 select CLKSRC_MMIO 727 select ARCH_REQUIRE_GPIOLIB 728 select GENERIC_CLOCKEVENTS 729 select GPIO_PXA 730 select PLAT_PXA 731 select SPARSE_IRQ 732 select AUTO_ZRELADDR 733 select MULTI_IRQ_HANDLER 734 select ARM_CPU_SUSPEND if PM 735 select HAVE_IDE 736 help 737 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 738 739config ARCH_MSM 740 bool "Qualcomm MSM" 741 select HAVE_CLK 742 select GENERIC_CLOCKEVENTS 743 select ARCH_REQUIRE_GPIOLIB 744 select CLKDEV_LOOKUP 745 help 746 Support for Qualcomm MSM/QSD based systems. This runs on the 747 apps processor of the MSM/QSD and depends on a shared memory 748 interface to the modem processor which runs the baseband 749 stack and controls some vital subsystems 750 (clock and power control, etc). 751 752config ARCH_SHMOBILE 753 bool "Renesas SH-Mobile / R-Mobile" 754 select HAVE_CLK 755 select CLKDEV_LOOKUP 756 select HAVE_MACH_CLKDEV 757 select HAVE_SMP 758 select GENERIC_CLOCKEVENTS 759 select MIGHT_HAVE_CACHE_L2X0 760 select NO_IOPORT 761 select SPARSE_IRQ 762 select MULTI_IRQ_HANDLER 763 select PM_GENERIC_DOMAINS if PM 764 select NEED_MACH_MEMORY_H 765 help 766 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 767 768config ARCH_RPC 769 bool "RiscPC" 770 select ARCH_ACORN 771 select FIQ 772 select ARCH_MAY_HAVE_PC_FDC 773 select HAVE_PATA_PLATFORM 774 select ISA_DMA_API 775 select NO_IOPORT 776 select ARCH_SPARSEMEM_ENABLE 777 select ARCH_USES_GETTIMEOFFSET 778 select HAVE_IDE 779 select NEED_MACH_IO_H 780 select NEED_MACH_MEMORY_H 781 help 782 On the Acorn Risc-PC, Linux can support the internal IDE disk and 783 CD-ROM interface, serial and parallel port, and the floppy drive. 784 785config ARCH_SA1100 786 bool "SA1100-based" 787 select CLKSRC_MMIO 788 select CPU_SA1100 789 select ISA 790 select ARCH_SPARSEMEM_ENABLE 791 select ARCH_MTD_XIP 792 select ARCH_HAS_CPUFREQ 793 select CPU_FREQ 794 select GENERIC_CLOCKEVENTS 795 select CLKDEV_LOOKUP 796 select ARCH_REQUIRE_GPIOLIB 797 select HAVE_IDE 798 select NEED_MACH_MEMORY_H 799 select SPARSE_IRQ 800 help 801 Support for StrongARM 11x0 based boards. 802 803config ARCH_S3C24XX 804 bool "Samsung S3C24XX SoCs" 805 select GENERIC_GPIO 806 select ARCH_HAS_CPUFREQ 807 select HAVE_CLK 808 select CLKDEV_LOOKUP 809 select ARCH_USES_GETTIMEOFFSET 810 select HAVE_S3C2410_I2C if I2C 811 select HAVE_S3C_RTC if RTC_CLASS 812 select HAVE_S3C2410_WATCHDOG if WATCHDOG 813 select NEED_MACH_IO_H 814 help 815 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 816 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 817 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 818 Samsung SMDK2410 development board (and derivatives). 819 820config ARCH_S3C64XX 821 bool "Samsung S3C64XX" 822 select PLAT_SAMSUNG 823 select CPU_V6 824 select ARM_VIC 825 select HAVE_CLK 826 select HAVE_TCM 827 select CLKDEV_LOOKUP 828 select NO_IOPORT 829 select ARCH_USES_GETTIMEOFFSET 830 select ARCH_HAS_CPUFREQ 831 select ARCH_REQUIRE_GPIOLIB 832 select SAMSUNG_CLKSRC 833 select SAMSUNG_IRQ_VIC_TIMER 834 select S3C_GPIO_TRACK 835 select S3C_DEV_NAND 836 select USB_ARCH_HAS_OHCI 837 select SAMSUNG_GPIOLIB_4BIT 838 select HAVE_S3C2410_I2C if I2C 839 select HAVE_S3C2410_WATCHDOG if WATCHDOG 840 help 841 Samsung S3C64XX series based systems 842 843config ARCH_S5P64X0 844 bool "Samsung S5P6440 S5P6450" 845 select CPU_V6 846 select GENERIC_GPIO 847 select HAVE_CLK 848 select CLKDEV_LOOKUP 849 select CLKSRC_MMIO 850 select HAVE_S3C2410_WATCHDOG if WATCHDOG 851 select GENERIC_CLOCKEVENTS 852 select HAVE_S3C2410_I2C if I2C 853 select HAVE_S3C_RTC if RTC_CLASS 854 help 855 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 856 SMDK6450. 857 858config ARCH_S5PC100 859 bool "Samsung S5PC100" 860 select GENERIC_GPIO 861 select HAVE_CLK 862 select CLKDEV_LOOKUP 863 select CPU_V7 864 select ARCH_USES_GETTIMEOFFSET 865 select HAVE_S3C2410_I2C if I2C 866 select HAVE_S3C_RTC if RTC_CLASS 867 select HAVE_S3C2410_WATCHDOG if WATCHDOG 868 help 869 Samsung S5PC100 series based systems 870 871config ARCH_S5PV210 872 bool "Samsung S5PV210/S5PC110" 873 select CPU_V7 874 select ARCH_SPARSEMEM_ENABLE 875 select ARCH_HAS_HOLES_MEMORYMODEL 876 select GENERIC_GPIO 877 select HAVE_CLK 878 select CLKDEV_LOOKUP 879 select CLKSRC_MMIO 880 select ARCH_HAS_CPUFREQ 881 select GENERIC_CLOCKEVENTS 882 select HAVE_S3C2410_I2C if I2C 883 select HAVE_S3C_RTC if RTC_CLASS 884 select HAVE_S3C2410_WATCHDOG if WATCHDOG 885 select NEED_MACH_MEMORY_H 886 help 887 Samsung S5PV210/S5PC110 series based systems 888 889config ARCH_EXYNOS 890 bool "SAMSUNG EXYNOS" 891 select CPU_V7 892 select ARCH_SPARSEMEM_ENABLE 893 select ARCH_HAS_HOLES_MEMORYMODEL 894 select GENERIC_GPIO 895 select HAVE_CLK 896 select CLKDEV_LOOKUP 897 select ARCH_HAS_CPUFREQ 898 select GENERIC_CLOCKEVENTS 899 select HAVE_S3C_RTC if RTC_CLASS 900 select HAVE_S3C2410_I2C if I2C 901 select HAVE_S3C2410_WATCHDOG if WATCHDOG 902 select NEED_MACH_MEMORY_H 903 help 904 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 905 906config ARCH_SHARK 907 bool "Shark" 908 select CPU_SA110 909 select ISA 910 select ISA_DMA 911 select ZONE_DMA 912 select PCI 913 select ARCH_USES_GETTIMEOFFSET 914 select NEED_MACH_MEMORY_H 915 select NEED_MACH_IO_H 916 help 917 Support for the StrongARM based Digital DNARD machine, also known 918 as "Shark" (<http://www.shark-linux.de/shark.html>). 919 920config ARCH_U300 921 bool "ST-Ericsson U300 Series" 922 depends on MMU 923 select CLKSRC_MMIO 924 select CPU_ARM926T 925 select HAVE_TCM 926 select ARM_AMBA 927 select ARM_PATCH_PHYS_VIRT 928 select ARM_VIC 929 select GENERIC_CLOCKEVENTS 930 select CLKDEV_LOOKUP 931 select COMMON_CLK 932 select GENERIC_GPIO 933 select ARCH_REQUIRE_GPIOLIB 934 help 935 Support for ST-Ericsson U300 series mobile platforms. 936 937config ARCH_U8500 938 bool "ST-Ericsson U8500 Series" 939 depends on MMU 940 select CPU_V7 941 select ARM_AMBA 942 select GENERIC_CLOCKEVENTS 943 select CLKDEV_LOOKUP 944 select ARCH_REQUIRE_GPIOLIB 945 select ARCH_HAS_CPUFREQ 946 select HAVE_SMP 947 select MIGHT_HAVE_CACHE_L2X0 948 help 949 Support for ST-Ericsson's Ux500 architecture 950 951config ARCH_NOMADIK 952 bool "STMicroelectronics Nomadik" 953 select ARM_AMBA 954 select ARM_VIC 955 select CPU_ARM926T 956 select COMMON_CLK 957 select GENERIC_CLOCKEVENTS 958 select PINCTRL 959 select MIGHT_HAVE_CACHE_L2X0 960 select ARCH_REQUIRE_GPIOLIB 961 help 962 Support for the Nomadik platform by ST-Ericsson 963 964config ARCH_DAVINCI 965 bool "TI DaVinci" 966 select GENERIC_CLOCKEVENTS 967 select ARCH_REQUIRE_GPIOLIB 968 select ZONE_DMA 969 select HAVE_IDE 970 select CLKDEV_LOOKUP 971 select GENERIC_ALLOCATOR 972 select GENERIC_IRQ_CHIP 973 select ARCH_HAS_HOLES_MEMORYMODEL 974 help 975 Support for TI's DaVinci platform. 976 977config ARCH_OMAP 978 bool "TI OMAP" 979 depends on MMU 980 select HAVE_CLK 981 select ARCH_REQUIRE_GPIOLIB 982 select ARCH_HAS_CPUFREQ 983 select CLKSRC_MMIO 984 select GENERIC_CLOCKEVENTS 985 select ARCH_HAS_HOLES_MEMORYMODEL 986 help 987 Support for TI's OMAP platform (OMAP1/2/3/4). 988 989config PLAT_SPEAR 990 bool "ST SPEAr" 991 select ARM_AMBA 992 select ARCH_REQUIRE_GPIOLIB 993 select CLKDEV_LOOKUP 994 select COMMON_CLK 995 select CLKSRC_MMIO 996 select GENERIC_CLOCKEVENTS 997 select HAVE_CLK 998 help 999 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 1000
1001config ARCH_VT8500 1002 bool "VIA/WonderMedia 85xx" 1003 select CPU_ARM926T 1004 select GENERIC_GPIO 1005 select ARCH_HAS_CPUFREQ 1006 select GENERIC_CLOCKEVENTS 1007 select ARCH_REQUIRE_GPIOLIB 1008 help 1009 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 1010 1011config ARCH_ZYNQ 1012 bool "Xilinx Zynq ARM Cortex A9 Platform" 1013 select CPU_V7 1014 select GENERIC_CLOCKEVENTS 1015 select CLKDEV_LOOKUP 1016 select ARM_GIC 1017 select ARM_AMBA 1018 select ICST 1019 select MIGHT_HAVE_CACHE_L2X0 1020 select USE_OF 1021 help 1022 Support for Xilinx Zynq ARM Cortex A9 Platform 1023endchoice 1024 1025# 1026# This is sorted alphabetically by mach-* pathname. However, plat-* 1027# Kconfigs may be included either alphabetically (according to the 1028# plat- suffix) or along side the corresponding mach-* source. 1029# 1030source "arch/arm/mach-mvebu/Kconfig" 1031 1032source "arch/arm/mach-at91/Kconfig" 1033 1034source "arch/arm/mach-bcmring/Kconfig" 1035 1036source "arch/arm/mach-clps711x/Kconfig" 1037 1038source "arch/arm/mach-cns3xxx/Kconfig" 1039 1040source "arch/arm/mach-davinci/Kconfig" 1041 1042source "arch/arm/mach-dove/Kconfig" 1043 1044source "arch/arm/mach-ep93xx/Kconfig" 1045 1046source "arch/arm/mach-footbridge/Kconfig" 1047 1048source "arch/arm/mach-gemini/Kconfig" 1049 1050source "arch/arm/mach-h720x/Kconfig" 1051 1052source "arch/arm/mach-integrator/Kconfig" 1053 1054source "arch/arm/mach-iop32x/Kconfig" 1055 1056source "arch/arm/mach-iop33x/Kconfig" 1057 1058source "arch/arm/mach-iop13xx/Kconfig" 1059 1060source "arch/arm/mach-ixp4xx/Kconfig" 1061 1062source "arch/arm/mach-kirkwood/Kconfig" 1063 1064source "arch/arm/mach-ks8695/Kconfig" 1065 1066source "arch/arm/mach-msm/Kconfig" 1067 1068source "arch/arm/mach-mv78xx0/Kconfig" 1069 1070source "arch/arm/plat-mxc/Kconfig" 1071 1072source "arch/arm/mach-mxs/Kconfig" 1073 1074source "arch/arm/mach-netx/Kconfig" 1075 1076source "arch/arm/mach-nomadik/Kconfig" 1077source "arch/arm/plat-nomadik/Kconfig" 1078 1079source "arch/arm/plat-omap/Kconfig" 1080 1081source "arch/arm/mach-omap1/Kconfig" 1082 1083source "arch/arm/mach-omap2/Kconfig" 1084 1085source "arch/arm/mach-orion5x/Kconfig" 1086 1087source "arch/arm/mach-pxa/Kconfig" 1088source "arch/arm/plat-pxa/Kconfig" 1089 1090source "arch/arm/mach-mmp/Kconfig" 1091 1092source "arch/arm/mach-realview/Kconfig" 1093 1094source "arch/arm/mach-sa1100/Kconfig" 1095 1096source "arch/arm/plat-samsung/Kconfig" 1097source "arch/arm/plat-s3c24xx/Kconfig" 1098 1099source "arch/arm/plat-spear/Kconfig" 1100 1101source "arch/arm/mach-s3c24xx/Kconfig" 1102if ARCH_S3C24XX 1103source "arch/arm/mach-s3c2412/Kconfig" 1104source "arch/arm/mach-s3c2440/Kconfig" 1105endif 1106 1107if ARCH_S3C64XX 1108source "arch/arm/mach-s3c64xx/Kconfig" 1109endif 1110 1111source "arch/arm/mach-s5p64x0/Kconfig" 1112 1113source "arch/arm/mach-s5pc100/Kconfig" 1114 1115source "arch/arm/mach-s5pv210/Kconfig" 1116 1117source "arch/arm/mach-exynos/Kconfig" 1118 1119source "arch/arm/mach-shmobile/Kconfig" 1120 1121source "arch/arm/mach-tegra/Kconfig" 1122 1123source "arch/arm/mach-u300/Kconfig" 1124 1125source "arch/arm/mach-ux500/Kconfig" 1126 1127source "arch/arm/mach-versatile/Kconfig" 1128 1129source "arch/arm/mach-vexpress/Kconfig" 1130source "arch/arm/plat-versatile/Kconfig" 1131 1132source "arch/arm/mach-vt8500/Kconfig" 1133 1134source "arch/arm/mach-w90x900/Kconfig" 1135 1136# Definitions to make life easier 1137config ARCH_ACORN 1138 bool 1139 1140config PLAT_IOP 1141 bool 1142 select GENERIC_CLOCKEVENTS 1143 1144config PLAT_ORION 1145 bool 1146 select CLKSRC_MMIO 1147 select GENERIC_IRQ_CHIP 1148 select IRQ_DOMAIN 1149 select COMMON_CLK 1150 1151config PLAT_PXA 1152 bool 1153 1154config PLAT_VERSATILE 1155 bool 1156 1157config ARM_TIMER_SP804 1158 bool 1159 select CLKSRC_MMIO 1160 select HAVE_SCHED_CLOCK 1161 1162source arch/arm/mm/Kconfig 1163 1164config ARM_NR_BANKS 1165 int 1166 default 16 if ARCH_EP93XX 1167 default 8 1168 1169config IWMMXT 1170 bool "Enable iWMMXt support" 1171 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1172 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1173 help 1174 Enable support for iWMMXt context switching at run time if 1175 running on a CPU that supports it. 1176 1177config XSCALE_PMU 1178 bool 1179 depends on CPU_XSCALE 1180 default y 1181 1182config CPU_HAS_PMU 1183 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1184 (!ARCH_OMAP3 || OMAP3_EMU) 1185 default y 1186 bool 1187 1188config MULTI_IRQ_HANDLER 1189 bool 1190 help 1191 Allow each machine to specify it's own IRQ handler at run time. 1192 1193if !MMU 1194source "arch/arm/Kconfig-nommu" 1195endif 1196 1197config ARM_ERRATA_326103 1198 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1199 depends on CPU_V6 1200 help 1201 Executing a SWP instruction to read-only memory does not set bit 11 1202 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1203 treat the access as a read, preventing a COW from occurring and 1204 causing the faulting task to livelock. 1205 1206config ARM_ERRATA_411920 1207 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1208 depends on CPU_V6 || CPU_V6K 1209 help 1210 Invalidation of the Instruction Cache operation can 1211 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1212 It does not affect the MPCore. This option enables the ARM Ltd. 1213 recommended workaround. 1214 1215config ARM_ERRATA_430973 1216 bool "ARM errata: Stale prediction on replaced interworking branch" 1217 depends on CPU_V7 1218 help 1219 This option enables the workaround for the 430973 Cortex-A8 1220 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1221 interworking branch is replaced with another code sequence at the 1222 same virtual address, whether due to self-modifying code or virtual 1223 to physical address re-mapping, Cortex-A8 does not recover from the 1224 stale interworking branch prediction. This results in Cortex-A8 1225 executing the new code sequence in the incorrect ARM or Thumb state. 1226 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1227 and also flushes the branch target cache at every context switch. 1228 Note that setting specific bits in the ACTLR register may not be 1229 available in non-secure mode. 1230 1231config ARM_ERRATA_458693 1232 bool "ARM errata: Processor deadlock when a false hazard is created" 1233 depends on CPU_V7 1234 help 1235 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1236 erratum. For very specific sequences of memory operations, it is 1237 possible for a hazard condition intended for a cache line to instead 1238 be incorrectly associated with a different cache line. This false 1239 hazard might then cause a processor deadlock. The workaround enables 1240 the L1 caching of the NEON accesses and disables the PLD instruction 1241 in the ACTLR register. Note that setting specific bits in the ACTLR 1242 register may not be available in non-secure mode. 1243 1244config ARM_ERRATA_460075 1245 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1246 depends on CPU_V7 1247 help 1248 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1249 erratum. Any asynchronous access to the L2 cache may encounter a 1250 situation in which recent store transactions to the L2 cache are lost 1251 and overwritten with stale memory contents from external memory. The 1252 workaround disables the write-allocate mode for the L2 cache via the 1253 ACTLR register. Note that setting specific bits in the ACTLR register 1254 may not be available in non-secure mode. 1255 1256config ARM_ERRATA_742230 1257 bool "ARM errata: DMB operation may be faulty" 1258 depends on CPU_V7 && SMP 1259 help 1260 This option enables the workaround for the 742230 Cortex-A9 1261 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1262 between two write operations may not ensure the correct visibility 1263 ordering of the two writes. This workaround sets a specific bit in 1264 the diagnostic register of the Cortex-A9 which causes the DMB 1265 instruction to behave as a DSB, ensuring the correct behaviour of 1266 the two writes. 1267 1268config ARM_ERRATA_742231 1269 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1270 depends on CPU_V7 && SMP 1271 help 1272 This option enables the workaround for the 742231 Cortex-A9 1273 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1274 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1275 accessing some data located in the same cache line, may get corrupted 1276 data due to bad handling of the address hazard when the line gets 1277 replaced from one of the CPUs at the same time as another CPU is 1278 accessing it. This workaround sets specific bits in the diagnostic 1279 register of the Cortex-A9 which reduces the linefill issuing 1280 capabilities of the processor. 1281 1282config PL310_ERRATA_588369 1283 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1284 depends on CACHE_L2X0 1285 help 1286 The PL310 L2 cache controller implements three types of Clean & 1287 Invalidate maintenance operations: by Physical Address 1288 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1289 They are architecturally defined to behave as the execution of a 1290 clean operation followed immediately by an invalidate operation, 1291 both performing to the same memory location. This functionality 1292 is not correctly implemented in PL310 as clean lines are not 1293 invalidated as a result of these operations. 1294 1295config ARM_ERRATA_720789 1296 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1297 depends on CPU_V7 1298 help 1299 This option enables the workaround for the 720789 Cortex-A9 (prior to 1300 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1301 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1302 As a consequence of this erratum, some TLB entries which should be 1303 invalidated are not, resulting in an incoherency in the system page 1304 tables. The workaround changes the TLB flushing routines to invalidate 1305 entries regardless of the ASID. 1306 1307config PL310_ERRATA_727915 1308 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1309 depends on CACHE_L2X0 1310 help 1311 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1312 operation (offset 0x7FC). This operation runs in background so that 1313 PL310 can handle normal accesses while it is in progress. Under very 1314 rare circumstances, due to this erratum, write data can be lost when 1315 PL310 treats a cacheable write transaction during a Clean & 1316 Invalidate by Way operation. 1317 1318config ARM_ERRATA_743622 1319 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1320 depends on CPU_V7 1321 help 1322 This option enables the workaround for the 743622 Cortex-A9 1323 (r2p*) erratum. Under very rare conditions, a faulty 1324 optimisation in the Cortex-A9 Store Buffer may lead to data 1325 corruption. This workaround sets a specific bit in the diagnostic 1326 register of the Cortex-A9 which disables the Store Buffer 1327 optimisation, preventing the defect from occurring. This has no 1328 visible impact on the overall performance or power consumption of the 1329 processor. 1330 1331config ARM_ERRATA_751472 1332 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1333 depends on CPU_V7 1334 help 1335 This option enables the workaround for the 751472 Cortex-A9 (prior 1336 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1337 completion of a following broadcasted operation if the second 1338 operation is received by a CPU before the ICIALLUIS has completed, 1339 potentially leading to corrupted entries in the cache or TLB. 1340 1341config PL310_ERRATA_753970 1342 bool "PL310 errata: cache sync operation may be faulty" 1343 depends on CACHE_PL310 1344 help 1345 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1346 1347 Under some condition the effect of cache sync operation on 1348 the store buffer still remains when the operation completes. 1349 This means that the store buffer is always asked to drain and 1350 this prevents it from merging any further writes. The workaround 1351 is to replace the normal offset of cache sync operation (0x730) 1352 by another offset targeting an unmapped PL310 register 0x740. 1353 This has the same effect as the cache sync operation: store buffer 1354 drain and waiting for all buffers empty. 1355 1356config ARM_ERRATA_754322 1357 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1358 depends on CPU_V7 1359 help 1360 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1361 r3p*) erratum. A speculative memory access may cause a page table walk 1362 which starts prior to an ASID switch but completes afterwards. This 1363 can populate the micro-TLB with a stale entry which may be hit with 1364 the new ASID. This workaround places two dsb instructions in the mm 1365 switching code so that no page table walks can cross the ASID switch. 1366 1367config ARM_ERRATA_754327 1368 bool "ARM errata: no automatic Store Buffer drain" 1369 depends on CPU_V7 && SMP 1370 help 1371 This option enables the workaround for the 754327 Cortex-A9 (prior to 1372 r2p0) erratum. The Store Buffer does not have any automatic draining 1373 mechanism and therefore a livelock may occur if an external agent 1374 continuously polls a memory location waiting to observe an update. 1375 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1376 written polling loops from denying visibility of updates to memory. 1377 1378config ARM_ERRATA_364296 1379 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1380 depends on CPU_V6 && !SMP 1381 help 1382 This options enables the workaround for the 364296 ARM1136 1383 r0p2 erratum (possible cache data corruption with 1384 hit-under-miss enabled). It sets the undocumented bit 31 in 1385 the auxiliary control register and the FI bit in the control 1386 register, thus disabling hit-under-miss without putting the 1387 processor into full low interrupt latency mode. ARM11MPCore 1388 is not affected. 1389 1390config ARM_ERRATA_764369 1391 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1392 depends on CPU_V7 && SMP 1393 help 1394 This option enables the workaround for erratum 764369 1395 affecting Cortex-A9 MPCore with two or more processors (all 1396 current revisions). Under certain timing circumstances, a data 1397 cache line maintenance operation by MVA targeting an Inner 1398 Shareable memory region may fail to proceed up to either the 1399 Point of Coherency or to the Point of Unification of the 1400 system. This workaround adds a DSB instruction before the 1401 relevant cache maintenance functions and sets a specific bit 1402 in the diagnostic control register of the SCU. 1403 1404config PL310_ERRATA_769419 1405 bool "PL310 errata: no automatic Store Buffer drain" 1406 depends on CACHE_L2X0 1407 help 1408 On revisions of the PL310 prior to r3p2, the Store Buffer does 1409 not automatically drain. This can cause normal, non-cacheable 1410 writes to be retained when the memory system is idle, leading 1411 to suboptimal I/O performance for drivers using coherent DMA. 1412 This option adds a write barrier to the cpu_idle loop so that, 1413 on systems with an outer cache, the store buffer is drained 1414 explicitly. 1415 1416config ARM_ERRATA_775420 1417 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1418 depends on CPU_V7 1419 help 1420 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1421 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1422 operation aborts with MMU exception, it might cause the processor 1423 to deadlock. This workaround puts DSB before executing ISB if 1424 an abort may occur on cache maintenance. 1425 1426endmenu 1427 1428source "arch/arm/common/Kconfig" 1429 1430menu "Bus support" 1431 1432config ARM_AMBA 1433 bool 1434 1435config ISA 1436 bool 1437 help 1438 Find out whether you have ISA slots on your motherboard. ISA is the 1439 name of a bus system, i.e. the way the CPU talks to the other stuff 1440 inside your box. Other bus systems are PCI, EISA, MicroChannel 1441 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1442 newer boards don't support it. If you have ISA, say Y, otherwise N. 1443 1444# Select ISA DMA controller support 1445config ISA_DMA 1446 bool 1447 select ISA_DMA_API 1448 1449# Select ISA DMA interface 1450config ISA_DMA_API 1451 bool 1452 1453config PCI 1454 bool "PCI support" if MIGHT_HAVE_PCI 1455 help 1456 Find out whether you have a PCI motherboard. PCI is the name of a 1457 bus system, i.e. the way the CPU talks to the other stuff inside 1458 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1459 VESA. If you have PCI, say Y, otherwise N. 1460 1461config PCI_DOMAINS 1462 bool 1463 depends on PCI 1464 1465config PCI_NANOENGINE 1466 bool "BSE nanoEngine PCI support" 1467 depends on SA1100_NANOENGINE 1468 help 1469 Enable PCI on the BSE nanoEngine board. 1470 1471config PCI_SYSCALL 1472 def_bool PCI 1473 1474# Select the host bridge type 1475config PCI_HOST_VIA82C505 1476 bool 1477 depends on PCI && ARCH_SHARK 1478 default y 1479 1480config PCI_HOST_ITE8152 1481 bool 1482 depends on PCI && MACH_ARMCORE 1483 default y 1484 select DMABOUNCE 1485 1486source "drivers/pci/Kconfig" 1487 1488source "drivers/pcmcia/Kconfig" 1489 1490endmenu 1491 1492menu "Kernel Features" 1493 1494config HAVE_SMP 1495 bool 1496 help 1497 This option should be selected by machines which have an SMP- 1498 capable CPU. 1499 1500 The only effect of this option is to make the SMP-related 1501 options available to the user for configuration. 1502 1503config SMP 1504 bool "Symmetric Multi-Processing" 1505 depends on CPU_V6K || CPU_V7 1506 depends on GENERIC_CLOCKEVENTS 1507 depends on HAVE_SMP 1508 depends on MMU 1509 select USE_GENERIC_SMP_HELPERS 1510 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1511 help 1512 This enables support for systems with more than one CPU. If you have 1513 a system with only one CPU, like most personal computers, say N. If 1514 you have a system with more than one CPU, say Y. 1515 1516 If you say N here, the kernel will run on single and multiprocessor 1517 machines, but will use only one CPU of a multiprocessor machine. If 1518 you say Y here, the kernel will run on many, but not all, single 1519 processor machines. On a single processor machine, the kernel will 1520 run faster if you say N here. 1521 1522 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1523 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1524 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1525 1526 If you don't know what to do here, say N. 1527 1528config SMP_ON_UP 1529 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1530 depends on EXPERIMENTAL 1531 depends on SMP && !XIP_KERNEL 1532 default y 1533 help 1534 SMP kernels contain instructions which fail on non-SMP processors. 1535 Enabling this option allows the kernel to modify itself to make 1536 these instructions safe. Disabling it allows about 1K of space 1537 savings. 1538 1539 If you don't know what to do here, say Y. 1540 1541config ARM_CPU_TOPOLOGY 1542 bool "Support cpu topology definition" 1543 depends on SMP && CPU_V7 1544 default y 1545 help 1546 Support ARM cpu topology definition. The MPIDR register defines 1547 affinity between processors which is then used to describe the cpu 1548 topology of an ARM System. 1549 1550config SCHED_MC 1551 bool "Multi-core scheduler support" 1552 depends on ARM_CPU_TOPOLOGY 1553 help 1554 Multi-core scheduler support improves the CPU scheduler's decision 1555 making when dealing with multi-core CPU chips at a cost of slightly 1556 increased overhead in some places. If unsure say N here. 1557 1558config SCHED_SMT 1559 bool "SMT scheduler support" 1560 depends on ARM_CPU_TOPOLOGY 1561 help 1562 Improves the CPU scheduler's decision making when dealing with 1563 MultiThreading at a cost of slightly increased overhead in some 1564 places. If unsure say N here. 1565 1566config HAVE_ARM_SCU 1567 bool 1568 help 1569 This option enables support for the ARM system coherency unit 1570 1571config ARM_ARCH_TIMER 1572 bool "Architected timer support" 1573 depends on CPU_V7 1574 help 1575 This option enables support for the ARM architected timer 1576 1577config HAVE_ARM_TWD 1578 bool 1579 depends on SMP 1580 help 1581 This options enables support for the ARM timer and watchdog unit 1582 1583choice 1584 prompt "Memory split" 1585 default VMSPLIT_3G 1586 help 1587 Select the desired split between kernel and user memory. 1588 1589 If you are not absolutely sure what you are doing, leave this 1590 option alone! 1591 1592 config VMSPLIT_3G 1593 bool "3G/1G user/kernel split" 1594 config VMSPLIT_2G 1595 bool "2G/2G user/kernel split" 1596 config VMSPLIT_1G 1597 bool "1G/3G user/kernel split" 1598endchoice 1599 1600config PAGE_OFFSET 1601 hex 1602 default 0x40000000 if VMSPLIT_1G 1603 default 0x80000000 if VMSPLIT_2G 1604 default 0xC0000000 1605 1606config NR_CPUS 1607 int "Maximum number of CPUs (2-32)" 1608 range 2 32 1609 depends on SMP 1610 default "4" 1611 1612config HOTPLUG_CPU 1613 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1614 depends on SMP && HOTPLUG && EXPERIMENTAL 1615 help 1616 Say Y here to experiment with turning CPUs off and on. CPUs 1617 can be controlled through /sys/devices/system/cpu. 1618 1619config LOCAL_TIMERS 1620 bool "Use local timer interrupts" 1621 depends on SMP 1622 default y 1623 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1624 help 1625 Enable support for local timers on SMP platforms, rather then the 1626 legacy IPI broadcast method. Local timers allows the system 1627 accounting to be spread across the timer interval, preventing a 1628 "thundering herd" at every timer tick. 1629 1630config ARCH_NR_GPIO 1631 int 1632 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1633 default 355 if ARCH_U8500 1634 default 264 if MACH_H4700 1635 default 512 if SOC_OMAP5 1636 default 0 1637 help 1638 Maximum number of GPIOs in the system. 1639 1640 If unsure, leave the default value. 1641 1642source kernel/Kconfig.preempt 1643 1644config HZ 1645 int 1646 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1647 ARCH_S5PV210 || ARCH_EXYNOS4 1648 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1649 default AT91_TIMER_HZ if ARCH_AT91 1650 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1651 default 100 1652 1653config THUMB2_KERNEL 1654 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1655 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1656 select AEABI 1657 select ARM_ASM_UNIFIED 1658 select ARM_UNWIND 1659 help 1660 By enabling this option, the kernel will be compiled in 1661 Thumb-2 mode. A compiler/assembler that understand the unified 1662 ARM-Thumb syntax is needed. 1663 1664 If unsure, say N. 1665 1666config THUMB2_AVOID_R_ARM_THM_JUMP11 1667 bool "Work around buggy Thumb-2 short branch relocations in gas" 1668 depends on THUMB2_KERNEL && MODULES 1669 default y 1670 help 1671 Various binutils versions can resolve Thumb-2 branches to 1672 locally-defined, preemptible global symbols as short-range "b.n" 1673 branch instructions. 1674 1675 This is a problem, because there's no guarantee the final 1676 destination of the symbol, or any candidate locations for a 1677 trampoline, are within range of the branch. For this reason, the 1678 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1679 relocation in modules at all, and it makes little sense to add 1680 support. 1681 1682 The symptom is that the kernel fails with an "unsupported 1683 relocation" error when loading some modules. 1684 1685 Until fixed tools are available, passing 1686 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1687 code which hits this problem, at the cost of a bit of extra runtime 1688 stack usage in some cases. 1689 1690 The problem is described in more detail at: 1691 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1692 1693 Only Thumb-2 kernels are affected. 1694 1695 Unless you are sure your tools don't have this problem, say Y. 1696 1697config ARM_ASM_UNIFIED 1698 bool 1699 1700config AEABI 1701 bool "Use the ARM EABI to compile the kernel" 1702 help 1703 This option allows for the kernel to be compiled using the latest 1704 ARM ABI (aka EABI). This is only useful if you are using a user 1705 space environment that is also compiled with EABI. 1706 1707 Since there are major incompatibilities between the legacy ABI and 1708 EABI, especially with regard to structure member alignment, this 1709 option also changes the kernel syscall calling convention to 1710 disambiguate both ABIs and allow for backward compatibility support 1711 (selected with CONFIG_OABI_COMPAT). 1712 1713 To use this you need GCC version 4.0.0 or later. 1714 1715config OABI_COMPAT 1716 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1717 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1718 default y 1719 help 1720 This option preserves the old syscall interface along with the 1721 new (ARM EABI) one. It also provides a compatibility layer to 1722 intercept syscalls that have structure arguments which layout 1723 in memory differs between the legacy ABI and the new ARM EABI 1724 (only for non "thumb" binaries). This option adds a tiny 1725 overhead to all syscalls and produces a slightly larger kernel. 1726 If you know you'll be using only pure EABI user space then you 1727 can say N here. If this option is not selected and you attempt 1728 to execute a legacy ABI binary then the result will be 1729 UNPREDICTABLE (in fact it can be predicted that it won't work 1730 at all). If in doubt say Y. 1731 1732config ARCH_HAS_HOLES_MEMORYMODEL 1733 bool 1734 1735config ARCH_SPARSEMEM_ENABLE 1736 bool 1737 1738config ARCH_SPARSEMEM_DEFAULT 1739 def_bool ARCH_SPARSEMEM_ENABLE 1740 1741config ARCH_SELECT_MEMORY_MODEL 1742 def_bool ARCH_SPARSEMEM_ENABLE 1743 1744config HAVE_ARCH_PFN_VALID 1745 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1746 1747config HIGHMEM 1748 bool "High Memory Support" 1749 depends on MMU 1750 help 1751 The address space of ARM processors is only 4 Gigabytes large 1752 and it has to accommodate user address space, kernel address 1753 space as well as some memory mapped IO. That means that, if you 1754 have a large amount of physical memory and/or IO, not all of the 1755 memory can be "permanently mapped" by the kernel. The physical 1756 memory that is not permanently mapped is called "high memory". 1757 1758 Depending on the selected kernel/user memory split, minimum 1759 vmalloc space and actual amount of RAM, you may not need this 1760 option which should result in a slightly faster kernel. 1761 1762 If unsure, say n. 1763 1764config HIGHPTE 1765 bool "Allocate 2nd-level pagetables from highmem" 1766 depends on HIGHMEM 1767 1768config HW_PERF_EVENTS 1769 bool "Enable hardware performance counter support for perf events" 1770 depends on PERF_EVENTS && CPU_HAS_PMU 1771 default y 1772 help 1773 Enable hardware performance counter support for perf events. If 1774 disabled, perf events will use software events only. 1775 1776source "mm/Kconfig" 1777 1778config FORCE_MAX_ZONEORDER 1779 int "Maximum zone order" if ARCH_SHMOBILE 1780 range 11 64 if ARCH_SHMOBILE 1781 default "9" if SA1111 1782 default "11" 1783 help 1784 The kernel memory allocator divides physically contiguous memory 1785 blocks into "zones", where each zone is a power of two number of 1786 pages. This option selects the largest power of two that the kernel 1787 keeps in the memory allocator. If you need to allocate very large 1788 blocks of physically contiguous memory, then you may need to 1789 increase this value. 1790 1791 This config option is actually maximum order plus one. For example, 1792 a value of 11 means that the largest free memory block is 2^10 pages. 1793 1794config LEDS 1795 bool "Timer and CPU usage LEDs" 1796 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1797 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1798 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1799 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1800 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1801 ARCH_AT91 || ARCH_DAVINCI || \ 1802 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1803 help 1804 If you say Y here, the LEDs on your machine will be used 1805 to provide useful information about your current system status. 1806 1807 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1808 be able to select which LEDs are active using the options below. If 1809 you are compiling a kernel for the EBSA-110 or the LART however, the 1810 red LED will simply flash regularly to indicate that the system is 1811 still functional. It is safe to say Y here if you have a CATS 1812 system, but the driver will do nothing. 1813 1814config LEDS_TIMER 1815 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1816 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1817 || MACH_OMAP_PERSEUS2 1818 depends on LEDS 1819 depends on !GENERIC_CLOCKEVENTS 1820 default y if ARCH_EBSA110 1821 help 1822 If you say Y here, one of the system LEDs (the green one on the 1823 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1824 will flash regularly to indicate that the system is still 1825 operational. This is mainly useful to kernel hackers who are 1826 debugging unstable kernels. 1827 1828 The LART uses the same LED for both Timer LED and CPU usage LED 1829 functions. You may choose to use both, but the Timer LED function 1830 will overrule the CPU usage LED. 1831 1832config LEDS_CPU 1833 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1834 !ARCH_OMAP) \ 1835 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1836 || MACH_OMAP_PERSEUS2 1837 depends on LEDS 1838 help 1839 If you say Y here, the red LED will be used to give a good real 1840 time indication of CPU usage, by lighting whenever the idle task 1841 is not currently executing. 1842 1843 The LART uses the same LED for both Timer LED and CPU usage LED 1844 functions. You may choose to use both, but the Timer LED function 1845 will overrule the CPU usage LED. 1846 1847config ALIGNMENT_TRAP 1848 bool 1849 depends on CPU_CP15_MMU 1850 default y if !ARCH_EBSA110 1851 select HAVE_PROC_CPU if PROC_FS 1852 help 1853 ARM processors cannot fetch/store information which is not 1854 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1855 address divisible by 4. On 32-bit ARM processors, these non-aligned 1856 fetch/store instructions will be emulated in software if you say 1857 here, which has a severe performance impact. This is necessary for 1858 correct operation of some network protocols. With an IP-only 1859 configuration it is safe to say N, otherwise say Y. 1860 1861config UACCESS_WITH_MEMCPY 1862 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1863 depends on MMU && EXPERIMENTAL 1864 default y if CPU_FEROCEON 1865 help 1866 Implement faster copy_to_user and clear_user methods for CPU 1867 cores where a 8-word STM instruction give significantly higher 1868 memory write throughput than a sequence of individual 32bit stores. 1869 1870 A possible side effect is a slight increase in scheduling latency 1871 between threads sharing the same address space if they invoke 1872 such copy operations with large buffers. 1873 1874 However, if the CPU data cache is using a write-allocate mode, 1875 this option is unlikely to provide any performance gain. 1876 1877config SECCOMP 1878 bool 1879 prompt "Enable seccomp to safely compute untrusted bytecode" 1880 ---help--- 1881 This kernel feature is useful for number crunching applications 1882 that may need to compute untrusted bytecode during their 1883 execution. By using pipes or other transports made available to 1884 the process as file descriptors supporting the read/write 1885 syscalls, it's possible to isolate those applications in 1886 their own address space using seccomp. Once seccomp is 1887 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1888 and the task is only allowed to execute a few safe syscalls 1889 defined by each seccomp mode. 1890 1891config CC_STACKPROTECTOR 1892 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1893 depends on EXPERIMENTAL 1894 help 1895 This option turns on the -fstack-protector GCC feature. This 1896 feature puts, at the beginning of functions, a canary value on 1897 the stack just before the return address, and validates 1898 the value just before actually returning. Stack based buffer 1899 overflows (that need to overwrite this return address) now also 1900 overwrite the canary, which gets detected and the attack is then 1901 neutralized via a kernel panic. 1902 This feature requires gcc version 4.2 or above. 1903 1904config DEPRECATED_PARAM_STRUCT 1905 bool "Provide old way to pass kernel parameters" 1906 help 1907 This was deprecated in 2001 and announced to live on for 5 years. 1908 Some old boot loaders still use this way. 1909 1910endmenu 1911 1912menu "Boot options" 1913 1914config USE_OF 1915 bool "Flattened Device Tree support" 1916 select OF 1917 select OF_EARLY_FLATTREE 1918 select IRQ_DOMAIN 1919 help 1920 Include support for flattened device tree machine descriptions. 1921 1922# Compressed boot loader in ROM. Yes, we really want to ask about 1923# TEXT and BSS so we preserve their values in the config files. 1924config ZBOOT_ROM_TEXT 1925 hex "Compressed ROM boot loader base address" 1926 default "0" 1927 help 1928 The physical address at which the ROM-able zImage is to be 1929 placed in the target. Platforms which normally make use of 1930 ROM-able zImage formats normally set this to a suitable 1931 value in their defconfig file. 1932 1933 If ZBOOT_ROM is not enabled, this has no effect. 1934 1935config ZBOOT_ROM_BSS 1936 hex "Compressed ROM boot loader BSS address" 1937 default "0" 1938 help 1939 The base address of an area of read/write memory in the target 1940 for the ROM-able zImage which must be available while the 1941 decompressor is running. It must be large enough to hold the 1942 entire decompressed kernel plus an additional 128 KiB. 1943 Platforms which normally make use of ROM-able zImage formats 1944 normally set this to a suitable value in their defconfig file. 1945 1946 If ZBOOT_ROM is not enabled, this has no effect. 1947 1948config ZBOOT_ROM 1949 bool "Compressed boot loader in ROM/flash" 1950 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1951 help 1952 Say Y here if you intend to execute your compressed kernel image 1953 (zImage) directly from ROM or flash. If unsure, say N. 1954 1955choice 1956 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1957 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1958 default ZBOOT_ROM_NONE 1959 help 1960 Include experimental SD/MMC loading code in the ROM-able zImage. 1961 With this enabled it is possible to write the ROM-able zImage 1962 kernel image to an MMC or SD card and boot the kernel straight 1963 from the reset vector. At reset the processor Mask ROM will load 1964 the first part of the ROM-able zImage which in turn loads the 1965 rest the kernel image to RAM. 1966 1967config ZBOOT_ROM_NONE 1968 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1969 help 1970 Do not load image from SD or MMC 1971 1972config ZBOOT_ROM_MMCIF 1973 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1974 help 1975 Load image from MMCIF hardware block. 1976 1977config ZBOOT_ROM_SH_MOBILE_SDHI 1978 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1979 help 1980 Load image from SDHI hardware block 1981 1982endchoice 1983 1984config ARM_APPENDED_DTB 1985 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1986 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1987 help 1988 With this option, the boot code will look for a device tree binary 1989 (DTB) appended to zImage 1990 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1991 1992 This is meant as a backward compatibility convenience for those 1993 systems with a bootloader that can't be upgraded to accommodate 1994 the documented boot protocol using a device tree. 1995 1996 Beware that there is very little in terms of protection against 1997 this option being confused by leftover garbage in memory that might 1998 look like a DTB header after a reboot if no actual DTB is appended 1999 to zImage. Do not leave this option active in a production kernel 2000 if you don't intend to always append a DTB. Proper passing of the
2001 location into r2 of a bootloader provided DTB is always preferable 2002 to this option. 2003 2004config ARM_ATAG_DTB_COMPAT 2005 bool "Supplement the appended DTB with traditional ATAG information" 2006 depends on ARM_APPENDED_DTB 2007 help 2008 Some old bootloaders can't be updated to a DTB capable one, yet 2009 they provide ATAGs with memory configuration, the ramdisk address, 2010 the kernel cmdline string, etc. Such information is dynamically 2011 provided by the bootloader and can't always be stored in a static 2012 DTB. To allow a device tree enabled kernel to be used with such 2013 bootloaders, this option allows zImage to extract the information 2014 from the ATAG list and store it at run time into the appended DTB. 2015 2016choice 2017 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 2018 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 2019 2020config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 2021 bool "Use bootloader kernel arguments if available" 2022 help 2023 Uses the command-line options passed by the boot loader instead of 2024 the device tree bootargs property. If the boot loader doesn't provide 2025 any, the device tree bootargs property will be used. 2026 2027config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 2028 bool "Extend with bootloader kernel arguments" 2029 help 2030 The command-line arguments provided by the boot loader will be 2031 appended to the the device tree bootargs property. 2032 2033endchoice 2034 2035config CMDLINE 2036 string "Default kernel command string" 2037 default "" 2038 help 2039 On some architectures (EBSA110 and CATS), there is currently no way 2040 for the boot loader to pass arguments to the kernel. For these 2041 architectures, you should supply some command-line options at build 2042 time by entering them here. As a minimum, you should specify the 2043 memory size and the root device (e.g., mem=64M root=/dev/nfs). 2044 2045choice 2046 prompt "Kernel command line type" if CMDLINE != "" 2047 default CMDLINE_FROM_BOOTLOADER 2048 2049config CMDLINE_FROM_BOOTLOADER 2050 bool "Use bootloader kernel arguments if available" 2051 help 2052 Uses the command-line options passed by the boot loader. If 2053 the boot loader doesn't provide any, the default kernel command 2054 string provided in CMDLINE will be used. 2055 2056config CMDLINE_EXTEND 2057 bool "Extend bootloader kernel arguments" 2058 help 2059 The command-line arguments provided by the boot loader will be 2060 appended to the default kernel command string. 2061 2062config CMDLINE_FORCE 2063 bool "Always use the default kernel command string" 2064 help 2065 Always use the default kernel command string, even if the boot 2066 loader passes other arguments to the kernel. 2067 This is useful if you cannot or don't want to change the 2068 command-line options your boot loader passes to the kernel. 2069endchoice 2070 2071config XIP_KERNEL 2072 bool "Kernel Execute-In-Place from ROM" 2073 depends on !ZBOOT_ROM && !ARM_LPAE 2074 help 2075 Execute-In-Place allows the kernel to run from non-volatile storage 2076 directly addressable by the CPU, such as NOR flash. This saves RAM 2077 space since the text section of the kernel is not loaded from flash 2078 to RAM. Read-write sections, such as the data section and stack, 2079 are still copied to RAM. The XIP kernel is not compressed since 2080 it has to run directly from flash, so it will take more space to 2081 store it. The flash address used to link the kernel object files, 2082 and for storing it, is configuration dependent. Therefore, if you 2083 say Y here, you must know the proper physical address where to 2084 store the kernel image depending on your own flash memory usage. 2085 2086 Also note that the make target becomes "make xipImage" rather than 2087 "make zImage" or "make Image". The final kernel binary to put in 2088 ROM memory will be arch/arm/boot/xipImage. 2089 2090 If unsure, say N. 2091 2092config XIP_PHYS_ADDR 2093 hex "XIP Kernel Physical Location" 2094 depends on XIP_KERNEL 2095 default "0x00080000" 2096 help 2097 This is the physical address in your flash memory the kernel will 2098 be linked for and stored to. This address is dependent on your 2099 own flash usage. 2100 2101config KEXEC 2102 bool "Kexec system call (EXPERIMENTAL)" 2103 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2104 help 2105 kexec is a system call that implements the ability to shutdown your 2106 current kernel, and to start another kernel. It is like a reboot 2107 but it is independent of the system firmware. And like a reboot 2108 you can start any kernel with it, not just Linux. 2109 2110 It is an ongoing process to be certain the hardware in a machine 2111 is properly shutdown, so do not be surprised if this code does not 2112 initially work for you. It may help to enable device hotplugging 2113 support. 2114 2115config ATAGS_PROC 2116 bool "Export atags in procfs" 2117 depends on KEXEC 2118 default y 2119 help 2120 Should the atags used to boot the kernel be exported in an "atags" 2121 file in procfs. Useful with kexec. 2122 2123config CRASH_DUMP 2124 bool "Build kdump crash kernel (EXPERIMENTAL)" 2125 depends on EXPERIMENTAL 2126 help 2127 Generate crash dump after being started by kexec. This should 2128 be normally only set in special crash dump kernels which are 2129 loaded in the main kernel with kexec-tools into a specially 2130 reserved region and then later executed after a crash by 2131 kdump/kexec. The crash dump kernel must be compiled to a 2132 memory address not used by the main kernel 2133 2134 For more details see Documentation/kdump/kdump.txt 2135 2136config AUTO_ZRELADDR 2137 bool "Auto calculation of the decompressed kernel image address" 2138 depends on !ZBOOT_ROM && !ARCH_U300 2139 help 2140 ZRELADDR is the physical address where the decompressed kernel 2141 image will be placed. If AUTO_ZRELADDR is selected, the address 2142 will be determined at run-time by masking the current IP with 2143 0xf8000000. This assumes the zImage being placed in the first 128MB 2144 from start of memory. 2145 2146endmenu 2147 2148menu "CPU Power Management" 2149 2150if ARCH_HAS_CPUFREQ 2151 2152source "drivers/cpufreq/Kconfig" 2153 2154config CPU_FREQ_IMX 2155 tristate "CPUfreq driver for i.MX CPUs" 2156 depends on ARCH_MXC && CPU_FREQ 2157 select CPU_FREQ_TABLE 2158 help 2159 This enables the CPUfreq driver for i.MX CPUs. 2160 2161config CPU_FREQ_SA1100 2162 bool 2163 2164config CPU_FREQ_SA1110 2165 bool 2166 2167config CPU_FREQ_INTEGRATOR 2168 tristate "CPUfreq driver for ARM Integrator CPUs" 2169 depends on ARCH_INTEGRATOR && CPU_FREQ 2170 default y 2171 help 2172 This enables the CPUfreq driver for ARM Integrator CPUs. 2173 2174 For details, take a look at <file:Documentation/cpu-freq>. 2175 2176 If in doubt, say Y. 2177 2178config CPU_FREQ_PXA 2179 bool 2180 depends on CPU_FREQ && ARCH_PXA && PXA25x 2181 default y 2182 select CPU_FREQ_TABLE 2183 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2184 2185config CPU_FREQ_S3C 2186 bool 2187 help 2188 Internal configuration node for common cpufreq on Samsung SoC 2189 2190config CPU_FREQ_S3C24XX 2191 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2192 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL 2193 select CPU_FREQ_S3C 2194 help 2195 This enables the CPUfreq driver for the Samsung S3C24XX family 2196 of CPUs. 2197 2198 For details, take a look at <file:Documentation/cpu-freq>. 2199 2200 If in doubt, say N. 2201 2202config CPU_FREQ_S3C24XX_PLL 2203 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2204 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2205 help 2206 Compile in support for changing the PLL frequency from the 2207 S3C24XX series CPUfreq driver. The PLL takes time to settle 2208 after a frequency change, so by default it is not enabled. 2209 2210 This also means that the PLL tables for the selected CPU(s) will 2211 be built which may increase the size of the kernel image. 2212 2213config CPU_FREQ_S3C24XX_DEBUG 2214 bool "Debug CPUfreq Samsung driver core" 2215 depends on CPU_FREQ_S3C24XX 2216 help 2217 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2218 2219config CPU_FREQ_S3C24XX_IODEBUG 2220 bool "Debug CPUfreq Samsung driver IO timing" 2221 depends on CPU_FREQ_S3C24XX 2222 help 2223 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2224 2225config CPU_FREQ_S3C24XX_DEBUGFS 2226 bool "Export debugfs for CPUFreq" 2227 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2228 help 2229 Export status information via debugfs. 2230 2231endif 2232 2233source "drivers/cpuidle/Kconfig" 2234 2235endmenu 2236 2237menu "Floating point emulation" 2238 2239comment "At least one emulation must be selected" 2240 2241config FPE_NWFPE 2242 bool "NWFPE math emulation" 2243 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2244 ---help--- 2245 Say Y to include the NWFPE floating point emulator in the kernel. 2246 This is necessary to run most binaries. Linux does not currently 2247 support floating point hardware so you need to say Y here even if 2248 your machine has an FPA or floating point co-processor podule. 2249 2250 You may say N here if you are going to load the Acorn FPEmulator 2251 early in the bootup. 2252 2253config FPE_NWFPE_XP 2254 bool "Support extended precision" 2255 depends on FPE_NWFPE 2256 help 2257 Say Y to include 80-bit support in the kernel floating-point 2258 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2259 Note that gcc does not generate 80-bit operations by default, 2260 so in most cases this option only enlarges the size of the 2261 floating point emulator without any good reason. 2262 2263 You almost surely want to say N here. 2264 2265config FPE_FASTFPE 2266 bool "FastFPE math emulation (EXPERIMENTAL)" 2267 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2268 ---help--- 2269 Say Y here to include the FAST floating point emulator in the kernel. 2270 This is an experimental much faster emulator which now also has full 2271 precision for the mantissa. It does not support any exceptions. 2272 It is very simple, and approximately 3-6 times faster than NWFPE. 2273 2274 It should be sufficient for most programs. It may be not suitable 2275 for scientific calculations, but you have to check this for yourself. 2276 If you do not feel you need a faster FP emulation you should better 2277 choose NWFPE. 2278 2279config VFP 2280 bool "VFP-format floating point maths" 2281 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2282 help 2283 Say Y to include VFP support code in the kernel. This is needed 2284 if your hardware includes a VFP unit. 2285 2286 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2287 release notes and additional status information. 2288 2289 Say N if your target does not have VFP hardware. 2290 2291config VFPv3 2292 bool 2293 depends on VFP 2294 default y if CPU_V7 2295 2296config NEON 2297 bool "Advanced SIMD (NEON) Extension support" 2298 depends on VFPv3 && CPU_V7 2299 help 2300 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2301 Extension. 2302 2303endmenu 2304 2305menu "Userspace binary formats" 2306 2307source "fs/Kconfig.binfmt" 2308 2309config ARTHUR 2310 tristate "RISC OS personality" 2311 depends on !AEABI 2312 help 2313 Say Y here to include the kernel code necessary if you want to run 2314 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2315 experimental; if this sounds frightening, say N and sleep in peace. 2316 You can also say M here to compile this support as a module (which 2317 will be called arthur). 2318 2319endmenu 2320 2321menu "Power management options" 2322 2323source "kernel/power/Kconfig" 2324 2325config ARCH_SUSPEND_POSSIBLE 2326 depends on !ARCH_S5PC100 && !ARCH_TEGRA 2327 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2328 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2329 def_bool y 2330 2331config ARM_CPU_SUSPEND 2332 def_bool PM_SLEEP 2333 2334endmenu 2335 2336source "net/Kconfig" 2337 2338source "drivers/Kconfig" 2339 2340source "fs/Kconfig" 2341 2342source "arch/arm/Kconfig.debug" 2343 2344source "security/Kconfig" 2345 2346source "crypto/Kconfig" 2347 2348source "lib/Kconfig" 2349