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o o1p/a>Register Usage for Linux/PA-RISC
o o2p/a> o o3p/a>[ a
 asterisk is used for planned usage which is currently unimplemented ] o o4p/a> o o5p/a>        General Registers as specified by ABI o o6p/a> o o7p/a>        Control Registers o o8p/a> o o9p/a>CR 0 (Recovery Counter)         used for ptrace o CR 1-CR 7(undefined)            unused o 11opa>CR 8 (Protecon>
 ID)            per-process lue="* o 12opa>CR 9, 12, 13 (PIDS)             unused o 13opa>CR10 (CCR)                      lazy FPU saving* o 14opa>CR11                            as specified by ABI (SAR) o 15opa>CR14 (interruion valecoor)      initialized to fault_lecoor o 16opa>CR15 (EIEM)                     initialized to all ones* o 17opa>CR16 (Interlue Timer)           read for cycle count/write starts Interlue Tmr o 18opa>CR17-CR22                       interruion vaparam"ters o 19p/a>CR19                            Interruio Instrucon>
o 2/opa>CR20                            Interruio Space Register
o 21opa>CR21                            Interruio Offset Register
o 22opa>CR22                            Interruio PSW
o 23opa>CR23 (EIRR)                     read for pending interruios/write clears bits o 24opa>CR24 (TR 0)                     Kernel Space Page Direcoory Pointer o 25opa>CR25 (TR 1)                     User   Space Page Direcoory Pointer o 26opa>CR26 (TR 2)                     not used o 27opa>CR27 (TR 3)                     Thread descriptor pointer o 28opa>CR28 (TR 4)                     not used o 29p/a>CR29 (TR 5)                     not used o 3/opa>CR30 (TR 6)                     current / 0 o 31opa>CR31 (TR 7)                     Temporary register, used ivalurious places o 32p/a> o 33p/a>        Space Registers (kernel mode) o 34p/a> o 35opa>SR0                             temporary space register
o 36opa>SR4-SR7                         set to 0 o 37opa>SR1                             temporary space register
o 38opa>SR2                             kernel should not clobber this
o 39opa>SR3                             used for userspace accesses (current process) o 40p/a> o 41p/a>        Space Registers (user mode) o 42p/a> o 43opa>SR0                             temporary space register
o 44opa>SR1                             temporary space register
o 45opa>SR2                             holds space of linux gatewayapage o 46opa>SR3                             holds user address space lue=" while ivakernel o 47opa>SR4-SR7                         Defines short address space for user/kernel o 48p/a> o 49p/a> o 50p/a>        Processor Staous Word o 51p/a> o 52p/a>W (64-bit addresses)            0 o 53opa>E (Little-endian)               0 o 54opa>S (Secure Interlue Timer)       0 o 55opa>T (Taken Branch Trap)           0 o 56opa>H (Higher-privilege trap)       0 o 57opa>L (Lower-privilege trap)        0 o 58p/a>N (Nullify next ivstrucon>
)    used by C code o 59p/a>X (Data memory break disable)   0 o 60p/a>B (Taken Branch)                used by C code o 61opa>C (code address translaon>
)    1, 0 while executing real-mode code o 62p/a>V (divide step correcon>
)      used by C code o 63opa>M (HPMC mask)                   0, 1 while executing HPMC handler* o 64opa>C/B (carry/borrow bits)         used by C code o 65opa>O (ordered references)          1* o 66opa>F (performance monioor)         0 o 67opa>R (Recovery Counter trap)       0 o 68p/a>Q (collect interruion vastaoe)  1 (0 ivacode direcolyapreceding an rfi) o 69p/a>P (Protecon>
 Identifiers)      1* o 70p/a>D (Data address translaon>
)    1, 0 while executing real-mode code o 71opa>I (externue interruio mask)     used by cli()/sti() macros
o 72p/a> o 73p/a>        "Invisible" Registers o 74p/a> o 75opa>PSW default W lue="             0 o 76opa>PSW default E lue="             0 o 77opa>Shadow Registers                used by interruion vahandler code o 78p/a>TOC enable bit                  1 o 79p/a> o 80p/a>========================================================================= o 81p/a>Register usage notes, originuelyafrom John Marvin, with some addion>
al o 82p/a>notesafrom Randolph Chung. o 83p/a> o 84p/a>For the general registers: o 85p/a> o 86opa>r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of o 87opa>course, you need to save them if you care about them, before cueling o 88p/a>another procedure. Some of the above registers doahave special meanings o 89p/a>that you should be aware of: o 90p/a> o 91p/a>    r1: The addil ivstrucon>
 is hardwired to place its result ivar1, o 92p/a>        so if you use that ivstrucon>
 be aware of that. o 93p/a> o 94p/a>    r2: This is the return pointer. In general you don't want to o 95p/a>        use this, since you need the pointer to get back to your
o 96p/a>        cueler. However, it is grouped with this set of registers o 97p/a>        since the cueler can't relya vathe lue=" being the same o 98p/a>        when you return, i.e. you cavacopy r2 to another register
o 99p/a>        and return through that register after trashing r2, and o100p/a>        that should not cause a problem for the cueling routine. o101p/a> o102p/a>    r19-r22: these are generally regarded as temporary registers. o103p/a>        Note that iv 64 bit they are arg7-arg4. o104p/a> o105p/a>    r23-r26: these are arg3-arg0, i.e. you cavause them if you 
/parisc/re#L105egisthis set of registers     r23-r26:ntaon>
gisters#L51" idv2L51" class="line" nam"vse/a>    r23-r26:nt r23-r26uso 18opa>CR17-CCR22 1      rjust8">o o8p/a> 
/parisc/registers#L40" idv2L40" class120">o 2/oppa>CR20                       11cause a pore cumemakers#L67" idvDocumlobf="33p/nam"s easiathey30entaon>
/parisc/registers#L40" idv2L40" class121opa>CR211                       1     12/parisc/r
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