linux/include/video/omapdss.h
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   1/*
   2 * Copyright (C) 2008 Nokia Corporation
   3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __OMAP_OMAPDSS_H
  19#define __OMAP_OMAPDSS_H
  20
  21#include <linux/list.h>
  22#include <linux/kobject.h>
  23#include <linux/device.h>
  24
  25#define DISPC_IRQ_FRAMEDONE             (1 << 0)
  26#define DISPC_IRQ_VSYNC                 (1 << 1)
  27#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  28#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  29#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  30#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  32#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  33#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  34#define DISPC_IRQ_OCP_ERR               (1 << 9)
  35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  36#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  38#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  39#define DISPC_IRQ_SYNC_LOST             (1 << 14)
  40#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  41#define DISPC_IRQ_WAKEUP                (1 << 16)
  42#define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  43#define DISPC_IRQ_VSYNC2                (1 << 18)
  44#define DISPC_IRQ_VID3_END_WIN          (1 << 19)
  45#define DISPC_IRQ_VID3_FIFO_UNDERFLOW   (1 << 20)
  46#define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  47#define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  48#define DISPC_IRQ_FRAMEDONEWB           (1 << 23)
  49#define DISPC_IRQ_FRAMEDONETV           (1 << 24)
  50#define DISPC_IRQ_WBBUFFEROVERFLOW      (1 << 25)
  51#define DISPC_IRQ_FRAMEDONE3            (1 << 26)
  52#define DISPC_IRQ_VSYNC3                (1 << 27)
  53#define DISPC_IRQ_ACBIAS_COUNT_STAT3    (1 << 28)
  54#define DISPC_IRQ_SYNC_LOST3            (1 << 29)
  55
  56struct omap_dss_device;
  57struct omap_overlay_manager;
  58struct snd_aes_iec958;
  59struct snd_cea_861_aud_if;
  60
  61enum omap_display_type {
  62        OMAP_DISPLAY_TYPE_NONE          = 0,
  63        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  64        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  65        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  66        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  67        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  68        OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  69};
  70
  71enum omap_plane {
  72        OMAP_DSS_GFX    = 0,
  73        OMAP_DSS_VIDEO1 = 1,
  74        OMAP_DSS_VIDEO2 = 2,
  75        OMAP_DSS_VIDEO3 = 3,
  76};
  77
  78enum omap_channel {
  79        OMAP_DSS_CHANNEL_LCD    = 0,
  80        OMAP_DSS_CHANNEL_DIGIT  = 1,
  81        OMAP_DSS_CHANNEL_LCD2   = 2,
  82        OMAP_DSS_CHANNEL_LCD3   = 3,
  83};
  84
  85enum omap_color_mode {
  86        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  87        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  88        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  89        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  90        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  91        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  92        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  93        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  94        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  95        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  96        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
  97        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
  98        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
  99        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
 100        OMAP_DSS_COLOR_NV12             = 1 << 14, /* NV12 format: YUV 4:2:0 */
 101        OMAP_DSS_COLOR_RGBA16           = 1 << 15, /* RGBA16 - 4444 */
 102        OMAP_DSS_COLOR_RGBX16           = 1 << 16, /* RGBx16 - 4444 */
 103        OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16 - 1555 */
 104        OMAP_DSS_COLOR_XRGB16_1555      = 1 << 18, /* xRGB16 - 1555 */
 105};
 106
 107enum omap_dss_load_mode {
 108        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
 109        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
 110        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 111        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 112};
 113
 114enum omap_dss_trans_key_type {
 115        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 116        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 117};
 118
 119enum omap_rfbi_te_mode {
 120        OMAP_DSS_RFBI_TE_MODE_1 = 1,
 121        OMAP_DSS_RFBI_TE_MODE_2 = 2,
 122};
 123
 124enum omap_dss_signal_level {
 125        OMAPDSS_SIG_ACTIVE_HIGH = 0,
 126        OMAPDSS_SIG_ACTIVE_LOW  = 1,
 127};
 128
 129enum omap_dss_signal_edge {
 130        OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
 131        OMAPDSS_DRIVE_SIG_RISING_EDGE,
 132        OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 133};
 134
 135enum omap_dss_venc_type {
 136        OMAP_DSS_VENC_TYPE_COMPOSITE,
 137        OMAP_DSS_VENC_TYPE_SVIDEO,
 138};
 139
 140enum omap_dss_dsi_pixel_format {
 141        OMAP_DSS_DSI_FMT_RGB888,
 142        OMAP_DSS_DSI_FMT_RGB666,
 143        OMAP_DSS_DSI_FMT_RGB666_PACKED,
 144        OMAP_DSS_DSI_FMT_RGB565,
 145};
 146
 147enum omap_dss_dsi_mode {
 148        OMAP_DSS_DSI_CMD_MODE = 0,
 149        OMAP_DSS_DSI_VIDEO_MODE,
 150};
 151
 152enum omap_display_caps {
 153        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 154        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 155};
 156
 157enum omap_dss_display_state {
 158        OMAP_DSS_DISPLAY_DISABLED = 0,
 159        OMAP_DSS_DISPLAY_ACTIVE,
 160        OMAP_DSS_DISPLAY_SUSPENDED,
 161};
 162
 163enum omap_dss_audio_state {
 164        OMAP_DSS_AUDIO_DISABLED = 0,
 165        OMAP_DSS_AUDIO_ENABLED,
 166        OMAP_DSS_AUDIO_CONFIGURED,
 167        OMAP_DSS_AUDIO_PLAYING,
 168};
 169
 170enum omap_dss_rotation_type {
 171        OMAP_DSS_ROT_DMA        = 1 << 0,
 172        OMAP_DSS_ROT_VRFB       = 1 << 1,
 173        OMAP_DSS_ROT_TILER      = 1 << 2,
 174};
 175
 176/* clockwise rotation angle */
 177enum omap_dss_rotation_angle {
 178        OMAP_DSS_ROT_0   = 0,
 179        OMAP_DSS_ROT_90  = 1,
 180        OMAP_DSS_ROT_180 = 2,
 181        OMAP_DSS_ROT_270 = 3,
 182};
 183
 184enum omap_overlay_caps {
 185        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 186        OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
 187        OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
 188        OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
 189};
 190
 191enum omap_overlay_manager_caps {
 192        OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
 193};
 194
 195enum omap_dss_clk_source {
 196        OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 197                                                 * OMAP4: DSS_FCLK */
 198        OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 199                                                 * OMAP4: PLL1_CLK1 */
 200        OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 201                                                 * OMAP4: PLL1_CLK2 */
 202        OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
 203        OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
 204};
 205
 206enum omap_hdmi_flags {
 207        OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
 208};
 209
 210/* RFBI */
 211
 212struct rfbi_timings {
 213        int cs_on_time;
 214        int cs_off_time;
 215        int we_on_time;
 216        int we_off_time;
 217        int re_on_time;
 218        int re_off_time;
 219        int we_cycle_time;
 220        int re_cycle_time;
 221        int cs_pulse_width;
 222        int access_time;
 223
 224        int clk_div;
 225
 226        u32 tim[5];             /* set by rfbi_convert_timings() */
 227
 228        int converted;
 229};
 230
 231void omap_rfbi_write_command(const void *buf, u32 len);
 232void omap_rfbi_read_data(void *buf, u32 len);
 233void omap_rfbi_write_data(const void *buf, u32 len);
 234void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 235                u16 x, u16 y,
 236                u16 w, u16 h);
 237int omap_rfbi_enable_te(bool enable, unsigned line);
 238int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 239                             unsigned hs_pulse_time, unsigned vs_pulse_time,
 240                             int hs_pol_inv, int vs_pol_inv, int extif_div);
 241void rfbi_bus_lock(void);
 242void rfbi_bus_unlock(void);
 243
 244/* DSI */
 245
 246struct omap_dss_dsi_videomode_data {
 247        /* DSI video mode blanking data */
 248        /* Unit: byte clock cycles */
 249        u16 hsa;
 250        u16 hfp;
 251        u16 hbp;
 252        /* Unit: line clocks */
 253        u16 vsa;
 254        u16 vfp;
 255        u16 vbp;
 256
 257        /* DSI blanking modes */
 258        int blanking_mode;
 259        int hsa_blanking_mode;
 260        int hbp_blanking_mode;
 261        int hfp_blanking_mode;
 262
 263        /* Video port sync events */
 264        bool vp_vsync_end;
 265        bool vp_hsync_end;
 266
 267        bool ddr_clk_always_on;
 268        int window_sync;
 269};
 270
 271void dsi_bus_lock(struct omap_dss_device *dssdev);
 272void dsi_bus_unlock(struct omap_dss_device *dssdev);
 273int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 274                int len);
 275int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 276                int len);
 277int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
 278int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
 279int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 280                u8 param);
 281int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
 282                u8 param);
 283int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
 284                u8 param1, u8 param2);
 285int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 286                u8 *data, int len);
 287int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
 288                u8 *data, int len);
 289int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 290                u8 *buf, int buflen);
 291int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
 292                int buflen);
 293int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
 294                u8 *buf, int buflen);
 295int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
 296                u8 param1, u8 param2, u8 *buf, int buflen);
 297int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 298                u16 len);
 299int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 300int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 301int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
 302void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
 303
 304/* Board specific data */
 305struct omap_dss_board_info {
 306        int (*get_context_loss_count)(struct device *dev);
 307        int num_devices;
 308        struct omap_dss_device **devices;
 309        struct omap_dss_device *default_device;
 310        int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
 311        void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
 312        int (*set_min_bus_tput)(struct device *dev, unsigned long r);
 313};
 314
 315/* Init with the board info */
 316extern int omap_display_init(struct omap_dss_board_info *board_data);
 317/* HDMI mux init*/
 318extern int omap_hdmi_init(enum omap_hdmi_flags flags);
 319
 320struct omap_video_timings {
 321        /* Unit: pixels */
 322        u16 x_res;
 323        /* Unit: pixels */
 324        u16 y_res;
 325        /* Unit: KHz */
 326        u32 pixel_clock;
 327        /* Unit: pixel clocks */
 328        u16 hsw;        /* Horizontal synchronization pulse width */
 329        /* Unit: pixel clocks */
 330        u16 hfp;        /* Horizontal front porch */
 331        /* Unit: pixel clocks */
 332        u16 hbp;        /* Horizontal back porch */
 333        /* Unit: line clocks */
 334        u16 vsw;        /* Vertical synchronization pulse width */
 335        /* Unit: line clocks */
 336        u16 vfp;        /* Vertical front porch */
 337        /* Unit: line clocks */
 338        u16 vbp;        /* Vertical back porch */
 339
 340        /* Vsync logic level */
 341        enum omap_dss_signal_level vsync_level;
 342        /* Hsync logic level */
 343        enum omap_dss_signal_level hsync_level;
 344        /* Interlaced or Progressive timings */
 345        bool interlace;
 346        /* Pixel clock edge to drive LCD data */
 347        enum omap_dss_signal_edge data_pclk_edge;
 348        /* Data enable logic level */
 349        enum omap_dss_signal_level de_level;
 350        /* Pixel clock edges to drive HSYNC and VSYNC signals */
 351        enum omap_dss_signal_edge sync_pclk_edge;
 352};
 353
 354#ifdef CONFIG_OMAP2_DSS_VENC
 355/* Hardcoded timings for tv modes. Venc only uses these to
 356 * identify the mode, and does not actually use the configs
 357 * itself. However, the configs should be something that
 358 * a normal monitor can also show */
 359extern const struct omap_video_timings omap_dss_pal_timings;
 360extern const struct omap_video_timings omap_dss_ntsc_timings;
 361#endif
 362
 363struct omap_dss_cpr_coefs {
 364        s16 rr, rg, rb;
 365        s16 gr, gg, gb;
 366        s16 br, bg, bb;
 367};
 368
 369struct omap_overlay_info {
 370        u32 paddr;
 371        u32 p_uv_addr;  /* for NV12 format */
 372        u16 screen_width;
 373        u16 width;
 374        u16 height;
 375        enum omap_color_mode color_mode;
 376        u8 rotation;
 377        enum omap_dss_rotation_type rotation_type;
 378        bool mirror;
 379
 380        u16 pos_x;
 381        u16 pos_y;
 382        u16 out_width;  /* if 0, out_width == width */
 383        u16 out_height; /* if 0, out_height == height */
 384        u8 global_alpha;
 385        u8 pre_mult_alpha;
 386        u8 zorder;
 387};
 388
 389struct omap_overlay {
 390        struct kobject kobj;
 391        struct list_head list;
 392
 393        /* static fields */
 394        const char *name;
 395        enum omap_plane id;
 396        enum omap_color_mode supported_modes;
 397        enum omap_overlay_caps caps;
 398
 399        /* dynamic fields */
 400        struct omap_overlay_manager *manager;
 401
 402        /*
 403         * The following functions do not block:
 404         *
 405         * is_enabled
 406         * set_overlay_info
 407         * get_overlay_info
 408         *
 409         * The rest of the functions may block and cannot be called from
 410         * interrupt context
 411         */
 412
 413        int (*enable)(struct omap_overlay *ovl);
 414        int (*disable)(struct omap_overlay *ovl);
 415        bool (*is_enabled)(struct omap_overlay *ovl);
 416
 417        int (*set_manager)(struct omap_overlay *ovl,
 418                struct omap_overlay_manager *mgr);
 419        int (*unset_manager)(struct omap_overlay *ovl);
 420
 421        int (*set_overlay_info)(struct omap_overlay *ovl,
 422                        struct omap_overlay_info *info);
 423        void (*get_overlay_info)(struct omap_overlay *ovl,
 424                        struct omap_overlay_info *info);
 425
 426        int (*wait_for_go)(struct omap_overlay *ovl);
 427};
 428
 429struct omap_overlay_manager_info {
 430        u32 default_color;
 431
 432        enum omap_dss_trans_key_type trans_key_type;
 433        u32 trans_key;
 434        bool trans_enabled;
 435
 436        bool partial_alpha_enabled;
 437
 438        bool cpr_enable;
 439        struct omap_dss_cpr_coefs cpr_coefs;
 440};
 441
 442struct omap_overlay_manager {
 443        struct kobject kobj;
 444
 445        /* static fields */
 446        const char *name;
 447        enum omap_channel id;
 448        enum omap_overlay_manager_caps caps;
 449        struct list_head overlays;
 450        enum omap_display_type supported_displays;
 451
 452        /* dynamic fields */
 453        struct omap_dss_device *device;
 454
 455        /*
 456         * The following functions do not block:
 457         *
 458         * set_manager_info
 459         * get_manager_info
 460         * apply
 461         *
 462         * The rest of the functions may block and cannot be called from
 463         * interrupt context
 464         */
 465
 466        int (*set_device)(struct omap_overlay_manager *mgr,
 467                struct omap_dss_device *dssdev);
 468        int (*unset_device)(struct omap_overlay_manager *mgr);
 469
 470        int (*set_manager_info)(struct omap_overlay_manager *mgr,
 471                        struct omap_overlay_manager_info *info);
 472        void (*get_manager_info)(struct omap_overlay_manager *mgr,
 473                        struct omap_overlay_manager_info *info);
 474
 475        int (*apply)(struct omap_overlay_manager *mgr);
 476        int (*wait_for_go)(struct omap_overlay_manager *mgr);
 477        int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 478};
 479
 480/* 22 pins means 1 clk lane and 10 data lanes */
 481#define OMAP_DSS_MAX_DSI_PINS 22
 482
 483struct omap_dsi_pin_config {
 484        int num_pins;
 485        /*
 486         * pin numbers in the following order:
 487         * clk+, clk-
 488         * data1+, data1-
 489         * data2+, data2-
 490         * ...
 491         */
 492        int pins[OMAP_DSS_MAX_DSI_PINS];
 493};
 494
 495struct omap_dss_device {
 496        struct device dev;
 497
 498        enum omap_display_type type;
 499
 500        enum omap_channel channel;
 501
 502        union {
 503                struct {
 504                        u8 data_lines;
 505                } dpi;
 506
 507                struct {
 508                        u8 channel;
 509                        u8 data_lines;
 510                } rfbi;
 511
 512                struct {
 513                        u8 datapairs;
 514                } sdi;
 515
 516                struct {
 517                        int module;
 518
 519                        bool ext_te;
 520                        u8 ext_te_gpio;
 521                } dsi;
 522
 523                struct {
 524                        enum omap_dss_venc_type type;
 525                        bool invert_polarity;
 526                } venc;
 527        } phy;
 528
 529        struct {
 530                struct {
 531                        struct {
 532                                u16 lck_div;
 533                                u16 pck_div;
 534                                enum omap_dss_clk_source lcd_clk_src;
 535                        } channel;
 536
 537                        enum omap_dss_clk_source dispc_fclk_src;
 538                } dispc;
 539
 540                struct {
 541                        /* regn is one greater than TRM's REGN value */
 542                        u16 regn;
 543                        u16 regm;
 544                        u16 regm_dispc;
 545                        u16 regm_dsi;
 546
 547                        u16 lp_clk_div;
 548                        enum omap_dss_clk_source dsi_fclk_src;
 549                } dsi;
 550
 551                struct {
 552                        /* regn is one greater than TRM's REGN value */
 553                        u16 regn;
 554                        u16 regm2;
 555                } hdmi;
 556        } clocks;
 557
 558        struct {
 559                struct omap_video_timings timings;
 560
 561                int acbi;       /* ac-bias pin transitions per interrupt */
 562                /* Unit: line clocks */
 563                int acb;        /* ac-bias pin frequency */
 564
 565                enum omap_dss_dsi_pixel_format dsi_pix_fmt;
 566                enum omap_dss_dsi_mode dsi_mode;
 567                struct omap_dss_dsi_videomode_data dsi_vm_data;
 568        } panel;
 569
 570        struct {
 571                u8 pixel_size;
 572                struct rfbi_timings rfbi_timings;
 573        } ctrl;
 574
 575        int reset_gpio;
 576
 577        int max_backlight_level;
 578
 579        const char *name;
 580
 581        /* used to match device to driver */
 582        const char *driver_name;
 583
 584        void *data;
 585
 586        struct omap_dss_driver *driver;
 587
 588        /* helper variable for driver suspend/resume */
 589        bool activate_after_resume;
 590
 591        enum omap_display_caps caps;
 592
 593        struct omap_overlay_manager *manager;
 594
 595        enum omap_dss_display_state state;
 596
 597        enum omap_dss_audio_state audio_state;
 598
 599        /* platform specific  */
 600        int (*platform_enable)(struct omap_dss_device *dssdev);
 601        void (*platform_disable)(struct omap_dss_device *dssdev);
 602        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 603        int (*get_backlight)(struct omap_dss_device *dssdev);
 604};
 605
 606struct omap_dss_hdmi_data
 607{
 608        int hpd_gpio;
 609};
 610
 611struct omap_dss_audio {
 612        struct snd_aes_iec958 *iec;
 613        struct snd_cea_861_aud_if *cea;
 614};
 615
 616struct omap_dss_driver {
 617        struct device_driver driver;
 618
 619        int (*probe)(struct omap_dss_device *);
 620        void (*remove)(struct omap_dss_device *);
 621
 622        int (*enable)(struct omap_dss_device *display);
 623        void (*disable)(struct omap_dss_device *display);
 624        int (*suspend)(struct omap_dss_device *display);
 625        int (*resume)(struct omap_dss_device *display);
 626        int (*run_test)(struct omap_dss_device *display, int test);
 627
 628        int (*update)(struct omap_dss_device *dssdev,
 629                               u16 x, u16 y, u16 w, u16 h);
 630        int (*sync)(struct omap_dss_device *dssdev);
 631
 632        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 633        int (*get_te)(struct omap_dss_device *dssdev);
 634
 635        u8 (*get_rotate)(struct omap_dss_device *dssdev);
 636        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 637
 638        bool (*get_mirror)(struct omap_dss_device *dssdev);
 639        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 640
 641        int (*memory_read)(struct omap_dss_device *dssdev,
 642                        void *buf, size_t size,
 643                        u16 x, u16 y, u16 w, u16 h);
 644
 645        void (*get_resolution)(struct omap_dss_device *dssdev,
 646                        u16 *xres, u16 *yres);
 647        void (*get_dimensions)(struct omap_dss_device *dssdev,
 648                        u32 *width, u32 *height);
 649        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 650
 651        int (*check_timings)(struct omap_dss_device *dssdev,
 652                        struct omap_video_timings *timings);
 653        void (*set_timings)(struct omap_dss_device *dssdev,
 654                        struct omap_video_timings *timings);
 655        void (*get_timings)(struct omap_dss_device *dssdev,
 656                        struct omap_video_timings *timings);
 657
 658        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 659        u32 (*get_wss)(struct omap_dss_device *dssdev);
 660
 661        int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
 662        bool (*detect)(struct omap_dss_device *dssdev);
 663
 664        /*
 665         * For display drivers that support audio. This encompasses
 666         * HDMI and DisplayPort at the moment.
 667         */
 668        /*
 669         * Note: These functions might sleep. Do not call while
 670         * holding a spinlock/readlock.
 671         */
 672        int (*audio_enable)(struct omap_dss_device *dssdev);
 673        void (*audio_disable)(struct omap_dss_device *dssdev);
 674        bool (*audio_supported)(struct omap_dss_device *dssdev);
 675        int (*audio_config)(struct omap_dss_device *dssdev,
 676                struct omap_dss_audio *audio);
 677        /* Note: These functions may not sleep */
 678        int (*audio_start)(struct omap_dss_device *dssdev);
 679        void (*audio_stop)(struct omap_dss_device *dssdev);
 680
 681};
 682
 683int omap_dss_register_driver(struct omap_dss_driver *);
 684void omap_dss_unregister_driver(struct omap_dss_driver *);
 685
 686void omap_dss_get_device(struct omap_dss_device *dssdev);
 687void omap_dss_put_device(struct omap_dss_device *dssdev);
 688#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 689struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 690struct omap_dss_device *omap_dss_find_device(void *data,
 691                int (*match)(struct omap_dss_device *dssdev, void *data));
 692
 693int omap_dss_start_device(struct omap_dss_device *dssdev);
 694void omap_dss_stop_device(struct omap_dss_device *dssdev);
 695
 696int omap_dss_get_num_overlay_managers(void);
 697struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 698
 699int omap_dss_get_num_overlays(void);
 700struct omap_overlay *omap_dss_get_overlay(int num);
 701
 702void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 703                u16 *xres, u16 *yres);
 704int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 705void omapdss_default_get_timings(struct omap_dss_device *dssdev,
 706                struct omap_video_timings *timings);
 707
 708typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 709int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 710int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 711
 712int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
 713int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 714                unsigned long timeout);
 715
 716#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 717#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 718
 719void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
 720                bool enable);
 721int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 722
 723int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
 724                void (*callback)(int, void *), void *data);
 725int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
 726int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
 727void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 728int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
 729                const struct omap_dsi_pin_config *pin_cfg);
 730
 731int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 732void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
 733                bool disconnect_lanes, bool enter_ulps);
 734
 735int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
 736void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
 737void dpi_set_timings(struct omap_dss_device *dssdev,
 738                        struct omap_video_timings *timings);
 739int dpi_check_timings(struct omap_dss_device *dssdev,
 740                        struct omap_video_timings *timings);
 741
 742int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
 743void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
 744
 745int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
 746void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
 747int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
 748                u16 *x, u16 *y, u16 *w, u16 *h);
 749int omap_rfbi_update(struct omap_dss_device *dssdev,
 750                u16 x, u16 y, u16 w, u16 h,
 751                void (*callback)(void *), void *data);
 752int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
 753                int data_lines);
 754
 755#endif
 756
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