linux/include/linux/pci_regs.h
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   1/*
   2 *      pci_regs.h
   3 *
   4 *      PCI standard defines
   5 *      Copyright 1994, Drew Eckhardt
   6 *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   7 *
   8 *      For more information, please consult the following manuals (look at
   9 *      http://www.pcisig.com/ for how to get them):
  10 *
  11 *      PCI BIOS Specification
  12 *      PCI Local Bus Specification
  13 *      PCI to PCI Bridge Specification
  14 *      PCI System Design Guide
  15 *
  16 *      For hypertransport information, please consult the following manuals
  17 *      from http://www.hypertransport.org
  18 *
  19 *      The Hypertransport I/O Link Specification
  20 */
  21
  22#ifndef LINUX_PCI_REGS_H
  23#define LINUX_PCI_REGS_H
  24
  25/*
  26 * Under PCI, each device has 256 bytes of configuration address space,
  27 * of which the first 64 bytes are standardized as follows:
  28 */
  29#define PCI_STD_HEADER_SIZEOF   64
  30#define PCI_VENDOR_ID           0x00    /* 16 bits */
  31#define PCI_DEVICE_ID           0x02    /* 16 bits */
  32#define PCI_COMMAND             0x04    /* 16 bits */
  33#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  34#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  35#define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  36#define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  37#define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  38#define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
  39#define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  40#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  41#define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  42#define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  43#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
  44
  45#define PCI_STATUS              0x06    /* 16 bits */
  46#define  PCI_STATUS_INTERRUPT   0x08    /* Interrupt status */
  47#define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
  48#define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
  49#define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
  50#define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  51#define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  52#define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  53#define  PCI_STATUS_DEVSEL_FAST         0x000
  54#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
  55#define  PCI_STATUS_DEVSEL_SLOW         0x400
  56#define  PCI_STATUS_SIG_TARGET_ABORT    0x800 /* Set on target abort */
  57#define  PCI_STATUS_REC_TARGET_ABORT    0x1000 /* Master ack of " */
  58#define  PCI_STATUS_REC_MASTER_ABORT    0x2000 /* Set on master abort */
  59#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000 /* Set when we drive SERR */
  60#define  PCI_STATUS_DETECTED_PARITY     0x8000 /* Set on parity error */
  61
  62#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8 revision */
  63#define PCI_REVISION_ID         0x08    /* Revision ID */
  64#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  65#define PCI_CLASS_DEVICE        0x0a    /* Device class */
  66
  67#define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  68#define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  69#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  70#define  PCI_HEADER_TYPE_NORMAL         0
  71#define  PCI_HEADER_TYPE_BRIDGE         1
  72#define  PCI_HEADER_TYPE_CARDBUS        2
  73
  74#define PCI_BIST                0x0f    /* 8 bits */
  75#define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
  76#define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
  77#define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
  78
  79/*
  80 * Base addresses specify locations in memory or I/O space.
  81 * Decoded size can be determined by writing a value of
  82 * 0xffffffff to the register, and reading it back.  Only
  83 * 1 bits are decoded.
  84 */
  85#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  86#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
  87#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
  88#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  89#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  90#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  91#define  PCI_BASE_ADDRESS_SPACE         0x01    /* 0 = memory, 1 = I/O */
  92#define  PCI_BASE_ADDRESS_SPACE_IO      0x01
  93#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
  94#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  95#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
  96#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
  97#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
  98#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
  99#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
 100#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
 101/* bit 1 is reserved if address_space = 1 */
 102
 103/* Header type 0 (normal devices) */
 104#define PCI_CARDBUS_CIS         0x28
 105#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
 106#define PCI_SUBSYSTEM_ID        0x2e
 107#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 108#define  PCI_ROM_ADDRESS_ENABLE 0x01
 109#define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
 110
 111#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 112
 113/* 0x35-0x3b are reserved */
 114#define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 115#define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 116#define PCI_MIN_GNT             0x3e    /* 8 bits */
 117#define PCI_MAX_LAT             0x3f    /* 8 bits */
 118
 119/* Header type 1 (PCI-to-PCI bridges) */
 120#define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 121#define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 122#define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
 123#define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
 124#define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
 125#define PCI_IO_LIMIT            0x1d
 126#define  PCI_IO_RANGE_TYPE_MASK 0x0fUL  /* I/O bridging type */
 127#define  PCI_IO_RANGE_TYPE_16   0x00
 128#define  PCI_IO_RANGE_TYPE_32   0x01
 129#define  PCI_IO_RANGE_MASK      (~0x0fUL) /* Standard 4K I/O windows */
 130#define  PCI_IO_1K_RANGE_MASK   (~0x03UL) /* Intel 1K I/O windows */
 131#define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 132#define PCI_MEMORY_BASE         0x20    /* Memory range behind */
 133#define PCI_MEMORY_LIMIT        0x22
 134#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
 135#define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
 136#define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
 137#define PCI_PREF_MEMORY_LIMIT   0x26
 138#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
 139#define  PCI_PREF_RANGE_TYPE_32 0x00
 140#define  PCI_PREF_RANGE_TYPE_64 0x01
 141#define  PCI_PREF_RANGE_MASK    (~0x0fUL)
 142#define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
 143#define PCI_PREF_LIMIT_UPPER32  0x2c
 144#define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
 145#define PCI_IO_LIMIT_UPPER16    0x32
 146/* 0x34 same as for htype 0 */
 147/* 0x35-0x3b is reserved */
 148#define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 149/* 0x3c-0x3d are same as for htype 0 */
 150#define PCI_BRIDGE_CONTROL      0x3e
 151#define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
 152#define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
 153#define  PCI_BRIDGE_CTL_ISA     0x04    /* Enable ISA mode */
 154#define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
 155#define  PCI_BRIDGE_CTL_MASTER_ABORT    0x20  /* Report master aborts */
 156#define  PCI_BRIDGE_CTL_BUS_RESET       0x40    /* Secondary bus reset */
 157#define  PCI_BRIDGE_CTL_FAST_BACK       0x80    /* Fast Back2Back enabled on secondary interface */
 158
 159/* Header type 2 (CardBus bridges) */
 160#define PCI_CB_CAPABILITY_LIST  0x14
 161/* 0x15 reserved */
 162#define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
 163#define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
 164#define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
 165#define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
 166#define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
 167#define PCI_CB_MEMORY_BASE_0    0x1c
 168#define PCI_CB_MEMORY_LIMIT_0   0x20
 169#define PCI_CB_MEMORY_BASE_1    0x24
 170#define PCI_CB_MEMORY_LIMIT_1   0x28
 171#define PCI_CB_IO_BASE_0        0x2c
 172#define PCI_CB_IO_BASE_0_HI     0x2e
 173#define PCI_CB_IO_LIMIT_0       0x30
 174#define PCI_CB_IO_LIMIT_0_HI    0x32
 175#define PCI_CB_IO_BASE_1        0x34
 176#define PCI_CB_IO_BASE_1_HI     0x36
 177#define PCI_CB_IO_LIMIT_1       0x38
 178#define PCI_CB_IO_LIMIT_1_HI    0x3a
 179#define  PCI_CB_IO_RANGE_MASK   (~0x03UL)
 180/* 0x3c-0x3d are same as for htype 0 */
 181#define PCI_CB_BRIDGE_CONTROL   0x3e
 182#define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
 183#define  PCI_CB_BRIDGE_CTL_SERR         0x02
 184#define  PCI_CB_BRIDGE_CTL_ISA          0x04
 185#define  PCI_CB_BRIDGE_CTL_VGA          0x08
 186#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
 187#define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
 188#define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
 189#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
 190#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
 191#define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
 192#define PCI_CB_SUBSYSTEM_VENDOR_ID      0x40
 193#define PCI_CB_SUBSYSTEM_ID             0x42
 194#define PCI_CB_LEGACY_MODE_BASE         0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
 195/* 0x48-0x7f reserved */
 196
 197/* Capability lists */
 198
 199#define PCI_CAP_LIST_ID         0       /* Capability ID */
 200#define  PCI_CAP_ID_PM          0x01    /* Power Management */
 201#define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
 202#define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
 203#define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
 204#define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
 205#define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
 206#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 207#define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
 208#define  PCI_CAP_ID_VNDR        0x09    /* Vendor specific */
 209#define  PCI_CAP_ID_DBG         0x0A    /* Debug port */
 210#define  PCI_CAP_ID_CCRC        0x0B    /* CompactPCI Central Resource Control */
 211#define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
 212#define  PCI_CAP_ID_SSVID       0x0D    /* Bridge subsystem vendor/device ID */
 213#define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 214#define  PCI_CAP_ID_SECDEV      0x0F    /* Secure Device */
 215#define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 216#define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
 217#define  PCI_CAP_ID_SATA        0x12    /* SATA Data/Index Conf. */
 218#define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
 219#define  PCI_CAP_ID_MAX         PCI_CAP_ID_AF
 220#define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 221#define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 222#define PCI_CAP_SIZEOF          4
 223
 224/* Power Management Registers */
 225
 226#define PCI_PM_PMC              2       /* PM Capabilities Register */
 227#define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
 228#define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
 229#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
 230#define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
 231#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxiliary power support mask */
 232#define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
 233#define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
 234#define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
 235#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
 236#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
 237#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
 238#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
 239#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
 240#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
 241#define  PCI_PM_CAP_PME_SHIFT   11      /* Start of the PME Mask in PMC */
 242#define PCI_PM_CTRL             4       /* PM control and status register */
 243#define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
 244#define  PCI_PM_CTRL_NO_SOFT_RESET      0x0008  /* No reset for D3hot->D0 */
 245#define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
 246#define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
 247#define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
 248#define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
 249#define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
 250#define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
 251#define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
 252#define PCI_PM_DATA_REGISTER    7       /* (??) */
 253#define PCI_PM_SIZEOF           8
 254
 255/* AGP registers */
 256
 257#define PCI_AGP_VERSION         2       /* BCD version number */
 258#define PCI_AGP_RFU             3       /* Rest of capability flags */
 259#define PCI_AGP_STATUS          4       /* Status register */
 260#define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
 261#define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
 262#define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
 263#define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
 264#define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
 265#define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
 266#define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
 267#define PCI_AGP_COMMAND         8       /* Control register */
 268#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
 269#define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
 270#define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
 271#define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
 272#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
 273#define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
 274#define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
 275#define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
 276#define PCI_AGP_SIZEOF          12
 277
 278/* Vital Product Data */
 279
 280#define PCI_VPD_ADDR            2       /* Address to access (15 bits!) */
 281#define  PCI_VPD_ADDR_MASK      0x7fff  /* Address mask */
 282#define  PCI_VPD_ADDR_F         0x8000  /* Write 0, 1 indicates completion */
 283#define PCI_VPD_DATA            4       /* 32-bits of data returned here */
 284#define PCI_CAP_VPD_SIZEOF      8
 285
 286/* Slot Identification */
 287
 288#define PCI_SID_ESR             2       /* Expansion Slot Register */
 289#define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
 290#define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
 291#define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
 292
 293/* Message Signalled Interrupts registers */
 294
 295#define PCI_MSI_FLAGS           2       /* Various flags */
 296#define  PCI_MSI_FLAGS_64BIT    0x80    /* 64-bit addresses allowed */
 297#define  PCI_MSI_FLAGS_QSIZE    0x70    /* Message queue size configured */
 298#define  PCI_MSI_FLAGS_QMASK    0x0e    /* Maximum queue size available */
 299#define  PCI_MSI_FLAGS_ENABLE   0x01    /* MSI feature enabled */
 300#define  PCI_MSI_FLAGS_MASKBIT  0x100   /* 64-bit mask bits allowed */
 301#define PCI_MSI_RFU             3       /* Rest of capability flags */
 302#define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
 303#define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 304#define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
 305#define PCI_MSI_MASK_32         12      /* Mask bits register for 32-bit devices */
 306#define PCI_MSI_PENDING_32      16      /* Pending intrs for 32-bit devices */
 307#define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
 308#define PCI_MSI_MASK_64         16      /* Mask bits register for 64-bit devices */
 309#define PCI_MSI_PENDING_64      20      /* Pending intrs for 64-bit devices */
 310
 311/* MSI-X registers */
 312#define PCI_MSIX_FLAGS          2
 313#define  PCI_MSIX_FLAGS_QSIZE   0x7FF
 314#define  PCI_MSIX_FLAGS_ENABLE  (1 << 15)
 315#define  PCI_MSIX_FLAGS_MASKALL (1 << 14)
 316#define PCI_MSIX_TABLE          4
 317#define PCI_MSIX_PBA            8
 318#define  PCI_MSIX_FLAGS_BIRMASK (7 << 0)
 319#define PCI_CAP_MSIX_SIZEOF     12      /* size of MSIX registers */
 320
 321/* MSI-X entry's format */
 322#define PCI_MSIX_ENTRY_SIZE             16
 323#define  PCI_MSIX_ENTRY_LOWER_ADDR      0
 324#define  PCI_MSIX_ENTRY_UPPER_ADDR      4
 325#define  PCI_MSIX_ENTRY_DATA            8
 326#define  PCI_MSIX_ENTRY_VECTOR_CTRL     12
 327#define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1
 328
 329/* CompactPCI Hotswap Register */
 330
 331#define PCI_CHSWP_CSR           2       /* Control and Status Register */
 332#define  PCI_CHSWP_DHA          0x01    /* Device Hiding Arm */
 333#define  PCI_CHSWP_EIM          0x02    /* ENUM# Signal Mask */
 334#define  PCI_CHSWP_PIE          0x04    /* Pending Insert or Extract */
 335#define  PCI_CHSWP_LOO          0x08    /* LED On / Off */
 336#define  PCI_CHSWP_PI           0x30    /* Programming Interface */
 337#define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
 338#define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
 339
 340/* PCI Advanced Feature registers */
 341
 342#define PCI_AF_LENGTH           2
 343#define PCI_AF_CAP              3
 344#define  PCI_AF_CAP_TP          0x01
 345#define  PCI_AF_CAP_FLR         0x02
 346#define PCI_AF_CTRL             4
 347#define  PCI_AF_CTRL_FLR        0x01
 348#define PCI_AF_STATUS           5
 349#define  PCI_AF_STATUS_TP       0x01
 350#define PCI_CAP_AF_SIZEOF       6       /* size of AF registers */
 351
 352/* PCI-X registers */
 353
 354#define PCI_X_CMD               2       /* Modes & Features */
 355#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
 356#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
 357#define  PCI_X_CMD_READ_512     0x0000  /* 512 byte maximum read byte count */
 358#define  PCI_X_CMD_READ_1K      0x0004  /* 1Kbyte maximum read byte count */
 359#define  PCI_X_CMD_READ_2K      0x0008  /* 2Kbyte maximum read byte count */
 360#define  PCI_X_CMD_READ_4K      0x000c  /* 4Kbyte maximum read byte count */
 361#define  PCI_X_CMD_MAX_READ     0x000c  /* Max Memory Read Byte Count */
 362                                /* Max # of outstanding split transactions */
 363#define  PCI_X_CMD_SPLIT_1      0x0000  /* Max 1 */
 364#define  PCI_X_CMD_SPLIT_2      0x0010  /* Max 2 */
 365#define  PCI_X_CMD_SPLIT_3      0x0020  /* Max 3 */
 366#define  PCI_X_CMD_SPLIT_4      0x0030  /* Max 4 */
 367#define  PCI_X_CMD_SPLIT_8      0x0040  /* Max 8 */
 368#define  PCI_X_CMD_SPLIT_12     0x0050  /* Max 12 */
 369#define  PCI_X_CMD_SPLIT_16     0x0060  /* Max 16 */
 370#define  PCI_X_CMD_SPLIT_32     0x0070  /* Max 32 */
 371#define  PCI_X_CMD_MAX_SPLIT    0x0070  /* Max Outstanding Split Transactions */
 372#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 373#define PCI_X_STATUS            4       /* PCI-X capabilities */
 374#define  PCI_X_STATUS_DEVFN     0x000000ff      /* A copy of devfn */
 375#define  PCI_X_STATUS_BUS       0x0000ff00      /* A copy of bus nr */
 376#define  PCI_X_STATUS_64BIT     0x00010000      /* 64-bit device */
 377#define  PCI_X_STATUS_133MHZ    0x00020000      /* 133 MHz capable */
 378#define  PCI_X_STATUS_SPL_DISC  0x00040000      /* Split Completion Discarded */
 379#define  PCI_X_STATUS_UNX_SPL   0x00080000      /* Unexpected Split Completion */
 380#define  PCI_X_STATUS_COMPLEX   0x00100000      /* Device Complexity */
 381#define  PCI_X_STATUS_MAX_READ  0x00600000      /* Designed Max Memory Read Count */
 382#define  PCI_X_STATUS_MAX_SPLIT 0x03800000      /* Designed Max Outstanding Split Transactions */
 383#define  PCI_X_STATUS_MAX_CUM   0x1c000000      /* Designed Max Cumulative Read Size */
 384#define  PCI_X_STATUS_SPL_ERR   0x20000000      /* Rcvd Split Completion Error Msg */
 385#define  PCI_X_STATUS_266MHZ    0x40000000      /* 266 MHz capable */
 386#define  PCI_X_STATUS_533MHZ    0x80000000      /* 533 MHz capable */
 387#define PCI_X_ECC_CSR           8       /* ECC control and status */
 388#define PCI_CAP_PCIX_SIZEOF_V0  8       /* size of registers for Version 0 */
 389#define PCI_CAP_PCIX_SIZEOF_V1  24      /* size for Version 1 */
 390#define PCI_CAP_PCIX_SIZEOF_V2  PCI_CAP_PCIX_SIZEOF_V1  /* Same for v2 */
 391
 392/* PCI Bridge Subsystem ID registers */
 393
 394#define PCI_SSVID_VENDOR_ID     4       /* PCI-Bridge subsystem vendor id register */
 395#define PCI_SSVID_DEVICE_ID     6       /* PCI-Bridge subsystem device id register */
 396
 397/* PCI Express capability registers */
 398
 399#define PCI_EXP_FLAGS           2       /* Capabilities register */
 400#define PCI_EXP_FLAGS_VERS      0x000f  /* Capability version */
 401#define PCI_EXP_FLAGS_TYPE      0x00f0  /* Device/Port type */
 402#define  PCI_EXP_TYPE_ENDPOINT  0x0     /* Express Endpoint */
 403#define  PCI_EXP_TYPE_LEG_END   0x1     /* Legacy Endpoint */
 404#define  PCI_EXP_TYPE_ROOT_PORT 0x4     /* Root Port */
 405#define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 406#define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 407#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
 408#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8   /* PCI/PCI-X to PCIE Bridge */
 409#define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 410#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 411#define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 412#define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 413#define PCI_EXP_DEVCAP          4       /* Device capabilities */
 414#define  PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
 415#define  PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
 416#define  PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
 417#define  PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
 418#define  PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
 419#define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
 420#define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
 421#define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
 422#define  PCI_EXP_DEVCAP_RBER    0x8000  /* Role-Based Error Reporting */
 423#define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
 424#define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
 425#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 426#define PCI_EXP_DEVCTL          8       /* Device Control */
 427#define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
 428#define  PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
 429#define  PCI_EXP_DEVCTL_FERE    0x0004  /* Fatal Error Reporting Enable */
 430#define  PCI_EXP_DEVCTL_URRE    0x0008  /* Unsupported Request Reporting En. */
 431#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
 432#define  PCI_EXP_DEVCTL_PAYLOAD 0x00e0  /* Max_Payload_Size */
 433#define  PCI_EXP_DEVCTL_EXT_TAG 0x0100  /* Extended Tag Field Enable */
 434#define  PCI_EXP_DEVCTL_PHANTOM 0x0200  /* Phantom Functions Enable */
 435#define  PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
 436#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 437#define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
 438#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 439#define PCI_EXP_DEVSTA          10      /* Device Status */
 440#define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
 441#define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
 442#define  PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
 443#define  PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
 444#define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
 445#define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
 446#define PCI_EXP_LNKCAP          12      /* Link Capabilities */
 447#define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
 448#define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
 449#define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 450#define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
 451#define  PCI_EXP_LNKCAP_L1EL    0x00038000 /* L1 Exit Latency */
 452#define  PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */
 453#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Surprise Down Error Reporting Capable */
 454#define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
 455#define  PCI_EXP_LNKCAP_LBNC    0x00200000 /* Link Bandwidth Notification Capability */
 456#define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 457#define PCI_EXP_LNKCTL          16      /* Link Control */
 458#define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
 459#define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
 460#define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
 461#define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
 462#define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
 463#define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
 464#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
 465#define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
 466#define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
 467#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 468#define PCI_EXP_LNKSTA          18      /* Link Status */
 469#define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
 470#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01  /* Current Link Speed 2.5GT/s */
 471#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02  /* Current Link Speed 5.0GT/s */
 472#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
 473#define  PCI_EXP_LNKSTA_NLW_SHIFT 4     /* start of NLW mask in link status */
 474#define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
 475#define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
 476#define  PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
 477#define  PCI_EXP_LNKSTA_LBMS    0x4000  /* Link Bandwidth Management Status */
 478#define  PCI_EXP_LNKSTA_LABS    0x8000  /* Link Autonomous Bandwidth Status */
 479#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1  20      /* v1 endpoints end here */
 480#define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
 481#define  PCI_EXP_SLTCAP_ABP     0x00000001 /* Attention Button Present */
 482#define  PCI_EXP_SLTCAP_PCP     0x00000002 /* Power Controller Present */
 483#define  PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */
 484#define  PCI_EXP_SLTCAP_AIP     0x00000008 /* Attention Indicator Present */
 485#define  PCI_EXP_SLTCAP_PIP     0x00000010 /* Power Indicator Present */
 486#define  PCI_EXP_SLTCAP_HPS     0x00000020 /* Hot-Plug Surprise */
 487#define  PCI_EXP_SLTCAP_HPC     0x00000040 /* Hot-Plug Capable */
 488#define  PCI_EXP_SLTCAP_SPLV    0x00007f80 /* Slot Power Limit Value */
 489#define  PCI_EXP_SLTCAP_SPLS    0x00018000 /* Slot Power Limit Scale */
 490#define  PCI_EXP_SLTCAP_EIP     0x00020000 /* Electromechanical Interlock Present */
 491#define  PCI_EXP_SLTCAP_NCCS    0x00040000 /* No Command Completed Support */
 492#define  PCI_EXP_SLTCAP_PSN     0xfff80000 /* Physical Slot Number */
 493#define PCI_EXP_SLTCTL          24      /* Slot Control */
 494#define  PCI_EXP_SLTCTL_ABPE    0x0001  /* Attention Button Pressed Enable */
 495#define  PCI_EXP_SLTCTL_PFDE    0x0002  /* Power Fault Detected Enable */
 496#define  PCI_EXP_SLTCTL_MRLSCE  0x0004  /* MRL Sensor Changed Enable */
 497#define  PCI_EXP_SLTCTL_PDCE    0x0008  /* Presence Detect Changed Enable */
 498#define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
 499#define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
 500#define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
 501#define  PCI_EXP_SLTCTL_PIC     0x0300  /* Power Indicator Control */
 502#define  PCI_EXP_SLTCTL_PCC     0x0400  /* Power Controller Control */
 503#define  PCI_EXP_SLTCTL_EIC     0x0800  /* Electromechanical Interlock Control */
 504#define  PCI_EXP_SLTCTL_DLLSCE  0x1000  /* Data Link Layer State Changed Enable */
 505#define PCI_EXP_SLTSTA          26      /* Slot Status */
 506#define  PCI_EXP_SLTSTA_ABP     0x0001  /* Attention Button Pressed */
 507#define  PCI_EXP_SLTSTA_PFD     0x0002  /* Power Fault Detected */
 508#define  PCI_EXP_SLTSTA_MRLSC   0x0004  /* MRL Sensor Changed */
 509#define  PCI_EXP_SLTSTA_PDC     0x0008  /* Presence Detect Changed */
 510#define  PCI_EXP_SLTSTA_CC      0x0010  /* Command Completed */
 511#define  PCI_EXP_SLTSTA_MRLSS   0x0020  /* MRL Sensor State */
 512#define  PCI_EXP_SLTSTA_PDS     0x0040  /* Presence Detect State */
 513#define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
 514#define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 515#define PCI_EXP_RTCTL           28      /* Root Control */
 516#define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
 517#define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */
 518#define  PCI_EXP_RTCTL_SEFEE    0x04    /* System Error on Fatal Error */
 519#define  PCI_EXP_RTCTL_PMEIE    0x08    /* PME Interrupt Enable */
 520#define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
 521#define PCI_EXP_RTCAP           30      /* Root Capabilities */
 522#define PCI_EXP_RTSTA           32      /* Root Status */
 523#define PCI_EXP_RTSTA_PME       0x10000 /* PME status */
 524#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
 525/*
 526 * Note that the following PCI Express 'Capability Structure' registers
 527 * were introduced with 'Capability Version' 0x2 (v2).  These registers
 528 * do not exist on devices with Capability Version 1.  Use pci_pcie_cap2()
 529 * to use these fields safely.
 530 */
 531#define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 532#define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
 533#define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
 534#define  PCI_EXP_OBFF_MASK      0xc0000 /* OBFF support mechanism */
 535#define  PCI_EXP_OBFF_MSG       0x40000 /* New message signaling */
 536#define  PCI_EXP_OBFF_WAKE      0x80000 /* Re-use WAKE# for OBFF */
 537#define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 538#define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
 539#define  PCI_EXP_IDO_REQ_EN     0x100   /* ID-based ordering request enable */
 540#define  PCI_EXP_IDO_CMP_EN     0x200   /* ID-based ordering completion enable */
 541#define  PCI_EXP_LTR_EN         0x400   /* Latency tolerance reporting */
 542#define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
 543#define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
 544#define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
 545#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2  44      /* v2 endpoints end here */
 546#define PCI_EXP_LNKCAP2         44      /* Link Capability 2 */
 547#define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
 548#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
 549#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
 550#define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
 551#define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 552#define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 553
 554/* Extended Capabilities (PCI-X 2.0 and Express) */
 555#define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
 556#define PCI_EXT_CAP_VER(header)         ((header >> 16) & 0xf)
 557#define PCI_EXT_CAP_NEXT(header)        ((header >> 20) & 0xffc)
 558
 559#define PCI_EXT_CAP_ID_ERR      0x01    /* Advanced Error Reporting */
 560#define PCI_EXT_CAP_ID_VC       0x02    /* Virtual Channel Capability */
 561#define PCI_EXT_CAP_ID_DSN      0x03    /* Device Serial Number */
 562#define PCI_EXT_CAP_ID_PWR      0x04    /* Power Budgeting */
 563#define PCI_EXT_CAP_ID_RCLD     0x05    /* Root Complex Link Declaration */
 564#define PCI_EXT_CAP_ID_RCILC    0x06    /* Root Complex Internal Link Control */
 565#define PCI_EXT_CAP_ID_RCEC     0x07    /* Root Complex Event Collector */
 566#define PCI_EXT_CAP_ID_MFVC     0x08    /* Multi-Function VC Capability */
 567#define PCI_EXT_CAP_ID_VC9      0x09    /* same as _VC */
 568#define PCI_EXT_CAP_ID_RCRB     0x0A    /* Root Complex RB? */
 569#define PCI_EXT_CAP_ID_VNDR     0x0B    /* Vendor Specific */
 570#define PCI_EXT_CAP_ID_CAC      0x0C    /* Config Access - obsolete */
 571#define PCI_EXT_CAP_ID_ACS      0x0D    /* Access Control Services */
 572#define PCI_EXT_CAP_ID_ARI      0x0E    /* Alternate Routing ID */
 573#define PCI_EXT_CAP_ID_ATS      0x0F    /* Address Translation Services */
 574#define PCI_EXT_CAP_ID_SRIOV    0x10    /* Single Root I/O Virtualization */
 575#define PCI_EXT_CAP_ID_MRIOV    0x11    /* Multi Root I/O Virtualization */
 576#define PCI_EXT_CAP_ID_MCAST    0x12    /* Multicast */
 577#define PCI_EXT_CAP_ID_PRI      0x13    /* Page Request Interface */
 578#define PCI_EXT_CAP_ID_AMD_XXX  0x14    /* reserved for AMD */
 579#define PCI_EXT_CAP_ID_REBAR    0x15    /* resizable BAR */
 580#define PCI_EXT_CAP_ID_DPA      0x16    /* dynamic power alloc */
 581#define PCI_EXT_CAP_ID_TPH      0x17    /* TPH request */
 582#define PCI_EXT_CAP_ID_LTR      0x18    /* latency tolerance reporting */
 583#define PCI_EXT_CAP_ID_SECPCI   0x19    /* Secondary PCIe */
 584#define PCI_EXT_CAP_ID_PMUX     0x1A    /* Protocol Multiplexing */
 585#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
 586#define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PASID
 587
 588#define PCI_EXT_CAP_DSN_SIZEOF  12
 589#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
 590
 591/* Advanced Error Reporting */
 592#define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
 593#define  PCI_ERR_UNC_TRAIN      0x00000001      /* Training */
 594#define  PCI_ERR_UNC_DLP        0x00000010      /* Data Link Protocol */
 595#define  PCI_ERR_UNC_SURPDN     0x00000020      /* Surprise Down */
 596#define  PCI_ERR_UNC_POISON_TLP 0x00001000      /* Poisoned TLP */
 597#define  PCI_ERR_UNC_FCP        0x00002000      /* Flow Control Protocol */
 598#define  PCI_ERR_UNC_COMP_TIME  0x00004000      /* Completion Timeout */
 599#define  PCI_ERR_UNC_COMP_ABORT 0x00008000      /* Completer Abort */
 600#define  PCI_ERR_UNC_UNX_COMP   0x00010000      /* Unexpected Completion */
 601#define  PCI_ERR_UNC_RX_OVER    0x00020000      /* Receiver Overflow */
 602#define  PCI_ERR_UNC_MALF_TLP   0x00040000      /* Malformed TLP */
 603#define  PCI_ERR_UNC_ECRC       0x00080000      /* ECRC Error Status */
 604#define  PCI_ERR_UNC_UNSUP      0x00100000      /* Unsupported Request */
 605#define  PCI_ERR_UNC_ACSV       0x00200000      /* ACS Violation */
 606#define  PCI_ERR_UNC_INTN       0x00400000      /* internal error */
 607#define  PCI_ERR_UNC_MCBTLP     0x00800000      /* MC blocked TLP */
 608#define  PCI_ERR_UNC_ATOMEG     0x01000000      /* Atomic egress blocked */
 609#define  PCI_ERR_UNC_TLPPRE     0x02000000      /* TLP prefix blocked */
 610#define PCI_ERR_UNCOR_MASK      8       /* Uncorrectable Error Mask */
 611        /* Same bits as above */
 612#define PCI_ERR_UNCOR_SEVER     12      /* Uncorrectable Error Severity */
 613        /* Same bits as above */
 614#define PCI_ERR_COR_STATUS      16      /* Correctable Error Status */
 615#define  PCI_ERR_COR_RCVR       0x00000001      /* Receiver Error Status */
 616#define  PCI_ERR_COR_BAD_TLP    0x00000040      /* Bad TLP Status */
 617#define  PCI_ERR_COR_BAD_DLLP   0x00000080      /* Bad DLLP Status */
 618#define  PCI_ERR_COR_REP_ROLL   0x00000100      /* REPLAY_NUM Rollover */
 619#define  PCI_ERR_COR_REP_TIMER  0x00001000      /* Replay Timer Timeout */
 620#define  PCI_ERR_COR_ADV_NFAT   0x00002000      /* Advisory Non-Fatal */
 621#define  PCI_ERR_COR_INTERNAL   0x00004000      /* Corrected Internal */
 622#define  PCI_ERR_COR_LOG_OVER   0x00008000      /* Header Log Overflow */
 623#define PCI_ERR_COR_MASK        20      /* Correctable Error Mask */
 624        /* Same bits as above */
 625#define PCI_ERR_CAP             24      /* Advanced Error Capabilities */
 626#define  PCI_ERR_CAP_FEP(x)     ((x) & 31)      /* First Error Pointer */
 627#define  PCI_ERR_CAP_ECRC_GENC  0x00000020      /* ECRC Generation Capable */
 628#define  PCI_ERR_CAP_ECRC_GENE  0x00000040      /* ECRC Generation Enable */
 629#define  PCI_ERR_CAP_ECRC_CHKC  0x00000080      /* ECRC Check Capable */
 630#define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
 631#define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
 632#define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
 633/* Correctable Err Reporting Enable */
 634#define PCI_ERR_ROOT_CMD_COR_EN         0x00000001
 635/* Non-fatal Err Reporting Enable */
 636#define PCI_ERR_ROOT_CMD_NONFATAL_EN    0x00000002
 637/* Fatal Err Reporting Enable */
 638#define PCI_ERR_ROOT_CMD_FATAL_EN       0x00000004
 639#define PCI_ERR_ROOT_STATUS     48
 640#define PCI_ERR_ROOT_COR_RCV            0x00000001      /* ERR_COR Received */
 641/* Multi ERR_COR Received */
 642#define PCI_ERR_ROOT_MULTI_COR_RCV      0x00000002
 643/* ERR_FATAL/NONFATAL Recevied */
 644#define PCI_ERR_ROOT_UNCOR_RCV          0x00000004
 645/* Multi ERR_FATAL/NONFATAL Recevied */
 646#define PCI_ERR_ROOT_MULTI_UNCOR_RCV    0x00000008
 647#define PCI_ERR_ROOT_FIRST_FATAL        0x00000010      /* First Fatal */
 648#define PCI_ERR_ROOT_NONFATAL_RCV       0x00000020      /* Non-Fatal Received */
 649#define PCI_ERR_ROOT_FATAL_RCV          0x00000040      /* Fatal Received */
 650#define PCI_ERR_ROOT_ERR_SRC    52      /* Error Source Identification */
 651
 652/* Virtual Channel */
 653#define PCI_VC_PORT_REG1        4
 654#define  PCI_VC_REG1_EVCC       0x7     /* extended vc count */
 655#define PCI_VC_PORT_REG2        8
 656#define  PCI_VC_REG2_32_PHASE   0x2
 657#define  PCI_VC_REG2_64_PHASE   0x4
 658#define  PCI_VC_REG2_128_PHASE  0x8
 659#define PCI_VC_PORT_CTRL        12
 660#define PCI_VC_PORT_STATUS      14
 661#define PCI_VC_RES_CAP          16
 662#define PCI_VC_RES_CTRL         20
 663#define PCI_VC_RES_STATUS       26
 664#define PCI_CAP_VC_BASE_SIZEOF          0x10
 665#define PCI_CAP_VC_PER_VC_SIZEOF        0x0C
 666
 667/* Power Budgeting */
 668#define PCI_PWR_DSR             4       /* Data Select Register */
 669#define PCI_PWR_DATA            8       /* Data Register */
 670#define  PCI_PWR_DATA_BASE(x)   ((x) & 0xff)        /* Base Power */
 671#define  PCI_PWR_DATA_SCALE(x)  (((x) >> 8) & 3)    /* Data Scale */
 672#define  PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)   /* PM Sub State */
 673#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
 674#define  PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7)   /* Type */
 675#define  PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)   /* Power Rail */
 676#define PCI_PWR_CAP             12      /* Capability */
 677#define  PCI_PWR_CAP_BUDGET(x)  ((x) & 1)       /* Included in system budget */
 678#define PCI_EXT_CAP_PWR_SIZEOF  16
 679
 680/*
 681 * Hypertransport sub capability types
 682 *
 683 * Unfortunately there are both 3 bit and 5 bit capability types defined
 684 * in the HT spec, catering for that is a little messy. You probably don't
 685 * want to use these directly, just use pci_find_ht_capability() and it
 686 * will do the right thing for you.
 687 */
 688#define HT_3BIT_CAP_MASK        0xE0
 689#define HT_CAPTYPE_SLAVE        0x00    /* Slave/Primary link configuration */
 690#define HT_CAPTYPE_HOST         0x20    /* Host/Secondary link configuration */
 691
 692#define HT_5BIT_CAP_MASK        0xF8
 693#define HT_CAPTYPE_IRQ          0x80    /* IRQ Configuration */
 694#define HT_CAPTYPE_REMAPPING_40 0xA0    /* 40 bit address remapping */
 695#define HT_CAPTYPE_REMAPPING_64 0xA2    /* 64 bit address remapping */
 696#define HT_CAPTYPE_UNITID_CLUMP 0x90    /* Unit ID clumping */
 697#define HT_CAPTYPE_EXTCONF      0x98    /* Extended Configuration Space Access */
 698#define HT_CAPTYPE_MSI_MAPPING  0xA8    /* MSI Mapping Capability */
 699#define  HT_MSI_FLAGS           0x02            /* Offset to flags */
 700#define  HT_MSI_FLAGS_ENABLE    0x1             /* Mapping enable */
 701#define  HT_MSI_FLAGS_FIXED     0x2             /* Fixed mapping only */
 702#define  HT_MSI_FIXED_ADDR      0x00000000FEE00000ULL   /* Fixed addr */
 703#define  HT_MSI_ADDR_LO         0x04            /* Offset to low addr bits */
 704#define  HT_MSI_ADDR_LO_MASK    0xFFF00000      /* Low address bit mask */
 705#define  HT_MSI_ADDR_HI         0x08            /* Offset to high addr bits */
 706#define HT_CAPTYPE_DIRECT_ROUTE 0xB0    /* Direct routing configuration */
 707#define HT_CAPTYPE_VCSET        0xB8    /* Virtual Channel configuration */
 708#define HT_CAPTYPE_ERROR_RETRY  0xC0    /* Retry on error configuration */
 709#define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 hypertransport configuration */
 710#define HT_CAPTYPE_PM           0xE0    /* Hypertransport powermanagement configuration */
 711#define HT_CAP_SIZEOF_LONG      28      /* slave & primary */
 712#define HT_CAP_SIZEOF_SHORT     24      /* host & secondary */
 713
 714/* Alternative Routing-ID Interpretation */
 715#define PCI_ARI_CAP             0x04    /* ARI Capability Register */
 716#define  PCI_ARI_CAP_MFVC       0x0001  /* MFVC Function Groups Capability */
 717#define  PCI_ARI_CAP_ACS        0x0002  /* ACS Function Groups Capability */
 718#define  PCI_ARI_CAP_NFN(x)     (((x) >> 8) & 0xff) /* Next Function Number */
 719#define PCI_ARI_CTRL            0x06    /* ARI Control Register */
 720#define  PCI_ARI_CTRL_MFVC      0x0001  /* MFVC Function Groups Enable */
 721#define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
 722#define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
 723#define PCI_EXT_CAP_ARI_SIZEOF  8
 724
 725/* Address Translation Service */
 726#define PCI_ATS_CAP             0x04    /* ATS Capability Register */
 727#define  PCI_ATS_CAP_QDEP(x)    ((x) & 0x1f)    /* Invalidate Queue Depth */
 728#define  PCI_ATS_MAX_QDEP       32      /* Max Invalidate Queue Depth */
 729#define PCI_ATS_CTRL            0x06    /* ATS Control Register */
 730#define  PCI_ATS_CTRL_ENABLE    0x8000  /* ATS Enable */
 731#define  PCI_ATS_CTRL_STU(x)    ((x) & 0x1f)    /* Smallest Translation Unit */
 732#define  PCI_ATS_MIN_STU        12      /* shift of minimum STU block */
 733#define PCI_EXT_CAP_ATS_SIZEOF  8
 734
 735/* Page Request Interface */
 736#define PCI_PRI_CTRL            0x04    /* PRI control register */
 737#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
 738#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
 739#define PCI_PRI_STATUS          0x06    /* PRI status register */
 740#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
 741#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
 742#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
 743#define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
 744#define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
 745#define PCI_EXT_CAP_PRI_SIZEOF  16
 746
 747/* PASID capability */
 748#define PCI_PASID_CAP           0x04    /* PASID feature register */
 749#define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
 750#define  PCI_PASID_CAP_PRIV     0x04    /* Priviledge Mode Supported */
 751#define PCI_PASID_CTRL          0x06    /* PASID control register */
 752#define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
 753#define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
 754#define  PCI_PASID_CTRL_PRIV    0x04    /* Priviledge Mode Enable */
 755#define PCI_EXT_CAP_PASID_SIZEOF        8
 756
 757/* Single Root I/O Virtualization */
 758#define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
 759#define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */
 760#define  PCI_SRIOV_CAP_INTR(x)  ((x) >> 21) /* Interrupt Message Number */
 761#define PCI_SRIOV_CTRL          0x08    /* SR-IOV Control */
 762#define  PCI_SRIOV_CTRL_VFE     0x01    /* VF Enable */
 763#define  PCI_SRIOV_CTRL_VFM     0x02    /* VF Migration Enable */
 764#define  PCI_SRIOV_CTRL_INTR    0x04    /* VF Migration Interrupt Enable */
 765#define  PCI_SRIOV_CTRL_MSE     0x08    /* VF Memory Space Enable */
 766#define  PCI_SRIOV_CTRL_ARI     0x10    /* ARI Capable Hierarchy */
 767#define PCI_SRIOV_STATUS        0x0a    /* SR-IOV Status */
 768#define  PCI_SRIOV_STATUS_VFM   0x01    /* VF Migration Status */
 769#define PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
 770#define PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
 771#define PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
 772#define PCI_SRIOV_FUNC_LINK     0x12    /* Function Dependency Link */
 773#define PCI_SRIOV_VF_OFFSET     0x14    /* First VF Offset */
 774#define PCI_SRIOV_VF_STRIDE     0x16    /* Following VF Stride */
 775#define PCI_SRIOV_VF_DID        0x1a    /* VF Device ID */
 776#define PCI_SRIOV_SUP_PGSIZE    0x1c    /* Supported Page Sizes */
 777#define PCI_SRIOV_SYS_PGSIZE    0x20    /* System Page Size */
 778#define PCI_SRIOV_BAR           0x24    /* VF BAR0 */
 779#define  PCI_SRIOV_NUM_BARS     6       /* Number of VF BARs */
 780#define PCI_SRIOV_VFM           0x3c    /* VF Migration State Array Offset*/
 781#define  PCI_SRIOV_VFM_BIR(x)   ((x) & 7)       /* State BIR */
 782#define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)     /* State Offset */
 783#define  PCI_SRIOV_VFM_UA       0x0     /* Inactive.Unavailable */
 784#define  PCI_SRIOV_VFM_MI       0x1     /* Dormant.MigrateIn */
 785#define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 786#define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 787#define PCI_EXT_CAP_SRIOV_SIZEOF 64
 788
 789#define PCI_LTR_MAX_SNOOP_LAT   0x4
 790#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
 791#define  PCI_LTR_VALUE_MASK     0x000003ff
 792#define  PCI_LTR_SCALE_MASK     0x00001c00
 793#define  PCI_LTR_SCALE_SHIFT    10
 794#define PCI_EXT_CAP_LTR_SIZEOF  8
 795
 796/* Access Control Service */
 797#define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 798#define  PCI_ACS_SV             0x01    /* Source Validation */
 799#define  PCI_ACS_TB             0x02    /* Translation Blocking */
 800#define  PCI_ACS_RR             0x04    /* P2P Request Redirect */
 801#define  PCI_ACS_CR             0x08    /* P2P Completion Redirect */
 802#define  PCI_ACS_UF             0x10    /* Upstream Forwarding */
 803#define  PCI_ACS_EC             0x20    /* P2P Egress Control */
 804#define  PCI_ACS_DT             0x40    /* Direct Translated P2P */
 805#define PCI_ACS_EGRESS_BITS     0x05    /* ACS Egress Control Vector Size */
 806#define PCI_ACS_CTRL            0x06    /* ACS Control Register */
 807#define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
 808
 809#define PCI_VSEC_HDR            4       /* extended cap - vendor specific */
 810#define  PCI_VSEC_HDR_LEN_SHIFT 20      /* shift for length field */
 811
 812/* sata capability */
 813#define PCI_SATA_REGS           4       /* SATA REGs specifier */
 814#define  PCI_SATA_REGS_MASK     0xF     /* location - BAR#/inline */
 815#define  PCI_SATA_REGS_INLINE   0xF     /* REGS in config space */
 816#define PCI_SATA_SIZEOF_SHORT   8
 817#define PCI_SATA_SIZEOF_LONG    16
 818
 819/* resizable BARs */
 820#define PCI_REBAR_CTRL          8       /* control register */
 821#define  PCI_REBAR_CTRL_NBAR_MASK       (7 << 5)        /* mask for # bars */
 822#define  PCI_REBAR_CTRL_NBAR_SHIFT      5       /* shift for # bars */
 823
 824/* dynamic power allocation */
 825#define PCI_DPA_CAP             4       /* capability register */
 826#define  PCI_DPA_CAP_SUBSTATE_MASK      0x1F    /* # substates - 1 */
 827#define PCI_DPA_BASE_SIZEOF     16      /* size with 0 substates */
 828
 829/* TPH Requester */
 830#define PCI_TPH_CAP             4       /* capability register */
 831#define  PCI_TPH_CAP_LOC_MASK   0x600   /* location mask */
 832#define   PCI_TPH_LOC_NONE      0x000   /* no location */
 833#define   PCI_TPH_LOC_CAP       0x200   /* in capability */
 834#define   PCI_TPH_LOC_MSIX      0x400   /* in MSI-X */
 835#define PCI_TPH_CAP_ST_MASK     0x07FF0000      /* st table mask */
 836#define PCI_TPH_CAP_ST_SHIFT    16      /* st table shift */
 837#define PCI_TPH_BASE_SIZEOF     12      /* size with no st table */
 838
 839#endif /* LINUX_PCI_REGS_H */
 840
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