linux/drivers/watchdog/coh901327_wdt.c
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   1/*
   2 * coh901327_wdt.c
   3 *
   4 * Copyright (C) 2008-2009 ST-Ericsson AB
   5 * License terms: GNU General Public License (GPL) version 2
   6 * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
   7 * Author: Linus Walleij <linus.walleij@stericsson.com>
   8 */
   9#include <linux/module.h>
  10#include <linux/types.h>
  11#include <linux/watchdog.h>
  12#include <linux/interrupt.h>
  13#include <linux/pm.h>
  14#include <linux/platform_device.h>
  15#include <linux/io.h>
  16#include <linux/bitops.h>
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/err.h>
  20
  21#define DRV_NAME "WDOG COH 901 327"
  22
  23/*
  24 * COH 901 327 register definitions
  25 */
  26
  27/* WDOG_FEED Register 32bit (-/W) */
  28#define U300_WDOG_FR                                                    0x00
  29#define U300_WDOG_FR_FEED_RESTART_TIMER                                 0xFEEDU
  30/* WDOG_TIMEOUT Register 32bit (R/W) */
  31#define U300_WDOG_TR                                                    0x04
  32#define U300_WDOG_TR_TIMEOUT_MASK                                       0x7FFFU
  33/* WDOG_DISABLE1 Register 32bit (-/W) */
  34#define U300_WDOG_D1R                                                   0x08
  35#define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER                            0x2BADU
  36/* WDOG_DISABLE2 Register 32bit (R/W) */
  37#define U300_WDOG_D2R                                                   0x0C
  38#define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER                            0xCAFEU
  39#define U300_WDOG_D2R_DISABLE_STATUS_DISABLED                           0xDABEU
  40#define U300_WDOG_D2R_DISABLE_STATUS_ENABLED                            0x0000U
  41/* WDOG_STATUS Register 32bit (R/W) */
  42#define U300_WDOG_SR                                                    0x10
  43#define U300_WDOG_SR_STATUS_TIMED_OUT                                   0xCFE8U
  44#define U300_WDOG_SR_STATUS_NORMAL                                      0x0000U
  45#define U300_WDOG_SR_RESET_STATUS_RESET                                 0xE8B4U
  46/* WDOG_COUNT Register 32bit (R/-) */
  47#define U300_WDOG_CR                                                    0x14
  48#define U300_WDOG_CR_VALID_IND                                          0x8000U
  49#define U300_WDOG_CR_VALID_STABLE                                       0x0000U
  50#define U300_WDOG_CR_COUNT_VALUE_MASK                                   0x7FFFU
  51/* WDOG_JTAGOVR Register 32bit (R/W) */
  52#define U300_WDOG_JOR                                                   0x18
  53#define U300_WDOG_JOR_JTAG_MODE_IND                                     0x0002U
  54#define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE                              0x0001U
  55/* WDOG_RESTART Register 32bit (-/W) */
  56#define U300_WDOG_RR                                                    0x1C
  57#define U300_WDOG_RR_RESTART_VALUE_RESUME                               0xACEDU
  58/* WDOG_IRQ_EVENT Register 32bit (R/W) */
  59#define U300_WDOG_IER                                                   0x20
  60#define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND                           0x0001U
  61#define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE                          0x0001U
  62/* WDOG_IRQ_MASK Register 32bit (R/W) */
  63#define U300_WDOG_IMR                                                   0x24
  64#define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE                              0x0001U
  65/* WDOG_IRQ_FORCE Register 32bit (R/W) */
  66#define U300_WDOG_IFR                                                   0x28
  67#define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE                        0x0001U
  68
  69/* Default timeout in seconds = 1 minute */
  70static unsigned int margin = 60;
  71static resource_size_t phybase;
  72static resource_size_t physize;
  73static int irq;
  74static void __iomem *virtbase;
  75static struct device *parent;
  76
  77/*
  78 * The watchdog block is of course always clocked, the
  79 * clk_enable()/clk_disable() calls are mainly for performing reference
  80 * counting higher up in the clock hierarchy.
  81 */
  82static struct clk *clk;
  83
  84/*
  85 * Enabling and disabling functions.
  86 */
  87static void coh901327_enable(u16 timeout)
  88{
  89        u16 val;
  90        unsigned long freq;
  91        unsigned long delay_ns;
  92
  93        clk_enable(clk);
  94        /* Restart timer if it is disabled */
  95        val = readw(virtbase + U300_WDOG_D2R);
  96        if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
  97                writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
  98                       virtbase + U300_WDOG_RR);
  99        /* Acknowledge any pending interrupt so it doesn't just fire off */
 100        writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
 101               virtbase + U300_WDOG_IER);
 102        /*
 103         * The interrupt is cleared in the 32 kHz clock domain.
 104         * Wait 3 32 kHz cycles for it to take effect
 105         */
 106        freq = clk_get_rate(clk);
 107        delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
 108        delay_ns = 3 * delay_ns; /* Wait 3 cycles */
 109        ndelay(delay_ns);
 110        /* Enable the watchdog interrupt */
 111        writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
 112        /* Activate the watchdog timer */
 113        writew(timeout, virtbase + U300_WDOG_TR);
 114        /* Start the watchdog timer */
 115        writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
 116        /*
 117         * Extra read so that this change propagate in the watchdog.
 118         */
 119        (void) readw(virtbase + U300_WDOG_CR);
 120        val = readw(virtbase + U300_WDOG_D2R);
 121        clk_disable(clk);
 122        if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
 123                dev_err(parent,
 124                        "%s(): watchdog not enabled! D2R value %04x\n",
 125                        __func__, val);
 126}
 127
 128static void coh901327_disable(void)
 129{
 130        u16 val;
 131
 132        clk_enable(clk);
 133        /* Disable the watchdog interrupt if it is active */
 134        writew(0x0000U, virtbase + U300_WDOG_IMR);
 135        /* If the watchdog is currently enabled, attempt to disable it */
 136        val = readw(virtbase + U300_WDOG_D2R);
 137        if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
 138                writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
 139                       virtbase + U300_WDOG_D1R);
 140                writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
 141                       virtbase + U300_WDOG_D2R);
 142                /* Write this twice (else problems occur) */
 143                writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
 144                       virtbase + U300_WDOG_D2R);
 145        }
 146        val = readw(virtbase + U300_WDOG_D2R);
 147        clk_disable(clk);
 148        if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
 149                dev_err(parent,
 150                        "%s(): watchdog not disabled! D2R value %04x\n",
 151                        __func__, val);
 152}
 153
 154static int coh901327_start(struct watchdog_device *wdt_dev)
 155{
 156        coh901327_enable(wdt_dev->timeout * 100);
 157        return 0;
 158}
 159
 160static int coh901327_stop(struct watchdog_device *wdt_dev)
 161{
 162        coh901327_disable();
 163        return 0;
 164}
 165
 166static int coh901327_ping(struct watchdog_device *wdd)
 167{
 168        clk_enable(clk);
 169        /* Feed the watchdog */
 170        writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 171               virtbase + U300_WDOG_FR);
 172        clk_disable(clk);
 173        return 0;
 174}
 175
 176static int coh901327_settimeout(struct watchdog_device *wdt_dev,
 177                                unsigned int time)
 178{
 179        wdt_dev->timeout = time;
 180        clk_enable(clk);
 181        /* Set new timeout value */
 182        writew(time * 100, virtbase + U300_WDOG_TR);
 183        /* Feed the dog */
 184        writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 185               virtbase + U300_WDOG_FR);
 186        clk_disable(clk);
 187        return 0;
 188}
 189
 190static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
 191{
 192        u16 val;
 193
 194        clk_enable(clk);
 195        /* Read repeatedly until the value is stable! */
 196        val = readw(virtbase + U300_WDOG_CR);
 197        while (val & U300_WDOG_CR_VALID_IND)
 198                val = readw(virtbase + U300_WDOG_CR);
 199        val &= U300_WDOG_CR_COUNT_VALUE_MASK;
 200        clk_disable(clk);
 201        if (val != 0)
 202                val /= 100;
 203
 204        return val;
 205}
 206
 207/*
 208 * This interrupt occurs 10 ms before the watchdog WILL bark.
 209 */
 210static irqreturn_t coh901327_interrupt(int irq, void *data)
 211{
 212        u16 val;
 213
 214        /*
 215         * Ack IRQ? If this occurs we're FUBAR anyway, so
 216         * just acknowledge, disable the interrupt and await the imminent end.
 217         * If you at some point need a host of callbacks to be called
 218         * when the system is about to watchdog-reset, add them here!
 219         *
 220         * NOTE: on future versions of this IP-block, it will be possible
 221         * to prevent a watchdog reset by feeding the watchdog at this
 222         * point.
 223         */
 224        clk_enable(clk);
 225        val = readw(virtbase + U300_WDOG_IER);
 226        if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
 227                writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
 228                       virtbase + U300_WDOG_IER);
 229        writew(0x0000U, virtbase + U300_WDOG_IMR);
 230        clk_disable(clk);
 231        dev_crit(parent, "watchdog is barking!\n");
 232        return IRQ_HANDLED;
 233}
 234
 235static const struct watchdog_info coh901327_ident = {
 236        .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
 237        .identity = DRV_NAME,
 238};
 239
 240static struct watchdog_ops coh901327_ops = {
 241        .owner = THIS_MODULE,
 242        .start = coh901327_start,
 243        .stop = coh901327_stop,
 244        .ping = coh901327_ping,
 245        .set_timeout = coh901327_settimeout,
 246        .get_timeleft = coh901327_gettimeleft,
 247};
 248
 249static struct watchdog_device coh901327_wdt = {
 250        .info = &coh901327_ident,
 251        .ops = &coh901327_ops,
 252        /*
 253         * Max timeout is 327 since the 10ms
 254         * timeout register is max
 255         * 0x7FFF = 327670ms ~= 327s.
901327_wdt.c#L248" id="L248" classhref="drivers/" name="L209"> 209 245       min="L245">      .0h901327_ops" class="sref">coh901327_ops,
 245       max="L245">      .7_oh901327_ops" class="sref">coh901327_ops,
 247};
 247};
val);
irq, void phref="+code=wdt_deplass="sref">wdt_dev)
 = {
 113        " class=un      * ="+code=watchdog_device" class=un      * ="+code="sresref">ops = &c!\n");
 224        ivers/wat+code=coh901327_disable" class="sref">coh901327_disable();
 225       free_ dev_crit irq, void phref="+code=wdt_deplass="sr27_disable();
 186        clk_disable(clk);
 147        clk_disable(clk);
 168       iounmade=coh901327_stoiounmadass="sref">readw(clk);
 229       rcohass_mem_    onref="+code=readw"ohass_mem_    on="sref">dev_crit(hyhref="+code=virtbas(hyhrefclass=>irq, void physizf="+code=virtbas(hysizf="srs="sref">clk);
 187        return 0;
 233}
 233}
val);
 249static structplatform="+code=watchdog_devicplatform="+code90132">irq, void phref="+code=wdt_deplass="sref">wdt_dev)
 = {
a>);
IRQ_HANDLED;
 186        u16 val;
> 249static structresourde=watchdog_devicresourde90132">irq, void res=watchdog_devicresclass="sref">val;
 248
 179       res=watchdog_devicresclasget_timeleft =platform=lass=esourde=watchdog_devicplatform=lass=esourde="sref">dev_crit(href="+code=wdt_deplass="ss=>irq, void IORESOURCE_MEMcode=IRQ_HANDLEDORESOURCE_MEMs="ss=timeout * 100);
 226! 179       res=watchdog_devicresclasref">wdt_dev)
 151 187       ENOEN=WDIOF_SETTIMEOUENOEN=class="sref">val;
 233}
 113       (ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss="sref">val;
 184       physizf="+code=virtbas(hysizf="srs="sref">val = dev_critres=watchdog_devicresclasrs="sref">val;
 225       (hyhref="+code=virtbas(hyhrefclass="sref">val = wdt_dev->.val;
 206
 137        if request_mem_    onref="+code=readw"quest_mem_    on="sref">dev_crit(hyhref="+code=virtbas(hyhrefclass=>irq, void physizf="+code=virtbas(hysizf="srs=>irq, void  val ==NULL="+code=DRV_NAMNULL="sr)s01327_wdt = {
 198                18ref="+code=readw"tref"s="- 179       EBUSYWDIOF_SETTIMEOUEBUSYass=s="sref">val;
 149goto>               ">      .7_oh90132lass="ss="sref">val;
="L233"> 233}
 131
 192        val ==ioremade=coh901327_stoioremad="sref">dev_crit(hyhref="+code=virtbas(hyhrefclass=>irq, void physizf="+code=virtbas(hysizf="srs="sref">clk);
 137! 179       ( 198                18ref="+code=readw"tref"s="- 179       ENOMEMcode=IRQ_HANDLEENOMEMs="ss="sref">val;
 149goto>               "> _no_remade=coh901327_sto"> _no_remads="ss="sref">val;
="L233"> 233}
 127
 168         = lk=las01327_settimeoutops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss=>irq, void NULL="+code=DRV_NAMNULL="sr)s="sref">val;
 137        if IS_ERode=U300_WDOG_IMIS_ERoref">clk_disable( = {
 140                18ref="+code=readw"tref"s="               PTR_ERode=U300_WDOG_IMPTR_ERoref">clk_disable(clk);
 151wdt_dev->hre href="+code=dev_err" class="srsref">ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss=>f">parent, );
 202goto>               "> _no_( _no_(val;
="L233"> 233}
 184        18ref="+code=readw"tref"s="               tclk_disable(clk);
 137        if  18ref="+code=readw"tref"ss01327_wdt = {
 151wdt_dev->hre href="+code=dev_err" class="srsref">ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss=>f">parent,  227goto>               "> _no_( _no_(val;
="L233"> 233}
 239
 230        val = readw(virtbase + U300_WDOG_IMR);
swihre26        if ( = {
cass">virtbase +  = {
 143               r" c.ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 198 143 f">parent,     timeoenttarhipevent chdog is barking!\n");
 1497_wdt.c=wr4FFF = 327670ms+code=coh901327_wdt" class="sref">c 245       mboot3>vaus=watchdog_devicboot3>vausname=|ef">options = WDI\n");
 151w181        vaushis IP-blcle" cdP-blowf="drivers/" name="L209"> 209 227bw" k\n");
cass">virtbase +  149                ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 150                        vaus,37;ment">  s haveAck IR cd.hdog is barking!\n");
 151bw" k\n");
default:1327_wdt = {
 143               r" c.ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 198 143 f">parent, vaus >-&g (bled! 8x)R value %04x> 230        );
 149bw" k\n");
="L233"> 233}
 127
 168        val = readw(virtbase + swihre26        if ( = {
cass">virtbase +  151wdt_dev->hre .ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss> f">parent, );
 202bw" k\n");
cass">virtbase +  198               hre .ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 149> 143 f">parent,  151wdt_dev-> ivers/wat+code=coh901327_disable" class="sref">coh901327_disable();
 227bw" k\n");
default:1327_wdt = {
 149                ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 150                         151 149                );
 202bw" k\n");
="L233"> 233}
 234
 195        /* Feed the watchdog */
 186        writew(virtbase + U300_WDOG_IMR);
 127
 168       i =platform=lassidev_crit(href="+code=wdt_deplass="ss=timeout * 100);
 137        if w"quest_idev_crit irq, void t" class="scode=coh901327_interrupt" class="sref">coh9013,>coh901327_ops,
 150         irq, void   = {
 151wdt_dev-> 18ref="+code=readw"tref"s="- 179       EIOref="+code=readEIO>WDI\n");
 202goto>               "> _no_  _no_ WDI\n");
="L233"> 233}
 234
 225        clk_disable(clk);
35 name="L206"> 206
 137        if marginref="+code=readmarginname=&lss 1 |_SETTIMEOUT |marginref="+code=readmarginname=&f">n32 ref">wdt_dev)
 198               marginref="+code=readmarginname== 6>        return 0;
 179       = 327670ms+code=coh901327_wdt" class="sref">c 245       mL245">      .7_oh90132lass="sref">set_timeout =marginref="+code=readmarginname        return 0;
 247};
 231        18ref="+code=readw"tref"s="               e" class=      * ="+code=watchdog_device" class=      * ="+code="sresref">ops = &c!\n");
 137        if w"8ref="+code=readw"tref"s="sref">val != 0)
 143               r" c.ops = &(href="+code=wdt_deplass="sref">wdt_dev->href="+code=wdt_delass="ss1327_wdt = {
 198 143                  230       marginref="+code=readmarginname!\n");
elsen");
 151goto>               "> _no_wf=" href="+code=ir"> _no_wf="name        return 0;
 127
 187        return 0;
 239
 _no_wf=" href="+code=ir"> _no_wf="name:1327_wdt = {
 231       free_ dev_crit irq, void phref="+code=wdt_deplass="sr27_disable();
 _no_  _no_ WDI:1327_wdt = {
 113       e" class="s unpret" ccode=clk_disable" class="s unpret" cref">clk_disable(clk);
 _no_( _no_( = {
 225        clk_disable(clk);
 _no_( _no_( = {
 147       iounmade=coh901327_stoiounmadass="sref">readw(clk);
 _no_remade=coh901327_sto"> _no_remads="s:1327_wdt = {
 179       reohass_mem_    onref="+code=readw"ohass_mem_    on="sref">dev_crit(hyhref="+code=virtbas(hyhrefclass=>irq, void SZ_4K="+code=virtbasSZ_4K="srs="sref">clk);
 e=coh901327_sto"> s="s:1327_wdt = {
 232        return 18ref="+code=readw"tref">IRQ_HANDLED;
 233}
 213
        returnCONFIG_PMcode=IRQ_HANDLECONFIG_PMname="L213"> 213
 213
 210static u16wf="href="sto ccode=clk_disablwf="href="sto cref">IRQ_HANDLED;
 210static u16 IRQ_HANDLED;
 248
);
 249static structplatform="+code=watchdog_devicplatform="+code90132">irq, void phref="+code=wdt_deplass="ss=>irq, void pm_message_ref="+code=parentm_message_rclass="sref">u16="L2e=watchdog_devic="L2e="srs="L248"> 248
 231        val = readw(virtbase + U3"sref" ref">1U>IRQ_HANDLED;
 192       wf="href="sto ccode=clk_disablwf="href="sto cref"s="sref">val = readw(virtbase +  195        /* Feis on,ust acknrit3resele thnowf="drivers/" name="L209"> 209 137        if wf="href="sto ccode=clk_disablwf="href="sto cref"s="sref">val ==  248
 149
coh901327_disable();
 187        return 0;
 233}
 248
);
 249static structplatform="+code=watchdog_devicplatform="+code90132">irq, void phref="+code=wdt_deplass="ss="L248"> 248
 195        /* Fesref">cohf="drivers/" name="L209"> 209 192       wwritew (0x0000U, virtbase + U300_WDOG_IMR);
 137        if wf="href="sto ccode=clk_disablwf="href="sto cref"s="sref">val ==  198 195        /* Feent"r ="drivers/" name="L209"> 209 149
writew( = {
 151149
virtbase + U300_WDOG_IMR);
 227
writew( 198149
virtbase + U300_WDOG_IMR);
="L233"> 233}
 187        return 0;
 233}
);
irq, void NULL="+code=DRV_NAMNULL="srn");

);
 206
/*
 2eL24ngaomment">/* Fessaommeonlyenty to perform a softw" clvent  ofaommass="comment">/*

 209 248
 195         209
writew( 149virtbase + U300_WDOG_IMR);
 252        /*
 149   = 5s, we haveAto wait for omment">/* Fevent  toass="comment">/*
 149/* Feis IP-blreloadedeisthaommass="comment">/*
 149/*
 149/*
 149/* F, so weass="comment">/*
 149);ofass="comment">/*
 149/* Febefo cait islsh   down by it327670ms ~= 327s.
 149
 149
ions ofaomment">/* F, omislventriction is27670ms ~= 327s.
 149/* Feis IP-blreloadedeisthaa default value (1 min)27670ms ~= 327s.
 149/* F27670ms ~= 327s.
 149
 149 209 230       2ivers/wathref="+code=clk_enableivers/wathref="ss="s50timeout * 100);
 195         209 233}
 213
 249static structplatform="3=watchdog_devicplatform="3="sr=>irq, void e" class="s3=watchdog_device" class="s3ref"s="01327_wdt = {
 245       ms3=watchdog_devics3ref"s="01327_wdt = {
 151 245       mowna>=watchdog_devicowna>name=""sref">val ==THIS_MODUARde=U300_WDOG_IMTHIS_MODUARs="ss1327_wdt = {
 227 245       m7" cde=U300_WDOG_IM7" cname="L=                  = {
}x1327_wdt = {
 245       mremovcde=U300_WDOG_IMremovcname="L227"> "sref">val ==__exit_de=coh901327_sto__exit_dss="sref">writewe" class="removcde=U300_WDOG_IMe" class="removcf">U3x1327_wdt = {
 245       msuspendde=coh901327_wdsuspend="sr=L227"> "sref">val ==rivers/watsuspendde=coh901327_wdt" class="suspend="srx1327_wdt = {
 245       mresumcoh901327_disablresumc="sra>L227"> "sref">val ==rivers/watresumcoh901327_disable" class="resumc="srx1327_wdt = {
 213
);
irq, void e" class="inite=coh901327_stoe" class="initss="svoids="L248"> 248
45 name="L196"> 187static structplatform="3_his e=watchdog_devicplatform="3_his ess="ssref">ops = &irq, void t" class="his e=watchdog_devict" class="his ef">U300_WDOG_IMR);
 233}
writewe" class="inite=coh901327_stoe" class="initss="300_WDOG_IMR);
 239
 179       __exite=coh901327_sto__exit="sr=>irq, void e" class="exite=coh901327_stoe" class="exitss="svoids="L248"> 248
 192       platform="3_un      * =watchdog_devicplatform="3_un      * ss="ssref">ops = &);
 233}
writewe" class="exite=coh901327_stoe" class="exitss="300_WDOG_IMR);
 213
value %04!\n");
 248
writewmarginref="+code=readmarginnames=>irq, void ua>)ref="+code=readua>)names=timeout * 100);
writewmarginref="+code=readmarginnames=>                131
);



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Tmmeoriginal LXR softw" clbyaomme"LXR    
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 /div>

lx .linux.no kindly ho  *dlbya"Redpill Linpro ASss=", hisvidereof Linux/aonsult4ngae thop* ations sercodes  timeo1995.
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