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53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
80#include <linux/seq_file.h>
81#include <linux/slab.h>
82#include <linux/delay.h>
83#include <linux/netdevice.h>
84#include <linux/vmalloc.h>
85#include <linux/init.h>
86#include <linux/ioctl.h>
87#include <linux/synclink.h>
88
89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
97#include <linux/dma-mapping.h>
98
99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC,
116 0,
117 HDLC_FLAG_UNDERRUN_ABORT15,
118 HDLC_ENCODING_NRZI_SPACE,
119 0,
120 0xff,
121 HDLC_CRC_16_CCITT,
122 HDLC_PREAMBLE_LENGTH_8BITS,
123 HDLC_PREAMBLE_PATTERN_NONE,
124 9600,
125 8,
126 1,
127 ASYNC_PARITY_NONE
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137 u32 phys_addr;
138 volatile u16 count;
139 volatile u16 status;
140 volatile u16 rcc;
141 u16 reserved;
142 u32 link;
143 char *virt_addr;
144 u32 phys_entry;
145 dma_addr_t dma_addr;
146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
156struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165};
166
167
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172};
173
174
175
176
177
178
179struct mgsl_struct {
180 int magic;
181 struct tty_port port;
182 int line;
183 int hw_version;
184
185 struct mgsl_icount icount;
186
187 int timeout;
188 int x_char;
189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer;
199 struct mgsl_struct *next_device;
200
201 spinlock_t irq_spinlock;
202 struct work_struct task;
203
204 u32 EventMask;
205 u32 RecordedEvents;
206
207 u32 max_frame_size;
208
209 u32 pending_bh;
210
211 bool bh_running;
212 int isr_overflow;
213 bool bh_requested;
214
215 int dcd_chkcount;
216 int cts_chkcount;
217 int dsr_chkcount;
218 int ri_chkcount;
219
220 char *buffer_list;
221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
223
224 unsigned int rx_buffer_count;
225 DMABUFFERENTRY *rx_buffer_list;
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers;
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count;
231 DMABUFFERENTRY *tx_buffer_list;
232 int start_tx_dma_buffer;
233 int current_tx_buffer;
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers;
238 int get_tx_holding_index;
239 int put_tx_holding_index;
240 int tx_holding_count;
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
246
247 bool tx_enabled;
248 bool tx_active;
249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25];
255
256 unsigned int bus_type;
257 unsigned char bus;
258 unsigned char function;
259
260 unsigned int io_base;
261 unsigned int io_addr_size;
262 bool io_addr_requested;
263
264 unsigned int irq_level;
265 unsigned long irq_flags;
266 bool irq_requested;
267
268 unsigned int dma_level;
269 bool dma_requested;
270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params;
276
277 unsigned char serial_signals;
278
279 bool irq_occurred;
280 unsigned int init_error;
281 int fDiagnosticsmode;
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base;
285 u32 phys_memory_base;
286 bool shared_mem_requested;
287
288 unsigned char* lcr_base;
289 u32 phys_lcr_base;
290 u32 lcr_offset;
291 bool lcr_mem_requested;
292
293 u32 misc_ctrl_value;
294 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
295 char char_buf[MAX_ASYNC_BUFFER_SIZE];
296 bool drop_rts_on_tx_done;
297
298 bool loopmode_insert_requested;
299 bool loopmode_send_done_requested;
300
301 struct _input_signal_events input_signal_events;
302
303
304 int netcount;
305 spinlock_t netlock;
306
307#if SYNCLINK_GENERIC_HDLC
308 struct net_device *netdev;
309#endif
310};
311
312#define MGSL_MAGIC 0x5401
313
314
315
316
317#ifndef SERIAL_XMIT_SIZE
318#define SERIAL_XMIT_SIZE 4096
319#endif
320
321
322
323
324
325
326
327#define DCPIN 2
328#define SDPIN 4
329
330#define DCAR 0
331#define CCAR SDPIN
332#define DATAREG DCPIN + SDPIN
333#define MSBONLY 0x41
334#define LSBONLY 0x40
335
336
337
338
339
340
341#define CMR 0x02
342#define CCSR 0x04
343#define CCR 0x06
344#define PSR 0x08
345#define PCR 0x0a
346#define TMDR 0x0c
347#define TMCR 0x0e
348#define CMCR 0x10
349#define HCR 0x12
350#define IVR 0x14
351#define IOCR 0x16
352#define ICR 0x18
353#define DCCR 0x1a
354#define MISR 0x1c
355#define SICR 0x1e
356#define RDR 0x20
357#define RMR 0x22
358#define RCSR 0x24
359#define RICR 0x26
360#define RSR 0x28
361#define RCLR 0x2a
362#define RCCR 0x2c
363#define TC0R 0x2e
364#define TDR 0x30
365#define TMR 0x32
366#define TCSR 0x34
367#define TICR 0x36
368#define TSR 0x38
369#define TCLR 0x3a
370#define TCCR 0x3c
371#define TC1R 0x3e
372
373
374
375
376
377
378#define DCR 0x06
379#define DACR 0x08
380#define BDCR 0x12
381#define DIVR 0x14
382#define DICR 0x18
383#define CDIR 0x1a
384#define SDIR 0x1c
385
386#define TDMR 0x02
387#define TDIAR 0x1e
388#define TBCR 0x2a
389#define TARL 0x2c
390#define TARU 0x2e
391#define NTBCR 0x3a
392#define NTARL 0x3c
393#define NTARU 0x3e
394
395#define RDMR 0x82
396#define RDIAR 0x9e
397#define RBCR 0xaa
398#define RARL 0xac
399#define RARU 0xae
400#define NRBCR 0xba
401#define NRARL 0xbc
402#define NRARU 0xbe
403
404
405
406
407
408
409#define MODEMSTATUS_DTR 0x80
410#define MODEMSTATUS_DSR 0x40
411#define MODEMSTATUS_RTS 0x20
412#define MODEMSTATUS_CTS 0x10
413#define MODEMSTATUS_RI 0x04
414#define MODEMSTATUS_DCD 0x01
415
416
417
418
419
420
421#define RTCmd_Null 0x0000
422#define RTCmd_ResetHighestIus 0x1000
423#define RTCmd_TriggerChannelLoadDma 0x2000
424#define RTCmd_TriggerRxDma 0x2800
425#define RTCmd_TriggerTxDma 0x3000
426#define RTCmd_TriggerRxAndTxDma 0x3800
427#define RTCmd_PurgeRxFifo 0x4800
428#define RTCmd_PurgeTxFifo 0x5000
429#define RTCmd_PurgeRxAndTxFifo 0x5800
430#define RTCmd_LoadRcc 0x6800
431#define RTCmd_LoadTcc 0x7000
432#define RTCmd_LoadRccAndTcc 0x7800
433#define RTCmd_LoadTC0 0x8800
434#define RTCmd_LoadTC1 0x9000
435#define RTCmd_LoadTC0AndTC1 0x9800
436#define RTCmd_SerialDataLSBFirst 0xa000
437#define RTCmd_SerialDataMSBFirst 0xa800
438#define RTCmd_SelectBigEndian 0xb000
439#define RTCmd_SelectLittleEndian 0xb800
440
441
442
443
444
445
446#define DmaCmd_Null 0x0000
447#define DmaCmd_ResetTxChannel 0x1000
448#define DmaCmd_ResetRxChannel 0x1200
449#define DmaCmd_StartTxChannel 0x2000
450#define DmaCmd_StartRxChannel 0x2200
451#define DmaCmd_ContinueTxChannel 0x3000
452#define DmaCmd_ContinueRxChannel 0x3200
453#define DmaCmd_PauseTxChannel 0x4000
454#define DmaCmd_PauseRxChannel 0x4200
455#define DmaCmd_AbortTxChannel 0x5000
456#define DmaCmd_AbortRxChannel 0x5200
457#define DmaCmd_InitTxChannel 0x7000
458#define DmaCmd_InitRxChannel 0x7200
459#define DmaCmd_ResetHighestDmaIus 0x8000
460#define DmaCmd_ResetAllChannels 0x9000
461#define DmaCmd_StartAllChannels 0xa000
462#define DmaCmd_ContinueAllChannels 0xb000
463#define DmaCmd_PauseAllChannels 0xc000
464#define DmaCmd_AbortAllChannels 0xd000
465#define DmaCmd_InitAllChannels 0xf000
466
467#define TCmd_Null 0x0000
468#define TCmd_ClearTxCRC 0x2000
469#define TCmd_SelectTicrTtsaData 0x4000
470#define TCmd_SelectTicrTxFifostatus 0x5000
471#define TCmd_SelectTicrIntLevel 0x6000
472#define TCmd_SelectTicrdma_level 0x7000
473#define TCmd_SendFrame 0x8000
474#define TCmd_SendAbort 0x9000
475#define TCmd_EnableDleInsertion 0xc000
476#define TCmd_DisableDleInsertion 0xd000
477#define TCmd_ClearEofEom 0xe000
478#define TCmd_SetEofEom 0xf000
479
480#define RCmd_Null 0x0000
481#define RCmd_ClearRxCRC 0x2000
482#define RCmd_EnterHuntmode 0x3000
483#define RCmd_SelectRicrRtsaData 0x4000
484#define RCmd_SelectRicrRxFifostatus 0x5000
485#define RCmd_SelectRicrIntLevel 0x6000
486#define RCmd_SelectRicrdma_level 0x7000
487
488
489
490
491
492#define RECEIVE_STATUS BIT5
493#define RECEIVE_DATA BIT4
494#define TRANSMIT_STATUS BIT3
495#define TRANSMIT_DATA BIT2
496#define IO_PIN BIT1
497#define MISC BIT0
498
499
500
501
502
503
504#define RXSTATUS_SHORT_FRAME BIT8
505#define RXSTATUS_CODE_VIOLATION BIT8
506#define RXSTATUS_EXITED_HUNT BIT7
507#define RXSTATUS_IDLE_RECEIVED BIT6
508#define RXSTATUS_BREAK_RECEIVED BIT5
509#define RXSTATUS_ABORT_RECEIVED BIT5
510#define RXSTATUS_RXBOUND BIT4
511#define RXSTATUS_CRC_ERROR BIT3
512#define RXSTATUS_FRAMING_ERROR BIT3
513#define RXSTATUS_ABORT BIT2
514#define RXSTATUS_PARITY_ERROR BIT2
515#define RXSTATUS_OVERRUN BIT1
516#define RXSTATUS_DATA_AVAILABLE BIT0
517#define RXSTATUS_ALL 0x01f6
518#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
519
520
521
522
523
524#define IDLEMODE_FLAGS 0x0000
525#define IDLEMODE_ALT_ONE_ZERO 0x0100
526#define IDLEMODE_ZERO 0x0200
527#define IDLEMODE_ONE 0x0300
528#define IDLEMODE_ALT_MARK_SPACE 0x0500
529#define IDLEMODE_SPACE 0x0600
530#define IDLEMODE_MARK 0x0700
531#define IDLEMODE_MASK 0x0700
532
533
534
535
536#define IUSC_SL1660 0x4d44
537#define IUSC_PRE_SL1660 0x4553
538
539
540
541
542
543#define TCSR_PRESERVE 0x0F00
544
545#define TCSR_UNDERWAIT BIT11
546#define TXSTATUS_PREAMBLE_SENT BIT7
547#define TXSTATUS_IDLE_SENT BIT6
548#define TXSTATUS_ABORT_SENT BIT5
549#define TXSTATUS_EOF_SENT BIT4
550#define TXSTATUS_EOM_SENT BIT4
551#define TXSTATUS_CRC_SENT BIT3
552#define TXSTATUS_ALL_SENT BIT2
553#define TXSTATUS_UNDERRUN BIT1
554#define TXSTATUS_FIFO_EMPTY BIT0
555#define TXSTATUS_ALL 0x00fa
556#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
557
558
559#define MISCSTATUS_RXC_LATCHED BIT15
560#define MISCSTATUS_RXC BIT14
561#define MISCSTATUS_TXC_LATCHED BIT13
562#define MISCSTATUS_TXC BIT12
563#define MISCSTATUS_RI_LATCHED BIT11
564#define MISCSTATUS_RI BIT10
565#define MISCSTATUS_DSR_LATCHED BIT9
566#define MISCSTATUS_DSR BIT8
567#define MISCSTATUS_DCD_LATCHED BIT7
568#define MISCSTATUS_DCD BIT6
569#define MISCSTATUS_CTS_LATCHED BIT5
570#define MISCSTATUS_CTS BIT4
571#define MISCSTATUS_RCC_UNDERRUN BIT3
572#define MISCSTATUS_DPLL_NO_SYNC BIT2
573#define MISCSTATUS_BRG1_ZERO BIT1
574#define MISCSTATUS_BRG0_ZERO BIT0
575
576#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
577#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578
579#define SICR_RXC_ACTIVE BIT15
580#define SICR_RXC_INACTIVE BIT14
581#define SICR_RXC (BIT15+BIT14)
582#define SICR_TXC_ACTIVE BIT13
583#define SICR_TXC_INACTIVE BIT12
584#define SICR_TXC (BIT13+BIT12)
585#define SICR_RI_ACTIVE BIT11
586#define SICR_RI_INACTIVE BIT10
587#define SICR_RI (BIT11+BIT10)
588#define SICR_DSR_ACTIVE BIT9
589#define SICR_DSR_INACTIVE BIT8
590#define SICR_DSR (BIT9+BIT8)
591#define SICR_DCD_ACTIVE BIT7
592#define SICR_DCD_INACTIVE BIT6
593#define SICR_DCD (BIT7+BIT6)
594#define SICR_CTS_ACTIVE BIT5
595#define SICR_CTS_INACTIVE BIT4
596#define SICR_CTS (BIT5+BIT4)
597#define SICR_RCC_UNDERFLOW BIT3
598#define SICR_DPLL_NO_SYNC BIT2
599#define SICR_BRG1_ZERO BIT1
600#define SICR_BRG0_ZERO BIT0
601
602void usc_DisableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableMasterIrqBit( struct mgsl_struct *info );
604void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
606void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
607
608#define usc_EnableInterrupts( a, b ) \
609 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610
611#define usc_DisableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613
614#define usc_EnableMasterIrqBit(a) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616
617#define usc_DisableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619
620#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
621
622
623
624
625
626
627#define TXSTATUS_PREAMBLE_SENT BIT7
628#define TXSTATUS_IDLE_SENT BIT6
629#define TXSTATUS_ABORT_SENT BIT5
630#define TXSTATUS_EOF BIT4
631#define TXSTATUS_CRC_SENT BIT3
632#define TXSTATUS_ALL_SENT BIT2
633#define TXSTATUS_UNDERRUN BIT1
634#define TXSTATUS_FIFO_EMPTY BIT0
635
636#define DICR_MASTER BIT15
637#define DICR_TRANSMIT BIT0
638#define DICR_RECEIVE BIT1
639
640#define usc_EnableDmaInterrupts(a,b) \
641 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642
643#define usc_DisableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645
646#define usc_EnableStatusIrqs(a,b) \
647 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648
649#define usc_DisablestatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651
652
653
654
655
656#define DISABLE_UNCONDITIONAL 0
657#define DISABLE_END_OF_FRAME 1
658#define ENABLE_UNCONDITIONAL 2
659#define ENABLE_AUTO_CTS 3
660#define ENABLE_AUTO_DCD 3
661#define usc_EnableTransmitter(a,b) \
662 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
663#define usc_EnableReceiver(a,b) \
664 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665
666static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
667static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
668static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
669
670static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
671static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
672static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
674void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
675
676#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
677#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678
679#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680
681static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
682static void usc_start_receiver( struct mgsl_struct *info );
683static void usc_stop_receiver( struct mgsl_struct *info );
684
685static void usc_start_transmitter( struct mgsl_struct *info );
686static void usc_stop_transmitter( struct mgsl_struct *info );
687static void usc_set_txidle( struct mgsl_struct *info );
688static void usc_load_txfifo( struct mgsl_struct *info );
689
690static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
691static void usc_enable_loopback( struct mgsl_struct *info, int enable );
692
693static void usc_get_serial_signals( struct mgsl_struct *info );
694static void usc_set_serial_signals( struct mgsl_struct *info );
695
696static void usc_reset( struct mgsl_struct *info );
697
698static void usc_set_sync_mode( struct mgsl_struct *info );
699static void usc_set_sdlc_mode( struct mgsl_struct *info );
700static void usc_set_async_mode( struct mgsl_struct *info );
701static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
702
703static void usc_loopback_frame( struct mgsl_struct *info );
704
705static void mgsl_tx_timeout(unsigned long context);
706
707
708static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
709static void usc_loopmode_insert_request( struct mgsl_struct * info );
710static int usc_loopmode_active( struct mgsl_struct * info);
711static void usc_loopmode_send_done( struct mgsl_struct * info );
712
713static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
714
715#if SYNCLINK_GENERIC_HDLC
716#define dev_to_port(D) (dev_to_hdlc(D)->priv)
717static void hdlcdev_tx_done(struct mgsl_struct *info);
718static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
719static int hdlcdev_init(struct mgsl_struct *info);
720static void hdlcdev_exit(struct mgsl_struct *info);
721#endif
722
723
724
725
726
727
728#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
729(0x00400020 + \
730((WrHold) << 30) + \
731((WrDly) << 28) + \
732((RdDly) << 26) + \
733((Nwdd) << 20) + \
734((Nwad) << 15) + \
735((Nxda) << 13) + \
736((Nrdd) << 11) + \
737((Nrad) << 6) )
738
739static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
740
741
742
743
744static bool mgsl_register_test( struct mgsl_struct *info );
745static bool mgsl_irq_test( struct mgsl_struct *info );
746static bool mgsl_dma_test( struct mgsl_struct *info );
747static bool mgsl_memory_test( struct mgsl_struct *info );
748static int mgsl_adapter_test( struct mgsl_struct *info );
749
750
751
752
753static int mgsl_claim_resources(struct mgsl_struct *info);
754static void mgsl_release_resources(struct mgsl_struct *info);
755static void mgsl_add_device(struct mgsl_struct *info);
756static struct mgsl_struct* mgsl_allocate_device(void);
757
758
759
760
761static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
762static bool mgsl_get_rx_frame( struct mgsl_struct *info );
763static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
764static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
765static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
766static int num_free_tx_dma_buffers(struct mgsl_struct *info);
767static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
768static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
769
770
771
772
773static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
774static void mgsl_free_dma_buffers(struct mgsl_struct *info);
775static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
777static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
778static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
779static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
781static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
782static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
783static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
784static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
785
786
787
788
789static void mgsl_bh_handler(struct work_struct *work);
790static void mgsl_bh_receive(struct mgsl_struct *info);
791static void mgsl_bh_transmit(struct mgsl_struct *info);
792static void mgsl_bh_status(struct mgsl_struct *info);
793
794
795
796
797static void mgsl_isr_null( struct mgsl_struct *info );
798static void mgsl_isr_transmit_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_data( struct mgsl_struct *info );
800static void mgsl_isr_receive_status( struct mgsl_struct *info );
801static void mgsl_isr_transmit_status( struct mgsl_struct *info );
802static void mgsl_isr_io_pin( struct mgsl_struct *info );
803static void mgsl_isr_misc( struct mgsl_struct *info );
804static void mgsl_isr_receive_dma( struct mgsl_struct *info );
805static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
806
807typedef void (*isr_dispatch_func)(struct mgsl_struct *);
808
809static isr_dispatch_func UscIsrTable[7] =
810{
811 mgsl_isr_null,
812 mgsl_isr_misc,
813 mgsl_isr_io_pin,
814 mgsl_isr_transmit_data,
815 mgsl_isr_transmit_status,
816 mgsl_isr_receive_data,
817 mgsl_isr_receive_status
818};
819
820
821
822
823static int tiocmget(struct tty_struct *tty);
824static int tiocmset(struct tty_struct *tty,
825 unsigned int set, unsigned int clear);
826static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
827 __user *user_icount);
828static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
829static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
830static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
831static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
832static int mgsl_txenable(struct mgsl_struct * info, int enable);
833static int mgsl_txabort(struct mgsl_struct * info);
834static int mgsl_rxenable(struct mgsl_struct * info, int enable);
835static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
836static int mgsl_loopmode_send_done( struct mgsl_struct * info );
837
838
839static bool pci_registered;
840
841
842
843
844static struct mgsl_struct *mgsl_device_list;
845static int mgsl_device_count;
846
847
848
849
850
851
852static bool break_on_load;
853
854
855
856
857
858static int ttymajor;
859
860
861
862
863static int io[MAX_ISA_DEVICES];
864static int irq[MAX_ISA_DEVICES];
865static int dma[MAX_ISA_DEVICES];
866static int debug_level;
867static int maxframe[MAX_TOTAL_DEVICES];
868static int txdmabufs[MAX_TOTAL_DEVICES];
869static int txholdbufs[MAX_TOTAL_DEVICES];
870
871module_param(break_on_load, bool, 0);
872module_param(ttymajor, int, 0);
873module_param_array(io, int, NULL, 0);
874module_param_array(irq, int, NULL, 0);
875module_param_array(dma, int, NULL, 0);
876module_param(debug_level, int, 0);
877module_param_array(maxframe, int, NULL, 0);
878module_param_array(txdmabufs, int, NULL, 0);
879module_param_array(txholdbufs, int, NULL, 0);
880
881static char *driver_name = "SyncLink serial driver";
882static char *driver_version = "$Revision: 4.38 $";
883
884static int synclink_init_one (struct pci_dev *dev,
885 const struct pci_device_id *ent);
886static void synclink_remove_one (struct pci_dev *dev);
887
888static struct pci_device_id synclink_pci_tbl[] = {
889 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
890 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
891 { 0, },
892};
893MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
894
895MODULE_LICENSE("GPL");
896
897static struct pci_driver synclink_pci_driver = {
898 .name = "synclink",
899 .id_table = synclink_pci_tbl,
900 .probe = synclink_init_one,
901 .remove = __devexit_p(synclink_remove_one),
902};
903
904static struct tty_driver *serial_driver;
905
906
907#define WAKEUP_CHARS 256
908
909
910static void mgsl_change_params(struct mgsl_struct *info);
911static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
912
913
914
915
916
917
918
919static void* mgsl_get_text_ptr(void)
920{
921 return mgsl_get_text_ptr;
922}
923
924static inline int mgsl_paranoia_check(struct mgsl_struct *info,
925 char *name, const char *routine)
926{
927#ifdef MGSL_PARANOIA_CHECK
928 static const char *badmagic =
929 "Warning: bad magic number for mgsl struct (%s) in %s\n";
930 static const char *badinfo =
931 "Warning: null mgsl_struct for (%s) in %s\n";
932
933 if (!info) {
934 printk(badinfo, name, routine);
935 return 1;
936 }
937 if (info->magic != MGSL_MAGIC) {
938 printk(badmagic, name, routine);
939 return 1;
940 }
941#else
942 if (!info)
943 return 1;
944#endif
945 return 0;
946}
947
948
949
950
951
952
953
954
955
956
957static void ldisc_receive_buf(struct tty_struct *tty,
958 const __u8 *data, char *flags, int count)
959{
960 struct tty_ldisc *ld;
961 if (!tty)
962 return;
963 ld = tty_ldisc_ref(tty);
964 if (ld) {
965 if (ld->ops->receive_buf)
966 ld->ops->receive_buf(tty, data, flags, count);
967 tty_ldisc_deref(ld);
968 }
969}
970
971
972
973
974
975
976static void mgsl_stop(struct tty_struct *tty)
977{
978 struct mgsl_struct *info = tty->driver_data;
979 unsigned long flags;
980
981 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
982 return;
983
984 if ( debug_level >= DEBUG_LEVEL_INFO )
985 printk("mgsl_stop(%s)\n",info->device_name);
986
987 spin_lock_irqsave(&info->irq_spinlock,flags);
988 if (info->tx_enabled)
989 usc_stop_transmitter(info);
990 spin_unlock_irqrestore(&info->irq_spinlock,flags);
991
992}
993
994
995
996
997
998
999static void mgsl_start(struct tty_struct *tty)
1000{
1001 struct mgsl_struct *info = tty->driver_data;
1002 unsigned long flags;
1003
1004 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1005 return;
1006
1007 if ( debug_level >= DEBUG_LEVEL_INFO )
1008 printk("mgsl_start(%s)\n",info->device_name);
1009
1010 spin_lock_irqsave(&info->irq_spinlock,flags);
1011 if (!info->tx_enabled)
1012 usc_start_transmitter(info);
1013 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1014
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024static int mgsl_bh_action(struct mgsl_struct *info)
1025{
1026 unsigned long flags;
1027 int rc = 0;
1028
1029 spin_lock_irqsave(&info->irq_spinlock,flags);
1030
1031 if (info->pending_bh & BH_RECEIVE) {
1032 info->pending_bh &= ~BH_RECEIVE;
1033 rc = BH_RECEIVE;
1034 } else if (info->pending_bh & BH_TRANSMIT) {
1035 info->pending_bh &= ~BH_TRANSMIT;
1036 rc = BH_TRANSMIT;
1037 } else if (info->pending_bh & BH_STATUS) {
1038 info->pending_bh &= ~BH_STATUS;
1039 rc = BH_STATUS;
1040 }
1041
1042 if (!rc) {
1043
1044 info->bh_running = false;
1045 info->bh_requested = false;
1046 }
1047
1048 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1049
1050 return rc;
1051}
1052
1053
1054
1055
1056static void mgsl_bh_handler(struct work_struct *work)
1057{
1058 struct mgsl_struct *info =
1059 container_of(work, struct mgsl_struct, task);
1060 int action;
1061
1062 if (!info)
1063 return;
1064
1065 if ( debug_level >= DEBUG_LEVEL_BH )
1066 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1067 __FILE__,__LINE__,info->device_name);
1068
1069 info->bh_running = true;
1070
1071 while((action = mgsl_bh_action(info)) != 0) {
1072
1073
1074 if ( debug_level >= DEBUG_LEVEL_BH )
1075 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1076 __FILE__,__LINE__,action);
1077
1078 switch (action) {
1079
1080 case BH_RECEIVE:
1081 mgsl_bh_receive(info);
1082 break;
1083 case BH_TRANSMIT:
1084 mgsl_bh_transmit(info);
1085 break;
1086 case BH_STATUS:
1087 mgsl_bh_status(info);
1088 break;
1089 default:
1090
1091 printk("Unknown work item ID=%08X!\n", action);
1092 break;
1093 }
1094 }
1095
1096 if ( debug_level >= DEBUG_LEVEL_BH )
1097 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1098 __FILE__,__LINE__,info->device_name);
1099}
1100
1101static void mgsl_bh_receive(struct mgsl_struct *info)
1102{
1103 bool (*get_rx_frame)(struct mgsl_struct *info) =
1104 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1105
1106 if ( debug_level >= DEBUG_LEVEL_BH )
1107 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1108 __FILE__,__LINE__,info->device_name);
1109
1110 do
1111 {
1112 if (info->rx_rcc_underrun) {
1113 unsigned long flags;
1114 spin_lock_irqsave(&info->irq_spinlock,flags);
1115 usc_start_receiver(info);
1116 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1117 return;
1118 }
1119 } while(get_rx_frame(info));
1120}
1121
1122static void mgsl_bh_transmit(struct mgsl_struct *info)
1123{
1124 struct tty_struct *tty = info->port.tty;
1125 unsigned long flags;
1126
1127 if ( debug_level >= DEBUG_LEVEL_BH )
1128 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1129 __FILE__,__LINE__,info->device_name);
1130
1131 if (tty)
1132 tty_wakeup(tty);
1133
1134
1135
1136
1137 spin_lock_irqsave(&info->irq_spinlock,flags);
1138 if ( !info->tx_active && info->loopmode_send_done_requested )
1139 usc_loopmode_send_done( info );
1140 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1141}
1142
1143static void mgsl_bh_status(struct mgsl_struct *info)
1144{
1145 if ( debug_level >= DEBUG_LEVEL_BH )
1146 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1147 __FILE__,__LINE__,info->device_name);
1148
1149 info->ri_chkcount = 0;
1150 info->dsr_chkcount = 0;
1151 info->dcd_chkcount = 0;
1152 info->cts_chkcount = 0;
1153}
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164static void mgsl_isr_receive_status( struct mgsl_struct *info )
1165{
1166 u16 status = usc_InReg( info, RCSR );
1167
1168 if ( debug_level >= DEBUG_LEVEL_ISR )
1169 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1170 __FILE__,__LINE__,status);
1171
1172 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1173 info->loopmode_insert_requested &&
1174 usc_loopmode_active(info) )
1175 {
1176 ++info->icount.rxabort;
1177 info->loopmode_insert_requested = false;
1178
1179
1180 info->cmr_value &= ~BIT13;
1181 usc_OutReg(info, CMR, info->cmr_value);
1182
1183
1184 usc_OutReg(info, RICR,
1185 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1186 }
1187
1188 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1189 if (status & RXSTATUS_EXITED_HUNT)
1190 info->icount.exithunt++;
1191 if (status & RXSTATUS_IDLE_RECEIVED)
1192 info->icount.rxidle++;
1193 wake_up_interruptible(&info->event_wait_q);
1194 }
1195
1196 if (status & RXSTATUS_OVERRUN){
1197 info->icount.rxover++;
1198 usc_process_rxoverrun_sync( info );
1199 }
1200
1201 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1202 usc_UnlatchRxstatusBits( info, status );
1203
1204}
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1217{
1218 u16 status = usc_InReg( info, TCSR );
1219
1220 if ( debug_level >= DEBUG_LEVEL_ISR )
1221 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1222 __FILE__,__LINE__,status);
1223
1224 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1225 usc_UnlatchTxstatusBits( info, status );
1226
1227 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1228 {
1229
1230
1231
1232
1233
1234 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1235 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1236 }
1237
1238 if ( status & TXSTATUS_EOF_SENT )
1239 info->icount.txok++;
1240 else if ( status & TXSTATUS_UNDERRUN )
1241 info->icount.txunder++;
1242 else if ( status & TXSTATUS_ABORT_SENT )
1243 info->icount.txabort++;
1244 else
1245 info->icount.txunder++;
1246
1247 info->tx_active = false;
1248 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1249 del_timer(&info->tx_timer);
1250
1251 if ( info->drop_rts_on_tx_done ) {
1252 usc_get_serial_signals( info );
1253 if ( info->serial_signals & SerialSignal_RTS ) {
1254 info->serial_signals &= ~SerialSignal_RTS;
1255 usc_set_serial_signals( info );
1256 }
1257 info->drop_rts_on_tx_done = false;
1258 }
1259
1260#if SYNCLINK_GENERIC_HDLC
1261 if (info->netcount)
1262 hdlcdev_tx_done(info);
1263 else
1264#endif
1265 {
1266 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1267 usc_stop_transmitter(info);
1268 return;
1269 }
1270 info->pending_bh |= BH_TRANSMIT;
1271 }
1272
1273}
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283static void mgsl_isr_io_pin( struct mgsl_struct *info )
1284{
1285 struct mgsl_icount *icount;
1286 u16 status = usc_InReg( info, MISR );
1287
1288 if ( debug_level >= DEBUG_LEVEL_ISR )
1289 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1290 __FILE__,__LINE__,status);
1291
1292 usc_ClearIrqPendingBits( info, IO_PIN );
1293 usc_UnlatchIostatusBits( info, status );
1294
1295 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1296 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1297 icount = &info->icount;
1298
1299 if (status & MISCSTATUS_RI_LATCHED) {
1300 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1301 usc_DisablestatusIrqs(info,SICR_RI);
1302 icount->rng++;
1303 if ( status & MISCSTATUS_RI )
1304 info->input_signal_events.ri_up++;
1305 else
1306 info->input_signal_events.ri_down++;
1307 }
1308 if (status & MISCSTATUS_DSR_LATCHED) {
1309 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1310 usc_DisablestatusIrqs(info,SICR_DSR);
1311 icount->dsr++;
1312 if ( status & MISCSTATUS_DSR )
1313 info->input_signal_events.dsr_up++;
1314 else
1315 info->input_signal_events.dsr_down++;
1316 }
1317 if (status & MISCSTATUS_DCD_LATCHED) {
1318 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1319 usc_DisablestatusIrqs(info,SICR_DCD);
1320 icount->dcd++;
1321 if (status & MISCSTATUS_DCD) {
1322 info->input_signal_events.dcd_up++;
1323 } else
1324 info->input_signal_events.dcd_down++;
1325#if SYNCLINK_GENERIC_HDLC
1326 if (info->netcount) {
1327 if (status & MISCSTATUS_DCD)
1328 netif_carrier_on(info->netdev);
1329 else
1330 netif_carrier_off(info->netdev);
1331 }
1332#endif
1333 }
1334 if (status & MISCSTATUS_CTS_LATCHED)
1335 {
1336 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1337 usc_DisablestatusIrqs(info,SICR_CTS);
1338 icount->cts++;
1339 if ( status & MISCSTATUS_CTS )
1340 info->input_signal_events.cts_up++;
1341 else
1342 info->input_signal_events.cts_down++;
1343 }
1344 wake_up_interruptible(&info->status_event_wait_q);
1345 wake_up_interruptible(&info->event_wait_q);
1346
1347 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1348 (status & MISCSTATUS_DCD_LATCHED) ) {
1349 if ( debug_level >= DEBUG_LEVEL_ISR )
1350 printk("%s CD now %s...", info->device_name,
1351 (status & MISCSTATUS_DCD) ? "on" : "off");
1352 if (status & MISCSTATUS_DCD)
1353 wake_up_interruptible(&info->port.open_wait);
1354 else {
1355 if ( debug_level >= DEBUG_LEVEL_ISR )
1356 printk("doing serial hangup...");
1357 if (info->port.tty)
1358 tty_hangup(info->port.tty);
1359 }
1360 }
1361
1362 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1363 (status & MISCSTATUS_CTS_LATCHED) ) {
1364 if (info->port.tty->hw_stopped) {
1365 if (status & MISCSTATUS_CTS) {
1366 if ( debug_level >= DEBUG_LEVEL_ISR )
1367 printk("CTS tx start...");
1368 if (info->port.tty)
1369 info->port.tty->hw_stopped = 0;
1370 usc_start_transmitter(info);
1371 info->pending_bh |= BH_TRANSMIT;
1372 return;
1373 }
1374 } else {
1375 if (!(status & MISCSTATUS_CTS)) {
1376 if ( debug_level >= DEBUG_LEVEL_ISR )
1377 printk("CTS tx stop...");
1378 if (info->port.tty)
1379 info->port.tty->hw_stopped = 1;
1380 usc_stop_transmitter(info);
1381 }
1382 }
1383 }
1384 }
1385
1386 info->pending_bh |= BH_STATUS;
1387
1388
1389 if ( status & MISCSTATUS_TXC_LATCHED ){
1390 usc_OutReg( info, SICR,
1391 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1392 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1393 info->irq_occurred = true;
1394 }
1395
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1406{
1407 if ( debug_level >= DEBUG_LEVEL_ISR )
1408 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1409 __FILE__,__LINE__,info->xmit_cnt);
1410
1411 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1412
1413 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1414 usc_stop_transmitter(info);
1415 return;
1416 }
1417
1418 if ( info->xmit_cnt )
1419 usc_load_txfifo( info );
1420 else
1421 info->tx_active = false;
1422
1423 if (info->xmit_cnt < WAKEUP_CHARS)
1424 info->pending_bh |= BH_TRANSMIT;
1425
1426}
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437static void mgsl_isr_receive_data( struct mgsl_struct *info )
1438{
1439 int Fifocount;
1440 u16 status;
1441 int work = 0;
1442 unsigned char DataByte;
1443 struct tty_struct *tty = info->port.tty;
1444 struct mgsl_icount *icount = &info->icount;
1445
1446 if ( debug_level >= DEBUG_LEVEL_ISR )
1447 printk("%s(%d):mgsl_isr_receive_data\n",
1448 __FILE__,__LINE__);
1449
1450 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1451
1452
1453 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1454
1455
1456
1457 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1458
1459
1460
1461 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1462 int flag;
1463
1464
1465 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1466 info->io_base + CCAR );
1467 DataByte = inb( info->io_base + CCAR );
1468
1469
1470 status = usc_InReg(info, RCSR);
1471 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1472 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1473 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1474
1475 icount->rx++;
1476
1477 flag = 0;
1478 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1479 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1480 printk("rxerr=%04X\n",status);
1481
1482 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1483 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1484 icount->brk++;
1485 } else if (status & RXSTATUS_PARITY_ERROR)
1486 icount->parity++;
1487 else if (status & RXSTATUS_FRAMING_ERROR)
1488 icount->frame++;
1489 else if (status & RXSTATUS_OVERRUN) {
1490
1491
1492 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1493 icount->overrun++;
1494 }
1495
1496
1497 if (status & info->ignore_status_mask)
1498 continue;
1499
1500 status &= info->read_status_mask;
1501
1502 if (status & RXSTATUS_BREAK_RECEIVED) {
1503 flag = TTY_BREAK;
1504 if (info->port.flags & ASYNC_SAK)
1505 do_SAK(tty);
1506 } else if (status & RXSTATUS_PARITY_ERROR)
1507 flag = TTY_PARITY;
1508 else if (status & RXSTATUS_FRAMING_ERROR)
1509 flag = TTY_FRAME;
1510 }
1511 tty_insert_flip_char(tty, DataByte, flag);
1512 if (status & RXSTATUS_OVERRUN) {
1513
1514
1515
1516
1517 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1518 }
1519 }
1520
1521 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1522 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1523 __FILE__,__LINE__,icount->rx,icount->brk,
1524 icount->parity,icount->frame,icount->overrun);
1525 }
1526
1527 if(work)
1528 tty_flip_buffer_push(tty);
1529}
1530
1531
1532
1533
1534
1535
1536
1537
1538static void mgsl_isr_misc( struct mgsl_struct *info )
1539{
1540 u16 status = usc_InReg( info, MISR );
1541
1542 if ( debug_level >= DEBUG_LEVEL_ISR )
1543 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1544 __FILE__,__LINE__,status);
1545
1546 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1547 (info->params.mode == MGSL_MODE_HDLC)) {
1548
1549
1550 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1551 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1552 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1553 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1554 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1555
1556
1557 info->pending_bh |= BH_RECEIVE;
1558 info->rx_rcc_underrun = true;
1559 }
1560
1561 usc_ClearIrqPendingBits( info, MISC );
1562 usc_UnlatchMiscstatusBits( info, status );
1563
1564}
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574static void mgsl_isr_null( struct mgsl_struct *info )
1575{
1576
1577}
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1599{
1600 u16 status;
1601
1602
1603 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1604
1605
1606
1607 status = usc_InDmaReg( info, RDMR );
1608
1609 if ( debug_level >= DEBUG_LEVEL_ISR )
1610 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1611 __FILE__,__LINE__,info->device_name,status);
1612
1613 info->pending_bh |= BH_RECEIVE;
1614
1615 if ( status & BIT3 ) {
1616 info->rx_overflow = true;
1617 info->icount.buf_overrun++;
1618 }
1619
1620}
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1643{
1644 u16 status;
1645
1646
1647 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1648
1649
1650
1651
1652 status = usc_InDmaReg( info, TDMR );
1653
1654 if ( debug_level >= DEBUG_LEVEL_ISR )
1655 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1656 __FILE__,__LINE__,info->device_name,status);
1657
1658 if ( status & BIT2 ) {
1659 --info->tx_dma_buffers_used;
1660
1661
1662
1663
1664 if ( load_next_tx_holding_buffer(info) ) {
1665
1666
1667
1668 info->pending_bh |= BH_TRANSMIT;
1669 }
1670 }
1671
1672}
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1686{
1687 struct mgsl_struct *info = dev_id;
1688 u16 UscVector;
1689 u16 DmaVector;
1690
1691 if ( debug_level >= DEBUG_LEVEL_ISR )
1692 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1693 __FILE__, __LINE__, info->irq_level);
1694
1695 spin_lock(&info->irq_spinlock);
1696
1697 for(;;) {
1698
1699 UscVector = usc_InReg(info, IVR) >> 9;
1700 DmaVector = usc_InDmaReg(info, DIVR);
1701
1702 if ( debug_level >= DEBUG_LEVEL_ISR )
1703 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1704 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1705
1706 if ( !UscVector && !DmaVector )
1707 break;
1708
1709
1710 if ( UscVector )
1711 (*UscIsrTable[UscVector])(info);
1712 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1713 mgsl_isr_transmit_dma(info);
1714 else
1715 mgsl_isr_receive_dma(info);
1716
1717 if ( info->isr_overflow ) {
1718 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1719 __FILE__, __LINE__, info->device_name, info->irq_level);
1720 usc_DisableMasterIrqBit(info);
1721 usc_DisableDmaInterrupts(info,DICR_MASTER);
1722 break;
1723 }
1724 }
1725
1726
1727
1728
1729
1730 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1731 if ( debug_level >= DEBUG_LEVEL_ISR )
1732 printk("%s(%d):%s queueing bh task.\n",
1733 __FILE__,__LINE__,info->device_name);
1734 schedule_work(&info->task);
1735 info->bh_requested = true;
1736 }
1737
1738 spin_unlock(&info->irq_spinlock);
1739
1740 if ( debug_level >= DEBUG_LEVEL_ISR )
1741 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1742 __FILE__, __LINE__, info->irq_level);
1743
1744 return IRQ_HANDLED;
1745}
1746
1747
1748
1749
1750
1751
1752
1753
1754static int startup(struct mgsl_struct * info)
1755{
1756 int retval = 0;
1757
1758 if ( debug_level >= DEBUG_LEVEL_INFO )
1759 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1760
1761 if (info->port.flags & ASYNC_INITIALIZED)
1762 return 0;
1763
1764 if (!info->xmit_buf) {
1765
1766 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1767 if (!info->xmit_buf) {
1768 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1769 __FILE__,__LINE__,info->device_name);
1770 return -ENOMEM;
1771 }
1772 }
1773
1774 info->pending_bh = 0;
1775
1776 memset(&info->icount, 0, sizeof(info->icount));
1777
1778 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1779
1780
1781 retval = mgsl_claim_resources(info);
1782
1783
1784 if ( !retval )
1785 retval = mgsl_adapter_test(info);
1786
1787 if ( retval ) {
1788 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1789 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1790 mgsl_release_resources(info);
1791 return retval;
1792 }
1793
1794
1795 mgsl_change_params(info);
1796
1797 if (info->port.tty)
1798 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1799
1800 info->port.flags |= ASYNC_INITIALIZED;
1801
1802 return 0;
1803
1804}
1805
1806
1807
1808
1809
1810
1811
1812
1813static void shutdown(struct mgsl_struct * info)
1814{
1815 unsigned long flags;
1816
1817 if (!(info->port.flags & ASYNC_INITIALIZED))
1818 return;
1819
1820 if (debug_level >= DEBUG_LEVEL_INFO)
1821 printk("%s(%d):mgsl_shutdown(%s)\n",
1822 __FILE__,__LINE__, info->device_name );
1823
1824
1825
1826 wake_up_interruptible(&info->status_event_wait_q);
1827 wake_up_interruptible(&info->event_wait_q);
1828
1829 del_timer_sync(&info->tx_timer);
1830
1831 if (info->xmit_buf) {
1832 free_page((unsigned long) info->xmit_buf);
1833 info->xmit_buf = NULL;
1834 }
1835
1836 spin_lock_irqsave(&info->irq_spinlock,flags);
1837 usc_DisableMasterIrqBit(info);
1838 usc_stop_receiver(info);
1839 usc_stop_transmitter(info);
1840 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1841 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1842 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1843
1844
1845
1846
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1848
1849
1850
1851
1852 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1853
1854 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1855 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1856 usc_set_serial_signals(info);
1857 }
1858
1859 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1860
1861 mgsl_release_resources(info);
1862
1863 if (info->port.tty)
1864 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1865
1866 info->port.flags &= ~ASYNC_INITIALIZED;
1867
1868}
1869
1870static void mgsl_program_hw(struct mgsl_struct *info)
1871{
1872 unsigned long flags;
1873
1874 spin_lock_irqsave(&info->irq_spinlock,flags);
1875
1876 usc_stop_receiver(info);
1877 usc_stop_transmitter(info);
1878 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1879
1880 if (info->params.mode == MGSL_MODE_HDLC ||
1881 info->params.mode == MGSL_MODE_RAW ||
1882 info->netcount)
1883 usc_set_sync_mode(info);
1884 else
1885 usc_set_async_mode(info);
1886
1887 usc_set_serial_signals(info);
1888
1889 info->dcd_chkcount = 0;
1890 info->cts_chkcount = 0;
1891 info->ri_chkcount = 0;
1892 info->dsr_chkcount = 0;
1893
1894 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1895 usc_EnableInterrupts(info, IO_PIN);
1896 usc_get_serial_signals(info);
1897
1898 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1899 usc_start_receiver(info);
1900
1901 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1902}
1903
1904
1905
1906static void mgsl_change_params(struct mgsl_struct *info)
1907{
1908 unsigned cflag;
1909 int bits_per_char;
1910
1911 if (!info->port.tty || !info->port.tty->termios)
1912 return;
1913
1914 if (debug_level >= DEBUG_LEVEL_INFO)
1915 printk("%s(%d):mgsl_change_params(%s)\n",
1916 __FILE__,__LINE__, info->device_name );
1917
1918 cflag = info->port.tty->termios->c_cflag;
1919
1920
1921
1922 if (cflag & CBAUD)
1923 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1924 else
1925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1926
1927
1928
1929 switch (cflag & CSIZE) {
1930 case CS5: info->params.data_bits = 5; break;
1931 case CS6: info->params.data_bits = 6; break;
1932 case CS7: info->params.data_bits = 7; break;
1933 case CS8: info->params.data_bits = 8; break;
1934
1935 default: info->params.data_bits = 7; break;
1936 }
1937
1938 if (cflag & CSTOPB)
1939 info->params.stop_bits = 2;
1940 else
1941 info->params.stop_bits = 1;
1942
1943 info->params.parity = ASYNC_PARITY_NONE;
1944 if (cflag & PARENB) {
1945 if (cflag & PARODD)
1946 info->params.parity = ASYNC_PARITY_ODD;
1947 else
1948 info->params.parity = ASYNC_PARITY_EVEN;
1949#ifdef CMSPAR
1950 if (cflag & CMSPAR)
1951 info->params.parity = ASYNC_PARITY_SPACE;
1952#endif
1953 }
1954
1955
1956
1957
1958 bits_per_char = info->params.data_bits +
1959 info->params.stop_bits + 1;
1960
1961
1962
1963
1964
1965 if (info->params.data_rate <= 460800)
1966 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1967
1968 if ( info->params.data_rate ) {
1969 info->timeout = (32*HZ*bits_per_char) /
1970 info->params.data_rate;
1971 }
1972 info->timeout += HZ/50;
1973
1974 if (cflag & CRTSCTS)
1975 info->port.flags |= ASYNC_CTS_FLOW;
1976 else
1977 info->port.flags &= ~ASYNC_CTS_FLOW;
1978
1979 if (cflag & CLOCAL)
1980 info->port.flags &= ~ASYNC_CHECK_CD;
1981 else
1982 info->port.flags |= ASYNC_CHECK_CD;
1983
1984
1985
1986 info->read_status_mask = RXSTATUS_OVERRUN;
1987 if (I_INPCK(info->port.tty))
1988 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1989 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1990 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991
1992 if (I_IGNPAR(info->port.tty))
1993 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1994 if (I_IGNBRK(info->port.tty)) {
1995 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1996
1997
1998
1999 if (I_IGNPAR(info->port.tty))
2000 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2001 }
2002
2003 mgsl_program_hw(info);
2004
2005}
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2017{
2018 struct mgsl_struct *info = tty->driver_data;
2019 unsigned long flags;
2020 int ret = 0;
2021
2022 if (debug_level >= DEBUG_LEVEL_INFO) {
2023 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2024 __FILE__, __LINE__, ch, info->device_name);
2025 }
2026
2027 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2028 return 0;
2029
2030 if (!info->xmit_buf)
2031 return 0;
2032
2033 spin_lock_irqsave(&info->irq_spinlock, flags);
2034
2035 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2036 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2037 info->xmit_buf[info->xmit_head++] = ch;
2038 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2039 info->xmit_cnt++;
2040 ret = 1;
2041 }
2042 }
2043 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2044 return ret;
2045
2046}
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056static void mgsl_flush_chars(struct tty_struct *tty)
2057{
2058 struct mgsl_struct *info = tty->driver_data;
2059 unsigned long flags;
2060
2061 if ( debug_level >= DEBUG_LEVEL_INFO )
2062 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2063 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2064
2065 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2066 return;
2067
2068 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2069 !info->xmit_buf)
2070 return;
2071
2072 if ( debug_level >= DEBUG_LEVEL_INFO )
2073 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2074 __FILE__,__LINE__,info->device_name );
2075
2076 spin_lock_irqsave(&info->irq_spinlock,flags);
2077
2078 if (!info->tx_active) {
2079 if ( (info->params.mode == MGSL_MODE_HDLC ||
2080 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2081
2082
2083
2084 mgsl_load_tx_dma_buffer(info,
2085 info->xmit_buf,info->xmit_cnt);
2086 }
2087 usc_start_transmitter(info);
2088 }
2089
2090 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2091
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106static int mgsl_write(struct tty_struct * tty,
2107 const unsigned char *buf, int count)
2108{
2109 int c, ret = 0;
2110 struct mgsl_struct *info = tty->driver_data;
2111 unsigned long flags;
2112
2113 if ( debug_level >= DEBUG_LEVEL_INFO )
2114 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2115 __FILE__,__LINE__,info->device_name,count);
2116
2117 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2118 goto cleanup;
2119
2120 if (!info->xmit_buf)
2121 goto cleanup;
2122
2123 if ( info->params.mode == MGSL_MODE_HDLC ||
2124 info->params.mode == MGSL_MODE_RAW ) {
2125
2126 if (info->tx_active) {
2127
2128 if ( info->params.mode == MGSL_MODE_HDLC ) {
2129 ret = 0;
2130 goto cleanup;
2131 }
2132
2133
2134
2135
2136
2137 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2138
2139 ret = 0;
2140 goto cleanup;
2141 }
2142
2143
2144 ret = count;
2145 save_tx_buffer_request(info,buf,count);
2146
2147
2148
2149
2150 spin_lock_irqsave(&info->irq_spinlock,flags);
2151 load_next_tx_holding_buffer(info);
2152 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2153 goto cleanup;
2154 }
2155
2156
2157
2158
2159
2160 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2161 !usc_loopmode_active(info) )
2162 {
2163 ret = 0;
2164 goto cleanup;
2165 }
2166
2167 if ( info->xmit_cnt ) {
2168
2169
2170 ret = 0;
2171
2172
2173
2174 mgsl_load_tx_dma_buffer(info,
2175 info->xmit_buf,info->xmit_cnt);
2176 if ( debug_level >= DEBUG_LEVEL_INFO )
2177 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2178 __FILE__,__LINE__,info->device_name);
2179 } else {
2180 if ( debug_level >= DEBUG_LEVEL_INFO )
2181 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2182 __FILE__,__LINE__,info->device_name);
2183 ret = count;
2184 info->xmit_cnt = count;
2185 mgsl_load_tx_dma_buffer(info,buf,count);
2186 }
2187 } else {
2188 while (1) {
2189 spin_lock_irqsave(&info->irq_spinlock,flags);
2190 c = min_t(int, count,
2191 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2192 SERIAL_XMIT_SIZE - info->xmit_head));
2193 if (c <= 0) {
2194 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2195 break;
2196 }
2197 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2198 info->xmit_head = ((info->xmit_head + c) &
2199 (SERIAL_XMIT_SIZE-1));
2200 info->xmit_cnt += c;
2201 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2202 buf += c;
2203 count -= c;
2204 ret += c;
2205 }
2206 }
2207
2208 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2209 spin_lock_irqsave(&info->irq_spinlock,flags);
2210 if (!info->tx_active)
2211 usc_start_transmitter(info);
2212 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2213 }
2214cleanup:
2215 if ( debug_level >= DEBUG_LEVEL_INFO )
2216 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2217 __FILE__,__LINE__,info->device_name,ret);
2218
2219 return ret;
2220
2221}
2222
2223
2224
2225
2226
2227
2228
2229
2230static int mgsl_write_room(struct tty_struct *tty)
2231{
2232 struct mgsl_struct *info = tty->driver_data;
2233 int ret;
2234
2235 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2236 return 0;
2237 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2238 if (ret < 0)
2239 ret = 0;
2240
2241 if (debug_level >= DEBUG_LEVEL_INFO)
2242 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2243 __FILE__,__LINE__, info->device_name,ret );
2244
2245 if ( info->params.mode == MGSL_MODE_HDLC ||
2246 info->params.mode == MGSL_MODE_RAW ) {
2247
2248 if ( info->tx_active )
2249 return 0;
2250 else
2251 return HDLC_MAX_FRAME_SIZE;
2252 }
2253
2254 return ret;
2255
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265static int mgsl_chars_in_buffer(struct tty_struct *tty)
2266{
2267 struct mgsl_struct *info = tty->driver_data;
2268
2269 if (debug_level >= DEBUG_LEVEL_INFO)
2270 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2271 __FILE__,__LINE__, info->device_name );
2272
2273 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2274 return 0;
2275
2276 if (debug_level >= DEBUG_LEVEL_INFO)
2277 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2278 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2279
2280 if ( info->params.mode == MGSL_MODE_HDLC ||
2281 info->params.mode == MGSL_MODE_RAW ) {
2282
2283 if ( info->tx_active )
2284 return info->max_frame_size;
2285 else
2286 return 0;
2287 }
2288
2289 return info->xmit_cnt;
2290}
2291
2292
2293
2294
2295
2296
2297
2298
2299static void mgsl_flush_buffer(struct tty_struct *tty)
2300{
2301 struct mgsl_struct *info = tty->driver_data;
2302 unsigned long flags;
2303
2304 if (debug_level >= DEBUG_LEVEL_INFO)
2305 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2306 __FILE__,__LINE__, info->device_name );
2307
2308 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2309 return;
2310
2311 spin_lock_irqsave(&info->irq_spinlock,flags);
2312 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2313 del_timer(&info->tx_timer);
2314 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2315
2316 tty_wakeup(tty);
2317}
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2328{
2329 struct mgsl_struct *info = tty->driver_data;
2330 unsigned long flags;
2331
2332 if (debug_level >= DEBUG_LEVEL_INFO)
2333 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2334 __FILE__,__LINE__, info->device_name, ch );
2335
2336 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2337 return;
2338
2339 info->x_char = ch;
2340 if (ch) {
2341
2342 spin_lock_irqsave(&info->irq_spinlock,flags);
2343 if (!info->tx_enabled)
2344 usc_start_transmitter(info);
2345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2346 }
2347}
2348
2349
2350
2351
2352
2353
2354
2355
2356static void mgsl_throttle(struct tty_struct * tty)
2357{
2358 struct mgsl_struct *info = tty->driver_data;
2359 unsigned long flags;
2360
2361 if (debug_level >= DEBUG_LEVEL_INFO)
2362 printk("%s(%d):mgsl_throttle(%s) entry\n",
2363 __FILE__,__LINE__, info->device_name );
2364
2365 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2366 return;
2367
2368 if (I_IXOFF(tty))
2369 mgsl_send_xchar(tty, STOP_CHAR(tty));
2370
2371 if (tty->termios->c_cflag & CRTSCTS) {
2372 spin_lock_irqsave(&info->irq_spinlock,flags);
2373 info->serial_signals &= ~SerialSignal_RTS;
2374 usc_set_serial_signals(info);
2375 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2376 }
2377}
2378
2379
2380
2381
2382
2383
2384
2385
2386static void mgsl_unthrottle(struct tty_struct * tty)
2387{
2388 struct mgsl_struct *info = tty->driver_data;
2389 unsigned long flags;
2390
2391 if (debug_level >= DEBUG_LEVEL_INFO)
2392 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2393 __FILE__,__LINE__, info->device_name );
2394
2395 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2396 return;
2397
2398 if (I_IXOFF(tty)) {
2399 if (info->x_char)
2400 info->x_char = 0;
2401 else
2402 mgsl_send_xchar(tty, START_CHAR(tty));
2403 }
2404
2405 if (tty->termios->c_cflag & CRTSCTS) {
2406 spin_lock_irqsave(&info->irq_spinlock,flags);
2407 info->serial_signals |= SerialSignal_RTS;
2408 usc_set_serial_signals(info);
2409 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2410 }
2411
2412}
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2424{
2425 int err;
2426
2427 if (debug_level >= DEBUG_LEVEL_INFO)
2428 printk("%s(%d):mgsl_get_params(%s)\n",
2429 __FILE__,__LINE__, info->device_name);
2430
2431 if (!user_icount) {
2432 memset(&info->icount, 0, sizeof(info->icount));
2433 } else {
2434 mutex_lock(&info->port.mutex);
2435 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2436 mutex_unlock(&info->port.mutex);
2437 if (err)
2438 return -EFAULT;
2439 }
2440
2441 return 0;
2442
2443}
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2455{
2456 int err;
2457 if (debug_level >= DEBUG_LEVEL_INFO)
2458 printk("%s(%d):mgsl_get_params(%s)\n",
2459 __FILE__,__LINE__, info->device_name);
2460
2461 mutex_lock(&info->port.mutex);
2462 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2463 mutex_unlock(&info->port.mutex);
2464 if (err) {
2465 if ( debug_level >= DEBUG_LEVEL_INFO )
2466 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2467 __FILE__,__LINE__,info->device_name);
2468 return -EFAULT;
2469 }
2470
2471 return 0;
2472
2473}
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2487{
2488 unsigned long flags;
2489 MGSL_PARAMS tmp_params;
2490 int err;
2491
2492 if (debug_level >= DEBUG_LEVEL_INFO)
2493 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2494 info->device_name );
2495 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2496 if (err) {
2497 if ( debug_level >= DEBUG_LEVEL_INFO )
2498 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2499 __FILE__,__LINE__,info->device_name);
2500 return -EFAULT;
2501 }
2502
2503 mutex_lock(&info->port.mutex);
2504 spin_lock_irqsave(&info->irq_spinlock,flags);
2505 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2506 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2507
2508 mgsl_change_params(info);
2509 mutex_unlock(&info->port.mutex);
2510
2511 return 0;
2512
2513}
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2525{
2526 int err;
2527
2528 if (debug_level >= DEBUG_LEVEL_INFO)
2529 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2530 __FILE__,__LINE__, info->device_name, info->idle_mode);
2531
2532 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2533 if (err) {
2534 if ( debug_level >= DEBUG_LEVEL_INFO )
2535 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2536 __FILE__,__LINE__,info->device_name);
2537 return -EFAULT;
2538 }
2539
2540 return 0;
2541
2542}
2543
2544
2545
2546
2547
2548
2549
2550
2551static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2552{
2553 unsigned long flags;
2554
2555 if (debug_level >= DEBUG_LEVEL_INFO)
2556 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2557 info->device_name, idle_mode );
2558
2559 spin_lock_irqsave(&info->irq_spinlock,flags);
2560 info->idle_mode = idle_mode;
2561 usc_set_txidle( info );
2562 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2563 return 0;
2564
2565}
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578static int mgsl_txenable(struct mgsl_struct * info, int enable)
2579{
2580 unsigned long flags;
2581
2582 if (debug_level >= DEBUG_LEVEL_INFO)
2583 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2584 info->device_name, enable);
2585
2586 spin_lock_irqsave(&info->irq_spinlock,flags);
2587 if ( enable ) {
2588 if ( !info->tx_enabled ) {
2589
2590 usc_start_transmitter(info);
2591
2592
2593
2594
2595
2596
2597
2598 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2599 usc_loopmode_insert_request( info );
2600 }
2601 } else {
2602 if ( info->tx_enabled )
2603 usc_stop_transmitter(info);
2604 }
2605 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2606 return 0;
2607
2608}
2609
2610
2611
2612
2613
2614
2615static int mgsl_txabort(struct mgsl_struct * info)
2616{
2617 unsigned long flags;
2618
2619 if (debug_level >= DEBUG_LEVEL_INFO)
2620 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2621 info->device_name);
2622
2623 spin_lock_irqsave(&info->irq_spinlock,flags);
2624 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2625 {
2626 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2627 usc_loopmode_cancel_transmit( info );
2628 else
2629 usc_TCmd(info,TCmd_SendAbort);
2630 }
2631 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2632 return 0;
2633
2634}
2635
2636
2637
2638
2639
2640
2641
2642static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2643{
2644 unsigned long flags;
2645
2646 if (debug_level >= DEBUG_LEVEL_INFO)
2647 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2648 info->device_name, enable);
2649
2650 spin_lock_irqsave(&info->irq_spinlock,flags);
2651 if ( enable ) {
2652 if ( !info->rx_enabled )
2653 usc_start_receiver(info);
2654 } else {
2655 if ( info->rx_enabled )
2656 usc_stop_receiver(info);
2657 }
2658 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2659 return 0;
2660
2661}
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2672{
2673 unsigned long flags;
2674 int s;
2675 int rc=0;
2676 struct mgsl_icount cprev, cnow;
2677 int events;
2678 int mask;
2679 struct _input_signal_events oldsigs, newsigs;
2680 DECLARE_WAITQUEUE(wait, current);
2681
2682 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2683 if (rc) {
2684 return -EFAULT;
2685 }
2686
2687 if (debug_level >= DEBUG_LEVEL_INFO)
2688 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2689 info->device_name, mask);
2690
2691 spin_lock_irqsave(&info->irq_spinlock,flags);
2692
2693
2694 usc_get_serial_signals(info);
2695 s = info->serial_signals;
2696 events = mask &
2697 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2698 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2699 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2700 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2701 if (events) {
2702 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2703 goto exit;
2704 }
2705
2706
2707 cprev = info->icount;
2708 oldsigs = info->input_signal_events;
2709
2710
2711 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2712 u16 oldreg = usc_InReg(info,RICR);
2713 u16 newreg = oldreg +
2714 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2715 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2716 if (oldreg != newreg)
2717 usc_OutReg(info, RICR, newreg);
2718 }
2719
2720 set_current_state(TASK_INTERRUPTIBLE);
2721 add_wait_queue(&info->event_wait_q, &wait);
2722
2723 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2724
2725
2726 for(;;) {
2727 schedule();
2728 if (signal_pending(current)) {
2729 rc = -ERESTARTSYS;
2730 break;
2731 }
2732
2733
2734 spin_lock_irqsave(&info->irq_spinlock,flags);
2735 cnow = info->icount;
2736 newsigs = info->input_signal_events;
2737 set_current_state(TASK_INTERRUPTIBLE);
2738 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2739
2740
2741 if (newsigs.dsr_up == oldsigs.dsr_up &&
2742 newsigs.dsr_down == oldsigs.dsr_down &&
2743 newsigs.dcd_up == oldsigs.dcd_up &&
2744 newsigs.dcd_down == oldsigs.dcd_down &&
2745 newsigs.cts_up == oldsigs.cts_up &&
2746 newsigs.cts_down == oldsigs.cts_down &&
2747 newsigs.ri_up == oldsigs.ri_up &&
2748 newsigs.ri_down == oldsigs.ri_down &&
2749 cnow.exithunt == cprev.exithunt &&
2750 cnow.rxidle == cprev.rxidle) {
2751 rc = -EIO;
2752 break;
2753 }
2754
2755 events = mask &
2756 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2757 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2758 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2759 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2760 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2761 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2762 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2763 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2764 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2765 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2766 if (events)
2767 break;
2768
2769 cprev = cnow;
2770 oldsigs = newsigs;
2771 }
2772
2773 remove_wait_queue(&info->event_wait_q, &wait);
2774 set_current_state(TASK_RUNNING);
2775
2776 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2777 spin_lock_irqsave(&info->irq_spinlock,flags);
2778 if (!waitqueue_active(&info->event_wait_q)) {
2779
2780 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2781 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2782 }
2783 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2784 }
2785exit:
2786 if ( rc == 0 )
2787 PUT_USER(rc, events, mask_ptr);
2788
2789 return rc;
2790
2791}
2792
2793static int modem_input_wait(struct mgsl_struct *info,int arg)
2794{
2795 unsigned long flags;
2796 int rc;
2797 struct mgsl_icount cprev, cnow;
2798 DECLARE_WAITQUEUE(wait, current);
2799
2800
2801 spin_lock_irqsave(&info->irq_spinlock,flags);
2802 cprev = info->icount;
2803 add_wait_queue(&info->status_event_wait_q, &wait);
2804 set_current_state(TASK_INTERRUPTIBLE);
2805 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2806
2807 for(;;) {
2808 schedule();
2809 if (signal_pending(current)) {
2810 rc = -ERESTARTSYS;
2811 break;
2812 }
2813
2814
2815 spin_lock_irqsave(&info->irq_spinlock,flags);
2816 cnow = info->icount;
2817 set_current_state(TASK_INTERRUPTIBLE);
2818 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2819
2820
2821 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2822 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2823 rc = -EIO;
2824 break;
2825 }
2826
2827
2828 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2829 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2830 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2831 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2832 rc = 0;
2833 break;
2834 }
2835
2836 cprev = cnow;
2837 }
2838 remove_wait_queue(&info->status_event_wait_q, &wait);
2839 set_current_state(TASK_RUNNING);
2840 return rc;
2841}
2842
2843
2844
2845static int tiocmget(struct tty_struct *tty)
2846{
2847 struct mgsl_struct *info = tty->driver_data;
2848 unsigned int result;
2849 unsigned long flags;
2850
2851 spin_lock_irqsave(&info->irq_spinlock,flags);
2852 usc_get_serial_signals(info);
2853 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2854
2855 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2856 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2857 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2858 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2859 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2860 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s tiocmget() value=%08X\n",
2864 __FILE__,__LINE__, info->device_name, result );
2865 return result;
2866}
2867
2868
2869
2870static int tiocmset(struct tty_struct *tty,
2871 unsigned int set, unsigned int clear)
2872{
2873 struct mgsl_struct *info = tty->driver_data;
2874 unsigned long flags;
2875
2876 if (debug_level >= DEBUG_LEVEL_INFO)
2877 printk("%s(%d):%s tiocmset(%x,%x)\n",
2878 __FILE__,__LINE__,info->device_name, set, clear);
2879
2880 if (set & TIOCM_RTS)
2881 info->serial_signals |= SerialSignal_RTS;
2882 if (set & TIOCM_DTR)
2883 info->serial_signals |= SerialSignal_DTR;
2884 if (clear & TIOCM_RTS)
2885 info->serial_signals &= ~SerialSignal_RTS;
2886 if (clear & TIOCM_DTR)
2887 info->serial_signals &= ~SerialSignal_DTR;
2888
2889 spin_lock_irqsave(&info->irq_spinlock,flags);
2890 usc_set_serial_signals(info);
2891 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2892
2893 return 0;
2894}
2895
2896
2897
2898
2899
2900
2901
2902static int mgsl_break(struct tty_struct *tty, int break_state)
2903{
2904 struct mgsl_struct * info = tty->driver_data;
2905 unsigned long flags;
2906
2907 if (debug_level >= DEBUG_LEVEL_INFO)
2908 printk("%s(%d):mgsl_break(%s,%d)\n",
2909 __FILE__,__LINE__, info->device_name, break_state);
2910
2911 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2912 return -EINVAL;
2913
2914 spin_lock_irqsave(&info->irq_spinlock,flags);
2915 if (break_state == -1)
2916 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2917 else
2918 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2919 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2920 return 0;
2921
2922}
2923
2924
2925
2926
2927
2928
2929
2930static int msgl_get_icount(struct tty_struct *tty,
2931 struct serial_icounter_struct *icount)
2932
2933{
2934 struct mgsl_struct * info = tty->driver_data;
2935 struct mgsl_icount cnow;
2936 unsigned long flags;
2937
2938 spin_lock_irqsave(&info->irq_spinlock,flags);
2939 cnow = info->icount;
2940 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2941
2942 icount->cts = cnow.cts;
2943 icount->dsr = cnow.dsr;
2944 icount->rng = cnow.rng;
2945 icount->dcd = cnow.dcd;
2946 icount->rx = cnow.rx;
2947 icount->tx = cnow.tx;
2948 icount->frame = cnow.frame;
2949 icount->overrun = cnow.overrun;
2950 icount->parity = cnow.parity;
2951 icount->brk = cnow.brk;
2952 icount->buf_overrun = cnow.buf_overrun;
2953 return 0;
2954}
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966static int mgsl_ioctl(struct tty_struct *tty,
2967 unsigned int cmd, unsigned long arg)
2968{
2969 struct mgsl_struct * info = tty->driver_data;
2970
2971 if (debug_level >= DEBUG_LEVEL_INFO)
2972 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2973 info->device_name, cmd );
2974
2975 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2976 return -ENODEV;
2977
2978 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2979 (cmd != TIOCMIWAIT)) {
2980 if (tty->flags & (1 << TTY_IO_ERROR))
2981 return -EIO;
2982 }
2983
2984 return mgsl_ioctl_common(info, cmd, arg);
2985}
2986
2987static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2988{
2989 void __user *argp = (void __user *)arg;
2990
2991 switch (cmd) {
2992 case MGSL_IOCGPARAMS:
2993 return mgsl_get_params(info, argp);
2994 case MGSL_IOCSPARAMS:
2995 return mgsl_set_params(info, argp);
2996 case MGSL_IOCGTXIDLE:
2997 return mgsl_get_txidle(info, argp);
2998 case MGSL_IOCSTXIDLE:
2999 return mgsl_set_txidle(info,(int)arg);
3000 case MGSL_IOCTXENABLE:
3001 return mgsl_txenable(info,(int)arg);
3002 case MGSL_IOCRXENABLE:
3003 return mgsl_rxenable(info,(int)arg);
3004 case MGSL_IOCTXABORT:
3005 return mgsl_txabort(info);
3006 case MGSL_IOCGSTATS:
3007 return mgsl_get_stats(info, argp);
3008 case MGSL_IOCWAITEVENT:
3009 return mgsl_wait_event(info, argp);
3010 case MGSL_IOCLOOPTXDONE:
3011 return mgsl_loopmode_send_done(info);
3012
3013
3014
3015 case TIOCMIWAIT:
3016 return modem_input_wait(info,(int)arg);
3017
3018 default:
3019 return -ENOIOCTLCMD;
3020 }
3021 return 0;
3022}
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3036{
3037 struct mgsl_struct *info = tty->driver_data;
3038 unsigned long flags;
3039
3040 if (debug_level >= DEBUG_LEVEL_INFO)
3041 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3042 tty->driver->name );
3043
3044 mgsl_change_params(info);
3045
3046
3047 if (old_termios->c_cflag & CBAUD &&
3048 !(tty->termios->c_cflag & CBAUD)) {
3049 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3050 spin_lock_irqsave(&info->irq_spinlock,flags);
3051 usc_set_serial_signals(info);
3052 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3053 }
3054
3055
3056 if (!(old_termios->c_cflag & CBAUD) &&
3057 tty->termios->c_cflag & CBAUD) {
3058 info->serial_signals |= SerialSignal_DTR;
3059 if (!(tty->termios->c_cflag & CRTSCTS) ||
3060 !test_bit(TTY_THROTTLED, &tty->flags)) {
3061 info->serial_signals |= SerialSignal_RTS;
3062 }
3063 spin_lock_irqsave(&info->irq_spinlock,flags);
3064 usc_set_serial_signals(info);
3065 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3066 }
3067
3068
3069 if (old_termios->c_cflag & CRTSCTS &&
3070 !(tty->termios->c_cflag & CRTSCTS)) {
3071 tty->hw_stopped = 0;
3072 mgsl_start(tty);
3073 }
3074
3075}
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089static void mgsl_close(struct tty_struct *tty, struct file * filp)
3090{
3091 struct mgsl_struct * info = tty->driver_data;
3092
3093 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3094 return;
3095
3096 if (debug_level >= DEBUG_LEVEL_INFO)
3097 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3098 __FILE__,__LINE__, info->device_name, info->port.count);
3099
3100 if (tty_port_close_start(&info->port, tty, filp) == 0)
3101 goto cleanup;
3102
3103 mutex_lock(&info->port.mutex);
3104 if (info->port.flags & ASYNC_INITIALIZED)
3105 mgsl_wait_until_sent(tty, info->timeout);
3106 mgsl_flush_buffer(tty);
3107 tty_ldisc_flush(tty);
3108 shutdown(info);
3109 mutex_unlock(&info->port.mutex);
3110
3111 tty_port_close_end(&info->port, tty);
3112 info->port.tty = NULL;
3113cleanup:
3114 if (debug_level >= DEBUG_LEVEL_INFO)
3115 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3116 tty->driver->name, info->port.count);
3117
3118}
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3132{
3133 struct mgsl_struct * info = tty->driver_data;
3134 unsigned long orig_jiffies, char_time;
3135
3136 if (!info )
3137 return;
3138
3139 if (debug_level >= DEBUG_LEVEL_INFO)
3140 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3141 __FILE__,__LINE__, info->device_name );
3142
3143 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3144 return;
3145
3146 if (!(info->port.flags & ASYNC_INITIALIZED))
3147 goto exit;
3148
3149 orig_jiffies = jiffies;
3150
3151
3152
3153
3154
3155
3156
3157 if ( info->params.data_rate ) {
3158 char_time = info->timeout/(32 * 5);
3159 if (!char_time)
3160 char_time++;
3161 } else
3162 char_time = 1;
3163
3164 if (timeout)
3165 char_time = min_t(unsigned long, char_time, timeout);
3166
3167 if ( info->params.mode == MGSL_MODE_HDLC ||
3168 info->params.mode == MGSL_MODE_RAW ) {
3169 while (info->tx_active) {
3170 msleep_interruptible(jiffies_to_msecs(char_time));
3171 if (signal_pending(current))
3172 break;
3173 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3174 break;
3175 }
3176 } else {
3177 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3178 info->tx_enabled) {
3179 msleep_interruptible(jiffies_to_msecs(char_time));
3180 if (signal_pending(current))
3181 break;
3182 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3183 break;
3184 }
3185 }
3186
3187exit:
3188 if (debug_level >= DEBUG_LEVEL_INFO)
3189 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3190 __FILE__,__LINE__, info->device_name );
3191
3192}
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202static void mgsl_hangup(struct tty_struct *tty)
3203{
3204 struct mgsl_struct * info = tty->driver_data;
3205
3206 if (debug_level >= DEBUG_LEVEL_INFO)
3207 printk("%s(%d):mgsl_hangup(%s)\n",
3208 __FILE__,__LINE__, info->device_name );
3209
3210 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3211 return;
3212
3213 mgsl_flush_buffer(tty);
3214 shutdown(info);
3215
3216 info->port.count = 0;
3217 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3218 info->port.tty = NULL;
3219
3220 wake_up_interruptible(&info->port.open_wait);
3221
3222}
3223
3224
3225
3226
3227
3228
3229
3230static int carrier_raised(struct tty_port *port)
3231{
3232 unsigned long flags;
3233 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3234
3235 spin_lock_irqsave(&info->irq_spinlock, flags);
3236 usc_get_serial_signals(info);
3237 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3238 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3239}
3240
3241static void dtr_rts(struct tty_port *port, int on)
3242{
3243 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3244 unsigned long flags;
3245
3246 spin_lock_irqsave(&info->irq_spinlock,flags);
3247 if (on)
3248 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3249 else
3250 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3251 usc_set_serial_signals(info);
3252 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3253}
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269static int block_til_ready(struct tty_struct *tty, struct file * filp,
3270 struct mgsl_struct *info)
3271{
3272 DECLARE_WAITQUEUE(wait, current);
3273 int retval;
3274 bool do_clocal = false;
3275 bool extra_count = false;
3276 unsigned long flags;
3277 int dcd;
3278 struct tty_port *port = &info->port;
3279
3280 if (debug_level >= DEBUG_LEVEL_INFO)
3281 printk("%s(%d):block_til_ready on %s\n",
3282 __FILE__,__LINE__, tty->driver->name );
3283
3284 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3285
3286 port->flags |= ASYNC_NORMAL_ACTIVE;
3287 return 0;
3288 }
3289
3290 if (tty->termios->c_cflag & CLOCAL)
3291 do_clocal = true;
3292
3293
3294
3295
3296
3297
3298
3299
3300 retval = 0;
3301 add_wait_queue(&port->open_wait, &wait);
3302
3303 if (debug_level >= DEBUG_LEVEL_INFO)
3304 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3305 __FILE__,__LINE__, tty->driver->name, port->count );
3306
3307 spin_lock_irqsave(&info->irq_spinlock, flags);
3308 if (!tty_hung_up_p(filp)) {
3309 extra_count = true;
3310 port->count--;
3311 }
3312 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3313 port->blocked_open++;
3314
3315 while (1) {
3316 if (tty->termios->c_cflag & CBAUD)
3317 tty_port_raise_dtr_rts(port);
3318
3319 set_current_state(TASK_INTERRUPTIBLE);
3320
3321 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3322 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3323 -EAGAIN : -ERESTARTSYS;
3324 break;
3325 }
3326
3327 dcd = tty_port_carrier_raised(&info->port);
3328
3329 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3330 break;
3331
3332 if (signal_pending(current)) {
3333 retval = -ERESTARTSYS;
3334 break;
3335 }
3336
3337 if (debug_level >= DEBUG_LEVEL_INFO)
3338 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3339 __FILE__,__LINE__, tty->driver->name, port->count );
3340
3341 tty_unlock();
3342 schedule();
3343 tty_lock();
3344 }
3345
3346 set_current_state(TASK_RUNNING);
3347 remove_wait_queue(&port->open_wait, &wait);
3348
3349
3350 if (extra_count)
3351 port->count++;
3352 port->blocked_open--;
3353
3354 if (debug_level >= DEBUG_LEVEL_INFO)
3355 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3356 __FILE__,__LINE__, tty->driver->name, port->count );
3357
3358 if (!retval)
3359 port->flags |= ASYNC_NORMAL_ACTIVE;
3360
3361 return retval;
3362
3363}
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375static int mgsl_open(struct tty_struct *tty, struct file * filp)
3376{
3377 struct mgsl_struct *info;
3378 int retval, line;
3379 unsigned long flags;
3380
3381
3382 line = tty->index;
3383 if (line >= mgsl_device_count) {
3384 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3385 __FILE__,__LINE__,line);
3386 return -ENODEV;
3387 }
3388
3389
3390 info = mgsl_device_list;
3391 while(info && info->line != line)
3392 info = info->next_device;
3393 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3394 return -ENODEV;
3395
3396 tty->driver_data = info;
3397 info->port.tty = tty;
3398
3399 if (debug_level >= DEBUG_LEVEL_INFO)
3400 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3401 __FILE__,__LINE__,tty->driver->name, info->port.count);
3402
3403
3404 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3405 if (info->port.flags & ASYNC_CLOSING)
3406 interruptible_sleep_on(&info->port.close_wait);
3407 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3408 -EAGAIN : -ERESTARTSYS);
3409 goto cleanup;
3410 }
3411
3412 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3413
3414 spin_lock_irqsave(&info->netlock, flags);
3415 if (info->netcount) {
3416 retval = -EBUSY;
3417 spin_unlock_irqrestore(&info->netlock, flags);
3418 goto cleanup;
3419 }
3420 info->port.count++;
3421 spin_unlock_irqrestore(&info->netlock, flags);
3422
3423 if (info->port.count == 1) {
3424
3425 retval = startup(info);
3426 if (retval < 0)
3427 goto cleanup;
3428 }
3429
3430 retval = block_til_ready(tty, filp, info);
3431 if (retval) {
3432 if (debug_level >= DEBUG_LEVEL_INFO)
3433 printk("%s(%d):block_til_ready(%s) returned %d\n",
3434 __FILE__,__LINE__, info->device_name, retval);
3435 goto cleanup;
3436 }
3437
3438 if (debug_level >= DEBUG_LEVEL_INFO)
3439 printk("%s(%d):mgsl_open(%s) success\n",
3440 __FILE__,__LINE__, info->device_name);
3441 retval = 0;
3442
3443cleanup:
3444 if (retval) {
3445 if (tty->count == 1)
3446 info->port.tty = NULL;
3447 if(info->port.count)
3448 info->port.count--;
3449 }
3450
3451 return retval;
3452
3453}
3454
3455
3456
3457
3458
3459static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3460{
3461 char stat_buf[30];
3462 unsigned long flags;
3463
3464 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3465 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3466 info->device_name, info->io_base, info->irq_level,
3467 info->phys_memory_base, info->phys_lcr_base);
3468 } else {
3469 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3470 info->device_name, info->io_base,
3471 info->irq_level, info->dma_level);
3472 }
3473
3474
3475 spin_lock_irqsave(&info->irq_spinlock,flags);
3476 usc_get_serial_signals(info);
3477 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3478
3479 stat_buf[0] = 0;
3480 stat_buf[1] = 0;
3481 if (info->serial_signals & SerialSignal_RTS)
3482 strcat(stat_buf, "|RTS");
3483 if (info->serial_signals & SerialSignal_CTS)
3484 strcat(stat_buf, "|CTS");
3485 if (info->serial_signals & SerialSignal_DTR)
3486 strcat(stat_buf, "|DTR");
3487 if (info->serial_signals & SerialSignal_DSR)
3488 strcat(stat_buf, "|DSR");
3489 if (info->serial_signals & SerialSignal_DCD)
3490 strcat(stat_buf, "|CD");
3491 if (info->serial_signals & SerialSignal_RI)
3492 strcat(stat_buf, "|RI");
3493
3494 if (info->params.mode == MGSL_MODE_HDLC ||
3495 info->params.mode == MGSL_MODE_RAW ) {
3496 seq_printf(m, " HDLC txok:%d rxok:%d",
3497 info->icount.txok, info->icount.rxok);
3498 if (info->icount.txunder)
3499 seq_printf(m, " txunder:%d", info->icount.txunder);
3500 if (info->icount.txabort)
3501 seq_printf(m, " txabort:%d", info->icount.txabort);
3502 if (info->icount.rxshort)
3503 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3504 if (info->icount.rxlong)
3505 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3506 if (info->icount.rxover)
3507 seq_printf(m, " rxover:%d", info->icount.rxover);
3508 if (info->icount.rxcrc)
3509 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3510 } else {
3511 seq_printf(m, " ASYNC tx:%d rx:%d",
3512 info->icount.tx, info->icount.rx);
3513 if (info->icount.frame)
3514 seq_printf(m, " fe:%d", info->icount.frame);
3515 if (info->icount.parity)
3516 seq_printf(m, " pe:%d", info->icount.parity);
3517 if (info->icount.brk)
3518 seq_printf(m, " brk:%d", info->icount.brk);
3519 if (info->icount.overrun)
3520 seq_printf(m, " oe:%d", info->icount.overrun);
3521 }
3522
3523
3524 seq_printf(m, " %s\n", stat_buf+1);
3525
3526 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3527 info->tx_active,info->bh_requested,info->bh_running,
3528 info->pending_bh);
3529
3530 spin_lock_irqsave(&info->irq_spinlock,flags);
3531 {
3532 u16 Tcsr = usc_InReg( info, TCSR );
3533 u16 Tdmr = usc_InDmaReg( info, TDMR );
3534 u16 Ticr = usc_InReg( info, TICR );
3535 u16 Rscr = usc_InReg( info, RCSR );
3536 u16 Rdmr = usc_InDmaReg( info, RDMR );
3537 u16 Ricr = usc_InReg( info, RICR );
3538 u16 Icr = usc_InReg( info, ICR );
3539 u16 Dccr = usc_InReg( info, DCCR );
3540 u16 Tmr = usc_InReg( info, TMR );
3541 u16 Tccr = usc_InReg( info, TCCR );
3542 u16 Ccar = inw( info->io_base + CCAR );
3543 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3544 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3545 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3546 }
3547 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3548}
3549
3550
3551static int mgsl_proc_show(struct seq_file *m, void *v)
3552{
3553 struct mgsl_struct *info;
3554
3555 seq_printf(m, "synclink driver:%s\n", driver_version);
3556
3557 info = mgsl_device_list;
3558 while( info ) {
3559 line_info(m, info);
3560 info = info->next_device;
3561 }
3562 return 0;
3563}
3564
3565static int mgsl_proc_open(struct inode *inode, struct file *file)
3566{
3567 return single_open(file, mgsl_proc_show, NULL);
3568}
3569
3570static const struct file_operations mgsl_proc_fops = {
3571 .owner = THIS_MODULE,
3572 .open = mgsl_proc_open,
3573 .read = seq_read,
3574 .llseek = seq_lseek,
3575 .release = single_release,
3576};
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3587{
3588 unsigned short BuffersPerFrame;
3589
3590 info->last_mem_alloc = 0;
3591
3592
3593
3594
3595
3596
3597 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3598 if ( info->max_frame_size % DMABUFFERSIZE )
3599 BuffersPerFrame++;
3600
3601 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3625 info->rx_buffer_count = 62 - info->tx_buffer_count;
3626 } else {
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3638 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3639
3640
3641
3642
3643
3644
3645 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3646 info->rx_buffer_count = 62 - info->tx_buffer_count;
3647
3648 }
3649
3650 if ( debug_level >= DEBUG_LEVEL_INFO )
3651 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3652 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3653
3654 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3655 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3656 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3657 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3658 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3659 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3660 return -ENOMEM;
3661 }
3662
3663 mgsl_reset_rx_dma_buffers( info );
3664 mgsl_reset_tx_dma_buffers( info );
3665
3666 return 0;
3667
3668}
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3694{
3695 unsigned int i;
3696
3697 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3698
3699 info->buffer_list = info->memory_base + info->last_mem_alloc;
3700 info->buffer_list_phys = info->last_mem_alloc;
3701 info->last_mem_alloc += BUFFERLISTSIZE;
3702 } else {
3703
3704
3705
3706
3707
3708
3709 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3710 if (info->buffer_list == NULL)
3711 return -ENOMEM;
3712 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3713 }
3714
3715
3716
3717 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3718
3719
3720
3721
3722 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3723 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3724 info->tx_buffer_list += info->rx_buffer_count;
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3736
3737 info->rx_buffer_list[i].phys_entry =
3738 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3739
3740
3741
3742
3743 info->rx_buffer_list[i].link = info->buffer_list_phys;
3744
3745 if ( i < info->rx_buffer_count - 1 )
3746 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3747 }
3748
3749 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3750
3751 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3752 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3753
3754
3755
3756
3757 info->tx_buffer_list[i].link = info->buffer_list_phys +
3758 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3759
3760 if ( i < info->tx_buffer_count - 1 )
3761 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3762 }
3763
3764 return 0;
3765
3766}
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3778{
3779 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3780 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3781
3782 info->buffer_list = NULL;
3783 info->rx_buffer_list = NULL;
3784 info->tx_buffer_list = NULL;
3785
3786}
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3805{
3806 int i;
3807 u32 phys_addr;
3808
3809
3810
3811 for ( i = 0; i < Buffercount; i++ ) {
3812 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3813
3814 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3815 phys_addr = info->last_mem_alloc;
3816 info->last_mem_alloc += DMABUFFERSIZE;
3817 } else {
3818
3819 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3820 if (BufferList[i].virt_addr == NULL)
3821 return -ENOMEM;
3822 phys_addr = (u32)(BufferList[i].dma_addr);
3823 }
3824 BufferList[i].phys_addr = phys_addr;
3825 }
3826
3827 return 0;
3828
3829}
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3846{
3847 int i;
3848
3849 if ( BufferList ) {
3850 for ( i = 0 ; i < Buffercount ; i++ ) {
3851 if ( BufferList[i].virt_addr ) {
3852 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3853 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3854 BufferList[i].virt_addr = NULL;
3855 }
3856 }
3857 }
3858
3859}
3860
3861
3862
3863
3864
3865
3866
3867
3868static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3869{
3870 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3871 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3872 mgsl_free_buffer_list_memory( info );
3873
3874}
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3890{
3891 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3892 if ( info->intermediate_rxbuffer == NULL )
3893 return -ENOMEM;
3894
3895 return 0;
3896
3897}
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3910{
3911 kfree(info->intermediate_rxbuffer);
3912 info->intermediate_rxbuffer = NULL;
3913
3914}
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3930{
3931 int i;
3932
3933 if ( debug_level >= DEBUG_LEVEL_INFO )
3934 printk("%s %s(%d) allocating %d tx holding buffers\n",
3935 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3936
3937 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3938
3939 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3940 info->tx_holding_buffers[i].buffer =
3941 kmalloc(info->max_frame_size, GFP_KERNEL);
3942 if (info->tx_holding_buffers[i].buffer == NULL) {
3943 for (--i; i >= 0; i--) {
3944 kfree(info->tx_holding_buffers[i].buffer);
3945 info->tx_holding_buffers[i].buffer = NULL;
3946 }
3947 return -ENOMEM;
3948 }
3949 }
3950
3951 return 0;
3952
3953}
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3966{
3967 int i;
3968
3969 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3970 kfree(info->tx_holding_buffers[i].buffer);
3971 info->tx_holding_buffers[i].buffer = NULL;
3972 }
3973
3974 info->get_tx_holding_index = 0;
3975 info->put_tx_holding_index = 0;
3976 info->tx_holding_count = 0;
3977
3978}
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
3996{
3997 bool ret = false;
3998
3999 if ( info->tx_holding_count ) {
4000
4001
4002
4003 struct tx_holding_buffer *ptx =
4004 &info->tx_holding_buffers[info->get_tx_holding_index];
4005 int num_free = num_free_tx_dma_buffers(info);
4006 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4007 if ( ptx->buffer_size % DMABUFFERSIZE )
4008 ++num_needed;
4009
4010 if (num_needed <= num_free) {
4011 info->xmit_cnt = ptx->buffer_size;
4012 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4013
4014 --info->tx_holding_count;
4015 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4016 info->get_tx_holding_index=0;
4017
4018
4019 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4020
4021 ret = true;
4022 }
4023 }
4024
4025 return ret;
4026}
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4042{
4043 struct tx_holding_buffer *ptx;
4044
4045 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4046 return 0;
4047 }
4048
4049 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4050 ptx->buffer_size = BufferSize;
4051 memcpy( ptx->buffer, Buffer, BufferSize);
4052
4053 ++info->tx_holding_count;
4054 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4055 info->put_tx_holding_index=0;
4056
4057 return 1;
4058}
4059
4060static int mgsl_claim_resources(struct mgsl_struct *info)
4061{
4062 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4063 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4064 __FILE__,__LINE__,info->device_name, info->io_base);
4065 return -ENODEV;
4066 }
4067 info->io_addr_requested = true;
4068
4069 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4070 info->device_name, info ) < 0 ) {
4071 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4072 __FILE__,__LINE__,info->device_name, info->irq_level );
4073 goto errout;
4074 }
4075 info->irq_requested = true;
4076
4077 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4078 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4079 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4080 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4081 goto errout;
4082 }
4083 info->shared_mem_requested = true;
4084 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4085 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4086 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4087 goto errout;
4088 }
4089 info->lcr_mem_requested = true;
4090
4091 info->memory_base = ioremap_nocache(info->phys_memory_base,
4092 0x40000);
4093 if (!info->memory_base) {
4094 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4095 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4096 goto errout;
4097 }
4098
4099 if ( !mgsl_memory_test(info) ) {
4100 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4101 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4102 goto errout;
4103 }
4104
4105 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4106 PAGE_SIZE);
4107 if (!info->lcr_base) {
4108 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4109 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4110 goto errout;
4111 }
4112 info->lcr_base += info->lcr_offset;
4113
4114 } else {
4115
4116
4117 if (request_dma(info->dma_level,info->device_name) < 0){
4118 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4119 __FILE__,__LINE__,info->device_name, info->dma_level );
4120 mgsl_release_resources( info );
4121 return -ENODEV;
4122 }
4123 info->dma_requested = true;
4124
4125
4126 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4127 enable_dma(info->dma_level);
4128 }
4129
4130 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4131 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4132 __FILE__,__LINE__,info->device_name, info->dma_level );
4133 goto errout;
4134 }
4135
4136 return 0;
4137errout:
4138 mgsl_release_resources(info);
4139 return -ENODEV;
4140
4141}
4142
4143static void mgsl_release_resources(struct mgsl_struct *info)
4144{
4145 if ( debug_level >= DEBUG_LEVEL_INFO )
4146 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4147 __FILE__,__LINE__,info->device_name );
4148
4149 if ( info->irq_requested ) {
4150 free_irq(info->irq_level, info);
4151 info->irq_requested = false;
4152 }
4153 if ( info->dma_requested ) {
4154 disable_dma(info->dma_level);
4155 free_dma(info->dma_level);
4156 info->dma_requested = false;
4157 }
4158 mgsl_free_dma_buffers(info);
4159 mgsl_free_intermediate_rxbuffer_memory(info);
4160 mgsl_free_intermediate_txbuffer_memory(info);
4161
4162 if ( info->io_addr_requested ) {
4163 release_region(info->io_base,info->io_addr_size);
4164 info->io_addr_requested = false;
4165 }
4166 if ( info->shared_mem_requested ) {
4167 release_mem_region(info->phys_memory_base,0x40000);
4168 info->shared_mem_requested = false;
4169 }
4170 if ( info->lcr_mem_requested ) {
4171 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4172 info->lcr_mem_requested = false;
4173 }
4174 if (info->memory_base){
4175 iounmap(info->memory_base);
4176 info->memory_base = NULL;
4177 }
4178 if (info->lcr_base){
4179 iounmap(info->lcr_base - info->lcr_offset);
4180 info->lcr_base = NULL;
4181 }
4182
4183 if ( debug_level >= DEBUG_LEVEL_INFO )
4184 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4185 __FILE__,__LINE__,info->device_name );
4186
4187}
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197static void mgsl_add_device( struct mgsl_struct *info )
4198{
4199 info->next_device = NULL;
4200 info->line = mgsl_device_count;
4201 sprintf(info->device_name,"ttySL%d",info->line);
4202
4203 if (info->line < MAX_TOTAL_DEVICES) {
4204 if (maxframe[info->line])
4205 info->max_frame_size = maxframe[info->line];
4206
4207 if (txdmabufs[info->line]) {
4208 info->num_tx_dma_buffers = txdmabufs[info->line];
4209 if (info->num_tx_dma_buffers < 1)
4210 info->num_tx_dma_buffers = 1;
4211 }
4212
4213 if (txholdbufs[info->line]) {
4214 info->num_tx_holding_buffers = txholdbufs[info->line];
4215 if (info->num_tx_holding_buffers < 1)
4216 info->num_tx_holding_buffers = 1;
4217 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4218 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4219 }
4220 }
4221
4222 mgsl_device_count++;
4223
4224 if ( !mgsl_device_list )
4225 mgsl_device_list = info;
4226 else {
4227 struct mgsl_struct *current_dev = mgsl_device_list;
4228 while( current_dev->next_device )
4229 current_dev = current_dev->next_device;
4230 current_dev->next_device = info;
4231 }
4232
4233 if ( info->max_frame_size < 4096 )
4234 info->max_frame_size = 4096;
4235 else if ( info->max_frame_size > 65535 )
4236 info->max_frame_size = 65535;
4237
4238 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4239 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4240 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4241 info->phys_memory_base, info->phys_lcr_base,
4242 info->max_frame_size );
4243 } else {
4244 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4245 info->device_name, info->io_base, info->irq_level, info->dma_level,
4246 info->max_frame_size );
4247 }
4248
4249#if SYNCLINK_GENERIC_HDLC
4250 hdlcdev_init(info);
4251#endif
4252
4253}
4254
4255static const struct tty_port_operations mgsl_port_ops = {
4256 .carrier_raised = carrier_raised,
4257 .dtr_rts = dtr_rts,
4258};
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268static struct mgsl_struct* mgsl_allocate_device(void)
4269{
4270 struct mgsl_struct *info;
4271
4272 info = kzalloc(sizeof(struct mgsl_struct),
4273 GFP_KERNEL);
4274
4275 if (!info) {
4276 printk("Error can't allocate device instance data\n");
4277 } else {
4278 tty_port_init(&info->port);
4279 info->port.ops = &mgsl_port_ops;
4280 info->magic = MGSL_MAGIC;
4281 INIT_WORK(&info->task, mgsl_bh_handler);
4282 info->max_frame_size = 4096;
4283 info->port.close_delay = 5*HZ/10;
4284 info->port.closing_wait = 30*HZ;
4285 init_waitqueue_head(&info->status_event_wait_q);
4286 init_waitqueue_head(&info->event_wait_q);
4287 spin_lock_init(&info->irq_spinlock);
4288 spin_lock_init(&info->netlock);
4289 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4290 info->idle_mode = HDLC_TXIDLE_FLAGS;
4291 info->num_tx_dma_buffers = 1;
4292 info->num_tx_holding_buffers = 0;
4293 }
4294
4295 return info;
4296
4297}
4298
4299static const struct tty_operations mgsl_ops = {
4300 .open = mgsl_open,
4301 .close = mgsl_close,
4302 .write = mgsl_write,
4303 .put_char = mgsl_put_char,
4304 .flush_chars = mgsl_flush_chars,
4305 .write_room = mgsl_write_room,
4306 .chars_in_buffer = mgsl_chars_in_buffer,
4307 .flush_buffer = mgsl_flush_buffer,
4308 .ioctl = mgsl_ioctl,
4309 .throttle = mgsl_throttle,
4310 .unthrottle = mgsl_unthrottle,
4311 .send_xchar = mgsl_send_xchar,
4312 .break_ctl = mgsl_break,
4313 .wait_until_sent = mgsl_wait_until_sent,
4314 .set_termios = mgsl_set_termios,
4315 .stop = mgsl_stop,
4316 .start = mgsl_start,
4317 .hangup = mgsl_hangup,
4318 .tiocmget = tiocmget,
4319 .tiocmset = tiocmset,
4320 .get_icount = msgl_get_icount,
4321 .proc_fops = &mgsl_proc_fops,
4322};
4323
4324
4325
4326
4327static int mgsl_init_tty(void)
4328{
4329 int rc;
4330
4331 serial_driver = alloc_tty_driver(128);
4332 if (!serial_driver)
4333 return -ENOMEM;
4334
4335 serial_driver->driver_name = "synclink";
4336 serial_driver->name = "ttySL";
4337 serial_driver->major = ttymajor;
4338 serial_driver->minor_start = 64;
4339 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4340 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4341 serial_driver->init_termios = tty_std_termios;
4342 serial_driver->init_termios.c_cflag =
4343 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4344 serial_driver->init_termios.c_ispeed = 9600;
4345 serial_driver->init_termios.c_ospeed = 9600;
4346 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4347 tty_set_operations(serial_driver, &mgsl_ops);
4348 if ((rc = tty_register_driver(serial_driver)) < 0) {
4349 printk("%s(%d):Couldn't register serial driver\n",
4350 __FILE__,__LINE__);
4351 put_tty_driver(serial_driver);
4352 serial_driver = NULL;
4353 return rc;
4354 }
4355
4356 printk("%s %s, tty major#%d\n",
4357 driver_name, driver_version,
4358 serial_driver->major);
4359 return 0;
4360}
4361
4362
4363
4364static void mgsl_enum_isa_devices(void)
4365{
4366 struct mgsl_struct *info;
4367 int i;
4368
4369
4370
4371 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4372 if ( debug_level >= DEBUG_LEVEL_INFO )
4373 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4374 io[i], irq[i], dma[i] );
4375
4376 info = mgsl_allocate_device();
4377 if ( !info ) {
4378
4379 if ( debug_level >= DEBUG_LEVEL_ERROR )
4380 printk( "can't allocate device instance data.\n");
4381 continue;
4382 }
4383
4384
4385 info->io_base = (unsigned int)io[i];
4386 info->irq_level = (unsigned int)irq[i];
4387 info->irq_level = irq_canonicalize(info->irq_level);
4388 info->dma_level = (unsigned int)dma[i];
4389 info->bus_type = MGSL_BUS_TYPE_ISA;
4390 info->io_addr_size = 16;
4391 info->irq_flags = 0;
4392
4393 mgsl_add_device( info );
4394 }
4395}
4396
4397static void synclink_cleanup(void)
4398{
4399 int rc;
4400 struct mgsl_struct *info;
4401 struct mgsl_struct *tmp;
4402
4403 printk("Unloading %s: %s\n", driver_name, driver_version);
4404
4405 if (serial_driver) {
4406 if ((rc = tty_unregister_driver(serial_driver)))
4407 printk("%s(%d) failed to unregister tty driver err=%d\n",
4408 __FILE__,__LINE__,rc);
4409 put_tty_driver(serial_driver);
4410 }
4411
4412 info = mgsl_device_list;
4413 while(info) {
4414#if SYNCLINK_GENERIC_HDLC
4415 hdlcdev_exit(info);
4416#endif
4417 mgsl_release_resources(info);
4418 tmp = info;
4419 info = info->next_device;
4420 kfree(tmp);
4421 }
4422
4423 if (pci_registered)
4424 pci_unregister_driver(&synclink_pci_driver);
4425}
4426
4427static int __init synclink_init(void)
4428{
4429 int rc;
4430
4431 if (break_on_load) {
4432 mgsl_get_text_ptr();
4433 BREAKPOINT();
4434 }
4435
4436 printk("%s %s\n", driver_name, driver_version);
4437
4438 mgsl_enum_isa_devices();
4439 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4440 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4441 else
4442 pci_registered = true;
4443
4444 if ((rc = mgsl_init_tty()) < 0)
4445 goto error;
4446
4447 return 0;
4448
4449error:
4450 synclink_cleanup();
4451 return rc;
4452}
4453
4454static void __exit synclink_exit(void)
4455{
4456 synclink_cleanup();
4457}
4458
4459module_init(synclink_init);
4460module_exit(synclink_exit);
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4484{
4485
4486
4487
4488 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4489
4490
4491 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4492 inw( info->io_base + CCAR );
4493
4494}
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4511{
4512
4513 outw( Cmd + info->mbre_bit, info->io_base );
4514
4515
4516 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4517 inw( info->io_base );
4518
4519}
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4538{
4539
4540
4541
4542 outw( RegAddr + info->mbre_bit, info->io_base );
4543 outw( RegValue, info->io_base );
4544
4545
4546 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4547 inw( info->io_base );
4548
4549}
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4567{
4568
4569
4570
4571 outw( RegAddr + info->mbre_bit, info->io_base );
4572 return inw( info->io_base );
4573
4574}
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4594{
4595 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4596 outw( RegValue, info->io_base + CCAR );
4597
4598
4599 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4600 inw( info->io_base + CCAR );
4601
4602}
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4619{
4620 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4621 return inw( info->io_base + CCAR );
4622
4623}
4624
4625
4626
4627
4628
4629
4630
4631
4632static void usc_set_sdlc_mode( struct mgsl_struct *info )
4633{
4634 u16 RegValue;
4635 bool PreSL1660;
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646 usc_OutReg(info,TMCR,0x1f);
4647 RegValue=usc_InReg(info,TMDR);
4648 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4649
4650 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4651 {
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664 RegValue = 0x8e06;
4665
4666
4667
4668
4669
4670 }
4671 else
4672 {
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684 if (info->params.mode == MGSL_MODE_RAW) {
4685 RegValue = 0x0001;
4686
4687 usc_OutReg( info, IOCR,
4688 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702 RegValue |= 0x0400;
4703 }
4704 else {
4705
4706 RegValue = 0x0606;
4707
4708 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4709 RegValue |= BIT14;
4710 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4711 RegValue |= BIT15;
4712 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4713 RegValue |= BIT15 + BIT14;
4714 }
4715
4716 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4717 RegValue |= BIT13;
4718 }
4719
4720 if ( info->params.mode == MGSL_MODE_HDLC &&
4721 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4722 RegValue |= BIT12;
4723
4724 if ( info->params.addr_filter != 0xff )
4725 {
4726
4727 usc_OutReg( info, RSR, info->params.addr_filter );
4728 RegValue |= BIT4;
4729 }
4730
4731 usc_OutReg( info, CMR, RegValue );
4732 info->cmr_value = RegValue;
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749 RegValue = 0x0500;
4750
4751 switch ( info->params.encoding ) {
4752 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4753 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4754 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4755 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4756 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4757 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4758 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4759 }
4760
4761 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4762 RegValue |= BIT9;
4763 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4764 RegValue |= ( BIT12 | BIT10 | BIT9 );
4765
4766 usc_OutReg( info, RMR, RegValue );
4767
4768
4769
4770
4771
4772
4773
4774
4775 usc_OutReg( info, RCLR, RCLRVALUE );
4776
4777 usc_RCmd( info, RCmd_SelectRicrdma_level );
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797 RegValue = usc_InReg( info, RICR ) & 0xc0;
4798
4799 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4800 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4801 else
4802 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4803
4804
4805
4806 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4807 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824 RegValue = 0x0400;
4825
4826 switch ( info->params.encoding ) {
4827 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4828 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4829 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4830 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4831 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4832 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4833 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4834 }
4835
4836 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4837 RegValue |= BIT9 + BIT8;
4838 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4839 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4840
4841 usc_OutReg( info, TMR, RegValue );
4842
4843 usc_set_txidle( info );
4844
4845
4846 usc_TCmd( info, TCmd_SelectTicrdma_level );
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4864 usc_OutReg( info, TICR, 0x0736 );
4865 else
4866 usc_OutReg( info, TICR, 0x1436 );
4867
4868 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4869 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888 info->tcsr_value = 0;
4889
4890 if ( !PreSL1660 )
4891 info->tcsr_value |= TCSR_UNDERWAIT;
4892
4893 usc_OutReg( info, TCSR, info->tcsr_value );
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908 RegValue = 0x0f40;
4909
4910 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4911 RegValue |= 0x0003;
4912 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4913 RegValue |= 0x0004;
4914 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4915 RegValue |= 0x0006;
4916 else
4917 RegValue |= 0x0007;
4918
4919 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4920 RegValue |= 0x0018;
4921 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4922 RegValue |= 0x0020;
4923 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4924 RegValue |= 0x0038;
4925 else
4926 RegValue |= 0x0030;
4927
4928 usc_OutReg( info, CMCR, RegValue );
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946 RegValue = 0x0000;
4947
4948 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4949 u32 XtalSpeed;
4950 u32 DpllDivisor;
4951 u16 Tc;
4952
4953
4954
4955
4956 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4957 XtalSpeed = 11059200;
4958 else
4959 XtalSpeed = 14745600;
4960
4961 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4962 DpllDivisor = 16;
4963 RegValue |= BIT10;
4964 }
4965 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4966 DpllDivisor = 8;
4967 RegValue |= BIT11;
4968 }
4969 else
4970 DpllDivisor = 32;
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986 if ( info->params.clock_speed )
4987 {
4988 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4989 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4990 / info->params.clock_speed) )
4991 Tc--;
4992 }
4993 else
4994 Tc = -1;
4995
4996
4997
4998 usc_OutReg( info, TC1R, Tc );
4999
5000 RegValue |= BIT4;
5001
5002 switch ( info->params.encoding ) {
5003 case HDLC_ENCODING_NRZ:
5004 case HDLC_ENCODING_NRZB:
5005 case HDLC_ENCODING_NRZI_MARK:
5006 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5007 case HDLC_ENCODING_BIPHASE_MARK:
5008 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5009 case HDLC_ENCODING_BIPHASE_LEVEL:
5010 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5011 }
5012 }
5013
5014 usc_OutReg( info, HCR, RegValue );
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035 usc_OutReg( info, CCSR, 0x1020 );
5036
5037
5038 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5039 usc_OutReg( info, SICR,
5040 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5041 }
5042
5043
5044
5045 usc_EnableMasterIrqBit( info );
5046
5047 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5048 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5049
5050
5051 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5052 usc_EnableInterrupts(info, MISC);
5053
5054 info->mbre_bit = 0;
5055 outw( 0, info->io_base );
5056 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5057 info->mbre_bit = BIT8;
5058 outw( BIT8, info->io_base );
5059
5060 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5061
5062
5063 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5064 }
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5089
5090 usc_OutDmaReg( info, DCR, 0xa00b );
5091 }
5092 else
5093 usc_OutDmaReg( info, DCR, 0x800b );
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109 usc_OutDmaReg( info, RDMR, 0xf200 );
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125 usc_OutDmaReg( info, TDMR, 0xf200 );
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141 usc_OutDmaReg( info, DICR, 0x9000 );
5142
5143 usc_InDmaReg( info, RDMR );
5144 usc_InDmaReg( info, TDMR );
5145 usc_OutDmaReg( info, CDIR, 0x0303 );
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161 RegValue = 0x8080;
5162
5163 switch ( info->params.preamble_length ) {
5164 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5165 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5166 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5167 }
5168
5169 switch ( info->params.preamble ) {
5170 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5171 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5172 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5173 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5174 }
5175
5176 usc_OutReg( info, CCR, RegValue );
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5187
5188 usc_OutDmaReg( info, BDCR, 0x0000 );
5189 }
5190 else
5191 usc_OutDmaReg( info, BDCR, 0x2000 );
5192
5193 usc_stop_transmitter(info);
5194 usc_stop_receiver(info);
5195
5196}
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5209{
5210 if (enable) {
5211
5212 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227 usc_OutReg( info, CMCR, 0x0f64 );
5228
5229
5230
5231 if (info->params.clock_speed) {
5232 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5233 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5234 else
5235 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5236 } else
5237 usc_OutReg(info, TC0R, (u16)8);
5238
5239
5240
5241 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5242
5243
5244 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5245
5246
5247 info->loopback_bits = 0x300;
5248 outw( 0x0300, info->io_base + CCAR );
5249 } else {
5250
5251 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5252
5253
5254 info->loopback_bits = 0;
5255 outw( 0,info->io_base + CCAR );
5256 }
5257
5258}
5259
5260
5261
5262
5263