linux/drivers/ptp/ptp_pch.c
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   1/*
   2 * PTP 1588 clock using the EG20T PCH
   3 *
   4 * Copyright (C) 2010 OMICRON electronics GmbH
   5 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
   6 *
   7 * This code was derived from the IXP46X driver.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; version 2 of the License.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  21 */
  22
  23#include <linux/device.h>
  24#include <linux/err.h>
  25#include <linux/init.h>
  26#include <linux/interrupt.h>
  27#include <linux/io.h>
  28#include <linux/irq.h>
  29#include <linux/kernel.h>
  30#include <linux/module.h>
  31#include <linux/pci.h>
  32#include <linux/ptp_clock_kernel.h>
  33#include <linux/slab.h>
  34
  35#define STATION_ADDR_LEN        20
  36#define PCI_DEVICE_ID_PCH_1588  0x8819
  37#define IO_MEM_BAR 1
  38
  39#define DEFAULT_ADDEND 0xA0000000
  40#define TICKS_NS_SHIFT  5
  41#define N_EXT_TS        2
  42
  43enum pch_status {
  44        PCH_SUCCESS,
  45        PCH_INVALIDPARAM,
  46        PCH_NOTIMESTAMP,
  47        PCH_INTERRUPTMODEINUSE,
  48        PCH_FAILED,
  49        PCH_UNSUPPORTED,
  50};
  51/**
  52 * struct pch_ts_regs - IEEE 1588 registers
  53 */
  54struct pch_ts_regs {
  55        u32 control;
  56        u32 event;
  57        u32 addend;
  58        u32 accum;
  59        u32 test;
  60        u32 ts_compare;
  61        u32 rsystime_lo;
  62        u32 rsystime_hi;
  63        u32 systime_lo;
  64        u32 systime_hi;
  65        u32 trgt_lo;
  66        u32 trgt_hi;
  67        u32 asms_lo;
  68        u32 asms_hi;
  69        u32 amms_lo;
  70        u32 amms_hi;
  71        u32 ch_control;
  72        u32 ch_event;
  73        u32 tx_snap_lo;
  74        u32 tx_snap_hi;
  75        u32 rx_snap_lo;
  76        u32 rx_snap_hi;
  77        u32 src_uuid_lo;
  78        u32 src_uuid_hi;
  79        u32 can_status;
  80        u32 can_snap_lo;
  81        u32 can_snap_hi;
  82        u32 ts_sel;
  83        u32 ts_st[6];
  84        u32 reserve1[14];
  85        u32 stl_max_set_en;
  86        u32 stl_max_set;
  87        u32 reserve2[13];
  88        u32 srst;
  89};
  90
  91#define PCH_TSC_RESET           (1 << 0)
  92#define PCH_TSC_TTM_MASK        (1 << 1)
  93#define PCH_TSC_ASMS_MASK       (1 << 2)
  94#define PCH_TSC_AMMS_MASK       (1 << 3)
  95#define PCH_TSC_PPSM_MASK       (1 << 4)
  96#define PCH_TSE_TTIPEND         (1 << 1)
  97#define PCH_TSE_SNS             (1 << 2)
  98#define PCH_TSE_SNM             (1 << 3)
  99#define PCH_TSE_PPS             (1 << 4)
 100#define PCH_CC_MM               (1 << 0)
 101#define PCH_CC_TA               (1 << 1)
 102
 103#define PCH_CC_MODE_SHIFT       16
 104#define PCH_CC_MODE_MASK        0x001F0000
 105#define PCH_CC_VERSION          (1 << 31)
 106#define PCH_CE_TXS              (1 << 0)
 107#define PCH_CE_RXS              (1 << 1)
 108#define PCH_CE_OVR              (1 << 0)
 109#define PCH_CE_VAL              (1 << 1)
 110#define PCH_ECS_ETH             (1 << 0)
 111
 112#define PCH_ECS_CAN             (1 << 1)
 113#define PCH_STATION_BYTES       6
 114
 115#define PCH_IEEE1588_ETH        (1 << 0)
 116#define PCH_IEEE1588_CAN        (1 << 1)
 117/**
 118 * struct pch_dev - Driver private data
 119 */
 120struct pch_dev {
 121        struct pch_ts_regs *regs;
 122        struct ptp_clock *ptp_clock;
 123        struct ptp_clock_info caps;
 124        int exts0_enabled;
 125        int exts1_enabled;
 126
 127        u32 mem_base;
 128        u32 mem_size;
 129        u32 irq;
 130        struct pci_dev *pdev;
 131        spinlock_t register_lock;
 132};
 133
 134/**
 135 * struct pch_params - 1588 module parameter
 136 */
 137struct pch_params {
 138        u8 station[STATION_ADDR_LEN];
 139};
 140
 141/* structure to hold the module parameters */
 142static struct pch_params pch_param = {
 143        "00:00:00:00:00:00"
 144};
 145
 146/*
 147 * Register access functions
 148 */
 149static inline void pch_eth_enable_set(struct pch_dev *chip)
 150{
 151        u32 val;
 152        /* SET the eth_enable bit */
 153        val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
 154        iowrite32(val, (&chip->regs->ts_sel));
 155}
 156
 157static u64 pch_systime_read(struct pch_ts_regs *regs)
 158{
 159        u64 ns;
 160        u32 lo, hi;
 161
 162        lo = ioread32(&regs->systime_lo);
 163        hi = ioread32(&regs->systime_hi);
 164
 165        ns = ((u64) hi) << 32;
 166        ns |= lo;
 167        ns <<= TICKS_NS_SHIFT;
 168
 169        return ns;
 170}
 171
 172static void pch_systime_write(struct pch_ts_regs *regs, u64 ns)
 173{
 174        u32 hi, lo;
 175
 176        ns >>= TICKS_NS_SHIFT;
 177        hi = ns >> 32;
 178        lo = ns & 0xffffffff;
 179
 180        iowrite32(lo, &regs->systime_lo);
 181        iowrite32(hi, &regs->systime_hi);
 182}
 183
 184static inline void pch_block_reset(struct pch_dev *chip)
 185{
 186        u32 val;
 187        /* Reset Hardware Assist block */
 188        val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
 189        iowrite32(val, (&chip->regs->control));
 190        val = val & ~PCH_TSC_RESET;
 191        iowrite32(val, (&chip->regs->control));
 192}
 193
 194u32 pch_ch_control_read(struct pci_dev *pdev)
 195{
 196        struct pch_dev *chip = pci_get_drvdata(pdev);
 197        u32 val;
 198
 199        val = ioread32(&chip->regs->ch_control);
 200
 201        return val;
 202}
 203EXPORT_SYMBOL(pch_ch_control_read);
 204
 205void pch_ch_control_write(struct pci_dev *pdev, u32 val)
 206{
 207        struct pch_dev *chip = pci_get_drvdata(pdev);
 208
 209        iowrite32(val, (&chip->regs->ch_control));
 210}
 211EXPORT_SYMBOL(pch_ch_control_write);
 212
 213u32 pch_ch_event_read(struct pci_dev *pdev)
 214{
 215        struct pch_dev *chip = pci_get_drvdata(pdev);
 216        u32 val;
 217
 218        val = ioread32(&chip->regs->ch_event);
 219
 220        return val;
 221}
 222EXPORT_SYMBOL(pch_ch_event_read);
 223
 224void pch_ch_event_write(struct pci_dev *pdev, u32 val)
 225{
 226        struct pch_dev *chip = pci_get_drvdata(pdev);
 227
 228        iowrite32(val, (&chip->regs->ch_event));
 229}
 230EXPORT_SYMBOL(pch_ch_event_write);
 231
 232u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
 233{
 234        struct pch_dev *chip = pci_get_drvdata(pdev);
 235        u32 val;
 236
 237        val = ioread32(&chip->regs->src_uuid_lo);
 238
 239        return val;
 240}
 241EXPORT_SYMBOL(pch_src_uuid_lo_read);
 242
 243u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
 244{
 245        struct pch_dev *chip = pci_get_drvdata(pdev);
 246        u32 val;
 247
 248        val = ioread32(&chip->regs->src_uuid_hi);
 249
 250        return val;
 251}
 252EXPORT_SYMBOL(pch_src_uuid_hi_read);
 253
 254u64 pch_rx_snap_read(struct pci_dev *pdev)
 255{
 256        struct pch_dev *chip = pci_get_drvdata(pdev);
 257        u64 ns;
 258        u32 lo, hi;
 259
 260        lo = ioread32(&chip->regs->rx_snap_lo);
 261        hi = ioread32(&chip->regs->rx_snap_hi);
 262
 263        ns = ((u64) hi) << 32;
 264        ns |= lo;
 265        ns <<= TICKS_NS_SHIFT;
 266
 267        return ns;
 268}
 269EXPORT_SYMBOL(pch_rx_snap_read);
 270
 271u64 pch_tx_snap_read(struct pci_dev *pdev)
 272{
 273        struct pch_dev *chip = pci_get_drvdata(pdev);
 274        u64 ns;
 275        u32 lo, hi;
 276
 277        lo = ioread32(&chip->regs->tx_snap_lo);
 278        hi = ioread32(&chip->regs->tx_snap_hi);
 279
 280        ns = ((u64) hi) << 32;
 281        ns |= lo;
 282        ns <<= TICKS_NS_SHIFT;
 283
 284        return ns;
 285}
 286EXPORT_SYMBOL(pch_tx_snap_read);
 287
 288/* This function enables all 64 bits in system time registers [high & low].
 289This is a work-around for non continuous value in the SystemTime Register*/
 290static void pch_set_system_time_count(struct pch_dev *chip)
 291{
 292        iowrite32(0x01, &chip->regs->stl_max_set_en);
 293        iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
 294        iowrite32(0x00, &chip->regs->stl_max_set_en);
 295}
 296
 297static void pch_reset(struct pch_dev *chip)
 298{
 299        /* Reset Hardware Assist */
 300        pch_block_reset(chip);
 301
 302        /* enable all 32 bits in system time registers */
 303        pch_set_system_time_count(chip);
 304}
 305
 306/**
 307 * pch_set_station_address() - This API sets the station address used by
 308 *                                  IEEE 1588 hardware when looking at PTP
 309 *                                  traffic on the  ethernet interface
 310 * @addr:       dress which contain the column separated address to be used.
 311 */
 312int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
 313{
 314        s32 i;
 315        struct pch_dev *chip = pci_get_drvdata(pdev);
 316
 317        /* Verify the parameter */
 318        if ((chip->regs == 0) || addr == (u8 *)NULL) {
 319                dev_err(&pdev->dev,
 320                        "invalid params returning PCH_INVALIDPARAM\n");
 321                return PCH_INVALIDPARAM;
 322        }
 323        /* For all station address bytes */
 324        for (i = 0; i < PCH_STATION_BYTES; i++) {
 325                u32 val;
 326                s32 tmp;
 327
 328                tmp = hex_to_bin(addr[i * 3]);
 329                if (tmp < 0) {
 330                        dev_err(&pdev->dev,
 331                                "invalid params returning PCH_INVALIDPARAM\n");
 332                        return PCH_INVALIDPARAM;
 333                }
 334                val = tmp * 16;
 335                tmp = hex_to_bin(addr[(i * 3) + 1]);
 336                if (tmp < 0) {
 337                        dev_err(&pdev->dev,
 338                                "invalid params returning PCH_INVALIDPARAM\n");
 339                        return PCH_INVALIDPARAM;
 340                }
 341                val += tmp;
 342                /* Expects ':' separated addresses */
 343                if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
 344                        dev_err(&pdev->dev,
 345                                "invalid params returning PCH_INVALIDPARAM\n");
 346                        return PCH_INVALIDPARAM;
 347                }
 348
 349                /* Ideally we should set the address only after validating
 350                                                         entire string */
 351                dev_dbg(&pdev->dev, "invoking pch_station_set\n");
 352                iowrite32(val, &chip->regs->ts_st[i]);
 353        }
 354        return 0;
 355}
 356EXPORT_SYMBOL(pch_set_station_address);
 357
 358/*
 359 * Interrupt service routine
 360 */
 361static irqreturn_t isr(int irq, void *priv)
 362{
 363        struct pch_dev *pch_dev = priv;
 364        struct pch_ts_regs *regs = pch_dev->regs;
 365        struct ptp_clock_event event;
 366        u32 ack = 0, lo, hi, val;
 367
 368        val = ioread32(&regs->event);
 369
 370        if (val & PCH_TSE_SNS) {
 371                ack |= PCH_TSE_SNS;
 372                if (pch_dev->exts0_enabled) {
 373                        hi = ioread32(&regs->asms_hi);
 374                        lo = ioread32(&regs->asms_lo);
 375                        event.type = PTP_CLOCK_EXTTS;
 376                        event.index = 0;
 377                        event.timestamp = ((u64) hi) << 32;
 378                        event.timestamp |= lo;
 379                        event.timestamp <<= TICKS_NS_SHIFT;
 380                        ptp_clock_event(pch_dev->ptp_clock, &event);
 381                }
 382        }
 383
 384        if (val & PCH_TSE_SNM) {
 385                ack |= PCH_TSE_SNM;
 386                if (pch_dev->exts1_enabled) {
 387                        hi = ioread32(&regs->amms_hi);
 388                        lo = ioread32(&regs->amms_lo);
 389                        event.type = PTP_CLOCK_EXTTS;
 390                        event.index = 1;
 391                        event.timestamp = ((u64) hi) << 32;
 392                        event.timestamp |= lo;
 393                        event.timestamp <<= TICKS_NS_SHIFT;
 394                        ptp_clock_event(pch_dev->ptp_clock, &event);
 395                }
 396        }
 397
 398        if (val & PCH_TSE_TTIPEND)
 399                ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
 400
 401        if (ack) {
 402                iowrite32(ack, &regs->event);
 403                return IRQ_HANDLED;
 404        } else
 405                return IRQ_NONE;
 406}
 407
 408/*
 409 * PTP clock operations
 410 */
 411
 412static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 413{
 414        u64 adj;
 415        u32 diff, addend;
 416        int neg_adj = 0;
 417        struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 418        struct pch_ts_regs *regs = pch_dev->regs;
 419
 420        if (ppb < 0) {
 421                neg_adj = 1;
 422                ppb = -ppb;
 423        }
 424        addend = DEFAULT_ADDEND;
 425        adj = addend;
 426        adj *= ppb;
 427        diff = div_u64(adj, 1000000000ULL);
 428
 429        addend = neg_adj ? addend - diff : addend + diff;
 430
 431        iowrite32(addend, &regs->addend);
 432
 433        return 0;
 434}
 435
 436static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
 437{
 438        s64 now;
 439        unsigned long flags;
 440        struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 441        struct pch_ts_regs *regs = pch_dev->regs;
 442
 443        spin_lock_irqsave(&pch_dev->register_lock, flags);
 444        now = pch_systime_read(regs);
 445        now += delta;
 446        pch_systime_write(regs, now);
 447        spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 448
 449        return 0;
 450}
 451
 452static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 453{
 454        u64 ns;
 455        u32 remainder;
 456        unsigned long flags;
 457        struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 458        struct pch_ts_regs *regs = pch_dev->regs;
 459
 460        spin_lock_irqsave(&pch_dev->register_lock, flags);
 461        ns = pch_systime_read(regs);
 462        spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 463
 464        ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 465        ts->tv_nsec = remainder;
 466        return 0;
 467}
 468
 469static int ptp_pch_settime(struct ptp_clock_info *ptp,
 470                           const struct timespec *ts)
 471{
 472        u64 ns;
 473        unsigned long flags;
 474        struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 475        struct pch_ts_regs *regs = pch_dev->regs;
 476
 477        ns = ts->tv_sec * 1000000000ULL;
 478        ns += ts->tv_nsec;
 479
 480        spin_lock_irqsave(&pch_dev->register_lock, flags);
 481        pch_systime_write(regs, ns);
 482        spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 483
 484        return 0;
 485}
 486
 487static int ptp_pch_enable(struct ptp_clock_info *ptp,
 488                          struct ptp_clock_request *rq, int on)
 489{
 490        struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 491
 492        switch (rq->type) {
 493        case PTP_CLK_REQ_EXTTS:
 494                switch (rq->extts.index) {
 495                case 0:
 496                        pch_dev->exts0_enabled = on ? 1 : 0;
 497                        break;
 498                case 1:
 499                        pch_dev->exts1_enabled = on ? 1 : 0;
 500                        break;
 501                default:
 502                        return -EINVAL;
 503                }
 504                return 0;
 505        default:
 506                break;
 507        }
 508
 509        return -EOPNOTSUPP;
 510}
 511
 512static struct ptp_clock_info ptp_pch_caps = {
 513        .owner          = THIS_MODULE,
 514        .name           = "PCH timer",
 515        .max_adj        = 50000000,
 516        .n_ext_ts       = N_EXT_TS,
 517        .pps            = 0,
 518        .adjfreq        = ptp_pch_adjfreq,
 519        .adjtime        = ptp_pch_adjtime,
 520        .gettime        = ptp_pch_gettime,
 521        .settime        = ptp_pch_settime,
 522        .enable         = ptp_pch_enable,
 523};
 524
 525
 526#ifdef CONFIG_PM
 527static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
 528{
 529        pci_disable_device(pdev);
 530        pci_enable_wake(pdev, PCI_D3hot, 0);
 531
 532        if (pci_save_state(pdev) != 0) {
 533                dev_err(&pdev->dev, "could not save PCI config state\n");
 534                return -ENOMEM;
 535        }
 536        pci_set_power_state(pdev, pci_choose_state(pdev, state));
 537
 538        return 0;
 539}
 540
 541static s32 pch_resume(struct pci_dev *pdev)
 542{
 543        s32 ret;
 544
 545        pci_set_power_state(pdev, PCI_D0);
 546        pci_restore_state(pdev);
 547        ret = pci_enable_device(pdev);
 548        if (ret) {
 549                dev_err(&pdev->dev, "pci_enable_device failed\n");
 550                return ret;
 551        }
 552        pci_enable_wake(pdev, PCI_D3hot, 0);
 553        return 0;
 554}
 555#else
 556#define pch_suspend NULL
 557#define pch_resume NULL
 558#endif
 559
 560static void __devexit pch_remove(struct pci_dev *pdev)
 561{
 562        struct pch_dev *chip = pci_get_drvdata(pdev);
 563
 564        ptp_clock_unregister(chip->ptp_clock);
 565        /* free the interrupt */
 566        if (pdev->irq != 0)
 567                free_irq(pdev->irq, chip);
 568
 569        /* unmap the virtual IO memory space */
 570        if (chip->regs != 0) {
 571                iounmap(chip->regs);
 572                chip->regs = 0;
 573        }
 574        /* release the reserved IO memory space */
 575        if (chip->mem_base != 0) {
 576                release_mem_region(chip->mem_base, chip->mem_size);
 577                chip->mem_base = 0;
 578        }
 579        pci_disable_device(pdev);
 580        kfree(chip);
 581        dev_info(&pdev->dev, "complete\n");
 582}
 583
 584static s32 __devinit
 585pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 586{
 587        s32 ret;
 588        unsigned long flags;
 589        struct pch_dev *chip;
 590
 591        chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
 592        if (chip == NULL)
 593                return -ENOMEM;
 594
 595        /* enable the 1588 pci device */
 596        ret = pci_enable_device(pdev);
 597        if (ret != 0) {
 598                dev_err(&pdev->dev, "could not enable the pci device\n");
 599                goto err_pci_en;
 600        }
 601
 602        chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
 603        if (!chip->mem_base) {
 604                dev_err(&pdev->dev, "could not locate IO memory address\n");
 605                ret = -ENODEV;
 606                goto err_pci_start;
 607        }
 608
 609        /* retrieve the available length of the IO memory space */
 610        chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
 611
 612        /* allocate the memory for the device registers */
 613        if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
 614                dev_err(&pdev->dev,
 615                        "could not allocate register memory space\n");
 616                ret = -EBUSY;
 617                goto err_req_mem_region;
 618        }
 619
 620        /* get the virtual address to the 1588 registers */
 621        chip->regs = ioremap(chip->mem_base, chip->mem_size);
 622
 623        if (!chip->regs) {
 624                dev_err(&pdev->dev, "Could not get virtual address\n");
 625                ret = -ENOMEM;
 626                goto err_ioremap;
 627        }
 628
 629        chip->caps = ptp_pch_caps;
 630        chip->ptp_clock = ptp_clock_register(&chip->caps);
 631
 632        if (IS_ERR(chip->ptp_clock))
 633                return PTR_ERR(chip->ptp_clock);
 634
 635        spin_lock_init(&chip->register_lock);
 636
 637        ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
 638        if (ret != 0) {
 639                dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
 640                goto err_req_irq;
 641        }
 642
 643        /* indicate success */
 644        chip->irq = pdev->irq;
 645        chip->pdev = pdev;
 646        pci_set_drvdata(pdev, chip);
 647
 648        spin_lock_irqsave(&chip->register_lock, flags);
 649        /* reset the ieee1588 h/w */
 650        pch_reset(chip);
 651
 652        iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
 653        iowrite32(1, &chip->regs->trgt_lo);
 654        iowrite32(0, &chip->regs->trgt_hi);
 655        iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
 656
 657        pch_eth_enable_set(chip);
 658
 659        if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
 660                if (pch_set_station_address(pch_param.station, pdev) != 0) {
 661                        dev_err(&pdev->dev,
 662                        "Invalid station address parameter\n"
 663                        "Module loaded but station address not set correctly\n"
 664                        );
 665                }
 666        }
 667        spin_unlock_irqrestore(&chip->register_lock, flags);
 668        return 0;
 669
 670err_req_irq:
 671        ptp_clock_unregister(chip->ptp_clock);
 672        iounmap(chip->regs);
 673        chip->regs = 0;
 674
 675err_ioremap:
 676        release_mem_region(chip->mem_base, chip->mem_size);
 677
 678err_req_mem_region:
 679        chip->mem_base = 0;
 680
 681err_pci_start:
 682        pci_disable_device(pdev);
 683
 684err_pci_en:
 685        kfree(chip);
 686        dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
 687
 688        return ret;
 689}
 690
 691static DEFINE_PCI_DEVICE_TABLE(pch_ieee1588_pcidev_id) = {
 692        {
 693          .vendor = PCI_VENDOR_ID_INTEL,
 694          .device = PCI_DEVICE_ID_PCH_1588
 695         },
 696        {0}
 697};
 698
 699static struct pci_driver pch_driver = {
 700        .name = KBUILD_MODNAME,
 701        .id_table = pch_ieee1588_pcidev_id,
 702        .probe = pch_probe,
 703        .remove = pch_remove,
 704        .suspend = pch_suspend,
 705        .resume = pch_resume,
 706};
 707
 708static void __exit ptp_pch_exit(void)
 709{
 710        pci_unregister_driver(&pch_driver);
 711}
 712
 713static s32 __init ptp_pch_init(void)
 714{
 715        s32 ret;
 716
 717        /* register the driver with the pci core */
 718        ret = pci_register_driver(&pch_driver);
 719
 720        return ret;
 721}
 722
 723module_init(ptp_pch_init);
 724module_exit(ptp_pch_exit);
 725
 726module_param_string(station, pch_param.station, sizeof pch_param.station, 0444);
 727MODULE_PARM_DESC(station,
 728         "IEEE 1588 station address to use - column separated hex values");
 729
 730MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
 731MODULE_DESCRIPTION("PTP clock using the EG20T timer");
 732MODULE_LICENSE("GPL");
 733
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