linux/drivers/mfd/mc13xxx-core.c
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   1/*
   2 * Copyright 2009-2010 Pengutronix
   3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4 *
   5 * loosely based on an earlier driver that has
   6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify it under
   9 * the terms of the GNU General Public License version 2 as published by the
  10 * Free Software Foundation.
  11 */
  12
  13#include <linux/slab.h>
  14#include <linux/module.h>
  15#include <linux/platform_device.h>
  16#include <linux/mutex.h>
  17#include <linux/interrupt.h>
  18#include <linux/mfd/core.h>
  19#include <linux/mfd/mc13xxx.h>
  20#include <linux/of.h>
  21#include <linux/of_device.h>
  22#include <linux/of_gpio.h>
  23
  24#include "mc13xxx.h"
  25
  26#define MC13XXX_IRQSTAT0        0
  27#define MC13XXX_IRQSTAT0_ADCDONEI       (1 << 0)
  28#define MC13XXX_IRQSTAT0_ADCBISDONEI    (1 << 1)
  29#define MC13XXX_IRQSTAT0_TSI            (1 << 2)
  30#define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  31#define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  32#define MC13XXX_IRQSTAT0_CHGDETI        (1 << 6)
  33#define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  34#define MC13XXX_IRQSTAT0_CHGREVI        (1 << 8)
  35#define MC13XXX_IRQSTAT0_CHGSHORTI      (1 << 9)
  36#define MC13XXX_IRQSTAT0_CCCVI          (1 << 10)
  37#define MC13XXX_IRQSTAT0_CHGCURRI       (1 << 11)
  38#define MC13XXX_IRQSTAT0_BPONI          (1 << 12)
  39#define MC13XXX_IRQSTAT0_LOBATLI        (1 << 13)
  40#define MC13XXX_IRQSTAT0_LOBATHI        (1 << 14)
  41#define MC13783_IRQSTAT0_UDPI           (1 << 15)
  42#define MC13783_IRQSTAT0_USBI           (1 << 16)
  43#define MC13783_IRQSTAT0_IDI            (1 << 19)
  44#define MC13783_IRQSTAT0_SE1I           (1 << 21)
  45#define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  46#define MC13783_IRQSTAT0_UDMI           (1 << 23)
  47
  48#define MC13XXX_IRQMASK0        1
  49#define MC13XXX_IRQMASK0_ADCDONEM       MC13XXX_IRQSTAT0_ADCDONEI
  50#define MC13XXX_IRQMASK0_ADCBISDONEM    MC13XXX_IRQSTAT0_ADCBISDONEI
  51#define MC13XXX_IRQMASK0_TSM            MC13XXX_IRQSTAT0_TSI
  52#define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  53#define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  54#define MC13XXX_IRQMASK0_CHGDETM        MC13XXX_IRQSTAT0_CHGDETI
  55#define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  56#define MC13XXX_IRQMASK0_CHGREVM        MC13XXX_IRQSTAT0_CHGREVI
  57#define MC13XXX_IRQMASK0_CHGSHORTM      MC13XXX_IRQSTAT0_CHGSHORTI
  58#define MC13XXX_IRQMASK0_CCCVM          MC13XXX_IRQSTAT0_CCCVI
  59#define MC13XXX_IRQMASK0_CHGCURRM       MC13XXX_IRQSTAT0_CHGCURRI
  60#define MC13XXX_IRQMASK0_BPONM          MC13XXX_IRQSTAT0_BPONI
  61#define MC13XXX_IRQMASK0_LOBATLM        MC13XXX_IRQSTAT0_LOBATLI
  62#define MC13XXX_IRQMASK0_LOBATHM        MC13XXX_IRQSTAT0_LOBATHI
  63#define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  64#define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  65#define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  66#define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  67#define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  68#define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  69
  70#define MC13XXX_IRQSTAT1        3
  71#define MC13XXX_IRQSTAT1_1HZI           (1 << 0)
  72#define MC13XXX_IRQSTAT1_TODAI          (1 << 1)
  73#define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  74#define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  75#define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  76#define MC13XXX_IRQSTAT1_SYSRSTI        (1 << 6)
  77#define MC13XXX_IRQSTAT1_RTCRSTI        (1 << 7)
  78#define MC13XXX_IRQSTAT1_PCI            (1 << 8)
  79#define MC13XXX_IRQSTAT1_WARMI          (1 << 9)
  80#define MC13XXX_IRQSTAT1_MEMHLDI        (1 << 10)
  81#define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  82#define MC13XXX_IRQSTAT1_THWARNLI       (1 << 12)
  83#define MC13XXX_IRQSTAT1_THWARNHI       (1 << 13)
  84#define MC13XXX_IRQSTAT1_CLKI           (1 << 14)
  85#define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  86#define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  87#define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  88#define MC13783_IRQSTAT1_HSLI           (1 << 19)
  89#define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  90#define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  91
  92#define MC13XXX_IRQMASK1        4
  93#define MC13XXX_IRQMASK1_1HZM           MC13XXX_IRQSTAT1_1HZI
  94#define MC13XXX_IRQMASK1_TODAM          MC13XXX_IRQSTAT1_TODAI
  95#define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
  96#define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
  97#define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
  98#define MC13XXX_IRQMASK1_SYSRSTM        MC13XXX_IRQSTAT1_SYSRSTI
  99#define MC13XXX_IRQMASK1_RTCRSTM        MC13XXX_IRQSTAT1_RTCRSTI
 100#define MC13XXX_IRQMASK1_PCM            MC13XXX_IRQSTAT1_PCI
 101#define MC13XXX_IRQMASK1_WARMM          MC13XXX_IRQSTAT1_WARMI
 102#define MC13XXX_IRQMASK1_MEMHLDM        MC13XXX_IRQSTAT1_MEMHLDI
 103#define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 104#define MC13XXX_IRQMASK1_THWARNLM       MC13XXX_IRQSTAT1_THWARNLI
 105#define MC13XXX_IRQMASK1_THWARNHM       MC13XXX_IRQSTAT1_THWARNHI
 106#define MC13XXX_IRQMASK1_CLKM           MC13XXX_IRQSTAT1_CLKI
 107#define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 108#define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 109#define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 110#define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 111#define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 112#define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 113
 114#define MC13XXX_REVISION        7
 115#define MC13XXX_REVISION_REVMETAL       (0x07 <<  0)
 116#define MC13XXX_REVISION_REVFULL        (0x03 <<  3)
 117#define MC13XXX_REVISION_ICID           (0x07 <<  6)
 118#define MC13XXX_REVISION_FIN            (0x03 <<  9)
 119#define MC13XXX_REVISION_FAB            (0x03 << 11)
 120#define MC13XXX_REVISION_ICIDCODE       (0x3f << 13)
 121
 122#define MC13XXX_ADC1            44
 123#define MC13XXX_ADC1_ADEN               (1 << 0)
 124#define MC13XXX_ADC1_RAND               (1 << 1)
 125#define MC13XXX_ADC1_ADSEL              (1 << 3)
 126#define MC13XXX_ADC1_ASC                (1 << 20)
 127#define MC13XXX_ADC1_ADTRIGIGN          (1 << 21)
 128
 129#define MC13XXX_ADC2            45
 130
 131void mc13xxx_lock(struct mc13xxx *mc13xxx)
 132{
 133        if (!mutex_trylock(&mc13xxx->lock)) {
 134                dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 135                                __func__, __builtin_return_address(0));
 136
 137                mutex_lock(&mc13xxx->lock);
 138        }
 139        dev_dbg(mc13xxx->dev, "%s from %pf\n",
 140                        __func__, __builtin_return_address(0));
 141}
 142EXPORT_SYMBOL(mc13xxx_lock);
 143
 144void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 145{
 146        dev_dbg(mc13xxx->dev, "%s from %pf\n",
 147                        __func__, __builtin_return_address(0));
 148        mutex_unlock(&mc13xxx->lock);
 149}
 150EXPORT_SYMBOL(mc13xxx_unlock);
 151
 152int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 153{
 154        int ret;
 155
 156        BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 157
 158        if (offset > MC13XXX_NUMREGS)
 159                return -EINVAL;
 160
 161        ret = regmap_read(mc13xxx->regmap, offset, val);
 162        dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 163
 164        return ret;
 165}
 166EXPORT_SYMBOL(mc13xxx_reg_read);
 167
 168int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 169{
 170        BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 171
 172        dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 173
 174        if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 175                return -EINVAL;
 176
 177        return regmap_write(mc13xxx->regmap, offset, val);
 178}
 179EXPORT_SYMBOL(mc13xxx_reg_write);
 180
 181int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 182                u32 mask, u32 val)
 183{
 184        BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 185        BUG_ON(val & ~mask);
 186        dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
 187                        offset, val, mask);
 188
 189        return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 190}
 191EXPORT_SYMBOL(mc13xxx_reg_rmw);
 192
 193int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
 194{
 195        int ret;
 196        unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 197        u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 198        u32 mask;
 199
 200        if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 201                return -EINVAL;
 202
 203        ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 204        if (ret)
 205                return ret;
 206
 207        if (mask & irqbit)
 208                /* already masked */
 209                return 0;
 210
 211        return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
 212}
 213EXPORT_SYMBOL(mc13xxx_irq_mask);
 214
 215int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
 216{
 217        int ret;
 218        unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 219        u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 220        u32 mask;
 221
 222        if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 223                return -EINVAL;
 224
 225        ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 226        if (ret)
 227                return ret;
 228
 229        if (!(mask & irqbit))
 230                /* already unmasked */
 231                return 0;
 232
 233        return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
 234}
 235EXPORT_SYMBOL(mc13xxx_irq_unmask);
 236
 237int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
 238                int *enabled, int *pending)
 239{
 240        int ret;
 241        unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 242        unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 243        u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 244
 245        if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 246                return -EINVAL;
 247
 248        if (enabled) {
 249                u32 mask;
 250
 251                ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 252                if (ret)
 253                        return ret;
 254
 255                *enabled = mask & irqbit;
 256        }
 257
 258        if (pending) {
 259                u32 stat;
 260
 261                ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 262                if (ret)
 263                        return ret;
 264
 265                *pending = stat & irqbit;
 266        }
 267
 268        return 0;
 269}
 270EXPORT_SYMBOL(mc13xxx_irq_status);
 271
 272int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
 273{
 274        unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 275        unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 276
 277        BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
 278
 279        return mc13xxx_reg_write(mc13xxx, offstat, val);
 280}
 281EXPORT_SYMBOL(mc13xxx_irq_ack);
 282
 283int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
 284                irq_handler_t handler, const char *name, void *dev)
 285{
 286        BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 287        BUG_ON(!handler);
 288
 289        if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 290                return -EINVAL;
 291
 292        if (mc13xxx->irqhandler[irq])
 293                return -EBUSY;
 294
 295        mc13xxx->irqhandler[irq] = handler;
 296        mc13xxx->irqdata[irq] = dev;
 297
 298        return 0;
 299}
 300EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
 301
 302int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
 303                irq_handler_t handler, const char *name, void *dev)
 304{
 305        int ret;
 306
 307        ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
 308        if (ret)
 309                return ret;
 310
 311        ret = mc13xxx_irq_unmask(mc13xxx, irq);
 312        if (ret) {
 313                mc13xxx->irqhandler[irq] = NULL;
 314                mc13xxx->irqdata[irq] = NULL;
 315                return ret;
 316        }
 317
 318        return 0;
 319}
 320EXPORT_SYMBOL(mc13xxx_irq_request);
 321
 322int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
 323{
 324        int ret;
 325        BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 326
 327        if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
 328                        mc13xxx->irqdata[irq] != dev)
 329                return -EINVAL;
 330
 331        ret = mc13xxx_irq_mask(mc13xxx, irq);
 332        if (ret)
 333                return ret;
 334
 335        mc13xxx->irqhandler[irq] = NULL;
 336        mc13xxx->irqdata[irq] = NULL;
 337
 338        return 0;
 339}
 340EXPORT_SYMBOL(mc13xxx_irq_free);
 341
 342static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
 343{
 344        return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
 345}
 346
 347/*
 348 * returns: number of handled irqs or negative error
 349 * locking: holds mc13xxx->lock
 350 */
 351static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 352                unsigned int offstat, unsigned int offmask, int baseirq)
 353{
 354        u32 stat, mask;
 355        int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 356        int num_handled = 0;
 357
 358        if (ret)
 359                return ret;
 360
 361        ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 362        if (ret)
 363                return ret;
 364
 365        while (stat & ~mask) {
 366                int irq = __ffs(stat & ~mask);
 367
 368                stat &= ~(1 << irq);
 369
 370                if (likely(mc13xxx->irqhandler[baseirq + irq])) {
 371                        irqreturn_t handled;
 372
 373                        handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
 374                        if (handled == IRQ_HANDLED)
 375                                num_handled++;
 376                } else {
 377                        dev_err(mc13xxx->dev,
 378                                        "BUG: irq %u but no handler\n",
 379                                        baseirq + irq);
 380
 381                        mask |= 1 << irq;
 382
 383                        ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
 384                }
 385        }
 386
 387        return num_handled;
 388}
 389
 390static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 391{
 392        struct mc13xxx *mc13xxx = data;
 393        irqreturn_t ret;
 394        int handled = 0;
 395
 396        mc13xxx_lock(mc13xxx);
 397
 398        ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
 399                        MC13XXX_IRQMASK0, 0);
 400        if (ret > 0)
 401                handled = 1;
 402
 403        ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
 404                        MC13XXX_IRQMASK1, 24);
 405        if (ret > 0)
 406                handled = 1;
 407
 408        mc13xxx_unlock(mc13xxx);
 409
 410        return IRQ_RETVAL(handled);
 411}
 412
 413static const char *mc13xxx_chipname[] = {
 414        [MC13XXX_ID_MC13783] = "mc13783",
 415        [MC13XXX_ID_MC13892] = "mc13892",
 416};
 417
 418#define maskval(reg, mask)      (((reg) & (mask)) >> __ffs(mask))
 419static int mc13xxx_identify(struct mc13xxx *mc13xxx)
 420{
 421        u32 icid;
 422        u32 revision;
 423        int ret;
 424
 425        /*
 426         * Get the generation ID from register 46, as apparently some older
 427         * IC revisions only have this info at this location. Newer ICs seem to
 428         * have both.
 429         */
 430        ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 431        if (ret)
 432                return ret;
 433
 434        icid = (icid >> 6) & 0x7;
 435
 436        switch (icid) {
 437        case 2:
 438                mc13xxx->ictype = MC13XXX_ID_MC13783;
 439                break;
 440        case 7:
 441                mc13xxx->ictype = MC13XXX_ID_MC13892;
 442                break;
 443        default:
 444                mc13xxx->ictype = MC13XXX_ID_INVALID;
 445                break;
 446        }
 447
 448        if (mc13xxx->ictype == MC13XXX_ID_MC13783 ||
 449                        mc13xxx->ictype == MC13XXX_ID_MC13892) {
 450                ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
 451
 452                dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 453                                "fin: %d, fab: %d, icid: %d/%d\n",
 454                                mc13xxx_chipname[mc13xxx->ictype],
 455                                maskval(revision, MC13XXX_REVISION_REVFULL),
 456                                maskval(revision, MC13XXX_REVISION_REVMETAL),
 457                                maskval(revision, MC13XXX_REVISION_FIN),
 458                                maskval(revision, MC13XXX_REVISION_FAB),
 459                                maskval(revision, MC13XXX_REVISION_ICID),
 460                                maskval(revision, MC13XXX_REVISION_ICIDCODE));
 461        }
 462
 463        return (mc13xxx->ictype == MC13XXX_ID_INVALID) ? -ENODEV : 0;
 464}
 465
 466static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 467{
 468        return mc13xxx_chipname[mc13xxx->ictype];
 469}
 470
 471int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
 472{
 473        return mc13xxx->flags;
 474}
 475EXPORT_SYMBOL(mc13xxx_get_flags);
 476
 477#define MC13XXX_ADC1_CHAN0_SHIFT        5
 478#define MC13XXX_ADC1_CHAN1_SHIFT        8
 479#define MC13783_ADC1_ATO_SHIFT          11
 480#define MC13783_ADC1_ATOX               (1 << 19)
 481
 482struct mc13xxx_adcdone_data {
 483        struct mc13xxx *mc13xxx;
 484        struct completion done;
 485};
 486
 487static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
 488{
 489        struct mc13xxx_adcdone_data *adcdone_data = data;
 490
 491        mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
 492
 493        complete_all(&adcdone_data->done);
 494
 495        return IRQ_HANDLED;
 496}
 497
 498#define MC13XXX_ADC_WORKING (1 << 0)
 499
 500int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 501                unsigned int channel, u8 ato, bool atox,
 502                unsigned int *sample)
 503{
 504        u32 adc0, adc1, old_adc0;
 505        int i, ret;
 506        struct mc13xxx_adcdone_data adcdone_data = {
 507                .mc13xxx = mc13xxx,
 508        };
 509        init_completion(&adcdone_data.done);
 510
 511        dev_dbg(mc13xxx->dev, "%s\n", __func__);
 512
 513        mc13xxx_lock(mc13xxx);
 514
 515        if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
 516                ret = -EBUSY;
 517                goto out;
 518        }
 519
 520        mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
 521
 522        mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
 523
 524        adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
 525        adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
 526
 527        if (channel > 7)
 528                adc1 |= MC13XXX_ADC1_ADSEL;
 529
 530        switch (mode) {
 531        case MC13XXX_ADC_MODE_TS:
 532                adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
 533                        MC13XXX_ADC0_TSMOD1;
 534                adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 535                break;
 536
 537        case MC13XXX_ADC_MODE_SINGLE_CHAN:
 538                adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 539                adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
 540                adc1 |= MC13XXX_ADC1_RAND;
 541                break;
 542
 543        case MC13XXX_ADC_MODE_MULT_CHAN:
 544                adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 545                adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 546                break;
 547
 548        default:
 549                mc13xxx_unlock(mc13xxx);
 550                return -EINVAL;
 551        }
 552
 553        adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
 554        if (atox)
 555                adc1 |= MC13783_ADC1_ATOX;
 556
 557        dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 558        mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 559                        mc13xxx_handler_adcdone, __func__, &adcdone_data);
 560        mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
 561
 562        mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
 563        mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
 564
 565        mc13xxx_unlock(mc13xxx);
 566
 567        ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 568
 569        if (!ret)
 570                ret = -ETIMEDOUT;
 571
 572        mc13xxx_lock(mc13xxx);
 573
 574        mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
 575
 576        if (ret > 0)
 577                for (i = 0; i < 4; ++i) {
 578                        ret = mc13xxx_reg_read(mc13xxx,
 579                                        MC13XXX_ADC2, &sample[i]);
 580                        if (ret)
 581                                break;
 582                }
 583
 584        if (mode == MC13XXX_ADC_MODE_TS)
 585                /* restore TSMOD */
 586                mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
 587
 588        mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
 589out:
 590        mc13xxx_unlock(mc13xxx);
 591
 592        return ret;
 593}
 594EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
 595
 596static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 597                const char *format, void *pdata, size_t pdata_size)
 598{
 599        char buf[30];
 600        const char *name = mc13xxx_get_chipname(mc13xxx);
 601
 602        struct mfd_cell cell = {
 603                .platform_data = pdata,
 604                .pdata_size = pdata_size,
 605        };
 606
 607        /* there is no asnprintf in the kernel :-( */
 608        if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
 609                return -E2BIG;
 610
 611        cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
 612        if (!cell.name)
 613                return -ENOMEM;
 614
 615        return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0, NULL);
 616}
 617
 618static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 619{
 620        return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
 621}
 622
 623#ifdef CONFIG_OF
 624static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 625{
 626        struct device_node *np = mc13xxx->dev->of_node;
 627
 628        if (!np)
 629                return -ENODEV;
 630
 631        if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
 632                mc13xxx->flags |= MC13XXX_USE_ADC;
 633
 634        if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
 635                mc13xxx->flags |= MC13XXX_USE_CODEC;
 636
 637        if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
 638                mc13xxx->flags |= MC13XXX_USE_RTC;
 639
 640        if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
 641                mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
 642
 643        return 0;
 644}
 645#else
 646static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 647{
 648        return -ENODEV;
 649}
 650#endif
 651
 652int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 653                struct mc13xxx_platform_data *pdata, int irq)
 654{
 655        int ret;
 656
 657        mc13xxx_lock(mc13xxx);
 658
 659        ret = mc13xxx_identify(mc13xxx);
 660        if (ret)
 661                goto err_revision;
 662
 663        /* mask all irqs */
 664        ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
 665        if (ret)
 666                goto err_mask;
 667
 668        ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
 669        if (ret)
 670                goto err_mask;
 671
 672        ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 673                        IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 674
 675        if (ret) {
 676err_mask:
 677err_revision:
 678                mc13xxx_unlock(mc13xxx);
 679                kfree(mc13xxx);
 680                return ret;
 681        }
 682
 683        mc13xxx->irq = irq;
 684
 685        mc13xxx_unlock(mc13xxx);
 686
 687        if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
 688                mc13xxx->flags = pdata->flags;
 689
 690        if (mc13xxx->flags & MC13XXX_USE_ADC)
 691                mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 692
 693        if (mc13xxx->flags & MC13XXX_USE_CODEC)
 694                mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
 695                                        pdata->codec, sizeof(*pdata->codec));
 696
 697        if (mc13xxx->flags & MC13XXX_USE_RTC)
 698                mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
 699
 700        if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
 701                mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
 702                                &pdata->touch, sizeof(pdata->touch));
 703
 704        if (pdata) {
 705                mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
 706                        &pdata->regulators, sizeof(pdata->regulators));
 707                mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
 708                                pdata->leds, sizeof(*pdata->leds));
 709                mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
 710                                pdata->buttons, sizeof(*pdata->buttons));
 711        } else {
 712                mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
 713                mc13xxx_add_subdevice(mc13xxx, "%s-led");
 714                mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
 715        }
 716
 717        return 0;
 718}
 719EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 720
 721void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 722{
 723        free_irq(mc13xxx->irq, mc13xxx);
 724
 725        mfd_remove_devices(mc13xxx->dev);
 726}
 727EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
 728
 729MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 730MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 731MODULE_LICENSE("GPL v2");
 732
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