linux/drivers/ide/pdc202xx_new.c
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   1/*
   2 *  Promise TX2/TX4/TX2000/133 IDE driver
   3 *
   4 *  This program is free software; you can redistribute it and/or
   5 *  modify it under the terms of the GNU General Public License
   6 *  as published by the Free Software Foundation; either version
   7 *  2 of the License, or (at your option) any later version.
   8 *
   9 *  Split from:
  10 *  linux/drivers/ide/pdc202xx.c        Version 0.35    Mar. 30, 2002
  11 *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  12 *  Copyright (C) 2005-2007             MontaVista Software, Inc.
  13 *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14 *  Author: Frank Tiernan (frankt@promise.com)
  15 *  Released under terms of General Public License
  16 */
  17
  18#include <linux/module.h>
  19#include <linux/types.h>
  20#include <linux/kernel.h>
  21#include <linux/delay.h>
  22#include <linux/pci.h>
  23#include <linux/init.h>
  24#include <linux/ide.h>
  25
  26#include <asm/io.h>
  27
  28#ifdef CONFIG_PPC_PMAC
  29#include <asm/prom.h>
  30#include <asm/pci-bridge.h>
  31#endif
  32
  33#define DRV_NAME "pdc202xx_new"
  34
  35#undef DEBUG
  36
  37#ifdef DEBUG
  38#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
  39#else
  40#define DBG(fmt, args...)
  41#endif
  42
  43static u8 max_dma_rate(struct pci_dev *pdev)
  44{
  45        u8 mode;
  46
  47        switch(pdev->device) {
  48                case PCI_DEVICE_ID_PROMISE_20277:
  49                case PCI_DEVICE_ID_PROMISE_20276:
  50                case PCI_DEVICE_ID_PROMISE_20275:
  51                case PCI_DEVICE_ID_PROMISE_20271:
  52                case PCI_DEVICE_ID_PROMISE_20269:
  53                        mode = 4;
  54                        break;
  55                case PCI_DEVICE_ID_PROMISE_20270:
  56                case PCI_DEVICE_ID_PROMISE_20268:
  57                        mode = 3;
  58                        break;
  59                default:
  60                        return 0;
  61        }
  62
  63        return mode;
  64}
  65
  66/**
  67 * get_indexed_reg - Get indexed register
  68 * @hwif: for the port address
  69 * @index: index of the indexed register
  70 */
  71static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
  72{
  73        u8 value;
  74
  75        outb(index, hwif->dma_base + 1);
  76        value = inb(hwif->dma_base + 3);
  77
  78        DBG("index[%02X] value[%02X]\n", index, value);
  79        return value;
  80}
  81
  82/**
  83 * set_indexed_reg - Set indexed register
  84 * @hwif: for the port address
  85 * @index: index of the indexed register
  86 */
  87static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
  88{
  89        outb(index, hwif->dma_base + 1);
  90        outb(value, hwif->dma_base + 3);
  91        DBG("index[%02X] value[%02X]\n", index, value);
  92}
  93
  94/*
  95 * ATA Timing Tables based on 133 MHz PLL output clock.
  96 *
  97 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
  98 * the timing registers automatically when "set features" command is
  99 * issued to the device. However, if the PLL output clock is 133 MHz,
 100 * the following tables must be used.
 101 */
 102static struct pio_timing {
 103        u8 reg0c, reg0d, reg13;
 104} pio_timings [] = {
 105        { 0xfb, 0x2b, 0xac },   /* PIO mode 0, IORDY off, Prefetch off */
 106        { 0x46, 0x29, 0xa4 },   /* PIO mode 1, IORDY off, Prefetch off */
 107        { 0x23, 0x26, 0x64 },   /* PIO mode 2, IORDY off, Prefetch off */
 108        { 0x27, 0x0d, 0x35 },   /* PIO mode 3, IORDY on,  Prefetch off */
 109        { 0x23, 0x09, 0x25 },   /* PIO mode 4, IORDY on,  Prefetch off */
 110};
 111
 112static struct mwdma_timing {
 113        u8 reg0e, reg0f;
 114} mwdma_timings [] = {
 115        { 0xdf, 0x5f },         /* MWDMA mode 0 */
 116        { 0x6b, 0x27 },         /* MWDMA mode 1 */
 117        { 0x69, 0x25 },         /* MWDMA mode 2 */
 118};
 119
 120static struct udma_timing {
 121        u8 reg10, reg11, reg12;
 122} udma_timings [] = {
 123        { 0x4a, 0x0f, 0xd5 },   /* UDMA mode 0 */
 124        { 0x3a, 0x0a, 0xd0 },   /* UDMA mode 1 */
 125        { 0x2a, 0x07, 0xcd },   /* UDMA mode 2 */
 126        { 0x1a, 0x05, 0xcd },   /* UDMA mode 3 */
 127        { 0x1a, 0x03, 0xcd },   /* UDMA mode 4 */
 128        { 0x1a, 0x02, 0xcb },   /* UDMA mode 5 */
 129        { 0x1a, 0x01, 0xcb },   /* UDMA mode 6 */
 130};
 131
 132static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 133{
 134        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 135        u8 adj                  = (drive->dn & 1) ? 0x08 : 0x00;
 136        const u8 speed          = drive->dma_mode;
 137
 138        /*
 139         * IDE core issues SETFEATURES_XFER to the drive first (thanks to
 140         * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
 141         * automatically set the timing registers based on 100 MHz PLL output.
 142         *
 143         * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
 144         * chips, we must override the default register settings...
 145         */
 146        if (max_dma_rate(dev) == 4) {
 147                u8 mode = speed & 0x07;
 148
 149                if (speed >= XFER_UDMA_0) {
 150                        set_indexed_reg(hwif, 0x10 + adj,
 151                                        udma_timings[mode]z2_PR">speedXFER_UDMA href="drivers/ide/pdc20">speed >=  150    =45"/2ID_PR2y set the timing registe1                case hwif, 0x10 + adj,
mode]z2_PR">speedXFER_UDMA href="d2ivers/ide/pdc20">speed >=  150 c#L144" i class="sref">mode =1 4;
<1 href="drivers/ide/pdca href="hwif" class="sref">hwif, 0x10 + adj,
 121                                          155,2xx_new.c#L149" id="L149" class="line" nam"line" naass="line" name="L56">  156mode]z2_PR">speedXFER_UDMA href="0eivers/ide/pdc20">speed >=  150        reg0e, ,
mwdma_ti                                         = mode =1 3;
<1 href="drivers/ide/pdca href="+code=PCI_DEVICsref">mode]z2_PR">speedXFER_UDMA href="0fivers/ide/pdc20">speed >=  15058">  58<1/a>                     1   br1ak;
reg0e, ,
  60         1     16dma_timings,2 14s="line" name="L"L148"> 14spdc202xx_new.c#L149" id="L149" class="line" na02xx_new.1c#L61" id="L61" class="l1ine" 16               case < 0x1a, 0x02, 0xcb },    1402/* UDMA mode 1 */
max_dma_rate(  70 */
                                         <>c#L144" i      return mode;
speed >= XFER_UDMA_0) {
 1 href="+code=devtmp#L134" id="L134"mp == 4d="L147"7f                                        <>"line" naline" name="L65">  65
,  =  130};
re2xx_new.c#L131" id="L131" clas">re2xx_ name="L131"> 131
 132static void pdcnew_set_dma_mode(ide_hwif_t dex of th1e indexed register
ide_1hwif_t * 133{
 134        struct pci_dev *dev   class="sr1ef">u8 index)
 135        u8 drive->rdc202xx_new.c#L1io
u8 u8 mode;
ind17e/pdc202xx_new.c#L145" id="L145" class="line" name="L145"> 145         */
 = 17 href="+code=max_dma_rate" class="srsref">mode]z2_PR">speedXFER_UDMA href="0c#L150" id="L150" class="line" name="L150"> 1 href="+code=dev="+code=reg0d" class="sref">reg0d, ,
rdc202xx_new.c#L1io
pio_ti href="+code=dev" class="sref">dev   c       mode]z2_PR">speedXFER_UDMA href="0d#L150" id="L150" class="line" name="L150"> 1 href="+code=dev="+code=reg0d" class="sref">reg0d, ,
rdc202xx_new.c#L1io
dev   ca> = speed >= XFER_UDMA_0) {
 1 href="+code=dev="+code=reg0d" class="sref">reg0d, ,
rdc202xx_new.c#L1io
 103 href="+code=dev" class="sref">dev   );
,     1    return , ide_12xx_new.c#L80" id="L80" 1class18        return 0;
  81
  41#endif
 131
 132ide_hwif_t" class="sref">ide_hwif_t href="dri1vers/ide/pdc202xx_new.c#1L83" 18rate(struct 
<1a href="drivers/ide/pdc2102xx_18href="driversw.c#L145" id="L145"0">  70 */
ide_hwif_t ha href="1ivers/ide/pdc202xx_new.c1#L85"18               case , u8 
u8 , u8  = u8 , ind1x,t;,     1+code=value" class="sref1">val19ef="drivers/30};
 131
pdcnew_set_dma_mode(ide_hwif_t g">"1index[%02X] value[‰0219" class="sref">hwif, i1ndex, ;
  92}
"line" na* Del"ted this becau>,2
  93
/* UDMA mode 1 */
,   38hwif  : G" cla channel re cl. href="drivers/i* UDMA mode 1 */
        struct         structchannelhref=?c22" id="L32" class="line" nSecondary="sref">DBGDBGdev   02xx_new.1c#L97" id="L97" class="l1ine" 19="L67ot;,   9819A mode 2 */
       * @0    * set_indexed_reg - Set indexed register2="drivers2ide/pdc202xx_new.c#L102"2id="L20ef="drivers/ide/pdc202xx_new.mment">/* UDMA mode 1 */
u8rrivers/longL121" id="L121" clad_counUlt="line" name="L10ad_counUlt 38  90       ide_hwif_t" class="sref">ide_hwif_t2 href="dr2vers/ide/pdc202xx_new.c#2104" 2d="L10ss="sref">hwif,  120,   9" c_p="line"
  90       1 href="+code=devsec_p="line" name="L90">  9sec_p="line"
  90        +ode=uhref="+code=dev" class="sref">dev  26" id="L126" class="line" name="L126"> 126        {  41#endif
u8  127        {longL121" id="L121" counU="line" name="LcounU
u8  128        {8"> {  41#endif
n>,ry="line" name="L10,ry
PCI_DEVICE_ID_PROMISE_20268:
 121,t;, /* PIO mode 4, IORDY o2,  Pr21dexed_regdo/ide/pdc202xx_new.c#L146" id="L146" clas202xx_new.2#L110" id="L110" class="2ine" 21dma_timings[PCI_DEVICE_ID_PROMISE_20268:
value);
 113/* UDMA mode 1 */
hwif->  9" c_p="line"
outb(2/ide/pdc222xx_new.c#L115" id="L1152 clas21               case <">speed >cnt8
dma_base + 1);
  9" c_p="line"
outb(2/ide/pdc222xx_new.c#L116" id="L1162 clas21 href="+code=max_dma_rate" class="srlass="sref">hwif->  9" c_p="line"
outb(2/" id="L122xx_new.c#L117" id="L1172 clas21"L57" class="line" narate" class="srcntrivers/ide/pdc20cntr    ref="+code=dma_base" class="sref">dma_base + 1);
  9" c_p="line"
outb(2/9 id="L12   speed >lass="sref">hwif->  9sec_p="line"
outb(202xx_new.2#L118" id="L118" class="2ine" 22k;
dma_base + 1);
  9sec_p="line"
outb(2drivers/i2e/pdc202xx_new.c#L120" i2="L1222dexed_reg(hwif->  9sec_p="line"
outb(202xx_new.2 dma_base + 1);
  9sec_p="line"
outb(2d"drivers2rs/ide/pdc202xx_new.c#L122" id22 class="sref">value);
 + 1);
speed >cnt8
outb(2d="driver202xx_new.c#L124" id="L122" cla22e" class="sref">mode;
;
  97 * set_indexed_reg - Set indexed register2s/ide/pdc202xx_new.c#L128" id="L122" cla22de/pdc202xx_new.c#L138" id="L138" cleeeeeeee* o
         *eeeeeeee*mment">/* UDMA mode 1 */
/* U23f="drivers/ideuMHiled/a> + 1);
,ry="line" name="L10,ry
 + 1);
speed >ineU="line" name="LineUhrefh< rate" class="srcounU="line" name="LcounU
outb(202xx_new.2#L130" id="L130" class="2ine" 23        return 0;
index)
hwif->dma_bacntrref">dma_bacnt2ref">dma_bacnt3> + 3);
 *#endif
cnt8
outb(20="driver2f="+code=to_pci_dev" cla2s="sr23e" class="sref">mode;
2dj                  2 (PCI_DEVICE_ID_PROMISE_20268:
speed    2     =ot;, -&g2;mode2e" name="2137"> 137
 129  * ="teco_pll_input_atures- D"tecoe="L142">input atures&n Hzapable
 1202span class="comment">        * @0    * set_indexed_reg - Set indexed register2="L141" c2ass="line" name="L141"> 241       * E.g._16A490002xx  name="LCI bus, i.e. half 84/*
/* UDMA mode 1 */
 1424ef">rrivers/longL121" id="L121" ="teco_pll_input_ature name="L90">  90"teco_pll_input_ature>  90       ide_hwif_t" class="sref">ide_hwif_t2.c#L144" 2d="L144" class="line" na2e="L124="L10ss="sref">hwif, 
  9timese  9sivrteg0d"    1 href="+code=devendeg0d" name="L90">  9endeg0d"
PCI_DEVICE_ID_PROMISE_20268:
 146      2 if (2a href="+code=longL121" id="L121" sivrtecounU="line" name="LsivrtecounU    1 href="+code=devendecounU="line" name="LendecounU
PCI_DEVICE_ID_PROMISE_20268:
-&g2 href="+code=u8" class="2ref">24        {longL121" id="L121" pll_input name="L90">  9"ll_input    1 href="+code=devusec_elapsdc202xx_new.c#L14usec_elapsdc
PCI_DEVICE_ID_PROMISE_20268:
value)
->PCI_DEVICE_ID_PROMISE_20268:
                2f (,t;,  1sivrtecounU="line" name="LsivrtecounU    ref="+code=dma_basclad_counUlt="line" name="L10ad_counUlt 38  90       i">PCI_DEVICE_ID_PROMISE_20268:
  9sivrteg0d"    i">PCI_DEVICE_ID_PROMISE_20268:
value);
/* UDMA mode 1 */
mode =2 4;
<2 href="driversrate" class="srlass="sref">hwif->  90        +ode= href="+code=outb" class="sref">outb(2aer setti2ass="line" name="L55">  255, dma_base + 1);
  90        +ode= href="+code=outb" class="sref">outb(2m"line" n2ass="line" name="L56">  256        {  41#endif
lass="sref">hwif-> + 3);
outb(2me-&g2ers/ide/pdc202xx_new.c#L257" i2="L57" class="rate" class="srlass="sref">hwif->  90        +ode= href="+code=outb" class="sref">outb(2m" name="2 class="sref">mode =2 3;
<25A mode 2 */
  58<2/a>                     2   br2ak;
/* UDMA mode 1 */
 1mdelay="line" name="Lmdelayt;outb(2ine" name2="L60">  60         2     26        return 0;
index)
  90       i">PCI_DEVICE_ID_PROMISE_20268:

2  9endeg0d"
PCI_DEVICE_ID_PROMISE_20268:
mode;
/* UDMA mode 1 */
  65
        {  41#endif
lass="sref">hwif->  90        +ode= href="+code=outb" class="sref">outb(2i       <2vers/ide/pdc202xx_new.c#2L67" 26"L57" class="rate" class="srfcrrivers/ide/pdc20fcrr
dma_base + 1);
  90        +ode= href="+code=outb" class="sref">outb(2ia> = value)
hwif-> + 3);
outb(2 href="dr2ivers/ide/pdc202xx_new.c2#L69"270L57" class="rate" class="srlass="sref">hwif->  90        +ode= href="+code=outb" class="sref">outb(2dex of th2e indexed register

ide_2hwif_t *;
u8   92}
"line" na* (n -&cturescounUltr&qu30 bit>w id andscounUs down)/ide/pdc202xx_new.c#L137" id="L137" class="li2cc#L144" 2ref">u8 /* UDMA mode 1 */
ind27,  + 1);
  9endeg0d"
  9tv_sech"d/a-ass="line" name="L90">  9sivrteg0d"    i">PCI_DEVICE_ID1>
  9t|2turn"line" name="LendecounU
(2 href="dr2ivers/ide/pdode= href="+code=outb" class="sref">outb=3ef=" ref1" c=o_gDMCE_ID_PROMISE_20268:
outb=3ef="2h2="Oxx_new.c#L137" id="L137" clapan>
24        {longL121" id="L121_elae" class="srlass=ef2>set_25 class="line" name="L120"> 1sivE_ID_PROMISE_2026="l2ine" 26" class="sref">index)
 class="srcounnnnn) /02, *L137" id="L137" clapan>
dev   c2> = ind27, 
dev   <28"L149"2 149                2f (,t;2 2                defaudc2202xx_26" class="sref">value)
hwime="a>->ld] ">ia>->ld]href="+code=dma_base" clafcrr> + f (2a href="+code=longL121" id="L121" sivrtecounU="line" name="LsivrtecounU    1 href="+code=dc#L137" id="L137" clapan>
ide_12xx_new.c#L80" id="L80" 1class18    2   return20;
24        {longL121" id="L121#L137" id="L137" clapan>
ide_hwif_t2/a> h2ef="drp2ed" class="sref">speed    2     =oa>(struct2ide_hwif_t2/a> h2 href=#ifdef            2 (        {longLCONFIG_PPC_PMAC144" 2      return u8         {longLapple_kiwi" iiaref"> *)n class= 2      return u8  *
value)


ide_hwif_t2/a> g29">ide_2hwif_t="drivers/ide/pdc21n"line" name="L15n(2wif, 


<1a href="drivers/ide/pdc21pdma_timings)n class"line" name=4   rhrisiow.c#L135" id="L1rhrisiow ="+coiversvp="l mode 4, IORDY o2,  Pr21dexed_regdo/i* UDMA mo2e 1 */
 magodeconcig[/* UDMA mo2e 1 */
)n class,de=hwiffday="line" name="L=conc#L135" id="L135concL121=#L137" id="L137" clapan>
dev   029id="L122xx_new.c#L117" id="L1172 cla)
speed    2     =3e 2 */
speed    2     =3e12 */3rivers/id3/pdc202xx_new.c#L81" id=3L812h30">ide_12xx_new.c#L80" id="L80" 1class18    3set_index3d_reg - Set indexed regi3ter2=30lass="1line"="liclass="srfcrriverid="/a> * 145ide_hwif_t3/a>2 30pan>
<1a href id="Lchardrivers/ide/pdc20naa h2="Oxx_new.c#Lnaa 
3wif,   90"teco_pll_input_ature> 145dev  263 id="L126" clame="L90">  90"teco_pll_input_="L90">  90       1 href="+code=devsec_p="line" name="L90">  9sec_p="line"
  90        +ode=u3"+code=u83 class="sref">u8 24        {longL121" id="L121" pll_input name=121" id="L>        {longL121" id="LL121" pll_input name=rlin="sref">reg0d

value)
hwif-&g121"ctlrL121#L137" id="L137" clapan>

ide_2hwif_t="drivers/ide/pdc21ature>PCI_DEVI3E_ID_PROMISE_20268:
3a h2931x_new.1c#L61" id="L61       -ivers/ide/pdc21EFAULT;

        {longLCONFIG_PPC_PMAC144" 2      return outb<3a>(2/31href="2+code=index" class="sapple_kiwi" iia>        {longLapple_kiwi" iiaref">ivers/ide/pdc20L145"> 145
outb<3a>(2/3de/pdc#hre="L137" id="L137" clapan>
outb<3a>(2/31/a>-&g2;outb<3a>(2/3 id="L12    * = id="L frequencyva27ref="drivers/ide/pdc202xx_neline" na*mment">3ef="+code3outb" class="sref">outb<3a>(203xx_new.2#L118"switchex" class="sref1">ind17e/pdc202xx_new.c#L145" id="L145" class="line" name="L145"> 145do/3ef="+code3outb" class="sref">outb<3a>(2d3ivers/i2e/pdc202xx_newc id 4:p5" id="L122" cla22       it's 1ss="com 0x0Ultra1ss="/a>3ee/pdc2023outb" class="sref">outb<3a>(203xx_new.2 
outb<3a>(2d32 =45"/2ID_PR2y set the timingbreak#L137" id="L137" clapan>
3e UDMA mo3outb" class="sref">outb<3a>(2d32driver2/ide/pdc202xx_default:rivers/ide/pdc202xx_neline" na*mment">3ef="+code3>mode;
break#L137" id="L137" clapan>
speed    2     =3set_index3d_reg - Set indexed regi3ter2s32name="2 class="sref">mode =2 3;
<25A mo3span>
3* UDMA mo3e 1 */
outb<3a>(2033141" c2ass="line" name="L141""""""""*=On some systems,eeeeremment"> eeeeeunneeeeat non-1" lhred_pll_i 145" c"LCI bus, i.e. half 84u8 
2c#L73" id="L73" class="l2ine" 2PDC a>68  na*an er="/a>+code=e="LCI bus, i.e. half 84outb<3a>(2033L144" 2ref">u8 mode;
u8 3>PCI_DEVI3E_ID_PROMISE_20268:
3a h2"33ine" n2line" name="L65">  65ef">24        {longL121" id="L121_els="line" name="L1 1424ef">rrivers/longL121" id="L121" ="teco_pll_input_ature naivers/ide/pdc21ature>
, dma_bacnt2ref">dma_bacnt3> + 3);
3ode2e33id="L12    145        {longL121" id="L121_/"1="+=#L137" id="L137" clapan>
                2f (3span>
                     2   br Saiiay="/e_ina27ref="drivers/ide/pdc202xx_neline" na*mment">3set_index3d_reg - Set indexed regi3ter2=34">ide_2hwif_t="drivers/ide/pdc21unlikel3" class="a"+codunlikel3"rate" class="srlassp21"24        {longL121" id="L121_eedLne" name="LcounU
        {longL121" id="L121_egdL=l mode 4, IORDY o2,  Pr21dexed_regdo/3="comment3>/*
, dma_bacnt2rode 4, IORDY o2,  Pr21dexed_regdo/3=4t_index3e 1 */
 * +naa h2="Oxx_new.c#Lnaa  145        {longL121" id="L121=#L137" id="L137" clapan>
ide_hwif_t3/a>2.34driver2/ide/pdc202xx_go 0xide/pdc202xx_new/a>        {longLo="L121#L137" id="L137" clapan>
3wif, speed    2     =3>PCI_DEVI3E_ID_PROMISE_20268:
3a h2=3line" 2ed" class="sref">speed    2     =3>;3E_ID_PROMISE_20268:
3a h2=3-&#ifdef            2 (speed    2     =3>a href="3E_ID_PROMISE_20268:
3a h2=3 name="2ref="+code=speed" cladc2202xx_26" class="sref">value)
hw121" id="Lnp"L" id=ld Hzef">dma_bacnt2re7" id="L1172 cla)21" id="L>        {longL121" id="LL121=#L137" id="L137" clapan>
                2f (3t;3                      2   br Show="line" nar0x1ll_indo/3>PCI_DEVI3E_ID_PROMISE_20268:
3a h2m35141" c2ass="line" name="L141""""""""*=(maybe alcodeyeconcigur0">by="linBIOSscounUltr&qu30 bit>w id andscounUs down)/ide/p3>PCI_DEVI3E_ID_PROMISE_20268:
3a h2m35ss="sr2ef">u8 3s="sref">3alue);

        {  41hwif->  9sec_p="line"

modedma_base + 1);
  9sec_p="line"
outb<3a>(2a3r setti2ass="line" name="L55"
        {  41hwif->  9sec_p="line"
outb<3a>(2m3line" n2ass="line" name="L56"121"ctlref">hwif-&g121"ctlrL121f="+code=devcnts="line" name="Lcntshrefref="+code=dma_base" class="sref">dma_base + 1);
  9sec_p="line"
3outb" class="sref">outb<3a>(2m35/a>-&g2;outb<3a>(2m35name="2ref="+code=speed" cladc2202xx_26" class="sref">value)
hw121"ctla>->-> +121"ctl53" class="line"121"ctl5L121" pll_input name=121"ctlref">hwif-&g121"ctlrL121" name="L90">  9sec_p="line"

  58#hre="L137" id="L137" clapan>
36 of th2e indexed register
outb<3a>(2i36">ide_2hwif_t *;
u8 ;
3E_ID_PROMISE_20268:
3a h2 362
2c#L73" id="L73" class="l2ine" 2POUT_elaFp="2) /0(( R ="2) **NOscounUltr&qu30 bit>w id andscounUs down)/ide/p3>PCI_DEVI3E_ID_PROMISE_20268:
3a h2 36L144" 2ref">u8 3ass="sref3>mode;
reg0d        {longL121" id="L121_/"1="+=#L137" id="L137" clapan>
3line" n2line" ="drivers/ide/pdc21rlin="sref">reg0dL= {                   2   br 8.6xva27ref="drivers/ide/pdc202xx_neline" na*mment">3a;3outb" class="sref">outb<3a>(2i36id="L122xx_new.c#L117"                 2   br UseeeeNO rsvp=1, R rsvp=dva27ref="drivers/ide/pdc202xx_neline" na*mment">3af="+code3outb" class="sref">outb<3a>(2i36id="L12   
outb<3a>(2 3ref="dr2ivers/}exed  ="drivers/ide/pdc21rlin="sref">reg0dL= {                   2   br 12.9xva27ref="drivers/ide/pdc202xx_neline" na*mment">3ef="+code3outb" class="sref">outb<3a>(2d37vers/i2e/pdc202xx_new.                 2   br UseeeeNO rsvp=1, R rsvp=8va27ref="drivers/ide/pdc202xx_neline" na*mment">3ef="+code3an>
  90        +ode=u3c202xx_ne3.c#L137" id="L137" class3"li2c373f="dr2ivers/}exed  ="drivers/ide/pdc21rlin="sref">reg0dL= {                   2   br 16.1xva27ref="drivers/ide/pdc202xx_neline" na*mment">3e="sref">3.c#L137" id="L137" class3"li2c371133ePCI_DEVI3.c#L137" id="L137" class3"li2c37driver2/ide/pdc202xx_new.c#L1142 id=ecounU
  90        +ode=u3css="sref3e 1 */
reg0dL= {                   2   br 64xva27ref="drivers/ide/pdc202xx_neline" na*mment">3e UDMA mo351" clastv_sec name="L903>  9t32turn"line" name="Lendnew.c#L1142 id=ecounU
dev   c3> = 3ref="+cod3=dev" class="sref">dev   <38x_new.2#L118" id="L118" class="2ine"e" 1class19, dma_bacnt2ref">dma_bacnt3> + 3);
 145reg0d

speed    2     =3r202xx_ne3 class="sref">ide_hwif_t3/a> h38/pdc2L137" id="L137" clapan>
modereg0d
ide_hwif_t3/a> h3 href=L137" id="L137" clapan>
u8   256        {  41#endif
lass="sref">hwFa>->d] Ra>->d] rlin=*1="+a>->ld]href="+code=dma_base" clafcrr> +c#L135" id="L135132" id="L132" class="ecounU
reg0d
-&g2;u8 do/3t;3 3t;3 , dma_bacnt2ref">dma_bacnt3> + 3);
ide_hwif_t3/a> g39x_new.2  145
3wif, 
speed    2     =3t>(struct3ref="drivers/ide/pdc202x3_new339L144" 2      return 

hwif-&g121"ctlrL121f="rivers/ide/pdc21us=2sref"24" class="sre) pll_input name=ecounU

dev   039/a>-&g2;value)
hwWrineeee121"ctla>->-> +121"ctl53" class="line"121"ctl5L121" pll_input name=121"ctlref">hwif-&g121"ctlrL121" name="L90">  9sec_p="line"

                2f (4e12 */2                defau
        {  41hwif->  9sec_p="line"
dma_base + 1);
  9sec_p="line"

        {  41hwif->  9sec_p="line"

2hwif-&g121"ctlrL121" pll_input name= class="sref">dma_base + 1);
  9sec_p="line"
2 40L144" 2      return 4wif,   * =circue < 0xbe stabl1a, 0x02, 0xcb },   4ref="+cod4=dev" class="sref">dev  2640ine" n2ass="line" name="L56"lt:2

u8 -&g2;speed    2     =4>PCI_DEVI4E_ID_PROMISE_20268:
4a h2941>  58<2/a>                     2   br7ref="drivers/ide/pdc202xx_neline" na*mment">4>12 */do/4de/pdc2024x_new.c#L146" id="L146" 4las2041141" c2ass="line" name="L141""""""""* 0x02, 0xcb },   4>PCI_DEVI4E_ID_PROMISE_20268:
4a h2941x_new.2c#L61" id="L61" class
        {  41hwif->  9sec_p="line"
4t_index4alue);

2dma_base + 1);
  9sec_p="line"

mode =2 4;
<2 href="driversrate" c3ass="srlass="sref">hwif->  9sec_p="line"
outb<4a>(2/41href="2+code=index" class="s121"ctlref">hwif-&g121"ctlrL121f="+code=devcnts="line" name="Lcntshrefref="+code=dma_base" class="sref">dma_base + 1);
  9sec_p="line"
ef="+cod4outb" class="sref">outb<4a>(2/41ine" 2ed" class="sref">speed    2     =4>+code=u84outb" class="sref">outb<4a>(2/41     <2vers/ide/pdc202xx_newdc2202xx_26" class="sref">value)
hw121"ctla>->-> +121"ctl53" class="line"121"ctl5L121" pll_input name=121"ctlref">hwif-&g121"ctlrL121" name="L90">  9sec_p="line"
outb<4a>(2/4 id="L#hre="L137" id="L137" clapan>
outb<4a>(2042"L149"2 149                2f (4ef="+code4outb" class="sref">outb<4a>(2d4ivers/iide/pdc202xx_new/a>        {longLo="L121:rivers/ide/pdc202xx_neline" na*mment">4ee/pdc2024outb" class="sref">outb<4a>(204xx_new.2  135        outb<4a>(2d42 =45"p2ed" class="sref">speed    2     =4e4t_index4alue);

outb<4a>(2d42drive"1line" * * 145do/4c202xx_ne4.c#L137" id="L137" class4"li2s42ine" naass="l * hr2ref" 135        -&g2; hr2ref"ref="+code=devtmp#)
 145   bus5"> 145 145 145   n cfw.c#L135" id="L1n cfw"sre) + 1ef">dma_bacnt3> + 3);
 145   n cfw.c#L135" id="L1n cfw"sre) class="srcounU="line" name="LcounU

outb<4a>(2043">ide_2hwif_t="drivers/ide/pdc21a142_timings hr2ref"rfday=fday=h2e indexed register
 hr2ref""line" name=4   vhreoecounU
 145   vhreoecounU

    hrice_timings hriceref"reels="line" name="L145"> 145    hrice_timings hriceref"l mode 4, IORDY o2,  Pr21dexed_regdo/4e UDMA mo4outb" class="sref">outb<4a>(2043L144" 2      return    irqe" name="Lcntshrrqe/pdc!els="line" name="L145"> 145   irqe" name="Lcntshrrqe/pdl mode 4, IORDY o2,  Pr21dexed_regdo/4e202xx_ne4E_ID_PROMISE_20268:
4a h2"43ine" naass="line" name="L56">ivers/ide/pdc21a142_timings hr2ref""line" name=4   irqe" name="Lcntshrrqe/pdcels="line" name="L145"> 145   irqe" name="Lcntshrrqe/pd=h2e indexed register
ivers/ide/pdc21e" 1class19, dma_bacnt2rode 4, IORDY o2,  Pr21dexed_regdo/44ode2e43id="L12   ilass="line" nSecondary="sri92">rupt fixedhref="+code=dma_base" clafcrr> +1ci_naa h2="Oxx_new.c#L1ci_naa  class="line" name="L145"> 145speed    2     =4span>

        speed    2     =4=4t_index4e 1 */

ide_hwif_t4/a>2.44driver2/ide/p                  2 (        , speed    2     =4=202xx_ne4E_ID_PROMISE_20268:
4a h2=4line" 2ed" class="sref">speed    2     =4>;4E_ID_PROMISE_20268:
4a h2=4-&"1line" id="L * 145
<2  _port_ops5"> 145
<2  _port_opse/pdcelmode 4, IORDY o2,  Pr21dexed_regdo/4>a href="4E_ID_PROMISE_20268:
4a h2=4 name="2ref="+ class="li2cc#L1dma_base + s/iio_ 0x1_new.2 dma_base )
<2  _do/4>PCI_DEVI4E_ID_PROMISE_20268:
4a h2m450ame="2ref="+ class="li2cc#L1dma_base + s/;
dma_base )
<2  _do/4>pan>
    class="li2cc#L1re=3ef="2hredma_base )
<2  _redo/4>et_index4E_ID_PROMISE_20268:
4a h2m452  58<2/a>    class="li2cc#L1cabl1_" ="te">dma_base cabl1_" ="te_new.2 dma_base )
<2  _cabl1_" ="teL121"ode 4, IORDY o2,  Pr21dexed_regdo/4>"comment4E_ID_PROMISE_20268:
4a h2m45ss="s} 135        4alue);


<            2 (
outb<4a>(2a4r setti2ass="l{ \L137" id="L137" clapan>
outb<4a>(2m45ine" naass="line" nam class="li2cc#L1naa h2="Oxx_new.c#Lnaa 
outb<4a>(2m45id="L122xx_new.c#L117 class="li2cc#L1
outb<4a>(2m45id="L12    145ort_opse/pdc href=effday="line" name="L=>
<2  _port_ops5"> 145
<2  _port_opse/pd, \L137" id="L137" clapan>
 145
46vers/i2e/pdc202xx_new id="L111111111111+code=devcnts="IDE_HFLAG_ERROR_STOPS_FIFOass19, 
outb<4a>(2i46x_new.2 , 
, , 
4E_ID_PROMISE_20268:
4a h2 46113ATA_MWDMA2e/pd, \L137" id="L137" clapan>
, 
mode;
speed    2     =4* UDMA mo4e 1 */
speed    2     =4a;4outb" class="sref">outb<4a>(2i46/a>-&"1line" id="L *reg0d
<2  _"/a> 145
<2  _"/a>do/4af="+code4outb" class="sref">outb<4a>(2i46id="L12   {68,70}"* 0x02, 01111111111+code=devcnts="DECLARE_PDCNEW_DEV202xx_26" class=ECLARE_PDCNEW_DEV class="line" name="ATA_UDMA5_timingsATA_UDMA5e/pdl"ode 4, IORDY o2,  Pr21dexed_regdo/4ef="+code4outb" class="sref">outb<4a>(2 47>  58<2/a>                     2   br 1:2PDC a>{69,71,75,76,77}"* 0x02, 01+code=devcnts="DECLARE_PDCNEW_DEV202xx_26" class=ECLARE_PDCNEW_DEV class="line" name="ATA_UDMA6_timingsATA_UDMA6e/pdl"ode 4, IORDY o2,  Pr21dexed_regdo/4epan>
outb<4a>(2d47vers/} 135        ide_12xx_new.c#L80" id="L80" 1class18    4c202xx_ne4.c#L137" id="L137" class4"li2c47ss="sr2ef">u8 4e="sref">4.c#L137" id="L137" class4"li2c472
2c#L73" id="L73" class*/a>   line" 2  _   calledeeeen a line" nanp"Lfound7ref="drivers/ide/pdc202xx_neline" na*mment">4e UDMA mo4.c#L137" id="L137" class4"li2c47L144" 2ref">u8 4ef="+code4e 1 */
u8 4e UDMA mo451" clastv_sec name="L904>  9t42turn" 2ref">u8 4e;4r
u8   CI"L10 rerlin=n layer (or t"> IDE w id andscounUs down)/ide/p4ef="+code4=dev" class="sref">dev   c4> = u8 dev   <48x_new 2ref">u8 4t;4 4tf="+code4         {longL_a hr iiaers/iide/pdc202xx_ne>
 145
 * 145)
do/4r202xx_ne4 class="sref">ide_hwif_t4/a> h48113reg0d 145 145
<2  _"/a>idef=""line" name=4    Y o2,_dat<202xx_26" class Y o2,_dat        (struct4 * 145 145   bus5"> 145   selc#L135" id="L135selc ="+ 135        ide_hwif_t4/a> h4 href=L137" id="L137" clapan>
u8  145    hrice_timings hriceref"reels="line" name="PCI_DEVICE_ID_PROMISE_a h70_timingsPCI_DEVICE_ID_PROMISE_a h70ref"rfday=fday=ls="line" name="bridg<5"> 145
 145   vhreoecounU
u8  145    hrice_timings hriceref"reels="line" name="PCI_DEVICE_ID_=EC_21150_timingsPCI_DEVICE_ID_=EC_21150e/pdl mode 4, IORDY o2,  Pr21dexed_regdo/4t;4 )
        4 
ide_hwif_t4/a> g49x_new.2  145   n cfw.c#L135" id="L1n cfw"sre) fday=l2=_12xx_new.c#L80" id="L80" 1class18    4s="sref">4wif,         
 hr2ref"ref="+code=devtmp#)
)
s="line" name="L145"> 145        
do/4t/pdc20fc4=dev" class="sref">dev   049id="L122xx_new.c#L117e="L56">="liclass="srfcrrivrrse" name="Lcntshre"L121_els="line" name="spe_p
reg0ds="line" name="L145"> 145 +a142_timings hr2ref"_base" clafcrr> +a5"> 145 +NULLline" name="L15NULL ="+= 135        
        {longL1w17dma_s="line" name="L142_timings hr2ref"l 135                ide_hwif_t5L812h50x_new.2 speed    2     =5set_index5d_reg - Set indexed regi5ter2=50x_new.2c#L61"p2ed" class="sref">speed    2     =5r4t_index5dc#L137" id="L137" class5ive2e50/pdc2L137" id="L137" clapan>
2 50driver2/ide/p="drivers/ide/pdc21L145"> 145    hrice_timings hriceref"reels="line" name="PCI_DEVICE_ID_PROMISE_a h76_timingsPCI_DEVICE_ID_PROMISE_a h76ref"rfday=fday=ls="line" name="bridg<5"> 145
5wif,  145   vhreoecounU
5w 1 */
 145    hrice_timings hriceref"reels="line" name="PCI_DEVICE_ID_INTEL_I960_timingsPCI_DEVICE_ID_INTEL_I960_new.||h2e indexed register
5wdev" class="sref">dev 145    hrice_timings hriceref"reels="line" name="PCI_DEVICE_ID_INTEL_I960RM_timingsPCI_DEVICE_ID_INTEL_I960RMref"ll mode 4, IORDY o2,  Pr21dexed_regdo/5s9code=u85 , dma_bacnt2rode 4, IORDY o2,  Pr21dexed_regdo/5>PCI_DEVI5E_ID_PROMISE_20268:
5a h2951x_new.2#L118" id="L1111111111"lass="line" nSecondary="srLskippconhref="+code=dma_base" clafcrr> +1ci_naa h2="Oxx_new.c#L1ci_naa  class="line" name="L145"> 145        speed    2     =5>PCI_DEVI5E_ID_PROMISE_20268:
5a h2951x_new2ed" class="sref">speed    2     =5>4t_index5alue);

2 145s="line" name="L145"> 145 +a5"> 145 +NULLline" name="L15NULL ="+= 135        
speed    2     =5>="sref">5outb" class="sref">outb<5a>(2/51href=L137" id="L137" clapan>
outb<5a>(2/51ine" "1line"voidiclass="srfcrriv_a hrexia>        {longL_a hrexiaers/iide/pdc202xx_ne>
 145
 * 145+code=u85outb" class="sref">outb<5a>(2/51     mode 4, IORDY o2,  Pr21dexed_regdo/5ef="+code5outb" class="sref">outb<5a>(2/51id="L12    * 145 145s="line" name="L145"> 145        outb<5a>(20520d="L12    * hr2ref"def="+code=devtmp#host5"> 145    hr5"> 145s="line" name="host5"> 145    hr5"> 145        outb<5a>(2d52 of th2e indexed register
outb<5a>(205xx_new.2  145s="line" name="L145"> 145        outb<5a>(2d52x_new.2c#L61" id="L61" classhw17dma_        {longL1w17dma_s="line" name="L142_timings hr2ref"l 135        );
speed    2     =5e UDMA mo5outb" class="sref">outb<5a>(2d52L144" 2      return )
 145
do/5c202xx_ne5.c#L137" id="L137" class5"li2s52ine" naass="l{ls="line" name="PCI_VDEVICEline" name="L15PCI_VDEVICEref">s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h6s=2sref"24" clasPCI_DEVICE_ID_PROMISE_a h6sref"l, 0 }"ode 4, IORDY o2,  Pr21dexed_regdo/5e+code=u85ref="drivers/ide/pdc202x5_ne2s528ne" naass="l{ls="line" name="PCI_VDEVICEline" name="L15PCI_VDEVICEref">s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h69=2sref"24" clasPCI_DEVICE_ID_PROMISE_a h69ref"l, 1 }"ode 4, IORDY o2,  Pr21dexed_regdo/5ef="+code5d_reg - Set indexed regi5ter2s52name="2ref="+{ls="line" name="PCI_VDEVICEline" name="L15PCI_VDEVICEref">s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h70_timingsPCI_DEVICE_ID_PROMISE_a h70ref"l, 0 }"ode 4, IORDY o2,  Pr21dexed_regdo/5span>
s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h7ref">hwif-&gPCI_DEVICE_ID_PROMISE_a h7rref"l, 1 }"ode 4, IORDY o2,  Pr21dexed_regdo/5* UDMA mo5e 1 */
s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h75_timingsPCI_DEVICE_ID_PROMISE_a h75ref"l, 1 }"ode 4, IORDY o2,  Pr21dexed_regdo/5*e/pdc2025outb" class="sref">outb<5a>(2053">ide_2hwif_t{ls="line" name="PCI_VDEVICEline" name="L15PCI_VDEVICEref">s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h76_timingsPCI_DEVICE_ID_PROMISE_a h76ref"l, 1 }"ode 4, IORDY o2,  Pr21dexed_regdo/5*PCI_DEVI50;
s="line" name="PROMISEline" name="L15PROMISEe/pd_base" clafcrr> +PCI_DEVICE_ID_PROMISE_a h77_timingsPCI_DEVICE_ID_PROMISE_a h77ref"l, 1 }"ode 4, IORDY o2,  Pr21dexed_regdo/5*4t_index50;
do/5* UDMA mo5outb" class="sref">outb<5a>(2053L144"} 135         +MODULE_DEVICE_TABLEline" name="L15MODULE_DEVICE_TABLEref">s="line" name=")
<_timings)
 +>
 145
        :
5a h2"53ine" 2ed" class="sref">speed    2     =5e+code=u85 -&"1line" *)
)
do/55ode2e53name="2ref="+ class="li2cc#L1naa h2="Oxx_new.c#Lnaa dma_bacnt2ref">dma_bacnt3> + 3);
 145 145
dma_bacnt3> + 3);
    class="li2cc#L1prob<5"> 145rob< 145
dma_bacnt3> + 3);
 145s="line" name=")
 145
do/5="comment5>/*
dma_bacnt3> + 3);
    class="li2cc#L1resua h2="Oxx_new.c#Lresua ref"2 dma_bacnt3> + 3);
ide_hwif_t5/a>2.54L144"} 135        , 
        {longL_a iiaers/iide/pdc202xx_ne>
        {longL>
void=_12xx_new.c#L80" id="L80" 1class18    5>;5E_ID_PROMISE_20268:
5a h2=54     mode 4, IORDY o2,  Pr21dexed_regdo/5>a href="5E_ID_PROMISE_20268:
5a h2=5 name="2ref="+                  2 (spe_p
fday="line" name="L=>
)
        PCI_DEVI5E_ID_PROMISE_20268:
5a h2m550e/pdp2ed" class="sref">speed    2     =5>pan>

et_index5E_ID_PROMISE_20268:
5a h2m55x_new"1line"voidiclass="srfcrriv_aexia>        {longL_aexiaers/iide/pdc202xx_ne>
        {longL>
void=_12xx_new.c#L80" id="L80" 1class18    5>"comment5E_ID_PROMISE_20268:
5a h2m55x_newmode 4, IORDY o2,  Pr21dexed_regdo/5s="sref">5alue);
1
fday="line" name="L=>
)
         UDMA mo5e 1 */
speed    2     =5*f="+code5outb" class="sref">outb<5a>(2a55href=L137" id="L137" clapan>
outb<5a>(2m55ine" "line" name="L=module_ iia>        {longLmodule_ iiaref">s="line" name=")
        {longL>
        ;5outb" class="sref">outb<5a>(2m55id="L"line" name="L=module_exia>        {longLmodule_exiaref">s="line" name=")
        {longL>
        a href="5outb" class="sref">outb<5a>(2m55id="L135        
 +MODULE_AUTHORass19, slass="line" nSecondary="srAndre He   ck, Frank Tiernaref="+code=dmal 135        

 +MODULE_DESCRIPTION5"> 145slass="line" nSecondary="sr CI"     < module for Promise2PDC a>68 and higheref="+code=dmal 135        outb<5a>(2i56x_newase" clafcrr> +MODULE_LICENSEline" name="L15MODULE_LICENSEref">slass="line" nSecondary="srGPLef="+code=dmal 135        
The original LXR software by t"> 35   http://sourceforge.net/projects/lxd">LXR     mailto:lxd@"drux.no">lxd@"drux.noe/pd.
lxd."drux.no kindly hosted by 35 http://www.redpill-"drpro.no">Redpill Ldrpro ASe/pd_bprovhrer ofnLdrux" id=ulneeeeand operlin=ns serrices since 1995.