linux/drivers/edac/e752x_edac.c
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70/30/fcd473802ab9a2e837aedcdb0505936b592a_3/0">L1" class="line" namon>L1">. .16/a>6spa  class="comment">/*6/spa >
L2" class="line" namon>L2">. .26/a>6spa  class="comment"> * Intel e752x Memory Controller kernel module6/spa >
L3" class="line" namon>L3">. .36/a>6spa  class="comment"> * (C) 2004 Linux Networx (http://lnxi.com)6/spa >
L4" class="line" namon>L4">. .46/a>6spa  class="comment"> * This file may be distributed under the terms of the6/spa >
L5" class="line" namon>L5">. .56/a>6spa  class="comment"> * GNU General Public License.6/spa >
L6" class="line" namon>L6">. .66/a>6spa  class="comment"> *6/spa >
L7" class="line" namon>L7">. .76/a>6spa  class="comment"> * Implement support for the e7520, E7525, e7320 and i3100 memory controllers.6/spa >
L8" class="line" namon>L8">. .86/a>6spa  class="comment"> *6/spa >
L9" class="line" namon>L9">. .96/a>6spa  class="comment"> * Datasheets:6/spa >
L10" class="line" namon>L10">. 11"
a>6spa  class="comment"> * n 2. http://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html6/spa >
L11" class="line" namon>L11">. 116/a>6spa  class="comment"> * n 2. ftp://download.intel.com/design/intarch/datashts/31345803.pdf6/spa >
L12" class="line" namon>L12">. 126/a>6spa  class="comment"> *6/spa >
L13" class="line" namon>L13">. 136/a>6spa  class="comment"> * Written by Tom Zimmerman6/spa >
L14" class="line" namon>L14">. 146/a>6spa  class="comment"> *6/spa >
L15" class="line" namon>L15">. 156/a>6spa  class="comment"> * Contributors:6/spa >
L16" class="line" namon>L16">. 166/a>6spa  class="comment"> * n 2. Thayne Harbaugh at realmsys.com (?)6/spa >
L17" class="line" namon>L17">. 176/a>6spa  class="comment"> *      Wang Zhenyu at intel.com6/spa >
L18" class="line" namon>L18">. 186/a>6spa  class="comment"> *      Dave Jiang at mvista.com6/spa >
L19" class="line" namon>L19">. 196/a>6spa  class="comment"> *6/spa >
L20" class="line" namon>L20">. 21"
a>6spa  class="comment"> */6/spa >
L21" class="line" namon>L21">. 216/a>
L22" class="line" namon>L22">. 226/a>#include <linux/module.h6/a>>
L23" class="line" namon>L23">. 236/a>#include <linux/init.h6/a>>
L24" class="line" namon>L24">. 246/a>#include <linux/pci.h6/a>>
L25" class="line" namon>L25">. 256/a>#include <linux/pci_ids.h6/a>>
L26" class="line" namon>L26">. 266/a>#include <linux/edac.h6/a>>
L27" class="line" namon>L27">. 276/a>#include "edac_core.h6/a>"
L28" class="line" namon>L28">. 286/a>
L29" class="line" namon>L29">. 296/a>#define.6a href="+code=E752X_REVISION" class="sref">E752X_REVISION6/a>  6spa  class="string">" Ver: 2.0.2"
L30" class="line" namon>L30">. 306/a>#define.6a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR6/a>    6spa  class="string">"e752x_edac"
L31" class="line" namon>L31">. 316/a>
L32" class="line" namon>L32">. 326/a>static int.6a href="+code=report_non_memory_errors" class="sref">report_non_memory_errors6/a>;
L33" class="line" namon>L33">. 336/a>static int.6a href="+code=force_func
	  _unhide" class="sref">force_func
	  _unhide6/a>;
L34" class="line" namon>L34">. 346/a>static int.6a href="+code=sysbus_parity" class="sref">sysbus_parity6/a> = -1;
L35" class="line" namon>L35">. 356/a>
L36" class="line" namon>L36">. 366/a>static struct.6a href="+code=edac_pci_ctl_info" class="sref">edac_pci_ctl_info6/a> *6a href="+code=e752x_pci" class="sref">e752x_pci6/a>;
L37" class="line" namon>L37">. 376/a>
L38" class="line" namon>L38">. 386/a>#define.6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=level" class="sref">level6/a>,.6a href="+code=fmt" class="sref">fmt6/a>,.6a href="+code=arg" class="sref">arg6/a>...) \
L39" class="line" namon>L39">. 396/a>        6a href="+code=edac_printk" class="sref">edac_printk6/a>(6a href="+code=level" class="sref">level6/a>,.6spa  class="string">"e752x",.6a href="+code=fmt" class="sref">fmt6/a>,.##arg)
L40" class="line" namon>L40">. 406/a>
L41" class="line" namon>L41">. 416/a>#define.6a href="+code=e752x_mc_printk" class="sref">e752x_mc_printk6/a>(6a href="+code=mci" class="sref">mci6/a>,.6a href="+code=level" class="sref">level6/a>,.6a href="+code=fmt" class="sref">fmt6/a>,.6a href="+code=arg" class="sref">arg6/a>...) \
L42" class="line" namon>L42">. 426/a>        6a href="+code=edac_mc_chipset_printk" class="sref">edac_mc_chipset_printk6/a>(6a href="+code=mci" class="sref">mci6/a>,.6a href="+code=level" class="sref">level6/a>,.6spa  class="string">"e752x",.6a href="+code=fmt" class="sref">fmt6/a>,.##arg)
L43" class="line" namon>L43">. 436/a>
L44" class="line" namon>L44">. 446/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7520_0" class="sref">PCI_DEVICE_ID_INTEL_7520_06/a>
L45" class="line" namon>L45">. 456/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7520_0" class="sref">PCI_DEVICE_ID_INTEL_7520_06/a>      0x3590
L46" class="line" namon>L46">. 466/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7520_0      */6/spa >
L47" class="line" namon>L47">. 476/a>
L48" class="line" namon>L48">. 486/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7520_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7520_1_ERR6/a>
L49" class="line" namon>L49">. 496/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7520_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7520_1_ERR6/a>  0x3591
L50" class="line" namon>L50">. 506/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7520_1_ERR  */6/spa >
L51" class="line" namon>L51">. 516/a>
L52" class="line" namon>L52">. 526/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7525_0" class="sref">PCI_DEVICE_ID_INTEL_7525_06/a>
L53" class="line" namon>L53">. 536/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7525_0" class="sref">PCI_DEVICE_ID_INTEL_7525_06/a>      0x359E
L54" class="line" namon>L54">. 546/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7525_0      */6/spa >
L55" class="line" namon>L55">. 556/a>
L56" class="line" namon>L56">. 566/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7525_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7525_1_ERR6/a>
L57" class="line" namon>L57">. 576/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7525_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7525_1_ERR6/a>  0x3593
L58" class="line" namon>L58">. 586/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7525_1_ERR  */6/spa >
L59" class="line" namon>L59">. 596/a>
L60" class="line" namon>L60">. 606/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7320_0" class="sref">PCI_DEVICE_ID_INTEL_7320_06/a>
L61" class="line" namon>L61">. 616/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7320_0" class="sref">PCI_DEVICE_ID_INTEL_7320_06/a>      0x3592
L62" class="line" namon>L62">. 626/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7320_0 */6/spa >
L63" class="line" namon>L63">. 636/a>
L64" class="line" namon>L64">. 646/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_7320_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7320_1_ERR6/a>
L65" class="line" namon>L65">. 656/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_7320_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7320_1_ERR6/a>  0x3593
L66" class="line" namon>L66">. 666/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_7320_1_ERR */6/spa >
L67" class="line" namon>L67">. 676/a>
L68" class="line" namon>L68">. 686/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_3100_0" class="sref">PCI_DEVICE_ID_INTEL_3100_06/a>
L69" class="line" namon>L69">. 696/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_3100_0" class="sref">PCI_DEVICE_ID_INTEL_3100_06/a>      0x35B0
L70" class="line" namon>L70">. 706/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_3100_0 */6/spa >
L71" class="line" namon>L71">. 716/a>
L72" class="line" namon>L72">. 726/a>#ifndef.6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>
L73" class="line" namon>L73">. 736/a>#define.6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>  0x35B1
L74" class="line" namon>L74">. 746/a>#endif                          6spa  class="comment">/* PCI_DEVICE_ID_INTEL_3100_1_ERR */6/spa >
L75" class="line" namon>L75">. 756/a>
L76" class="line" namon>L76">. 766/a>#define.6a href="+code=E752X_NR_CSROWS" class="sref">E752X_NR_CSROWS6/a>         8       6spa  class="comment">/* number of csrows */6/spa >
L77" class="line" namon>L77">. 776/a>
L78" class="line" namon>L78">. 786/a>6spa  class="comment">/* E752X register addresses - device 0 func
	   0 */6/spa >
L79" class="line" namon>L79">. 796/a>#define.6a href="+code=E752X_MCHSCRB" class="sref">E752X_MCHSCRB6/a>           0x52    6spa  class="comment">/* Memory Scrub register (16b) */6/spa >
L80" class="line" namon>L80">. 806/a>                                        6spa  class="comment">/*6/spa >
L81" class="line" namon>L81">. 816/a>6spa  class="comment">                                         * 6:5     Scrub Comple
	   Count6/spa >
L82" class="line" namon>L82">. 826/a>6spa  class="comment">                                         * 3:2     Scrub Rate (i3100 only)6/spa >
L83" class="line" namon>L83">. 836/a>6spa  class="comment">                                         *      01=fast 10=normal6/spa >
L84" class="line" namon>L84">. 846/a>6spa  class="comment">                                         * 1:0     Scrub Mode enable6/spa >
L85" class="line" namon>L85">. 856/a>6spa  class="comment">                                         *      00=off 10=on6/spa >
L86" class="line" namon>L86">. 866/a>6spa  class="comment">                                         */6/spa >
L87" class="line" namon>L87">. 876/a>#define.6a href="+code=E752X_DRB" class="sref">E752X_DRB6/a>               0x60    6spa  class="comment">/* DRAM row boundary register (8b) */6/spa >
L88" class="line" namon>L88">. 886/a>#define.6a href="+code=E752X_DRA" class="sref">E752X_DRA6/a>               0x70    6spa  class="comment">/* DRAM row attribute register (8b) */6/spa >
L89" class="line" namon>L89">. 896/a>                                        6spa  class="comment">/*6/spa >
L90" class="line" namon>L90">. 91"
a>6spa  class="comment">                                         * 31:30   Device width row 76/spa >
L91" class="line" namon>L91">. 916/a>6spa  class="comment">                                         *      01=x8 10=x4 11=x8 DDR26/spa >
L92" class="line" namon>L92">. 926/a>6spa  class="comment">                                         * 27:26   Device width row 66/spa >
L93" class="line" namon>L93">. 936/a>6spa  class="comment">                                         * 23:22   Device width row 56/spa >
L94" class="line" namon>L94">. 946/a>6spa  class="comment">                                         * 19:20   Device width row 46/spa >
L95" class="line" namon>L95">. 956/a>6spa  class="comment">                                         * 15:14   Device width row 36/spa >
L96" class="line" namon>L96">. 966/a>6spa  class="comment">                                         * 11:10   Device width row 26/spa >
L97" class="line" namon>L97">. 976/a>6spa  class="comment">                                         *  7:6    Device width row 16/spa >
L98" class="line" namon>L98">. 986/a>6spa  class="comment">                                         *  3:2    Device width row 06/spa >
L99" class="line" namon>L99">. 996/a>6spa  class="comment">                                         */6/spa >
L100" class="line" namon>L100">.1006/a>#define.6a href="+code=E752X_DRC" class="sref">E752X_DRC6/a>               0x7C    6spa  class="comment">/* DRAM controller mode reg (32b) */6/spa >
L101" class="line" namon>L101">.1016/a>                                        6spa  class="comment">/* FIXME:IS THIS RIGHT? */6/spa >
L102" class="line" namon>L102">.1026/a>                                        6spa  class="comment">/*6/spa >
L103" class="line" namon>L103">.1036/a>6spa  class="comment">                                         * 22    Number channels 0=1,1=26/spa >
L104" class="line" namon>L104">.1046/a>6spa  class="comment">                                         * 19:18 DRB Granularity 32/64MB6/spa >
L105" class="line" namon>L105">.1056/a>6spa  class="comment">                                         */6/spa >
L106" class="line" namon>L106">.1066/a>#define.6a href="+code=E752X_DRM" class="sref">E752X_DRM6/a>               0x80    6spa  class="comment">/* Dimm mapping register */6/spa >
L107" class="line" namon>L107">.1076/a>#define.6a href="+code=E752X_DDRCSR" class="sref">E752X_DDRCSR6/a>            0x9A    6spa  class="comment">/* DDR control and status reg (16b) */6/spa >
L108" class="line" namon>L108">.1086/a>                                        6spa  class="comment">/*6/spa >
L109" class="line" namon>L109">.1096/a>6spa  class="comment">                                         * 14:12 1 single A, 2 single B, 3 dual6/spa >
L110" class="line" namon>L110">.111"
a>6spa  class="comment">                                         */6/spa >
L111" class="line" namon>L111">.1116/a>#define.6a href="+code=E752X_TOLM" class="sref">E752X_TOLM6/a>              0xC4    6spa  class="comment">/* DRAM top of low memory reg (16b) */6/spa >
L112" class="line" namon>L112">.1126/a>#define.6a href="+code=E752X_REMAPBASE" class="sref">E752X_REMAPBASE6/a>         0xC6    6spa  class="comment">/* DRAM remap base address reg (16b) */6/spa >
L113" class="line" namon>L113">.1136/a>#define.6a href="+code=E752X_REMAPLIMIT" class="sref">E752X_REMAPLIMIT6/a>        0xC8    6spa  class="comment">/* DRAM remap limit address reg (16b) */6/spa >
L114" class="line" namon>L114">.1146/a>#define.6a href="+code=E752X_REMAPOFFSET" class="sref">E752X_REMAPOFFSET6/a>       0xCA    6spa  class="comment">/* DRAM remap limit offset reg (16b) */6/spa >
L115" class="line" namon>L115">.1156/a>
L116" class="line" namon>L116">.1166/a>6spa  class="comment">/* E752X register addresses - device 0 func
	   1 */6/spa >
L117" class="line" namon>L117">.1176/a>#define.6a href="+code=E752X_FERR_GLOBAL" class="sref">E752X_FERR_GLOBAL6/a>       0x40    6spa  class="comment">/* Global first error register (32b) */6/spa >
L118" class="line" namon>L118">.1186/a>#define.6a href="+code=E752X_NERR_GLOBAL" class="sref">E752X_NERR_GLOBAL6/a>       0x44    6spa  class="comment">/* Global next error register (32b) */6/spa >
L119" class="line" namon>L119">.1196/a>#define.6a href="+code=E752X_HI_FERR" class="sref">E752X_HI_FERR6/a>           0x50    6spa  class="comment">/* Hub interface first error reg (8b) */6/spa >
L120" class="line" namon>L120">.1206/a>#define.6a href="+code=E752X_HI_NERR" class="sref">E752X_HI_NERR6/a>           0x52    6spa  class="comment">/* Hub interface next error reg (8b) */6/spa >
L121" class="line" namon>L121">.1216/a>#define.6a href="+code=E752X_HI_ERRMASK" class="sref">E752X_HI_ERRMASK6/a>        0x54    6spa  class="comment">/* Hub interface error mask reg (8b) */6/spa >
L122" class="line" namon>L122">.1226/a>#define.6a href="+code=E752X_HI_SMICMD" class="sref">E752X_HI_SMICMD6/a>         0x5A    6spa  class="comment">/* Hub interface SMI command reg (8b) */6/spa >
L123" class="line" namon>L123">.1236/a>#define.6a href="+code=E752X_SYSBUS_FERR" class="sref">E752X_SYSBUS_FERR6/a>       0x60    6spa  class="comment">/* System buss first error reg (16b) */6/spa >
L124" class="line" namon>L124">.1246/a>#define.6a href="+code=E752X_SYSBUS_NERR" class="sref">E752X_SYSBUS_NERR6/a>       0x62    6spa  class="comment">/* System buss next error reg (16b) */6/spa >
L125" class="line" namon>L125">.1256/a>#define.6a href="+code=E752X_SYSBUS_ERRMASK" class="sref">E752X_SYSBUS_ERRMASK6/a>    0x64    6spa  class="comment">/* System buss error mask reg (16b) */6/spa >
L126" class="line" namon>L126">.1266/a>#define.6a href="+code=E752X_SYSBUS_SMICMD" class="sref">E752X_SYSBUS_SMICMD6/a>     0x6A    6spa  class="comment">/* System buss SMI command reg (16b) */6/spa >
L127" class="line" namon>L127">.1276/a>#define.6a href="+code=E752X_BUF_FERR" class="sref">E752X_BUF_FERR6/a>          0x70    6spa  class="comment">/* Memory buffer first error reg (8b) */6/spa >
L128" class="line" namon>L128">.1286/a>#define.6a href="+code=E752X_BUF_NERR" class="sref">E752X_BUF_NERR6/a>          0x72    6spa  class="comment">/* Memory buffer next error reg (8b) */6/spa >
L129" class="line" namon>L129">.1296/a>#define.6a href="+code=E752X_BUF_ERRMASK" class="sref">E752X_BUF_ERRMASK6/a>       0x74    6spa  class="comment">/* Memory buffer error mask reg (8b) */6/spa >
L130" class="line" namon>L130">.1306/a>#define.6a href="+code=E752X_BUF_SMICMD" class="sref">E752X_BUF_SMICMD6/a>        0x7A    6spa  class="comment">/* Memory buffer SMI cmd reg (8b) */6/spa >
L131" class="line" namon>L131">.1316/a>#define.6a href="+code=E752X_DRAM_FERR" class="sref">E752X_DRAM_FERR6/a>         0x80    6spa  class="comment">/* DRAM first error register (16b) */6/spa >
L132" class="line" namon>L132">.1326/a>#define.6a href="+code=E752X_DRAM_NERR" class="sref">E752X_DRAM_NERR6/a>         0x82    6spa  class="comment">/* DRAM next error register (16b) */6/spa >
L133" class="line" namon>L133">.1336/a>#define.6a href="+code=E752X_DRAM_ERRMASK" class="sref">E752X_DRAM_ERRMASK6/a>      0x84    6spa  class="comment">/* DRAM error mask register (8b) */6/spa >
L134" class="line" namon>L134">.1346/a>#define.6a href="+code=E752X_DRAM_SMICMD" class="sref">E752X_DRAM_SMICMD6/a>       0x8A    6spa  class="comment">/* DRAM SMI command register (8b) */6/spa >
L135" class="line" namon>L135">.1356/a>#define.6a href="+code=E752X_DRAM_RETR_ADD" class="sref">E752X_DRAM_RETR_ADD6/a>     0xAC    6spa  class="comment">/* DRAM Retry address register (32b) */6/spa >
L136" class="line" namon>L136">.1366/a>#define.6a href="+code=E752X_DRAM_SEC1_ADD" class="sref">E752X_DRAM_SEC1_ADD6/a>     0xA0    6spa  class="comment">/* DRAM first correctable memory */6/spa >
L137" class="line" namon>L137">.1376/a>                                        6spa  class="comment">/*     error address register (32b) */6/spa >
L138" class="line" namon>L138">.1386/a>                                        6spa  class="comment">/*6/spa >
L139" class="line" namon>L139">.1396/a>6spa  class="comment">                                         * 31    Reserved6/spa >
L140" class="line" namon>L140">.141"
a>6spa  class="comment">                                         * 30:2  CE address (64 byte block 34:66/spa >
L141" class="line" namon>L141">.1416/a>6spa  class="comment">                                         * 1     Reserved6/spa >
L142" class="line" namon>L142">.1426/a>6spa  class="comment">                                         * 0     HiLoCS6/spa >
L143" class="line" namon>L143">.1436/a>6spa  class="comment">                                         */6/spa >
L144" class="line" namon>L144">.1446/a>#define.6a href="+code=E752X_DRAM_SEC2_ADD" class="sref">E752X_DRAM_SEC2_ADD6/a>     0xC8    6spa  class="comment">/* DRAM first correctable memory */6/spa >
L145" class="line" namon>L145">.1456/a>                                        6spa  class="comment">/*     error address register (32b) */6/spa >
L146" class="line" namon>L146">.1466/a>                                        6spa  class="comment">/*6/spa >
L147" class="line" namon>L147">.1476/a>6spa  class="comment">                                         * 31    Reserved6/spa >
L148" class="line" namon>L148">.1486/a>6spa  class="comment">                                         * 30:2  CE address (64 byte block 34:6)6/spa >
L149" class="line" namon>L149">.1496/a>6spa  class="comment">                                         * 1     Reserved6/spa >
L150" class="line" namon>L150">.151"
a>6spa  class="comment">                                         * 0     HiLoCS6/spa >
L151" class="line" namon>L151">.1516/a>6spa  class="comment">                                         */6/spa >
L152" class="line" namon>L152">.1526/a>#define.6a href="+code=E752X_DRAM_DED_ADD" class="sref">E752X_DRAM_DED_ADD6/a>      0xA4    6spa  class="comment">/* DRAM first uncorrectable memory */6/spa >
L153" class="line" namon>L153">.1536/a>                                        6spa  class="comment">/*     error address register (32b) */6/spa >
L154" class="line" namon>L154">.1546/a>                                        6spa  class="comment">/*6/spa >
L155" class="line" namon>L155">.1556/a>6spa  class="comment">                                         * 31    Reserved6/spa >
L156" class="line" namon>L156">.1566/a>6spa  class="comment">                                         * 30:2  CE address (64 byte block 34:6)6/spa >
L157" class="line" namon>L157">.1576/a>6spa  class="comment">                                         * 1     Reserved6/spa >
L158" class="line" namon>L158">.1586/a>6spa  class="comment">                                         * 0     HiLoCS6/spa >
L159" class="line" namon>L159">.1596/a>6spa  class="comment">                                         */6/spa >
L160" class="line" namon>L160">.1606/a>#define.6a href="+code=E752X_DRAM_SCRB_ADD" class="sref">E752X_DRAM_SCRB_ADD6/a>     0xA8    6spa  class="comment">/* DRAM 1st uncorrectable scrub mem */6/spa >
L161" class="line" namon>L161">.1616/a>                                        6spa  class="comment">/*     error address register (32b) */6/spa >
L162" class="line" namon>L162">.1626/a>                                        6spa  class="comment">/*6/spa >
L163" class="line" namon>L163">.1636/a>6spa  class="comment">                                         * 31    Reserved6/spa >
L164" class="line" namon>L164">.1646/a>6spa  class="comment">                                         * 30:2  CE address (64 byte block 34:66/spa >
L165" class="line" namon>L165">.1656/a>6spa  class="comment">                                         * 1     Reserved6/spa >
L166" class="line" namon>L166">.1666/a>6spa  class="comment">                                         * 0     HiLoCS6/spa >
L167" class="line" namon>L167">.1676/a>6spa  class="comment">                                         */6/spa >
L168" class="line" namon>L168">.1686/a>#define.6a href="+code=E752X_DRAM_SEC1_SYNDROME" class="sref">E752X_DRAM_SEC1_SYNDROME6/a> 0xC4   6spa  class="comment">/* DRAM first correctable memory */6/spa >
L169" class="line" namon>L169">.1696/a>                                        6spa  class="comment">/*     error syndrome register (16b) */6/spa >
L170" class="line" namon>L170">.1706/a>#define.6a href="+code=E752X_DRAM_SEC2_SYNDROME" class="sref">E752X_DRAM_SEC2_SYNDROME6/a> 0xC6   6spa  class="comment">/* DRAM second correctable memory */6/spa >
L171" class="line" namon>L171">.1716/a>                                        6spa  class="comment">/*     error syndrome register (16b) */6/spa >
L172" class="line" namon>L172">.1726/a>#define.6a href="+code=E752X_DEVPRES1" class="sref">E752X_DEVPRES16/a>          0xF4    6spa  class="comment">/* Device Present 1 register (8b) */6/spa >
L173" class="line" namon>L173">.1736/a>
L174" class="line" namon>L174">.1746/a>6spa  class="comment">/* 3100 IMCH specific register addresses - device 0 func
	   1 */6/spa >
L175" class="line" namon>L175">.1756/a>#define.6a href="+code=I3100_NSI_FERR" class="sref">I3100_NSI_FERR6/a>          0x48    6spa  class="comment">/* NSI first error reg (32b) */6/spa >
L176" class="line" namon>L176">.1766/a>#define.6a href="+code=I3100_NSI_NERR" class="sref">I3100_NSI_NERR6/a>          0x4C    6spa  class="comment">/* NSI next error reg (32b) */6/spa >
L177" class="line" namon>L177">.1776/a>#define.6a href="+code=I3100_NSI_SMICMD" class="sref">I3100_NSI_SMICMD6/a>        0x54    6spa  class="comment">/* NSI SMI command register (32b) */6/spa >
L178" class="line" namon>L178">.1786/a>#define.6a href="+code=I3100_NSI_EMASK" class="sref">I3100_NSI_EMASK6/a>         0x90    6spa  class="comment">/* NSI error mask register (32b) */6/spa >
L179" class="line" namon>L179">.1796/a>
L180" class="line" namon>L180">.181"
a>6spa  class="comment">/* ICH5R register addresses - device 30 func
	   0 */6/spa >
L181" class="line" namon>L181">.1816/a>#define.6a href="+code=ICH5R_PCI_STAT" class="sref">ICH5R_PCI_STAT6/a>          0x06    6spa  class="comment">/* PCI status register (16b) */6/spa >
L182" class="line" namon>L182">.1826/a>#define.6a href="+code=ICH5R_PCI_2ND_STAT" class="sref">ICH5R_PCI_2ND_STAT6/a>      0x1E    6spa  class="comment">/* PCI status secondary reg (16b) */6/spa >
L183" class="line" namon>L183">.1836/a>#define.6a href="+code=ICH5R_PCI_BRIDGE_CTL" class="sref">ICH5R_PCI_BRIDGE_CTL6/a>    0x3E    6spa  class="comment">/* PCI bridge control register (16b) */6/spa >
L184" class="line" namon>L184">.1846/a>
L185" class="line" namon>L185">.1856/a>enum.6a href="+code=e752x_chips" class="sref">e752x_chips6/a> {
L186" class="line" namon>L186">.1866/a>        6a href="+code=E7520" class="sref">E75206/a> = 0,
L187" class="line" namon>L187">.1876/a>        6a href="+code=E7525" class="sref">E75256/a> = 1,
L188" class="line" namon>L188">.1886/a>        6a href="+code=E7320" class="sref">E73206/a> = 2,
L189" class="line" namon>L189">.1896/a>        6a href="+code=I3100" class="sref">I31006/a> = 3
L190" class="line" namon>L190">.191"
a>};
L191" class="line" namon>L191">.1916/a>
L192" class="line" namon>L192">.1926/a>6spa  class="comment">/*6/spa >
L193" class="line" namon>L193">.1936/a>6spa  class="comment"> * Those chips Support single-rank and dual-rank memories only.6/spa >
L194" class="line" namon>L194">.1946/a>6spa  class="comment"> *6/spa >
L195" class="line" namon>L195">.1956/a>6spa  class="comment"> * On e752x chips, the odd rows are present only on dual-rank memories.6/spa >
L196" class="line" namon>L196">.1966/a>6spa  class="comment"> * Dividing the rank by two will provide the dimm#6/spa >
L197" class="line" namon>L197">.1976/a>6spa  class="comment"> *6/spa >
L198" class="line" namon>L198">.1986/a>6spa  class="comment"> * i3100 MC has a different mapping: it supports only 4 ranks.6/spa >
L199" class="line" namon>L199">.1996/a>6spa  class="comment"> *6/spa >
L200" class="line" namon>L200">.201"
a>6spa  class="comment"> * The mapping is (from 1 to n):6/spa >
L201" class="line" namon>L201">.2016/a>6spa  class="comment"> *      slot       single-ranked        double-ranked6/spa >
L202" class="line" namon>L202">.2026/a>6spa  class="comment"> *      dimm #1 -> rank #4              NA6/spa >
L203" class="line" namon>L203">.2036/a>6spa  class="comment"> *      dimm #2 -> rank #3              NA6/spa >
L204" class="line" namon>L204">.2046/a>6spa  class="comment"> *      dimm #3 -> rank #2              Ranks 2 and 36/spa >
L205" class="line" namon>L205">.2056/a>6spa  class="comment"> *      dimm #4 -> rank $1              Ranks 1 and 46/spa >
L206" class="line" namon>L206">.2066/a>6spa  class="comment"> *6/spa >
L207" class="line" namon>L207">.2076/a>6spa  class="comment"> * FIXME: The current mapping for i3100 considers that it supports up to 86/spa >
L208" class="line" namon>L208">.2086/a>6spa  class="comment"> *        ranks/chanel, but datasheet says that the MC supports only 4 ranks.6/spa >
L209" class="line" namon>L209">.2096/a>6spa  class="comment"> */6/spa >
L210" class="line" namon>L210">.2106/a>
L211" class="line" namon>L211">.2116/a>struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> {
L212" class="line" namon>L212">.2126/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=bridge_ck" class="sref">bridge_ck6/a>;
L213" class="line" namon>L213">.2136/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev_d0f0" class="sref">dev_d0f06/a>;
L214" class="line" namon>L214">.2146/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>;
L215" class="line" namon>L215">.2156/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=tolm" class="sref">tolm6/a>;
L216" class="line" namon>L216">.2166/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=remapbase" class="sref">remapbase6/a>;
L217" class="line" namon>L217">.2176/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=remaplimit" class="sref">remaplimit6/a>;
L218" class="line" namon>L218">.2186/a>        int.6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a>;
L219" class="line" namon>L219">.2196/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=map" class="sref">map6/a>[8];
L220" class="line" namon>L220">.2206/a>        int.6a href="+code=map_type" class="sref">map_type6/a>;
L221" class="line" namon>L221">.2216/a>        const struct.6a href="+code=e752x_dev_info" class="sref">e752x_dev_info6/a> *6a href="+code=dev_info" class="sref">dev_info6/a>;
L222" class="line" namon>L222">.2226/a>};
L223" class="line" namon>L223">.2236/a>
L224" class="line" namon>L224">.2246/a>struct.6a href="+code=e752x_dev_info" class="sref">e752x_dev_info6/a> {
L225" class="line" namon>L225">.2256/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=err_dev" class="sref">err_dev6/a>;
L226" class="line" namon>L226">.2266/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=ctl_dev" class="sref">ctl_dev6/a>;
L227" class="line" namon>L227">.2276/a>        const char *6a href="+code=ctl_namo" class="sref">ctl_namo6/a>;
L228" class="line" namon>L228">.2286/a>};
L229" class="line" namon>L229">.2296/a>
L230" class="line" namon>L230">.2306/a>struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> {
L231" class="line" namon>L231">.2316/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=ferr_global" class="sref">ferr_global6/a>;
L232" class="line" namon>L232">.2326/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=nerr_global" class="sref">nerr_global6/a>;
L233" class="line" namon>L233">.2336/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a>;   6spa  class="comment">/* 3100 only */6/spa >
L234" class="line" namon>L234">.2346/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a>;   6spa  class="comment">/* 3100 only */6/spa >
L235" class="line" namon>L235">.2356/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=hi_ferr" class="sref">hi_ferr6/a>;     6spa  class="comment">/* all but 3100 */6/spa >
L236" class="line" namon>L236">.2366/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=hi_nerr" class="sref">hi_nerr6/a>;     6spa  class="comment">/* all but 3100 */6/spa >
L237" class="line" namon>L237">.2376/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=sysbus_ferr" class="sref">sysbus_ferr6/a>;
L238" class="line" namon>L238">.2386/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=sysbus_nerr" class="sref">sysbus_nerr6/a>;
L239" class="line" namon>L239">.2396/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=buf_ferr" class="sref">buf_ferr6/a>;
L240" class="line" namon>L240">.2406/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=buf_nerr" class="sref">buf_nerr6/a>;
L241" class="line" namon>L241">.2416/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=dram_ferr" class="sref">dram_ferr6/a>;
L242" class="line" namon>L242">.2426/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=dram_nerr" class="sref">dram_nerr6/a>;
L243" class="line" namon>L243">.2436/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dram_sec1_add" class="sref">dram_sec1_add6/a>;
L244" class="line" namon>L244">.2446/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dram_sec2_add" class="sref">dram_sec2_add6/a>;
L245" class="line" namon>L245">.2456/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=dram_sec1_syndrome" class="sref">dram_sec1_syndrome6/a>;
L246" class="line" namon>L246">.2466/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=dram_sec2_syndrome" class="sref">dram_sec2_syndrome6/a>;
L247" class="line" namon>L247">.2476/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dram_ded_add" class="sref">dram_ded_add6/a>;
L248" class="line" namon>L248">.2486/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dram_scrb_add" class="sref">dram_scrb_add6/a>;
L249" class="line" namon>L249">.2496/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dram_retr_add" class="sref">dram_retr_add6/a>;
L250" class="line" namon>L250">.251"
a>};
L251" class="line" namon>L251">.2516/a>
L252" class="line" namon>L252">.2526/a>static const struct.6a href="+code=e752x_dev_info" class="sref">e752x_dev_info6/a> 6a href="+code=e752x_devs" class="sref">e752x_devs6/a>[] = {
L253" class="line" namon>L253">.2536/a>        [6a href="+code=E7520" class="sref">E75206/a>] = {
L254" class="line" namon>L254">.2546/a>                .6a href="+code=err_dev" class="sref">err_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7520_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7520_1_ERR6/a>,
L255" class="line" namon>L255">.2556/a>                .6a href="+code=ctl_dev" class="sref">ctl_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7520_0" class="sref">PCI_DEVICE_ID_INTEL_7520_06/a>,
L256" class="line" namon>L256">.2566/a>                .6a href="+code=ctl_namo" class="sref">ctl_namo6/a> = 6spa  class="string">"E7520"6/spa >},
L257" class="line" namon>L257">.2576/a>        [6a href="+code=E7525" class="sref">E75256/a>] = {
L258" class="line" namon>L258">.2586/a>                .6a href="+code=err_dev" class="sref">err_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7525_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7525_1_ERR6/a>,
L259" class="line" namon>L259">.2596/a>                .6a href="+code=ctl_dev" class="sref">ctl_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7525_0" class="sref">PCI_DEVICE_ID_INTEL_7525_06/a>,
L260" class="line" namon>L260">.2606/a>                .6a href="+code=ctl_namo" class="sref">ctl_namo6/a> = 6spa  class="string">"E7525"6/spa >},
L261" class="line" namon>L261">.2616/a>        [6a href="+code=E7320" class="sref">E73206/a>] = {
L262" class="line" namon>L262">.2626/a>                .6a href="+code=err_dev" class="sref">err_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7320_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_7320_1_ERR6/a>,
L263" class="line" namon>L263">.2636/a>                .6a href="+code=ctl_dev" class="sref">ctl_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_7320_0" class="sref">PCI_DEVICE_ID_INTEL_7320_06/a>,
L264" class="line" namon>L264">.2646/a>                .6a href="+code=ctl_namo" class="sref">ctl_namo6/a> = 6spa  class="string">"E7320"6/spa >},
L265" class="line" namon>L265">.2656/a>        [6a href="+code=I3100" class="sref">I31006/a>] = {
L266" class="line" namon>L266">.2666/a>                .6a href="+code=err_dev" class="sref">err_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>,
L267" class="line" namon>L267">.2676/a>                .6a href="+code=ctl_dev" class="sref">ctl_dev6/a> = 6a href="+code=PCI_DEVICE_ID_INTEL_3100_0" class="sref">PCI_DEVICE_ID_INTEL_3100_06/a>,
L268" class="line" namon>L268">.2686/a>                .6a href="+code=ctl_namo" class="sref">ctl_namo6/a> = 6spa  class="string">"3100"6/spa >},
L269" class="line" namon>L269">.2696/a>};
L270" class="line" namon>L270">.2706/a>
L271" class="line" namon>L271">.2716/a>6spa  class="comment">/* Valid scrub rates for the e752x/3100 hardware memory scrubber. We6/spa >
L272" class="line" namon>L272">.2726/a>6spa  class="comment"> * map the scrubbing bandwidth to a hardware register value. The 'set'6/spa >
L273" class="line" namon>L273">.2736/a>6spa  class="comment"> * operat	   finds the 'matching or higher value'.  Note that scrubbing6/spa >
L274" class="line" namon>L274">.2746/a>6spa  class="comment"> * on the e752x ca  only be enabled/disabled.  The 3100 supports6/spa >
L275" class="line" namon>L275">.2756/a>6spa  class="comment"> * a normal and fast mode.6/spa >
L276" class="line" namon>L276">.2766/a>6spa  class="comment"> */6/spa >
L277" class="line" namon>L277">.2776/a>
L278" class="line" namon>L278">.2786/a>#define.6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a> 0xFFFFFFFF
L279" class="line" namon>L279">.2796/a>
L280" class="line" namon>L280">.2806/a>struct.6a href="+code=scrubrate" class="sref">scrubrate6/a> {
L281" class="line" namon>L281">.2816/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=bandwidth" class="sref">bandwidth6/a>;  6spa  class="comment">/* bandwidth consumed by scrubbing in bytes/sec */6/spa >
L282" class="line" namon>L282">.2826/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=scrubval" class="sref">scrubval6/a>;   6spa  class="comment">/* register value for scrub rate */6/spa >
L283" class="line" namon>L283">.2836/a>};
L284" class="line" namon>L284">.2846/a>
L285" class="line" namon>L285">.2856/a>6spa  class="comment">/* Rate below assumes samo performance as i3100 using PC3200 DDR2 in6/spa >
L286" class="line" namon>L286">.2866/a>6spa  class="comment"> * normal mode.  e752x bridges don't support choosing normal or fast mode,6/spa >
L287" class="line" namon>L287">.2876/a>6spa  class="comment"> * so the scrubbing bandwidth value isn't all that important - scrubbing is6/spa >
L288" class="line" namon>L288">.2886/a>6spa  class="comment"> * either on or off.6/spa >
L289" class="line" namon>L289">.2896/a>6spa  class="comment"> */6/spa >
L290" class="line" namon>L290">.2906/a>static const struct.6a href="+code=scrubrate" class="sref">scrubrate6/a> 6a href="+code=scrubrates_e752x" class="sref">scrubrates_e752x6/a>[] = {
L291" class="line" namon>L291">.2916/a>        {0,             0x00},  6spa  class="comment">/* Scrubbing Off */6/spa >
L292" class="line" namon>L292">.2926/a>        {500000,        0x02},  6spa  class="comment">/* Scrubbing On */6/spa >
L293" class="line" namon>L293">.2936/a>        {6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>,    0x00}   6spa  class="comment">/* End of Table */6/spa >
L294" class="line" namon>L294">.2946/a>};
L295" class="line" namon>L295">.2956/a>
L296" class="line" namon>L296">.2966/a>6spa  class="comment">/* Fast mode: 2 GByte PC3200 DDR2 scrubbed in 33s = 63161283 bytes/s6/spa >
L297" class="line" namon>L297">.2976/a>6spa  class="comment"> * Normal mode:.125 (32000 /.256) times slower tha  fast mode.6/spa >
L298" class="line" namon>L298">.2986/a>6spa  class="comment"> */6/spa >
L299" class="line" namon>L299">.2996/a>static const struct.6a href="+code=scrubrate" class="sref">scrubrate6/a> 6a href="+code=scrubrates_i3100" class="sref">scrubrates_i31006/a>[] = {
L300" class="line" namon>L300">.3006/a>        {0,             0x00},  6spa  class="comment">/* Scrubbing Off */6/spa >
L301" class="line" namon>L301">.3016/a>        {500000,        0x0a},  6spa  class="comment">/* Normal mode - 32k clocks */6/spa >
L302" class="line" namon>L302">.3026/a>        {62500000,      0x06},  6spa  class="comment">/* Fast mode - 256 clocks */6/spa >
L303" class="line" namon>L303">.3036/a>        {6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>,    0x00}   6spa  class="comment">/* End of Table */6/spa >
L304" class="line" namon>L304">.3046/a>};
L305" class="line" namon>L305">.3056/a>
L306" class="line" namon>L306">.3066/a>static unsigned long 6a href="+code=ctl_page_to_phys" class="sref">ctl_page_to_phys6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>,
L307" class="line" namon>L307">.3076/a>                                unsigned long 6a href="+code=page" class="sref">page6/a>)
L308" class="line" namon>L308">.3086/a>{
L309" class="line" namon>L309">.3096/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=remap" class="sref">remap6/a>;
L310" class="line" namon>L310">.3106/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L311" class="line" namon>L311">.3116/a>
L312" class="line" namon>L312">.3126/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L313" class="line" namon>L313">.3136/a>
L314" class="line" namon>L314">.3146/a>        if (6a href="+code=page" class="sref">page6/a> < 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=tolm" class="sref">tolm6/a>)
L315" class="line" namon>L315">.3156/a>                return 6a href="+code=page" class="sref">page6/a>;
L316" class="line" namon>L316">.3166/a>
L317" class="line" namon>L317">.3176/a>        if ((6a href="+code=page" class="sref">page6/a> >= 0x100000) && (6a href="+code=page" class="sref">page6/a> < 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remapbase" class="sref">remapbase6/a>))
L318" class="line" namon>L318">.3186/a>                return 6a href="+code=page" class="sref">page6/a>;
L319" class="line" namon>L319">.3196/a>
L320" class="line" namon>L320">.3206/a>        6a href="+code=remap" class="sref">remap6/a> = (6a href="+code=page" class="sref">page6/a> - 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=tolm" class="sref">tolm6/a>) + 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remapbase" class="sref">remapbase6/a>;
L321" class="line" namon>L321">.3216/a>
L322" class="line" namon>L322">.3226/a>        if (6a href="+code=remap" class="sref">remap6/a> < 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remaplimit" class="sref">remaplimit6/a>)
L323" class="line" namon>L323">.3236/a>                return 6a href="+code=remap" class="sref">remap6/a>;
L324" class="line" namon>L324">.3246/a>
L325" class="line" namon>L325">.3256/a>        6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_ERR" class="sref">KERN_ERR6/a>, 6spa  class="string">"Invalid page %lx - out of range\n"6/spa >, 6a href="+code=page" class="sref">page6/a>);
L326" class="line" namon>L326">.3266/a>        return 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=tolm" class="sref">tolm6/a> - 1;
L327" class="line" namon>L327">.3276/a>}
L328" class="line" namon>L328">.3286/a>
L329" class="line" namon>L329">.3296/a>static void 6a href="+code=do_process_ce" class="sref">do_process_ce6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error_one" class="sref">error_one6/a>,
L330" class="line" namon>L330">.3306/a>                        6a href="+code=u32" class="sref">u326/a> 6a href="+code=sec1_add" class="sref">sec1_add6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=sec1_syndrome" class="sref">sec1_syndrome6/a>)
L331" class="line" namon>L331">.3316/a>{
L332" class="line" namon>L332">.3326/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=page" class="sref">page6/a>;
L333" class="line" namon>L333">.3336/a>        int.6a href="+code=row" class="sref">row6/a>;
L334" class="line" namon>L334">.3346/a>        int.6a href="+code=channel" class="sref">channel6/a>;
L335" class="line" namon>L335">.3356/a>        int.6a href="+code=i" class="sref">i6/a>;
L336" class="line" namon>L336">.3366/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L337" class="line" namon>L337">.3376/a>
L338" class="line" namon>L338">.3386/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L339" class="line" namon>L339">.3396/a>
L340" class="line" namon>L340">.3406/a>        6spa  class="comment">/* convert the addr to 4k page */6/spa >
L341" class="line" namon>L341">.3416/a>        6a href="+code=page" class="sref">page6/a> = 6a href="+code=sec1_add" class="sref">sec1_add6/a> >> (6a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT6/a> - 4);
L342" class="line" namon>L342">.3426/a>
L343" class="line" namon>L343">.3436/a>        6spa  class="comment">/* FIXME - check for -1 */6/spa >
L344" class="line" namon>L344">.3446/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a>) {
L345" class="line" namon>L345">.3456/a>                6spa  class="comment">/* chip select.are bits 14 & 13 */6/spa >
L346" class="line" namon>L346">.3466/a>                6a href="+code=row" class="sref">row6/a> = ((6a href="+code=page" class="sref">page6/a> >> 1) & 3);
L347" class="line" namon>L347">.3476/a>                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>,
L348" class="line" namon>L348">.3486/a>                        6spa  class="string">"Test row %d Table %d %d %d %d %d %d %d %d\n"6/spa >, 6a href="+code=row" class="sref">row6/a>,
L349" class="line" namon>L349">.3496/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[0], 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[1], 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[2], 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[3],
L350" class="line" namon>L350">.3506/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[4], 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[5], 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6],
L351" class="line" namon>L351">.3516/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[7]);
L352" class="line" namon>L352">.3526/a>
L353" class="line" namon>L353">.3536/a>                6spa  class="comment">/* test for channel remapping */6/spa >
L354" class="line" namon>L354">.3546/a>                for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 8; 6a href="+code=i" class="sref">i6/a>++) {
L355" class="line" namon>L355">.3556/a>                        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6a href="+code=i" class="sref">i6/a>] == 6a href="+code=row" class="sref">row6/a>)
L356" class="line" namon>L356">.3566/a>                                break;
L357" class="line" namon>L357">.3576/a>                }
L358" class="line" namon>L358">.3586/a>
L359" class="line" namon>L359">.3596/a>                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"Test computed row %d\n"6/spa >, 6a href="+code=i" class="sref">i6/a>);
L360" class="line" namon>L360">.3606/a>
L361" class="line" namon>L361">.3616/a>                if (6a href="+code=i" class="sref">i6/a> < 8)
L362" class="line" namon>L362">.3626/a>                        6a href="+code=row" class="sref">row6/a> = 6a href="+code=i" class="sref">i6/a>;
L363" class="line" namon>L363">.3636/a>                else
L364" class="line" namon>L364">.3646/a>                        6a href="+code=e752x_mc_printk" class="sref">e752x_mc_printk6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>,
L365" class="line" namon>L365">.3656/a>                                        6spa  class="string">"row %d not found in remap table\n"6/spa >,
L366" class="line" namon>L366">.3666/a>                                        6a href="+code=row" class="sref">row6/a>);
L367" class="line" namon>L367">.3676/a>        } else
L368" class="line" namon>L368">.3686/a>                6a href="+code=row" class="sref">row6/a> = 6a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=page" class="sref">page6/a>);
L369" class="line" namon>L369">.3696/a>
L370" class="line" namon>L370">.3706/a>        6spa  class="comment">/* 0 = channel A, 1 = channel B */6/spa >
L371" class="line" namon>L371">.3716/a>        6a href="+code=channel" class="sref">channel6/a> = !(6a href="+code=error_one" class="sref">error_one6/a> & 1);
L372" class="line" namon>L372">.3726/a>
L373" class="line" namon>L373">.3736/a>        6spa  class="comment">/* e752x mc reads 34:6 of the DRAM linear address */6/spa >
L374" class="line" namon>L374">.3746/a>        6a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error6/a>(6a href="+code=HW_EVENT_ERR_CORRECTED" class="sref">HW_EVENT_ERR_CORRECTED6/a>, 6a href="+code=mci" class="sref">mci6/a>, 1,
L375" class="line" namon>L375">.3756/a>                             6a href="+code=page" class="sref">page6/a>, 6a href="+code=offset_in_page" class="sref">offset_in_page6/a>(6a href="+code=sec1_add" class="sref">sec1_add6/a> << 4), 6a href="+code=sec1_syndrome" class="sref">sec1_syndrome6/a>,
L376" class="line" namon>L376">.3766/a>                             6a href="+code=row" class="sref">row6/a>, 6a href="+code=channel" class="sref">channel6/a>, -1,
L377" class="line" namon>L377">.3776/a>                             6spa  class="string">"e752x CE"6/spa >, 6spa  class="string">""6/spa >);
L378" class="line" namon>L378">.3786/a>}
L379" class="line" namon>L379">.3796/a>
L380" class="line" namon>L380">.3806/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=process_ce" class="sref">process_ce6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error_one" class="sref">error_one6/a>,
L381" class="line" namon>L381">.3816/a>                        6a href="+code=u32" class="sref">u326/a> 6a href="+code=sec1_add" class="sref">sec1_add6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=sec1_syndrome" class="sref">sec1_syndrome6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L382" class="line" namon>L382">.3826/a>                        int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L383" class="line" namon>L383">.3836/a>{
L384" class="line" namon>L384">.3846/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L385" class="line" namon>L385">.3856/a>
L386" class="line" namon>L386">.3866/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L387" class="line" namon>L387">.3876/a>                6a href="+code=do_process_ce" class="sref">do_process_ce6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=sec1_add" class="sref">sec1_add6/a>, 6a href="+code=sec1_syndrome" class="sref">sec1_syndrome6/a>);
L388" class="line" namon>L388">.3886/a>}
L389" class="line" namon>L389">.3896/a>
L390" class="line" namon>L390">.3906/a>static void 6a href="+code=do_process_ue" class="sref">do_process_ue6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error_one" class="sref">error_one6/a>,
L391" class="line" namon>L391">.3916/a>                        6a href="+code=u32" class="sref">u326/a> 6a href="+code=ded_add" class="sref">ded_add6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=scrb_add" class="sref">scrb_add6/a>)
L392" class="line" namon>L392">.3926/a>{
L393" class="line" namon>L393">.3936/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=error_2b" class="sref">error_2b6/a>, 6a href="+code=block_page" class="sref">block_page6/a>;
L394" class="line" namon>L394">.3946/a>        int.6a href="+code=row" class="sref">row6/a>;
L395" class="line" namon>L395">.3956/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L396" class="line" namon>L396">.3966/a>
L397" class="line" namon>L397">.3976/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L398" class="line" namon>L398">.3986/a>
L399" class="line" namon>L399">.3996/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x0202) {
L400" class="line" namon>L400">.4006/a>                6a href="+code=error_2b" class="sref">error_2b6/a> = 6a href="+code=ded_add" class="sref">ded_add6/a>;
L401" class="line" namon>L401">.4016/a>
L402" class="line" namon>L402">.4026/a>                6spa  class="comment">/* convert to 4k address */6/spa >
L403" class="line" namon>L403">.4036/a>                6a href="+code=block_page" class="sref">block_page6/a> = 6a href="+code=error_2b" class="sref">error_2b6/a> >> (6a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT6/a> - 4);
L404" class="line" namon>L404">.4046/a>
L405" class="line" namon>L405">.4056/a>                6a href="+code=row" class="sref">row6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a> ?
L406" class="line" namon>L406">.4066/a>                6spa  class="comment">/* chip select.are bits 14 & 13 */6/spa >
L407" class="line" namon>L407">.4076/a>                        ((6a href="+code=block_page" class="sref">block_page6/a> >> 1) & 3) :
L408" class="line" namon>L408">.4086/a>                        6a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=block_page" class="sref">block_page6/a>);
L409" class="line" namon>L409">.4096/a>
L410" class="line" namon>L410">.4106/a>                6spa  class="comment">/* e752x mc reads 34:6 of the DRAM linear address */6/spa >
L411" class="line" namon>L411">.4116/a>                6a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error6/a>(6a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED6/a>, 6a href="+code=mci" class="sref">mci6/a>, 1,
L412" class="line" namon>L412">.4126/a>                                        6a href="+code=block_page" class="sref">block_page6/a>,
L413" class="line" namon>L413">.4136/a>                                        6a href="+code=offset_in_page" class="sref">offset_in_page6/a>(6a href="+code=error_2b" class="sref">error_2b6/a> << 4), 0,
L414" class="line" namon>L414">.4146/a>                                         6a href="+code=row" class="sref">row6/a>, -1, -1,
L415" class="line" namon>L415">.4156/a>                                        6spa  class="string">"e752x UE from Read"6/spa >, 6spa  class="string">""6/spa >);
L416" class="line" namon>L416">.4166/a>
L417" class="line" namon>L417">.4176/a>        }
L418" class="line" namon>L418">.4186/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x0404) {
L419" class="line" namon>L419">.4196/a>                6a href="+code=error_2b" class="sref">error_2b6/a> = 6a href="+code=scrb_add" class="sref">scrb_add6/a>;
L420" class="line" namon>L420">.4206/a>
L421" class="line" namon>L421">.4216/a>                6spa  class="comment">/* convert to 4k address */6/spa >
L422" class="line" namon>L422">.4226/a>                6a href="+code=block_page" class="sref">block_page6/a> = 6a href="+code=error_2b" class="sref">error_2b6/a> >> (6a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT6/a> - 4);
L423" class="line" namon>L423">.4236/a>
L424" class="line" namon>L424">.4246/a>                6a href="+code=row" class="sref">row6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a> ?
L425" class="line" namon>L425">.4256/a>                6spa  class="comment">/* chip select.are bits 14 & 13 */6/spa >
L426" class="line" namon>L426">.4266/a>                        ((6a href="+code=block_page" class="sref">block_page6/a> >> 1) & 3) :
L427" class="line" namon>L427">.4276/a>                        6a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=block_page" class="sref">block_page6/a>);
L428" class="line" namon>L428">.4286/a>
L429" class="line" namon>L429">.4296/a>                6spa  class="comment">/* e752x mc reads 34:6 of the DRAM linear address */6/spa >
L430" class="line" namon>L430">.4306/a>                6a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error6/a>(6a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED6/a>, 6a href="+code=mci" class="sref">mci6/a>, 1,
L431" class="line" namon>L431">.4316/a>                                        6a href="+code=block_page" class="sref">block_page6/a>,
L432" class="line" namon>L432">.4326/a>                                        6a href="+code=offset_in_page" class="sref">offset_in_page6/a>(6a href="+code=error_2b" class="sref">error_2b6/a> << 4), 0,
L433" class="line" namon>L433">.4336/a>                                        6a href="+code=row" class="sref">row6/a>, -1, -1,
L434" class="line" namon>L434">.4346/a>                                        6spa  class="string">"e752x UE from Scruber"6/spa >, 6spa  class="string">""6/spa >);
L435" class="line" namon>L435">.4356/a>        }
L436" class="line" namon>L436">.4366/a>}
L437" class="line" namon>L437">.4376/a>
L438" class="line" namon>L438">.4386/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=process_ue" class="sref">process_ue6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error_one" class="sref">error_one6/a>,
L439" class="line" namon>L439">.4396/a>                        6a href="+code=u32" class="sref">u326/a> 6a href="+code=ded_add" class="sref">ded_add6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=scrb_add" class="sref">scrb_add6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L440" class="line" namon>L440">.4406/a>                        int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L441" class="line" namon>L441">.4416/a>{
L442" class="line" namon>L442">.4426/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L443" class="line" namon>L443">.4436/a>
L444" class="line" namon>L444">.4446/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L445" class="line" namon>L445">.4456/a>                6a href="+code=do_process_ue" class="sref">do_process_ue6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=ded_add" class="sref">ded_add6/a>, 6a href="+code=scrb_add" class="sref">scrb_add6/a>);
L446" class="line" namon>L446">.4466/a>}
L447" class="line" namon>L447">.4476/a>
L448" class="line" namon>L448">.4486/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=process_ue_no_info_wr" class="sref">process_ue_no_info_wr6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>,
L449" class="line" namon>L449">.4496/a>                                         int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L450" class="line" namon>L450">.4506/a>{
L451" class="line" namon>L451">.4516/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L452" class="line" namon>L452">.4526/a>
L453" class="line" namon>L453">.4536/a>        if (!6a href="+code=handle_error" class="sref">handle_error6/a>)
L454" class="line" namon>L454">.4546/a>                return;
L455" class="line" namon>L455">.4556/a>
L456" class="line" namon>L456">.4566/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L457" class="line" namon>L457">.4576/a>        6a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error6/a>(6a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED6/a>, 6a href="+code=mci" class="sref">mci6/a>, 1, 0, 0, 0,
L458" class="line" namon>L458">.4586/a>                             -1, -1, -1,
L459" class="line" namon>L459">.4596/a>                             6spa  class="string">"e752x UE log memory write"6/spa >, 6spa  class="string">""6/spa >);
L460" class="line" namon>L460">.4606/a>}
L461" class="line" namon>L461">.4616/a>
L462" class="line" namon>L462">.4626/a>static void 6a href="+code=do_process_ded_retry" class="sref">do_process_ded_retry6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error" class="sref">error6/a>,
L463" class="line" namon>L463">.4636/a>                                 6a href="+code=u32" class="sref">u326/a> 6a href="+code=retry_add" class="sref">retry_add6/a>)
L464" class="line" namon>L464">.4646/a>{
L465" class="line" namon>L465">.4656/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=error_1b" class="sref">error_1b6/a>, 6a href="+code=page" class="sref">page6/a>;
L466" class="line" namon>L466">.4666/a>        int.6a href="+code=row" class="sref">row6/a>;
L467" class="line" namon>L467">.4676/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L468" class="line" namon>L468">.4686/a>
L469" class="line" namon>L469">.4696/a>        6a href="+code=error_1b" class="sref">error_1b6/a> = 6a href="+code=retry_add" class="sref">retry_add6/a>;
L470" class="line" namon>L470">.4706/a>        6a href="+code=page" class="sref">page6/a> = 6a href="+code=error_1b" class="sref">error_1b6/a> >> (6a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT6/a> - 4);  6spa  class="comment">/* convert the addr to 4k page */6/spa >
L471" class="line" namon>L471">.4716/a>
L472" class="line" namon>L472">.4726/a>        6spa  class="comment">/* chip select.are bits 14 & 13 */6/spa >
L473" class="line" namon>L473">.4736/a>        6a href="+code=row" class="sref">row6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a> ? ((6a href="+code=page" class="sref">page6/a> >> 1) & 3) :
L474" class="line" namon>L474">.4746/a>                6a href="+code=edac_mc_find_csrow_by_page" class="sref">edac_mc_find_csrow_by_page6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=page" class="sref">page6/a>);
L475" class="line" namon>L475">.4756/a>
L476" class="line" namon>L476">.4766/a>        6a href="+code=e752x_mc_printk" class="sref">e752x_mc_printk6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>,
L477" class="line" namon>L477">.4776/a>                        6spa  class="string">"CE page 0x%lx, row %d : Memory read retry\n"6/spa >,
L478" class="line" namon>L478">.4786/a>                        (long unsigned int)6a href="+code=page" class="sref">page6/a>, 6a href="+code=row" class="sref">row6/a>);
L479" class="line" namon>L479">.4796/a>}
L480" class="line" namon>L480">.4806/a>
L481" class="line" namon>L481">.4816/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=process_ded_retry" class="sref">process_ded_retry6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error" class="sref">error6/a>,
L482" class="line" namon>L482">.4826/a>                                6a href="+code=u32" class="sref">u326/a> 6a href="+code=retry_add" class="sref">retry_add6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L483" class="line" namon>L483">.4836/a>                                int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L484" class="line" namon>L484">.4846/a>{
L485" class="line" namon>L485">.4856/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L486" class="line" namon>L486">.4866/a>
L487" class="line" namon>L487">.4876/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L488" class="line" namon>L488">.4886/a>                6a href="+code=do_process_ded_retry" class="sref">do_process_ded_retry6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error" class="sref">error6/a>, 6a href="+code=retry_add" class="sref">retry_add6/a>);
L489" class="line" namon>L489">.4896/a>}
L490" class="line" namon>L490">.4906/a>
L491" class="line" namon>L491">.4916/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=process_threshold_ce" class="sref">process_threshold_ce6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u16" class="sref">u166/a> 6a href="+code=error" class="sref">error6/a>,
L492" class="line" namon>L492">.4926/a>                                        int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L493" class="line" namon>L493">.4936/a>{
L494" class="line" namon>L494">.4946/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L495" class="line" namon>L495">.4956/a>
L496" class="line" namon>L496">.4966/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L497" class="line" namon>L497">.4976/a>                6a href="+code=e752x_mc_printk" class="sref">e752x_mc_printk6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"Memory threshold CE\n"6/spa >);
L498" class="line" namon>L498">.4986/a>}
L499" class="line" namon>L499">.4996/a>
L500" class="line" namon>L500">.5006/a>static char *6a href="+code=global_message" class="sref">global_message6/a>[11] = {
L501" class="line" namon>L501">.5016/a>        6spa  class="string">"PCI Express C1"6/spa >,
L502" class="line" namon>L502">.5026/a>        6spa  class="string">"PCI Express C"6/spa >,
L503" class="line" namon>L503">.5036/a>        6spa  class="string">"PCI Express B1"6/spa >,
L504" class="line" namon>L504">.5046/a>        6spa  class="string">"PCI Express B"6/spa >,
L505" class="line" namon>L505">.5056/a>        6spa  class="string">"PCI Express A1"6/spa >,
L506" class="line" namon>L506">.5066/a>        6spa  class="string">"PCI Express A"6/spa >,
L507" class="line" namon>L507">.5076/a>        6spa  class="string">"DMA Controller"6/spa >,
L508" class="line" namon>L508">.5086/a>        6spa  class="string">"HUB or NS Interface"6/spa >,
L509" class="line" namon>L509">.5096/a>        6spa  class="string">"System Bus"6/spa >,
L510" class="line" namon>L510">.5106/a>        6spa  class="string">"DRAM Controller"6/spa >,  6spa  class="comment">/* 9th entry */6/spa >
L511" class="line" namon>L511">.5116/a>        6spa  class="string">"Internal Buffer"6/spa >
L512" class="line" namon>L512">.5126/a>};
L513" class="line" namon>L513">.5136/a>
L514" class="line" namon>L514">.5146/a>#define 6a href="+code=DRAM_ENTRY" class="sref">DRAM_ENTRY6/a>      9
L515" class="line" namon>L515">.5156/a>
L516" class="line" namon>L516">.5166/a>static char *6a href="+code=fatal_message" class="sref">fatal_message6/a>[2] = { 6spa  class="string">"Non-Fatal "6/spa >, 6spa  class="string">"Fatal "6/spa > };
L517" class="line" namon>L517">.5176/a>
L518" class="line" namon>L518">.5186/a>static void 6a href="+code=do_global_error" class="sref">do_global_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>)
L519" class="line" namon>L519">.5196/a>{
L520" class="line" namon>L520">.5206/a>        int.6a href="+code=i" class="sref">i6/a>;
L521" class="line" namon>L521">.5216/a>
L522" class="line" namon>L522">.5226/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 11; 6a href="+code=i" class="sref">i6/a>++) {
L523" class="line" namon>L523">.5236/a>                if (6a href="+code=errors" class="sref">errors6/a> & (1 << 6a href="+code=i" class="sref">i6/a>)) {
L524" class="line" namon>L524">.5246/a>                        6spa  class="comment">/* If the error is from DRAM Controller OR6/spa >
L525" class="line" namon>L525">.5256/a>6spa  class="comment">                         * we.are to report ALL errors, then6/spa >
L526" class="line" namon>L526">.5266/a>6spa  class="comment">                         * report the error6/spa >
L527" class="line" namon>L527">.5276/a>6spa  class="comment">                         */6/spa >
L528" class="line" namon>L528">.5286/a>                        if ((6a href="+code=i" class="sref">i6/a> == 6a href="+code=DRAM_ENTRY" class="sref">DRAM_ENTRY6/a>) || 6a href="+code=report_non_memory_errors" class="sref">report_non_memory_errors6/a>)
L529" class="line" namon>L529">.5296/a>                                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"%sError %s\n"6/spa >,
L530" class="line" namon>L530">.5306/a>                                        6a href="+code=fatal_message" class="sref">fatal_message6/a>[6a href="+code=fatal" class="sref">fatal6/a>],
L531" class="line" namon>L531">.5316/a>                                        6a href="+code=global_message" class="sref">global_message6/a>[6a href="+code=i" class="sref">i6/a>]);
L532" class="line" namon>L532">.5326/a>                }
L533" class="line" namon>L533">.5336/a>        }
L534" class="line" namon>L534">.5346/a>}
L535" class="line" namon>L535">.5356/a>
L536" class="line" namon>L536">.5366/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=global_error" class="sref">global_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L537" class="line" namon>L537">.5376/a>                                int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L538" class="line" namon>L538">.5386/a>{
L539" class="line" namon>L539">.5396/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L540" class="line" namon>L540">.5406/a>
L541" class="line" namon>L541">.5416/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L542" class="line" namon>L542">.5426/a>                6a href="+code=do_global_error" class="sref">do_global_error6/a>(6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=errors" class="sref">errors6/a>);
L543" class="line" namon>L543">.5436/a>}
L544" class="line" namon>L544">.5446/a>
L545" class="line" namon>L545">.5456/a>static char *6a href="+code=hub_message" class="sref">hub_message6/a>[7] = {
L546" class="line" namon>L546">.5466/a>        6spa  class="string">"HI Address or Command Parity"6/spa >, 6spa  class="string">"HI Illegal Access"6/spa >,
L547" class="line" namon>L547">.5476/a>        6spa  class="string">"HI Internal Parity"6/spa >, 6spa  class="string">"Out of Range Access"6/spa >,
L548" class="line" namon>L548">.5486/a>        6spa  class="string">"HI Data Parity"6/spa >, 6spa  class="string">"Enhanced Config Access"6/spa >,
L549" class="line" namon>L549">.5496/a>        6spa  class="string">"Hub Interface Target Abort"6/spa >
L550" class="line" namon>L550">.5506/a>};
L551" class="line" namon>L551">.5516/a>
L552" class="line" namon>L552">.5526/a>static void 6a href="+code=do_hub_error" class="sref">do_hub_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u8" class="sref">u86/a> 6a href="+code=errors" class="sref">errors6/a>)
L553" class="line" namon>L553">.5536/a>{
L554" class="line" namon>L554">.5546/a>        int.6a href="+code=i" class="sref">i6/a>;
L555" class="line" namon>L555">.5556/a>
L556" class="line" namon>L556">.5566/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 7; 6a href="+code=i" class="sref">i6/a>++) {
L557" class="line" namon>L557">.5576/a>                if (6a href="+code=errors" class="sref">errors6/a> & (1 << 6a href="+code=i" class="sref">i6/a>))
L558" class="line" namon>L558">.5586/a>                        6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"%sError %s\n"6/spa >,
L559" class="line" namon>L559">.5596/a>                                6a href="+code=fatal_message" class="sref">fatal_message6/a>[6a href="+code=fatal" class="sref">fatal6/a>],.6a href="+code=hub_message" class="sref">hub_message6/a>[6a href="+code=i" class="sref">i6/a>]);
L560" class="line" namon>L560">.5606/a>        }
L561" class="line" namon>L561">.5616/a>}
L562" class="line" namon>L562">.5626/a>
L563" class="line" namon>L563">.5636/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=hub_error" class="sref">hub_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u8" class="sref">u86/a> 6a href="+code=errors" class="sref">errors6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L564" class="line" namon>L564">.5646/a>                        int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L565" class="line" namon>L565">.5656/a>{
L566" class="line" namon>L566">.5666/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L567" class="line" namon>L567">.5676/a>
L568" class="line" namon>L568">.5686/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L569" class="line" namon>L569">.5696/a>                6a href="+code=do_hub_error" class="sref">do_hub_error6/a>(6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=errors" class="sref">errors6/a>);
L570" class="line" namon>L570">.5706/a>}
L571" class="line" namon>L571">.5716/a>
L572" class="line" namon>L572">.5726/a>#define 6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a>          0x0c080081
L573" class="line" namon>L573">.5736/a>#define 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>      0x23a0ba64
L574" class="line" namon>L574">.5746/a>#define 6a href="+code=NSI_ERR_MASK" class="sref">NSI_ERR_MASK6/a>            (6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a> | 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>)
L575" class="line" namon>L575">.5756/a>
L576" class="line" namon>L576">.5766/a>static char *6a href="+code=nsi_message" class="sref">nsi_message6/a>[30] = {
L577" class="line" namon>L577">.5776/a>        6spa  class="string">"NSI Link Down"6/spa >,        6spa  class="comment">/* NSI_FERR/NSI_NERR bit 0, fatal error */6/spa >
L578" class="line" namon>L578">.5786/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L579" class="line" namon>L579">.5796/a>        6spa  class="string">"NSI Parity Error"6/spa >,                             6spa  class="comment">/* bit 2, non-fatal */6/spa >
L580" class="line" namon>L580">.5806/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L581" class="line" namon>L581">.5816/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L582" class="line" namon>L582">.5826/a>        6spa  class="string">"Correctable Error Message"6/spa >,                    6spa  class="comment">/* bit 5, non-fatal */6/spa >
L583" class="line" namon>L583">.5836/a>        6spa  class="string">"Non-Fatal Error Message"6/spa >,                      6spa  class="comment">/* bit 6, non-fatal */6/spa >
L584" class="line" namon>L584">.5846/a>        6spa  class="string">"Fatal Error Message"6/spa >,                          6spa  class="comment">/* bit 7, fatal */6/spa >
L585" class="line" namon>L585">.5856/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L586" class="line" namon>L586">.5866/a>        6spa  class="string">"Receiver Error"6/spa >,                               6spa  class="comment">/* bit 9, non-fatal */6/spa >
L587" class="line" namon>L587">.5876/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L588" class="line" namon>L588">.5886/a>        6spa  class="string">"Bad TLP"6/spa >,                                      6spa  class="comment">/* bit 11, non-fatal */6/spa >
L589" class="line" namon>L589">.5896/a>        6spa  class="string">"Bad DLLP"6/spa >,                                     6spa  class="comment">/* bit 12, non-fatal */6/spa >
L590" class="line" namon>L590">.5906/a>        6spa  class="string">"REPLAY_NUM Rollover"6/spa >,                          6spa  class="comment">/* bit 13, non-fatal */6/spa >
L591" class="line" namon>L591">.5916/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L592" class="line" namon>L592">.5926/a>        6spa  class="string">"Replay Timer Timeout"6/spa >,                         6spa  class="comment">/* bit 15, non-fatal */6/spa >
L593" class="line" namon>L593">.5936/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L594" class="line" namon>L594">.5946/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L595" class="line" namon>L595">.5956/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L596" class="line" namon>L596">.5966/a>        6spa  class="string">"Data Link Protocol Error"6/spa >,                     6spa  class="comment">/* bit 19, fatal */6/spa >
L597" class="line" namon>L597">.5976/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L598" class="line" namon>L598">.5986/a>        6spa  class="string">"Poisoned TLP"6/spa >,                                 6spa  class="comment">/* bit 21, non-fatal */6/spa >
L599" class="line" namon>L599">.5996/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L600" class="line" namon>L600">.6006/a>        6spa  class="string">"Completion Timeout"6/spa >,                           6spa  class="comment">/* bit 23, non-fatal */6/spa >
L601" class="line" namon>L601">.6016/a>        6spa  class="string">"Completer Abort"6/spa >,                              6spa  class="comment">/* bit 24, non-fatal */6/spa >
L602" class="line" namon>L602">.6026/a>        6spa  class="string">"Unexpected Completion"6/spa >,                        6spa  class="comment">/* bit 25, non-fatal */6/spa >
L603" class="line" namon>L603">.6036/a>        6spa  class="string">"Receiver Overflow"6/spa >,                            6spa  class="comment">/* bit 26, fatal */6/spa >
L604" class="line" namon>L604">.6046/a>        6spa  class="string">"Malformed TLP"6/spa >,                                6spa  class="comment">/* bit 27, fatal */6/spa >
L605" class="line" namon>L605">.6056/a>        6spa  class="string">""6/spa >,                                             6spa  class="comment">/* reserved */6/spa >
L606" class="line" namon>L606">.6066/a>        6spa  class="string">"Unsupported Request"6/spa >                           6spa  class="comment">/* bit 29, non-fatal */6/spa >
L607" class="line" namon>L607">.6076/a>};
L608" class="line" namon>L608">.6086/a>
L609" class="line" namon>L609">.6096/a>static void 6a href="+code=do_nsi_error" class="sref">do_nsi_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>)
L610" class="line" namon>L610">.6106/a>{
L611" class="line" namon>L611">.6116/a>        int.6a href="+code=i" class="sref">i6/a>;
L612" class="line" namon>L612">.6126/a>
L613" class="line" namon>L613">.6136/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 30; 6a href="+code=i" class="sref">i6/a>++) {
L614" class="line" namon>L614">.6146/a>                if (6a href="+code=errors" class="sref">errors6/a> & (1 << 6a href="+code=i" class="sref">i6/a>))
L615" class="line" namon>L615">.6156/a>                        6a href="+code=printk" class="sref">printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a> 6spa  class="string">"%sError %s\n"6/spa >,
L616" class="line" namon>L616">.6166/a>                               6a href="+code=fatal_message" class="sref">fatal_message6/a>[6a href="+code=fatal" class="sref">fatal6/a>],.6a href="+code=nsi_message" class="sref">nsi_message6/a>[6a href="+code=i" class="sref">i6/a>]);
L617" class="line" namon>L617">.6176/a>        }
L618" class="line" namon>L618">.6186/a>}
L619" class="line" namon>L619">.6196/a>
L620" class="line" namon>L620">.6206/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=nsi_error" class="sref">nsi_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L621" class="line" namon>L621">.6216/a>                int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L622" class="line" namon>L622">.6226/a>{
L623" class="line" namon>L623">.6236/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L624" class="line" namon>L624">.6246/a>
L625" class="line" namon>L625">.6256/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L626" class="line" namon>L626">.6266/a>                6a href="+code=do_nsi_error" class="sref">do_nsi_error6/a>(6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=errors" class="sref">errors6/a>);
L627" class="line" namon>L627">.6276/a>}
L628" class="line" namon>L628">.6286/a>
L629" class="line" namon>L629">.6296/a>static char *6a href="+code=membuf_message" class="sref">membuf_message6/a>[4] = {
L630" class="line" namon>L630">.6306/a>        6spa  class="string">"Internal PMWB to DRAM parity"6/spa >,
L631" class="line" namon>L631">.6316/a>        6spa  class="string">"Internal PMWB to System Bus Parity"6/spa >,
L632" class="line" namon>L632">.6326/a>        6spa  class="string">"Internal System Bus or IO to PMWB Parity"6/spa >,
L633" class="line" namon>L633">.6336/a>        6spa  class="string">"Internal DRAM to PMWB Parity"6/spa >
L634" class="line" namon>L634">.6346/a>};
L635" class="line" namon>L635">.6356/a>
L636" class="line" namon>L636">.6366/a>static void 6a href="+code=do_membuf_error" class="sref">do_membuf_error6/a>(6a href="+code=u8" class="sref">u86/a> 6a href="+code=errors" class="sref">errors6/a>)
L637" class="line" namon>L637">.6376/a>{
L638" class="line" namon>L638">.6386/a>        int.6a href="+code=i" class="sref">i6/a>;
L639" class="line" namon>L639">.6396/a>
L640" class="line" namon>L640">.6406/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 4; 6a href="+code=i" class="sref">i6/a>++) {
L641" class="line" namon>L641">.6416/a>                if (6a href="+code=errors" class="sref">errors6/a> & (1 << 6a href="+code=i" class="sref">i6/a>))
L642" class="line" namon>L642">.6426/a>                        6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"Non-Fatal Error %s\n"6/spa >,
L643" class="line" namon>L643">.6436/a>                                6a href="+code=membuf_message" class="sref">membuf_message6/a>[6a href="+code=i" class="sref">i6/a>]);
L644" class="line" namon>L644">.6446/a>        }
L645" class="line" namon>L645">.6456/a>}
L646" class="line" namon>L646">.6466/a>
L647" class="line" namon>L647">.6476/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=membuf_error" class="sref">membuf_error6/a>(6a href="+code=u8" class="sref">u86/a> 6a href="+code=errors" class="sref">errors6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L648" class="line" namon>L648">.6486/a>{
L649" class="line" namon>L649">.6496/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L650" class="line" namon>L650">.6506/a>
L651" class="line" namon>L651">.6516/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L652" class="line" namon>L652">.6526/a>                6a href="+code=do_membuf_error" class="sref">do_membuf_error6/a>(6a href="+code=errors" class="sref">errors6/a>);
L653" class="line" namon>L653">.6536/a>}
L654" class="line" namon>L654">.6546/a>
L655" class="line" namon>L655">.6556/a>static char *6a href="+code=sysbus_message" class="sref">sysbus_message6/a>[10] = {
L656" class="line" namon>L656">.6566/a>        6spa  class="string">"Addr or Request Parity"6/spa >,
L657" class="line" namon>L657">.6576/a>        6spa  class="string">"Data Strobe Glitch"6/spa >,
L658" class="line" namon>L658">.6586/a>        6spa  class="string">"Addr Strobe Glitch"6/spa >,
L659" class="line" namon>L659">.6596/a>        6spa  class="string">"Data Parity"6/spa >,
L660" class="line" namon>L660">.6606/a>        6spa  class="string">"Addr Above TOM"6/spa >,
L661" class="line" namon>L661">.6616/a>        6spa  class="string">"Non DRAM Lock Error"6/spa >,
L662" class="line" namon>L662">.6626/a>        6spa  class="string">"MCERR"6/spa >, 6spa  class="string">"BINIT"6/spa >,
L663" class="line" namon>L663">.6636/a>        6spa  class="string">"Memory Parity"6/spa >,
L664" class="line" namon>L664">.6646/a>        6spa  class="string">"IO Subsystem Parity"6/spa >
L665" class="line" namon>L665">.6656/a>};
L666" class="line" namon>L666">.6666/a>
L667" class="line" namon>L667">.6676/a>static void 6a href="+code=do_sysbus_error" class="sref">do_sysbus_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>)
L668" class="line" namon>L668">.6686/a>{
L669" class="line" namon>L669">.6696/a>        int.6a href="+code=i" class="sref">i6/a>;
L670" class="line" namon>L670">.6706/a>
L671" class="line" namon>L671">.6716/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 10; 6a href="+code=i" class="sref">i6/a>++) {
L672" class="line" namon>L672">.6726/a>                if (6a href="+code=errors" class="sref">errors6/a> & (1 << 6a href="+code=i" class="sref">i6/a>))
L673" class="line" namon>L673">.6736/a>                        6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>, 6spa  class="string">"%sError System Bus %s\n"6/spa >,
L674" class="line" namon>L674">.6746/a>                                6a href="+code=fatal_message" class="sref">fatal_message6/a>[6a href="+code=fatal" class="sref">fatal6/a>],.6a href="+code=sysbus_message" class="sref">sysbus_message6/a>[6a href="+code=i" class="sref">i6/a>]);
L675" class="line" namon>L675">.6756/a>        }
L676" class="line" namon>L676">.6766/a>}
L677" class="line" namon>L677">.6776/a>
L678" class="line" namon>L678">.6786/a>static 6a href="+code=inline" class="sref">inline6/a> void 6a href="+code=sysbus_error" class="sref">sysbus_error6/a>(int.6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=errors" class="sref">errors6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L679" class="line" namon>L679">.6796/a>                                int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L680" class="line" namon>L680">.6806/a>{
L681" class="line" namon>L681">.6816/a>        *6a href="+code=error_found" class="sref">error_found6/a> = 1;
L682" class="line" namon>L682">.6826/a>
L683" class="line" namon>L683">.6836/a>        if (6a href="+code=handle_error" class="sref">handle_error6/a>)
L684" class="line" namon>L684">.6846/a>                6a href="+code=do_sysbus_error" class="sref">do_sysbus_error6/a>(6a href="+code=fatal" class="sref">fatal6/a>, 6a href="+code=errors" class="sref">errors6/a>);
L685" class="line" namon>L685">.6856/a>}
L686" class="line" namon>L686">.6866/a>
L687" class="line" namon>L687">.6876/a>static void 6a href="+code=e752x_check_hub_interface" class="sref">e752x_check_hub_interface6/a>(struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>,
L688" class="line" namon>L688">.6886/a>                                int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L689" class="line" namon>L689">.6896/a>{
L690" class="line" namon>L690">.6906/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=stat8" class="sref">stat86/a>;
L691" class="line" namon>L691">.6916/a>
L692" class="line" namon>L692">.6926/a>        6spa  class="comment">//pci_read_config_byte(dev,E752X_HI_FERR,&stat8);6/spa >
L693" class="line" namon>L693">.6936/a>
L694" class="line" namon>L694">.6946/a>        6a href="+code=stat8" class="sref">stat86/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_ferr" class="sref">hi_ferr6/a>;
L695" class="line" namon>L695">.6956/a>
L696" class="line" namon>L696">.6966/a>        if (6a href="+code=stat8" class="sref">stat86/a> & 0x7f) {     6spa  class="comment">/* Error, so process */6/spa >
L697" class="line" namon>L697">.6976/a>                6a href="+code=stat8" class="sref">stat86/a> &= 0x7f;
L698" class="line" namon>L698">.6986/a>
L699" class="line" namon>L699">.6996/a>                if (6a href="+code=stat8" class="sref">stat86/a> & 0x2b)
L700" class="line" namon>L700">.7006/a>                        6a href="+code=hub_error" class="sref">hub_error6/a>(1,.6a href="+code=stat8" class="sref">stat86/a> & 0x2b, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L701" class="line" namon>L701">.7016/a>
L702" class="line" namon>L702">.7026/a>                if (6a href="+code=stat8" class="sref">stat86/a> & 0x54)
L703" class="line" namon>L703">.7036/a>                        6a href="+code=hub_error" class="sref">hub_error6/a>(0,.6a href="+code=stat8" class="sref">stat86/a> & 0x54, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L704" class="line" namon>L704">.7046/a>        }
L705" class="line" namon>L705">.7056/a>        6spa  class="comment">//pci_read_config_byte(dev,E752X_HI_NERR,&stat8);6/spa >
L706" class="line" namon>L706">.7066/a>
L707" class="line" namon>L707">.7076/a>        6a href="+code=stat8" class="sref">stat86/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_nerr" class="sref">hi_nerr6/a>;
L708" class="line" namon>L708">.7086/a>
L709" class="line" namon>L709">.7096/a>        if (6a href="+code=stat8" class="sref">stat86/a> & 0x7f) {     6spa  class="comment">/* Error, so process */6/spa >
L710" class="line" namon>L710">.7106/a>                6a href="+code=stat8" class="sref">stat86/a> &= 0x7f;
L711" class="line" namon>L711">.7116/a>
L712" class="line" namon>L712">.7126/a>                if (6a href="+code=stat8" class="sref">stat86/a> & 0x2b)
L713" class="line" namon>L713">.7136/a>                        6a href="+code=hub_error" class="sref">hub_error6/a>(1,.6a href="+code=stat8" class="sref">stat86/a> & 0x2b, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L714" class="line" namon>L714">.7146/a>
L715" class="line" namon>L715">.7156/a>                if (6a href="+code=stat8" class="sref">stat86/a> & 0x54)
L716" class="line" namon>L716">.7166/a>                        6a href="+code=hub_error" class="sref">hub_error6/a>(0,.6a href="+code=stat8" class="sref">stat86/a> & 0x54, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L717" class="line" namon>L717">.7176/a>        }
L718" class="line" namon>L718">.7186/a>}
L719" class="line" namon>L719">.7196/a>
L720" class="line" namon>L720">.7206/a>static void 6a href="+code=e752x_check_ns_interface" class="sref">e752x_check_ns_interface6/a>(struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>,
L721" class="line" namon>L721">.7216/a>                                int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L722" class="line" namon>L722">.7226/a>{
L723" class="line" namon>L723">.7236/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=stat32" class="sref">stat326/a>;
L724" class="line" namon>L724">.7246/a>
L725" class="line" namon>L725">.7256/a>        6a href="+code=stat32" class="sref">stat326/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a>;
L726" class="line" namon>L726">.7266/a>        if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_ERR_MASK" class="sref">NSI_ERR_MASK6/a>) { 6spa  class="comment">/* Error, so process */6/spa >
L727" class="line" namon>L727">.7276/a>                if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a>)    6spa  class="comment">/* check for fatal errors */6/spa >
L728" class="line" namon>L728">.7286/a>                        6a href="+code=nsi_error" class="sref">nsi_error6/a>(1,.6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a>, 6a href="+code=error_found" class="sref">error_found6/a>,
L729" class="line" namon>L729">.7296/a>                                  6a href="+code=handle_error" class="sref">handle_error6/a>);
L730" class="line" namon>L730">.7306/a>                if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>) 6spa  class="comment">/* check for non-fatal ones */6/spa >
L731" class="line" namon>L731">.7316/a>                        6a href="+code=nsi_error" class="sref">nsi_error6/a>(0,.6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>, 6a href="+code=error_found" class="sref">error_found6/a>,
L732" class="line" namon>L732">.7326/a>                                  6a href="+code=handle_error" class="sref">handle_error6/a>);
L733" class="line" namon>L733">.7336/a>        }
L734" class="line" namon>L734">.7346/a>        6a href="+code=stat32" class="sref">stat326/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a>;
L735" class="line" namon>L735">.7356/a>        if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_ERR_MASK" class="sref">NSI_ERR_MASK6/a>) {
L736" class="line" namon>L736">.7366/a>                if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a>)
L737" class="line" namon>L737">.7376/a>                        6a href="+code=nsi_error" class="sref">nsi_error6/a>(1,.6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_FATAL_MASK" class="sref">NSI_FATAL_MASK6/a>, 6a href="+code=error_found" class="sref">error_found6/a>,
L738" class="line" namon>L738">.7386/a>                                  6a href="+code=handle_error" class="sref">handle_error6/a>);
L739" class="line" namon>L739">.7396/a>                if (6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>)
L740" class="line" namon>L740">.7406/a>                        6a href="+code=nsi_error" class="sref">nsi_error6/a>(0,.6a href="+code=stat32" class="sref">stat326/a> & 6a href="+code=NSI_NON_FATAL_MASK" class="sref">NSI_NON_FATAL_MASK6/a>, 6a href="+code=error_found" class="sref">error_found6/a>,
L741" class="line" namon>L741">.7416/a>                                  6a href="+code=handle_error" class="sref">handle_error6/a>);
L742" class="line" namon>L742">.7426/a>        }
L743" class="line" namon>L743">.7436/a>}
L744" class="line" namon>L744">.7446/a>
L745" class="line" namon>L745">.7456/a>static void 6a href="+code=e752x_check_sysbus" class="sref">e752x_check_sysbus6/a>(struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>,
L746" class="line" namon>L746">.7466/a>                        int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L747" class="line" namon>L747">.7476/a>{
L748" class="line" namon>L748">.7486/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=stat32" class="sref">stat326/a>, 6a href="+code=error32" class="sref">error326/a>;
L749" class="line" namon>L749">.7496/a>
L750" class="line" namon>L750">.7506/a>        6spa  class="comment">//pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);6/spa >
L751" class="line" namon>L751">.7516/a>        6a href="+code=stat32" class="sref">stat326/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_ferr" class="sref">sysbus_ferr6/a> + (6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_nerr" class="sref">sysbus_nerr6/a> << 16);
L752" class="line" namon>L752">.7526/a>
L753" class="line" namon>L753">.7536/a>        if (6a href="+code=stat32" class="sref">stat326/a> == 0)
L754" class="line" namon>L754">.7546/a>                return;         6spa  class="comment">/* no errors */6/spa >
L755" class="line" namon>L755">.7556/a>
L756" class="line" namon>L756">.7566/a>        6a href="+code=error32" class="sref">error326/a> = (6a href="+code=stat32" class="sref">stat326/a> >> 16) & 0x3ff;
L757" class="line" namon>L757">.7576/a>        6a href="+code=stat32" class="sref">stat326/a> = 6a href="+code=stat32" class="sref">stat326/a> & 0x3ff;
L758" class="line" namon>L758">.7586/a>
L759" class="line" namon>L759">.7596/a>        if (6a href="+code=stat32" class="sref">stat326/a> & 0x087)
L760" class="line" namon>L760">.7606/a>                6a href="+code=sysbus_error" class="sref">sysbus_error6/a>(1,.6a href="+code=stat32" class="sref">stat326/a> & 0x087, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L761" class="line" namon>L761">.7616/a>
L762" class="line" namon>L762">.7626/a>        if (6a href="+code=stat32" class="sref">stat326/a> & 0x378)
L763" class="line" namon>L763">.7636/a>                6a href="+code=sysbus_error" class="sref">sysbus_error6/a>(0,.6a href="+code=stat32" class="sref">stat326/a> & 0x378, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L764" class="line" namon>L764">.7646/a>
L765" class="line" namon>L765">.7656/a>        if (6a href="+code=error32" class="sref">error326/a> & 0x087)
L766" class="line" namon>L766">.7666/a>                6a href="+code=sysbus_error" class="sref">sysbus_error6/a>(1,.6a href="+code=error32" class="sref">error326/a> & 0x087, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L767" class="line" namon>L767">.7676/a>
L768" class="line" namon>L768">.7686/a>        if (6a href="+code=error32" class="sref">error326/a> & 0x378)
L769" class="line" namon>L769">.7696/a>                6a href="+code=sysbus_error" class="sref">sysbus_error6/a>(0,.6a href="+code=error32" class="sref">error326/a> & 0x378, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L770" class="line" namon>L770">.7706/a>}
L771" class="line" namon>L771">.7716/a>
L772" class="line" namon>L772">.7726/a>static void 6a href="+code=e752x_check_membuf" class="sref">e752x_check_membuf6/a>(struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>,
L773" class="line" namon>L773">.7736/a>                        int.*6a href="+code=error_found" class="sref">error_found6/a>, int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L774" class="line" namon>L774">.7746/a>{
L775" class="line" namon>L775">.7756/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=stat8" class="sref">stat86/a>;
L776" class="line" namon>L776">.7766/a>
L777" class="line" namon>L777">.7776/a>        6a href="+code=stat8" class="sref">stat86/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_ferr" class="sref">buf_ferr6/a>;
L778" class="line" namon>L778">.7786/a>
L779" class="line" namon>L779">.7796/a>        if (6a href="+code=stat8" class="sref">stat86/a> & 0x0f) {     6spa  class="comment">/* Error, so process */6/spa >
L780" class="line" namon>L780">.7806/a>                6a href="+code=stat8" class="sref">stat86/a> &= 0x0f;
L781" class="line" namon>L781">.7816/a>                6a href="+code=membuf_error" class="sref">membuf_error6/a>(6a href="+code=stat8" class="sref">stat86/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L782" class="line" namon>L782">.7826/a>        }
L783" class="line" namon>L783">.7836/a>
L784" class="line" namon>L784">.7846/a>        6a href="+code=stat8" class="sref">stat86/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_nerr" class="sref">buf_nerr6/a>;
L785" class="line" namon>L785">.7856/a>
L786" class="line" namon>L786">.7866/a>        if (6a href="+code=stat8" class="sref">stat86/a> & 0x0f) {     6spa  class="comment">/* Error, so process */6/spa >
L787" class="line" namon>L787">.7876/a>                6a href="+code=stat8" class="sref">stat86/a> &= 0x0f;
L788" class="line" namon>L788">.7886/a>                6a href="+code=membuf_error" class="sref">membuf_error6/a>(6a href="+code=stat8" class="sref">stat86/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L789" class="line" namon>L789">.7896/a>        }
L790" class="line" namon>L790">.7906/a>}
L791" class="line" namon>L791">.7916/a>
L792" class="line" namon>L792">.7926/a>static void 6a href="+code=e752x_check_dram" class="sref">e752x_check_dram6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>,
L793" class="line" namon>L793">.7936/a>                        struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>, int.*6a href="+code=error_found" class="sref">error_found6/a>,
L794" class="line" namon>L794">.7946/a>                        int.6a href="+code=handle_error" class="sref">handle_error6/a>)
L795" class="line" namon>L795">.7956/a>{
L796" class="line" namon>L796">.7966/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=error_next" class="sref">error_next6/a>;
L797" class="line" namon>L797">.7976/a>
L798" class="line" namon>L798">.7986/a>        6a href="+code=error_one" class="sref">error_one6/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ferr" class="sref">dram_ferr6/a>;
L799" class="line" namon>L799">.7996/a>        6a href="+code=error_next" class="sref">error_next6/a> = 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_nerr" class="sref">dram_nerr6/a>;
L800" class="line" namon>L800">.8006/a>
L801" class="line" namon>L801">.8016/a>        6spa  class="comment">/* decode and report errors */6/spa >
L802" class="line" namon>L802">.8026/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x0101) 6spa  class="comment">/* check first error correctable */6/spa >
L803" class="line" namon>L803">.8036/a>                6a href="+code=process_ce" class="sref">process_ce6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec1_add" class="sref">dram_sec1_add6/a>,
L804" class="line" namon>L804">.8046/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec1_syndrome" class="sref">dram_sec1_syndrome6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L805" class="line" namon>L805">.8056/a>
L806" class="line" namon>L806">.8066/a>        if (6a href="+code=error_next" class="sref">error_next6/a> & 0x0101)        6spa  class="comment">/* check next error correctable */6/spa >
L807" class="line" namon>L807">.8076/a>                6a href="+code=process_ce" class="sref">process_ce6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_next" class="sref">error_next6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec2_add" class="sref">dram_sec2_add6/a>,
L808" class="line" namon>L808">.8086/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec2_syndrome" class="sref">dram_sec2_syndrome6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L809" class="line" namon>L809">.8096/a>
L810" class="line" namon>L810">.8106/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x4040)
L811" class="line" namon>L811">.8116/a>                6a href="+code=process_ue_no_info_wr" class="sref">process_ue_no_info_wr6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L812" class="line" namon>L812">.8126/a>
L813" class="line" namon>L813">.8136/a>        if (6a href="+code=error_next" class="sref">error_next6/a> & 0x4040)
L814" class="line" namon>L814">.8146/a>                6a href="+code=process_ue_no_info_wr" class="sref">process_ue_no_info_wr6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L815" class="line" namon>L815">.8156/a>
L816" class="line" namon>L816">.8166/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x2020)
L817" class="line" namon>L817">.8176/a>                6a href="+code=process_ded_retry" class="sref">process_ded_retry6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_retr_add" class="sref">dram_retr_add6/a>,
L818" class="line" namon>L818">.8186/a>                                6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L819" class="line" namon>L819">.8196/a>
L820" class="line" namon>L820">.8206/a>        if (6a href="+code=error_next" class="sref">error_next6/a> & 0x2020)
L821" class="line" namon>L821">.8216/a>                6a href="+code=process_ded_retry" class="sref">process_ded_retry6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_next" class="sref">error_next6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_retr_add" class="sref">dram_retr_add6/a>,
L822" class="line" namon>L822">.8226/a>                                6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L823" class="line" namon>L823">.8236/a>
L824" class="line" namon>L824">.8246/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x0808)
L825" class="line" namon>L825">.8256/a>                6a href="+code=process_threshold_ce" class="sref">process_threshold_ce6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L826" class="line" namon>L826">.8266/a>
L827" class="line" namon>L827">.8276/a>        if (6a href="+code=error_next" class="sref">error_next6/a> & 0x0808)
L828" class="line" namon>L828">.8286/a>                6a href="+code=process_threshold_ce" class="sref">process_threshold_ce6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_next" class="sref">error_next6/a>, 6a href="+code=error_found" class="sref">error_found6/a>,
L829" class="line" namon>L829">.8296/a>                                6a href="+code=handle_error" class="sref">handle_error6/a>);
L830" class="line" namon>L830">.8306/a>
L831" class="line" namon>L831">.8316/a>        if (6a href="+code=error_one" class="sref">error_one6/a> & 0x0606)
L832" class="line" namon>L832">.8326/a>                6a href="+code=process_ue" class="sref">process_ue6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_one" class="sref">error_one6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ded_add" class="sref">dram_ded_add6/a>,
L833" class="line" namon>L833">.8336/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_scrb_add" class="sref">dram_scrb_add6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L834" class="line" namon>L834">.8346/a>
L835" class="line" namon>L835">.8356/a>        if (6a href="+code=error_next" class="sref">error_next6/a> & 0x0606)
L836" class="line" namon>L836">.8366/a>                6a href="+code=process_ue" class="sref">process_ue6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=error_next" class="sref">error_next6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ded_add" class="sref">dram_ded_add6/a>,
L837" class="line" namon>L837">.8376/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_scrb_add" class="sref">dram_scrb_add6/a>, 6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_error" class="sref">handle_error6/a>);
L838" class="line" namon>L838">.8386/a>}
L839" class="line" namon>L839">.8396/a>
L840" class="line" namon>L840">.8406/a>static void 6a href="+code=e752x_get_error_info" class="sref">e752x_get_error_info6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>,
L841" class="line" namon>L841">.8416/a>                                 struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>)
L842" class="line" namon>L842">.8426/a>{
L843" class="line" namon>L843">.8436/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev" class="sref">dev6/a>;
L844" class="line" namon>L844">.8446/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>;
L845" class="line" namon>L845">.8456/a>
L846" class="line" namon>L846">.8466/a>        6a href="+code=memset" class="sref">memset6/a>(6a href="+code=info" class="sref">info6/a>, 0, sizeof(*6a href="+code=info" class="sref">info6/a>));
L847" class="line" namon>L847">.8476/a>        6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L848" class="line" namon>L848">.8486/a>        6a href="+code=dev" class="sref">dev6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>;
L849" class="line" namon>L849">.8496/a>        6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_FERR_GLOBAL" class="sref">E752X_FERR_GLOBAL6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=ferr_global" class="sref">ferr_global6/a>);
L850" class="line" namon>L850">.8506/a>
L851" class="line" namon>L851">.8516/a>        if (6a href="+code=info" class="sref">info6/a>->6a href="+code=ferr_global" class="sref">ferr_global6/a>) {
L852" class="line" namon>L852">.8526/a>                if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=err_dev" class="sref">err_dev6/a> == 6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>) {
L853" class="line" namon>L853">.8536/a>                        6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_FERR" class="sref">I3100_NSI_FERR6/a>,
L854" class="line" namon>L854">.8546/a>                                             &6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a>);
L855" class="line" namon>L855">.8556/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_ferr" class="sref">hi_ferr6/a> = 0;
L856" class="line" namon>L856">.8566/a>                } else {
L857" class="line" namon>L857">.8576/a>                        6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_FERR" class="sref">E752X_HI_FERR6/a>,
L858" class="line" namon>L858">.8586/a>                                             &6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_ferr" class="sref">hi_ferr6/a>);
L859" class="line" namon>L859">.8596/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a> = 0;
L860" class="line" namon>L860">.8606/a>                }
L861" class="line" namon>L861">.8616/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_FERR" class="sref">E752X_SYSBUS_FERR6/a>,
L862" class="line" namon>L862">.8626/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_ferr" class="sref">sysbus_ferr6/a>);
L863" class="line" namon>L863">.8636/a>                6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_FERR" class="sref">E752X_BUF_FERR6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_ferr" class="sref">buf_ferr6/a>);
L864" class="line" namon>L864">.8646/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_FERR" class="sref">E752X_DRAM_FERR6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ferr" class="sref">dram_ferr6/a>);
L865" class="line" namon>L865">.8656/a>                6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SEC1_ADD" class="sref">E752X_DRAM_SEC1_ADD6/a>,
L866" class="line" namon>L866">.8666/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec1_add" class="sref">dram_sec1_add6/a>);
L867" class="line" namon>L867">.8676/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SEC1_SYNDROME" class="sref">E752X_DRAM_SEC1_SYNDROME6/a>,
L868" class="line" namon>L868">.8686/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec1_syndrome" class="sref">dram_sec1_syndrome6/a>);
L869" class="line" namon>L869">.8696/a>                6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_DED_ADD" class="sref">E752X_DRAM_DED_ADD6/a>,
L870" class="line" namon>L870">.8706/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ded_add" class="sref">dram_ded_add6/a>);
L871" class="line" namon>L871">.8716/a>                6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SCRB_ADD" class="sref">E752X_DRAM_SCRB_ADD6/a>,
L872" class="line" namon>L872">.8726/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_scrb_add" class="sref">dram_scrb_add6/a>);
L873" class="line" namon>L873">.8736/a>                6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_RETR_ADD" class="sref">E752X_DRAM_RETR_ADD6/a>,
L874" class="line" namon>L874">.8746/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_retr_add" class="sref">dram_retr_add6/a>);
L875" class="line" namon>L875">.8756/a>
L876" class="line" namon>L876">.8766/a>                6spa  class="comment">/* ignore the reserved bits just i  case */6/spa >
L877" class="line" namon>L877">.8776/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_ferr" class="sref">hi_ferr6/a> & 0x7f)
L878" class="line" namon>L878">.8786/a>                        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_FERR" class="sref">E752X_HI_FERR6/a>,
L879" class="line" namon>L879">.8796/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_ferr" class="sref">hi_ferr6/a>);
L880" class="line" namon>L880">.8806/a>
L881" class="line" namon>L881">.8816/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a> & 6a href="+code=NSI_ERR_MASK" class="sref">NSI_ERR_MASK6/a>)
L882" class="line" namon>L882">.8826/a>                        6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_FERR" class="sref">I3100_NSI_FERR6/a>,
L883" class="line" namon>L883">.8836/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_ferr" class="sref">nsi_ferr6/a>);
L884" class="line" namon>L884">.8846/a>
L885" class="line" namon>L885">.8856/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_ferr" class="sref">sysbus_ferr6/a>)
L886" class="line" namon>L886">.8866/a>                        6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_FERR" class="sref">E752X_SYSBUS_FERR6/a>,
L887" class="line" namon>L887">.8876/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_ferr" class="sref">sysbus_ferr6/a>);
L888" class="line" namon>L888">.8886/a>
L889" class="line" namon>L889">.8896/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_ferr" class="sref">buf_ferr6/a> & 0x0f)
L890" class="line" namon>L890">.8906/a>                        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_FERR" class="sref">E752X_BUF_FERR6/a>,
L891" class="line" namon>L891">.8916/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_ferr" class="sref">buf_ferr6/a>);
L892" class="line" namon>L892">.8926/a>
L893" class="line" namon>L893">.8936/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ferr" class="sref">dram_ferr6/a>)
L894" class="line" namon>L894">.8946/a>                        6a href="+code=pci_write_bits16" class="sref">pci_write_bits166/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>, 6a href="+code=E752X_DRAM_FERR" class="sref">E752X_DRAM_FERR6/a>,
L895" class="line" namon>L895">.8956/a>                                         6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ferr" class="sref">dram_ferr6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_ferr" class="sref">dram_ferr6/a>);
L896" class="line" namon>L896">.8966/a>
L897" class="line" namon>L897">.8976/a>                6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_FERR_GLOBAL" class="sref">E752X_FERR_GLOBAL6/a>,
L898" class="line" namon>L898">.8986/a>                                6a href="+code=info" class="sref">info6/a>->6a href="+code=ferr_global" class="sref">ferr_global6/a>);
L899" class="line" namon>L899">.8996/a>        }
L900" class="line" namon>L900">.9006/a>
L901" class="line" namon>L901">.9016/a>        6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_NERR_GLOBAL" class="sref">E752X_NERR_GLOBAL6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=nerr_global" class="sref">nerr_global6/a>);
L902" class="line" namon>L902">.9026/a>
L903" class="line" namon>L903">.9036/a>        if (6a href="+code=info" class="sref">info6/a>->6a href="+code=nerr_global" class="sref">nerr_global6/a>) {
L904" class="line" namon>L904">.9046/a>                if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=err_dev" class="sref">err_dev6/a> == 6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>) {
L905" class="line" namon>L905">.9056/a>                        6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_NERR" class="sref">I3100_NSI_NERR6/a>,
L906" class="line" namon>L906">.9066/a>                                             &6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a>);
L907" class="line" namon>L907">.9076/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_nerr" class="sref">hi_nerr6/a> = 0;
L908" class="line" namon>L908">.9086/a>                } else {
L909" class="line" namon>L909">.9096/a>                        6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_NERR" class="sref">E752X_HI_NERR6/a>,
L910" class="line" namon>L910">.9106/a>                                             &6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_nerr" class="sref">hi_nerr6/a>);
L911" class="line" namon>L911">.9116/a>                        6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a> = 0;
L912" class="line" namon>L912">.9126/a>                }
L913" class="line" namon>L913">.9136/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_NERR" class="sref">E752X_SYSBUS_NERR6/a>,
L914" class="line" namon>L914">.9146/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_nerr" class="sref">sysbus_nerr6/a>);
L915" class="line" namon>L915">.9156/a>                6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_NERR" class="sref">E752X_BUF_NERR6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_nerr" class="sref">buf_nerr6/a>);
L916" class="line" namon>L916">.9166/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_NERR" class="sref">E752X_DRAM_NERR6/a>, &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_nerr" class="sref">dram_nerr6/a>);
L917" class="line" namon>L917">.9176/a>                6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SEC2_ADD" class="sref">E752X_DRAM_SEC2_ADD6/a>,
L918" class="line" namon>L918">.9186/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec2_add" class="sref">dram_sec2_add6/a>);
L919" class="line" namon>L919">.9196/a>                6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SEC2_SYNDROME" class="sref">E752X_DRAM_SEC2_SYNDROME6/a>,
L920" class="line" namon>L920">.9206/a>                                &6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_sec2_syndrome" class="sref">dram_sec2_syndrome6/a>);
L921" class="line" namon>L921">.9216/a>
L922" class="line" namon>L922">.9226/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_nerr" class="sref">hi_nerr6/a> & 0x7f)
L923" class="line" namon>L923">.9236/a>                        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_NERR" class="sref">E752X_HI_NERR6/a>,
L924" class="line" namon>L924">.9246/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=hi_nerr" class="sref">hi_nerr6/a>);
L925" class="line" namon>L925">.9256/a>
L926" class="line" namon>L926">.9266/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a> & 6a href="+code=NSI_ERR_MASK" class="sref">NSI_ERR_MASK6/a>)
L927" class="line" namon>L927">.9276/a>                        6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_NERR" class="sref">I3100_NSI_NERR6/a>,
L928" class="line" namon>L928">.9286/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=nsi_nerr" class="sref">nsi_nerr6/a>);
L929" class="line" namon>L929">.9296/a>
L930" class="line" namon>L930">.9306/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_nerr" class="sref">sysbus_nerr6/a>)
L931" class="line" namon>L931">.9316/a>                        6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_NERR" class="sref">E752X_SYSBUS_NERR6/a>,
L932" class="line" namon>L932">.9326/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=sysbus_nerr" class="sref">sysbus_nerr6/a>);
L933" class="line" namon>L933">.9336/a>
L934" class="line" namon>L934">.9346/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_nerr" class="sref">buf_nerr6/a> & 0x0f)
L935" class="line" namon>L935">.9356/a>                        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_NERR" class="sref">E752X_BUF_NERR6/a>,
L936" class="line" namon>L936">.9366/a>                                        6a href="+code=info" class="sref">info6/a>->6a href="+code=buf_nerr" class="sref">buf_nerr6/a>);
L937" class="line" namon>L937">.9376/a>
L938" class="line" namon>L938">.9386/a>                if (6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_nerr" class="sref">dram_nerr6/a>)
L939" class="line" namon>L939">.9396/a>                        6a href="+code=pci_write_bits16" class="sref">pci_write_bits166/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>, 6a href="+code=E752X_DRAM_NERR" class="sref">E752X_DRAM_NERR6/a>,
L940" class="line" namon>L940">.9406/a>                                         6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_nerr" class="sref">dram_nerr6/a>, 6a href="+code=info" class="sref">info6/a>->6a href="+code=dram_nerr" class="sref">dram_nerr6/a>);
L941" class="line" namon>L941">.9416/a>
L942" class="line" namon>L942">.9426/a>                6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_NERR_GLOBAL" class="sref">E752X_NERR_GLOBAL6/a>,
L943" class="line" namon>L943">.9436/a>                                6a href="+code=info" class="sref">info6/a>->6a href="+code=nerr_global" class="sref">nerr_global6/a>);
L944" class="line" namon>L944">.9446/a>        }
L945" class="line" namon>L945">.9456/a>}
L946" class="line" namon>L946">.9466/a>
L947" class="line" namon>L947">.9476/a>static int.6a href="+code=e752x_process_error_info" class="sref">e752x_process_error_info6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>,
L948" class="line" namon>L948">.9486/a>                                struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> *6a href="+code=info" class="sref">info6/a>,
L949" class="line" namon>L949">.9496/a>                                int.6a href="+code=handle_errors" class="sref">handle_errors6/a>)
L950" class="line" namon>L950">.9506/a>{
L951" class="line" namon>L951">.9516/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=error32" class="sref">error326/a>, 6a href="+code=stat32" class="sref">stat326/a>;
L952" class="line" namon>L952">.9526/a>        int.6a href="+code=error_found" class="sref">error_found6/a>;
L953" class="line" namon>L953">.9536/a>
L954" class="line" namon>L954">.9546/a>        6a href="+code=error_found" class="sref">error_found6/a> = 0;
L955" class="line" namon>L955">.9556/a>        6a href="+code=error32" class="sref">error326/a> = (6a href="+code=info" class="sref">info6/a>->6a href="+code=ferr_global" class="sref">ferr_global6/a> >> 18) & 0x3ff;
L956" class="line" namon>L956">.9566/a>        6a href="+code=stat32" class="sref">stat326/a> = (6a href="+code=info" class="sref">info6/a>->6a href="+code=ferr_global" class="sref">ferr_global6/a> >> 4) & 0x7ff;
L957" class="line" namon>L957">.9576/a>
L958" class="line" namon>L958">.9586/a>        if (6a href="+code=error32" class="sref">error326/a>)
L959" class="line" namon>L959">.9596/a>                6a href="+code=global_error" class="sref">global_error6/a>(1, 6a href="+code=error32" class="sref">error326/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L960" class="line" namon>L960">.9606/a>
L961" class="line" namon>L961">.9616/a>        if (6a href="+code=stat32" class="sref">stat326/a>)
L962" class="line" namon>L962">.9626/a>                6a href="+code=global_error" class="sref">global_error6/a>(0, 6a href="+code=stat32" class="sref">stat326/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L963" class="line" namon>L963">.9636/a>
L964" class="line" namon>L964">.9646/a>        6a href="+code=error32" class="sref">error326/a> = (6a href="+code=info" class="sref">info6/a>->6a href="+code=nerr_global" class="sref">nerr_global6/a> >> 18) & 0x3ff;
L965" class="line" namon>L965">.9656/a>        6a href="+code=stat32" class="sref">stat326/a> = (6a href="+code=info" class="sref">info6/a>->6a href="+code=nerr_global" class="sref">nerr_global6/a> >> 4) & 0x7ff;
L966" class="line" namon>L966">.9666/a>
L967" class="line" namon>L967">.9676/a>        if (6a href="+code=error32" class="sref">error326/a>)
L968" class="line" namon>L968">.9686/a>                6a href="+code=global_error" class="sref">global_error6/a>(1, 6a href="+code=error32" class="sref">error326/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L969" class="line" namon>L969">.9696/a>
L970" class="line" namon>L970">.9706/a>        if (6a href="+code=stat32" class="sref">stat326/a>)
L971" class="line" namon>L971">.9716/a>                6a href="+code=global_error" class="sref">global_error6/a>(0, 6a href="+code=stat32" class="sref">stat326/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L972" class="line" namon>L972">.9726/a>
L973" class="line" namon>L973">.9736/a>        6a href="+code=e752x_check_hub_interface" class="sref">e752x_check_hub_interface6/a>(6a href="+code=info" class="sref">info6/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L974" class="line" namon>L974">.9746/a>        6a href="+code=e752x_check_ns_interface" class="sref">e752x_check_ns_interface6/a>(6a href="+code=info" class="sref">info6/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L975" class="line" namon>L975">.9756/a>        6a href="+code=e752x_check_sysbus" class="sref">e752x_check_sysbus6/a>(6a href="+code=info" class="sref">info6/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L976" class="line" namon>L976">.9766/a>        6a href="+code=e752x_check_membuf" class="sref">e752x_check_membuf6/a>(6a href="+code=info" class="sref">info6/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L977" class="line" namon>L977">.9776/a>        6a href="+code=e752x_check_dram" class="sref">e752x_check_dram6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=info" class="sref">info6/a>, &6a href="+code=error_found" class="sref">error_found6/a>, 6a href="+code=handle_errors" class="sref">handle_errors6/a>);
L978" class="line" namon>L978">.9786/a>        return.6a href="+code=error_found" class="sref">error_found6/a>;
L979" class="line" namon>L979">.9796/a>}
L980" class="line" namon>L980">.9806/a>
L981" class="line" namon>L981">.9816/a>static void 6a href="+code=e752x_check" class="sref">e752x_check6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>)
L982" class="line" namon>L982">.9826/a>{
L983" class="line" namon>L983">.9836/a>        struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a> 6a href="+code=info" class="sref">info6/a>;
L984" class="line" namon>L984">.9846/a>
L985" class="line" namon>L985">.9856/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L986" class="line" namon>L986">.9866/a>        6a href="+code=e752x_get_error_info" class="sref">e752x_get_error_info6/a>(6a href="+code=mci" class="sref">mci6/a>, &6a href="+code=info" class="sref">info6/a>);
L987" class="line" namon>L987">.9876/a>        6a href="+code=e752x_process_error_info" class="sref">e752x_process_error_info6/a>(6a href="+code=mci" class="sref">mci6/a>, &6a href="+code=info" class="sref">info6/a>, 1);
L988" class="line" namon>L988">.9886/a>}
L989" class="line" namon>L989">.9896/a>
L990" class="line" namon>L990">.9906/a>6spa  class="comment">/* Program byte/sec bandwidth scrub rate to hardware */6/spa >
L991" class="line" namon>L991">.9916/a>static int.6a href="+code=set_sdram_scrub_rate" class="sref">set_sdram_scrub_rate6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=u32" class="sref">u326/a> 6a href="+code=new_bw" class="sref">new_bw6/a>)
L992" class="line" namon>L992">.9926/a>{
L993" class="line" namon>L993">.9936/a>        const struct.6a href="+code=scrubrate" class="sref">scrubrate6/a> *6a href="+code=scrubrates" class="sref">scrubrates6/a>;
L994" class="line" namon>L994">.9946/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *).6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L995" class="line" namon>L995">.9956/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f0" class="sref">dev_d0f06/a>;
L996" class="line" namon>L996">.9966/a>        int.6a href="+code=i" class="sref">i6/a>;
L997" class="line" namon>L997">.9976/a>
L998" class="line" namon>L998">.9986/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=ctl_dev" class="sref">ctl_dev6/a> == 6a href="+code=PCI_DEVICE_ID_INTEL_3100_0" class="sref">PCI_DEVICE_ID_INTEL_3100_06/a>)
L999" class="line" namon>L999">.9996/a>                6a href="+code=scrubrates" class="sref">scrubrates6/a> = 6a href="+code=scrubrates_i3100" class="sref">scrubrates_i31006/a>;
L1000" class="line" namon>L1000">10006/a>        else
70/30/fcd473802ab9a2e837aedcdb0505936b592a_3/1000">L1001" class="line" namon>L1001">10016/a>                6a href="+code=scrubrates" class="sref">scrubrates6/a> = 6a href="+code=scrubrates_e752x" class="sref">scrubrates_e752x6/a>;
L1002" class="line" namon>L1002">10026/a>
L1003" class="line" namon>L1003">10036/a>        6spa  class="comment">/* Translate the desired scrub rate to a e752x/3100 register value.6/spa >
L1004" class="line" namon>L1004">10046/a>6spa  class="comment">         * Search for the bandwidth that is equal or greater than the6/spa >
L1005" class="line" namon>L1005">10056/a>6spa  class="comment">         * desired rate and program the cooresponding register value.6/spa >
L1006" class="line" namon>L1006">10066/a>6spa  class="comment">         */6/spa >
L1007" class="line" namon>L1007">10076/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a> != 6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>;.6a href="+code=i" class="sref">i6/a>++)
L1008" class="line" namon>L1008">10086/a>                if (6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a> >= 6a href="+code=new_bw" class="sref">new_bw6/a>)
L1009" class="line" namon>L1009">10096/a>                        break;
L1010" class="line" namon>L1010">10106/a>
L1011" class="line" namon>L1011">10116/a>        if (6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a> == 6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>)
L1012" class="line" namon>L1012">10126/a>                return.-1;
L1013" class="line" namon>L1013">10136/a>
L1014" class="line" namon>L1014">10146/a>        6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_MCHSCRB" class="sref">E752X_MCHSCRB6/a>, 6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=scrubval" class="sref">scrubval6/a>);
L1015" class="line" namon>L1015">10156/a>
L1016" class="line" namon>L1016">10166/a>        return.6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a>;
L1017" class="line" namon>L1017">10176/a>}
L1018" class="line" namon>L1018">10186/a>
L1019" class="line" namon>L1019">10196/a>6spa  class="comment">/* Convert current scrub rate value into byte/sec bandwidth */6/spa >
L1020" class="line" namon>L1020">10206/a>static int.6a href="+code=get_sdram_scrub_rate" class="sref">get_sdram_scrub_rate6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>)
L1021" class="line" namon>L1021">10216/a>{
L1022" class="line" namon>L1022">10226/a>        const struct.6a href="+code=scrubrate" class="sref">scrubrate6/a> *6a href="+code=scrubrates" class="sref">scrubrates6/a>;
L1023" class="line" namon>L1023">10236/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *).6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L1024" class="line" namon>L1024">10246/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f0" class="sref">dev_d0f06/a>;
L1025" class="line" namon>L1025">10256/a>        6a href="+code=u16" class="sref">u166/a> 6a href="+code=scrubval" class="sref">scrubval6/a>;
L1026" class="line" namon>L1026">10266/a>        int.6a href="+code=i" class="sref">i6/a>;
L1027" class="line" namon>L1027">10276/a>
L1028" class="line" namon>L1028">10286/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=ctl_dev" class="sref">ctl_dev6/a> == 6a href="+code=PCI_DEVICE_ID_INTEL_3100_0" class="sref">PCI_DEVICE_ID_INTEL_3100_06/a>)
L1029" class="line" namon>L1029">10296/a>                6a href="+code=scrubrates" class="sref">scrubrates6/a> = 6a href="+code=scrubrates_i3100" class="sref">scrubrates_i31006/a>;
L1030" class="line" namon>L1030">10306/a>        else
L1031" class="line" namon>L1031">10316/a>                6a href="+code=scrubrates" class="sref">scrubrates6/a> = 6a href="+code=scrubrates_e752x" class="sref">scrubrates_e752x6/a>;
L1032" class="line" namon>L1032">10326/a>
L1033" class="line" namon>L1033">10336/a>        6spa  class="comment">/* Find the bandwidth matching the memory scrubber configuration */6/spa >
L1034" class="line" namon>L1034">10346/a>        6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_MCHSCRB" class="sref">E752X_MCHSCRB6/a>, &6a href="+code=scrubval" class="sref">scrubval6/a>);
L1035" class="line" namon>L1035">10356/a>        6a href="+code=scrubval" class="sref">scrubval6/a> = 6a href="+code=scrubval" class="sref">scrubval6/a> & 0x0f;
L1036" class="line" namon>L1036">10366/a>
L1037" class="line" namon>L1037">10376/a>        for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a> != 6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>;.6a href="+code=i" class="sref">i6/a>++)
L1038" class="line" namon>L1038">10386/a>                if (6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=scrubval" class="sref">scrubval6/a> == 6a href="+code=scrubval" class="sref">scrubval6/a>)
L1039" class="line" namon>L1039">10396/a>                        break;
L1040" class="line" namon>L1040">10406/a>
L1041" class="line" namon>L1041">10416/a>        if (6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a> == 6a href="+code=SDRATE_EOT" class="sref">SDRATE_EOT6/a>) {
L1042" class="line" namon>L1042">10426/a>                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>,
L1043" class="line" namon>L1043">10436/a>                        6spa  class="string">"Invalid sdram scrub control value: 0x%x\n"6/spa >, 6a href="+code=scrubval" class="sref">scrubval6/a>);
L1044" class="line" namon>L1044">10446/a>                return.-1;
L1045" class="line" namon>L1045">10456/a>        }
L1046" class="line" namon>L1046">10466/a>        return.6a href="+code=scrubrates" class="sref">scrubrates6/a>[6a href="+code=i" class="sref">i6/a>].6a href="+code=bandwidth" class="sref">bandwidth6/a>;
L1047" class="line" namon>L1047">10476/a>
L1048" class="line" namon>L1048">10486/a>}
L1049" class="line" namon>L1049">10496/a>
L1050" class="line" namon>L1050">10506/a>6spa  class="comment">/* Return.1 if dual channel mode is active.  Else return.0. */6/spa >
L1051" class="line" namon>L1051">10516/a>static 6a href="+code=inline" class="sref">inline6/a> int.6a href="+code=dual_channel_active" class="sref">dual_channel_active6/a>(6a href="+code=u16" class="sref">u166/a> 6a href="+code=ddrcsr" class="sref">ddrcsr6/a>)
L1052" class="line" namon>L1052">10526/a>{
L1053" class="line" namon>L1053">10536/a>        return.(((6a href="+code=ddrcsr" class="sref">ddrcsr6/a> >> 12) & 3) == 3);
L1054" class="line" namon>L1054">10546/a>}
L1055" class="line" namon>L1055">10556/a>
L1056" class="line" namon>L1056">10566/a>6spa  class="comment">/* Remap csrow index numbers if map_type is "reverse"6/spa >
L1057" class="line" namon>L1057">10576/a>6spa  class="comment"> */6/spa >
L1058" class="line" namon>L1058">10586/a>static 6a href="+code=inline" class="sref">inline6/a> int.6a href="+code=remap_csrow_index" class="sref">remap_csrow_index6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, int.6a href="+code=index" class="sref">index6/a>)
L1059" class="line" namon>L1059">10596/a>{
L1060" class="line" namon>L1060">10606/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a> = 6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L1061" class="line" namon>L1061">10616/a>
L1062" class="line" namon>L1062">10626/a>        if (!6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map_type" class="sref">map_type6/a>)
L1063" class="line" namon>L1063">10636/a>                return.(7 -.6a href="+code=index" class="sref">index6/a>);
L1064" class="line" namon>L1064">10646/a>
L1065" class="line" namon>L1065">10656/a>        return.(6a href="+code=index" class="sref">index6/a>);
L1066" class="line" namon>L1066">10666/a>}
L1067" class="line" namon>L1067">10676/a>
L1068" class="line" namon>L1068">10686/a>static void 6a href="+code=e752x_init_csrows" class="sref">e752x_init_csrows6/a>(struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>, struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>,
L1069" class="line" namon>L1069">10696/a>                        6a href="+code=u16" class="sref">u166/a> 6a href="+code=ddrcsr" class="sref">ddrcsr6/a>)
L1070" class="line" namon>L1070">10706/a>{
L1071" class="line" namon>L1071">10716/a>        struct.6a href="+code=csrow_info" class="sref">csrow_info6/a> *6a href="+code=csrow" class="sref">csrow6/a>;
L1072" class="line" namon>L1072">10726/a>        enum 6a href="+code=edac_type" class="sref">edac_type6/a> 6a href="+code=edac_mode" class="sref">edac_mode6/a>;
L1073" class="line" namon>L1073">10736/a>        unsigned long 6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a>;
L1074" class="line" namon>L1074">10746/a>        int.6a href="+code=index" class="sref">index6/a>, 6a href="+code=mem_dev" class="sref">mem_dev6/a>, 6a href="+code=drc_chan" class="sref">drc_chan6/a>;
L1075" class="line" namon>L1075">10756/a>        int.6a href="+code=drc_drbg" class="sref">drc_drbg6/a>;.          6spa  class="comment">/* DRB granularity 0=64mb, 1=128mb */6/spa >
L1076" class="line" namon>L1076">10766/a>        int.6a href="+code=drc_ddim" class="sref">drc_ddim6/a>;.          6spa  class="comment">/* DRAM Data Integrity Mode 0=none, 2=edac */6/spa >
L1077" class="line" namon>L1077">10776/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=value" class="sref">value6/a>;
L1078" class="line" namon>L1078">10786/a>        6a href="+code=u32" class="sref">u326/a> 6a href="+code=dra" class="sref">dra6/a>, 6a href="+code=drc" class="sref">drc6/a>, 6a href="+code=cumul_size" class="sref">cumul_size6/a>, 6a href="+code=i" class="sref">i6/a>, 6a href="+code=nr_pages" class="sref">nr_pages6/a>;
L1079" class="line" namon>L1079">10796/a>
L1080" class="line" namon>L1080">10806/a>        6a href="+code=dra" class="sref">dra6/a> = 0;
L1081" class="line" namon>L1081">10816/a>        for (6a href="+code=index" class="sref">index6/a> = 0; 6a href="+code=index" class="sref">index6/a> < 4; 6a href="+code=index" class="sref">index6/a>++) {
L1082" class="line" namon>L1082">10826/a>                6a href="+code=u8" class="sref">u86/a> 6a href="+code=dra_reg" class="sref">dra_reg6/a>;
L1083" class="line" namon>L1083">10836/a>                6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRA" class="sref">E752X_DRA6/a> +.6a href="+code=index" class="sref">index6/a>, &6a href="+code=dra_reg" class="sref">dra_reg6/a>);
L1084" class="line" namon>L1084">10846/a>                6a href="+code=dra" class="sref">dra6/a> |= 6a href="+code=dra_reg" class="sref">dra_reg6/a> << (6a href="+code=index" class="sref">index6/a> * 8);
L1085" class="line" namon>L1085">10856/a>        }
L1086" class="line" namon>L1086">10866/a>        6a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRC" class="sref">E752X_DRC6/a>, &6a href="+code=drc" class="sref">drc6/a>);
L1087" class="line" namon>L1087">10876/a>        6a href="+code=drc_chan" class="sref">drc_chan6/a> = 6a href="+code=dual_channel_active" class="sref">dual_channel_active6/a>(6a href="+code=ddrcsr" class="sref">ddrcsr6/a>) ? 1 : 0;
L1088" class="line" namon>L1088">10886/a>        6a href="+code=drc_drbg" class="sref">drc_drbg6/a> = 6a href="+code=drc_chan" class="sref">drc_chan6/a> + 1;.       6spa  class="comment">/* 128 in dual mode, 64 in single */6/spa >
L1089" class="line" namon>L1089">10896/a>        6a href="+code=drc_ddim" class="sref">drc_ddim6/a> = (6a href="+code=drc" class="sref">drc6/a> >> 20) & 0x3;
L1090" class="line" namon>L1090">10906/a>
L1091" class="line" namon>L1091">10916/a>        6spa  class="comment">/* The dram row boundary (DRB) reg values are boundary address for6/spa >
L1092" class="line" namon>L1092">10926/a>6spa  class="comment">         * each DRAM row with a granularity of 64 or 128MB (single/dual6/spa >
L1093" class="line" namon>L1093">10936/a>6spa  class="comment">         * channel operation).  DRB regs are cumulative; therefore DRB7 will6/spa >
L1094" class="line" namon>L1094">10946/a>6spa  class="comment">         * contain the total memory contained in all eight rows.6/spa >
L1095" class="line" namon>L1095">10956/a>6spa  class="comment">         */6/spa >
L1096" class="line" namon>L1096">10966/a>        for (6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a> = 6a href="+code=index" class="sref">index6/a> = 0; 6a href="+code=index" class="sref">index6/a> < 6a href="+code=mci" class="sref">mci6/a>->6a href="+code=nr_csrows" class="sref">nr_csrows6/a>;.6a href="+code=index" class="sref">index6/a>++) {
L1097" class="line" namon>L1097">10976/a>                6spa  class="comment">/* mem_dev 0=x8, 1=x4 */6/spa >
L1098" class="line" namon>L1098">10986/a>                6a href="+code=mem_dev" class="sref">mem_dev6/a> = (6a href="+code=dra" class="sref">dra6/a> >> (6a href="+code=index" class="sref">index6/a> * 4 + 2)) & 0x3;
L1099" class="line" namon>L1099">10996/a>                6a href="+code=csrow" class="sref">csrow6/a> = 6a href="+code=mci" class="sref">mci6/a>->6a href="+code=csrows" class="sref">csrows6/a>[6a href="+code=remap_csrow_index" class="sref">remap_csrow_index6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=index" class="sref">index6/a>)];
L1100" class="line" namon>L1100">11006/a>
L1101" class="line" namon>L1101">11016/a>                6a href="+code=mem_dev" class="sref">mem_dev6/a> = (6a href="+code=mem_dev" class="sref">mem_dev6/a> == 2);
L1102" class="line" namon>L1102">11026/a>                6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRB" class="sref">E752X_DRB6/a> +.6a href="+code=index" class="sref">index6/a>, &6a href="+code=value" class="sref">value6/a>);
L1103" class="line" namon>L1103">11036/a>                6spa  class="comment">/* convert a 128 or 64 MiB DRB to a page size. */6/spa >
L1104" class="line" namon>L1104">11046/a>                6a href="+code=cumul_size" class="sref">cumul_size6/a> = 6a href="+code=value" class="sref">value6/a> << (25 +.6a href="+code=drc_drbg" class="sref">drc_drbg6/a> -.6a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT6/a>);
L1105" class="line" namon>L1105">11056/a>                6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"(%d) cumul_size 0x%x\n"6/spa >, 6a href="+code=index" class="sref">index6/a>, 6a href="+code=cumul_size" class="sref">cumul_size6/a>);
L1106" class="line" namon>L1106">11066/a>                if (6a href="+code=cumul_size" class="sref">cumul_size6/a> == 6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a>)
L1107" class="line" namon>L1107">11076/a>                        continue;.      6spa  class="comment">/* not populated */6/spa >
L1108" class="line" namon>L1108">11086/a>
L1109" class="line" namon>L1109">11096/a>                6a href="+code=csrow" class="sref">csrow6/a>->6a href="+code=first_page" class="sref">first_page6/a> = 6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a>;
L1110" class="line" namon>L1110">11106/a>                6a href="+code=csrow" class="sref">csrow6/a>->6a href="+code=last_page" class="sref">last_page6/a> = 6a href="+code=cumul_size" class="sref">cumul_size6/a> - 1;
L1111" class="line" namon>L1111">11116/a>                6a href="+code=nr_pages" class="sref">nr_pages6/a> = 6a href="+code=cumul_size" class="sref">cumul_size6/a> - 6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a>;
L1112" class="line" namon>L1112">11126/a>                6a href="+code=last_cumul_size" class="sref">last_cumul_size6/a> = 6a href="+code=cumul_size" class="sref">cumul_size6/a>;
L1113" class="line" namon>L1113">11136/a>
L1114" class="line" namon>L1114">11146/a>                6spa  class="comment">/*6/spa >
L1115" class="line" namon>L1115">11156/a>6spa  class="comment">                * if single channel or x8 devices then SECDED6/spa >
L1116" class="line" namon>L1116">11166/a>6spa  class="comment">                * if dual channel and x4 then S4ECD4ED6/spa >
L1117" class="line" namon>L1117">11176/a>6spa  class="comment">                */6/spa >
L1118" class="line" namon>L1118">11186/a>                if (6a href="+code=drc_ddim" class="sref">drc_ddim6/a>) {
L1119" class="line" namon>L1119">11196/a>                        if (6a href="+code=drc_chan" class="sref">drc_chan6/a> && 6a href="+code=mem_dev" class="sref">mem_dev6/a>) {
L1120" class="line" namon>L1120">11206/a>                                6a href="+code=edac_mode" class="sref">edac_mode6/a> = 6a href="+code=EDAC_S4ECD4ED" class="sref">EDAC_S4ECD4ED6/a>;
L1121" class="line" namon>L1121">11216/a>                                6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_cap" class="sref">edac_cap6/a> |= 6a href="+code=EDAC_FLAG_S4ECD4ED" class="sref">EDAC_FLAG_S4ECD4ED6/a>;
L1122" class="line" namon>L1122">11226/a>                        } else {
L1123" class="line" namon>L1123">11236/a>                                6a href="+code=edac_mode" class="sref">edac_mode6/a> = 6a href="+code=EDAC_SECDED" class="sref">EDAC_SECDED6/a>;
L1124" class="line" namon>L1124">11246/a>                                6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_cap" class="sref">edac_cap6/a> |= 6a href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDED6/a>;
L1125" class="line" namon>L1125">11256/a>                        }
L1126" class="line" namon>L1126">11266/a>                } else
L1127" class="line" namon>L1127">11276/a>                        6a href="+code=edac_mode" class="sref">edac_mode6/a> = 6a href="+code=EDAC_NONE" class="sref">EDAC_NONE6/a>;
L1128" class="line" namon>L1128">11286/a>                for (6a href="+code=i" class="sref">i6/a> = 0; 6a href="+code=i" class="sref">i6/a> < 6a href="+code=csrow" class="sref">csrow6/a>->6a href="+code=nr_channels" class="sref">nr_channels6/a>;.6a href="+code=i" class="sref">i6/a>++) {
L1129" class="line" namon>L1129">11296/a>                        struct.6a href="+code=dimm_info" class="sref">dimm_info6/a> *6a href="+code=dimm" class="sref">dimm6/a> = 6a href="+code=csrow" class="sref">csrow6/a>->6a href="+code=channels" class="sref">channels6/a>[6a href="+code=i" class="sref">i6/a>]->6a href="+code=dimm" class="sref">dimm6/a>;
L1130" class="line" namon>L1130">11306/a>
L1131" class="line" namon>L1131">11316/a>                        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"Initializing rank at (%i,%i)\n"6/spa >, 6a href="+code=index" class="sref">index6/a>, 6a href="+code=i" class="sref">i6/a>);
L1132" class="line" namon>L1132">11326/a>                        6a href="+code=dimm" class="sref">dimm6/a>->6a href="+code=nr_pages" class="sref">nr_pages6/a> = 6a href="+code=nr_pages" class="sref">nr_pages6/a> / 6a href="+code=csrow" class="sref">csrow6/a>->6a href="+code=nr_channels" class="sref">nr_channels6/a>;
L1133" class="line" namon>L1133">11336/a>                        6a href="+code=dimm" class="sref">dimm6/a>->6a href="+code=grain" class="sref">grain6/a> = 1 << 12;  6spa  class="comment">/* 4KiB - resolution of CELOG */6/spa >
L1134" class="line" namon>L1134">11346/a>                        6a href="+code=dimm" class="sref">dimm6/a>->6a href="+code=mtype" class="sref">mtype6/a> = 6a href="+code=MEM_RDDR" class="sref">MEM_RDDR6/a>;.6spa  class="comment">/* only one type supported */6/spa >
L1135" class="line" namon>L1135">11356/a>                        6a href="+code=dimm" class="sref">dimm6/a>->6a href="+code=dtype" class="sref">dtype6/a> = 6a href="+code=mem_dev" class="sref">mem_dev6/a> ? 6a href="+code=DEV_X4" class="sref">DEV_X46/a> : 6a href="+code=DEV_X8" class="sref">DEV_X86/a>;
L1136" class="line" namon>L1136">11366/a>                        6a href="+code=dimm" class="sref">dimm6/a>->6a href="+code=edac_mode" class="sref">edac_mode6/a> = 6a href="+code=edac_mode" class="sref">edac_mode6/a>;
L1137" class="line" namon>L1137">11376/a>                }
L1138" class="line" namon>L1138">11386/a>        }
L1139" class="line" namon>L1139">11396/a>}
L1140" class="line" namon>L1140">11406/a>
L1141" class="line" namon>L1141">11416/a>static void 6a href="+code=e752x_init_mem_map_table" class="sref">e752x_init_mem_map_table6/a>(struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>,
L1142" class="line" namon>L1142">11426/a>                                struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>)
L1143" class="line" namon>L1143">11436/a>{
L1144" class="line" namon>L1144">11446/a>        int.6a href="+code=index" class="sref">index6/a>;
L1145" class="line" namon>L1145">11456/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=value" class="sref">value6/a>, 6a href="+code=last" class="sref">last6/a>, 6a href="+code=row" class="sref">row6/a>;
L1146" class="line" namon>L1146">11466/a>
L1147" class="line" namon>L1147">11476/a>        6a href="+code=last" class="sref">last6/a> = 0;
L1148" class="line" namon>L1148">11486/a>        6a href="+code=row" class="sref">row6/a> = 0;
L1149" class="line" namon>L1149">11496/a>
L1150" class="line" namon>L1150">11506/a>        for (6a href="+code=index" class="sref">index6/a> = 0; 6a href="+code=index" class="sref">index6/a> < 8; 6a href="+code=index" class="sref">index6/a> += 2) {
L1151" class="line" namon>L1151">11516/a>                6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRB" class="sref">E752X_DRB6/a> +.6a href="+code=index" class="sref">index6/a>, &6a href="+code=value" class="sref">value6/a>);
L1152" class="line" namon>L1152">11526/a>                6spa  class="comment">/* test if there is a dimm in this slot */6/spa >
L1153" class="line" namon>L1153">11536/a>                if (6a href="+code=value" class="sref">value6/a> == 6a href="+code=last" class="sref">last6/a>) {
L1154" class="line" namon>L1154">11546/a>                        6spa  class="comment">/* no dimm in the slot, so flag it as empty */6/spa >
L1155" class="line" namon>L1155">11556/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6a href="+code=index" class="sref">index6/a>] = 0xff;
L1156" class="line" namon>L1156">11566/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6a href="+code=index" class="sref">index6/a> + 1] = 0xff;
L1157" class="line" namon>L1157">11576/a>                } else {        6spa  class="comment">/* there is a dimm in the slot */6/spa >
L1158" class="line" namon>L1158">11586/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6a href="+code=index" class="sref">index6/a>] = 6a href="+code=row" class="sref">row6/a>;
L1159" class="line" namon>L1159">11596/a>                        6a href="+code=row" class="sref">row6/a>++;
L1160" class="line" namon>L1160">11606/a>                        6a href="+code=last" class="sref">last6/a> = 6a href="+code=value" class="sref">value6/a>;
L1161" class="line" namon>L1161">11616/a>                        6spa  class="comment">/* test the next value to see if the dimm is double6/spa >
L1162" class="line" namon>L1162">11626/a>6spa  class="comment">                         * sided6/spa >
L1163" class="line" namon>L1163">11636/a>6spa  class="comment">                         */6/spa >
L1164" class="line" namon>L1164">11646/a>                        6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRB" class="sref">E752X_DRB6/a> +.6a href="+code=index" class="sref">index6/a> + 1,
L1165" class="line" namon>L1165">11656/a>                                        &6a href="+code=value" class="sref">value6/a>);
L1166" class="line" namon>L1166">11666/a>
L1167" class="line" namon>L1167">11676/a>                        6spa  class="comment">/* the dimm is single sided, so flag as empty */6/spa >
L1168" class="line" namon>L1168">11686/a>                        6spa  class="comment">/* this is a double sided dimm to save the next row #*/6/spa >
L1169" class="line" namon>L1169">11696/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map" class="sref">map6/a>[6a href="+code=index" class="sref">index6/a> + 1] = (6a href="+code=value" class="sref">value6/a> == 6a href="+code=last" class="sref">last6/a>) ? 0xff :  6a href="+code=row" class="sref">row6/a>;
L1170" class="line" namon>L1170">11706/a>                        6a href="+code=row" class="sref">row6/a>++;
L1171" class="line" namon>L1171">11716/a>                        6a href="+code=last" class="sref">last6/a> = 6a href="+code=value" class="sref">value6/a>;
L1172" class="line" namon>L1172">11726/a>                }
L1173" class="line" namon>L1173">11736/a>        }
L1174" class="line" namon>L1174">11746/a>}
L1175" class="line" namon>L1175">11756/a>
L1176" class="line" namon>L1176">11766/a>6spa  class="comment">/* Return.0 on success or 1 on failure. */6/spa >
L1177" class="line" namon>L1177">11776/a>static int.6a href="+code=e752x_get_devs" class="sref">e752x_get_devs6/a>(struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>, int.6a href="+code=dev_idx" class="sref">dev_idx6/a>,
L1178" class="line" namon>L1178">11786/a>                        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>)
L1179" class="line" namon>L1179">11796/a>{
L1180" class="line" namon>L1180">11806/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev" class="sref">dev6/a>;
L1181" class="line" namon>L1181">11816/a>
L1182" class="line" namon>L1182">11826/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a> = 6a href="+code=pci_get_device" class="sref">pci_get_device6/a>(6a href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTEL6/a>,
L1183" class="line" namon>L1183">11836/a>                                6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=err_dev" class="sref">err_dev6/a>, 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>);
L1184" class="line" namon>L1184">11846/a>
L1185" class="line" namon>L1185">11856/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a> == 6a href="+code=NULL" class="sref">NULL6/a>)
L1186" class="line" namon>L1186">11866/a>                6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a> = 6a href="+code=pci_scan_single_device" class="sref">pci_scan_single_device6/a>(6a href="+code=pdev" class="sref">pdev6/a>->6a href="+code=bus" class="sref">bus6/a>,
L1187" class="line" namon>L1187">11876/a>                                                        6a href="+code=PCI_DEVFN" class="sref">PCI_DEVFN6/a>(0, 1));
L1188" class="line" namon>L1188">11886/a>
L1189" class="line" namon>L1189">11896/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a> == 6a href="+code=NULL" class="sref">NULL6/a>) {
L1190" class="line" namon>L1190">11906/a>                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_ERR" class="sref">KERN_ERR6/a>, 6spa  class="string">"error reporting device not found:"6/spa >
L1191" class="line" namon>L1191">11916/a>                        6spa  class="string">"vendor %x device 0x%x (broken BIOS?)\n"6/spa >,
L1192" class="line" namon>L1192">11926/a>                        6a href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTEL6/a>, 6a href="+code=e752x_devs" class="sref">e752x_devs6/a>[6a href="+code=dev_idx" class="sref">dev_idx6/a>].6a href="+code=err_dev" class="sref">err_dev6/a>);
L1193" class="line" namon>L1193">11936/a>                return.1;
L1194" class="line" namon>L1194">11946/a>        }
L1195" class="line" namon>L1195">11956/a>
L1196" class="line" namon>L1196">11966/a>        6a href="+code=dev" class="sref">dev6/a> = 6a href="+code=pci_get_device" class="sref">pci_get_device6/a>(6a href="+code=PCI_VENDOR_ID_INTEL" class="sref">PCI_VENDOR_ID_INTEL6/a>,
L1197" class="line" namon>L1197">11976/a>                                6a href="+code=e752x_devs" class="sref">e752x_devs6/a>[6a href="+code=dev_idx" class="sref">dev_idx6/a>].6a href="+code=ctl_dev" class="sref">ctl_dev6/a>,
L1198" class="line" namon>L1198">11986/a>                                6a href="+code=NULL" class="sref">NULL6/a>);
L1199" class="line" namon>L1199">11996/a>
L1200" class="line" namon>L1200">12006/a>        if (6a href="+code=dev" class="sref">dev6/a> == 6a href="+code=NULL" class="sref">NULL6/a>)
L1201" class="line" namon>L1201">12016/a>                goto 6a href="+code=fail" class="sref">fail6/a>;
L1202" class="line" namon>L1202">12026/a>
L1203" class="line" namon>L1203">12036/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f0" class="sref">dev_d0f06/a> = 6a href="+code=dev" class="sref">dev6/a>;
L1204" class="line" namon>L1204">12046/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a> = 6a href="+code=pci_dev_get" class="sref">pci_dev_get6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>);
L1205" class="line" namon>L1205">12056/a>
L1206" class="line" namon>L1206">12066/a>        return.0;
L1207" class="line" namon>L1207">12076/a>
L1208" class="line" namon>L1208">12086/a>6a href="+code=fail" class="sref">fail6/a>:
L1209" class="line" namon>L1209">12096/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>);
L1210" class="line" namon>L1210">12106/a>        return.1;
L1211" class="line" namon>L1211">12116/a>}
L1212" class="line" namon>L1212">12126/a>
L1213" class="line" namon>L1213">12136/a>6spa  class="comment">/* Setup system bus parity mask register.6/spa >
L1214" class="line" namon>L1214">12146/a>6spa  class="comment"> * Sysbus parity supported on:6/spa >
L1215" class="line" namon>L1215">12156/a>6spa  class="comment"> * e7320/e7520/e7525 +.Xeon6/spa >
L1216" class="line" namon>L1216">12166/a>6spa  class="comment"> */6/spa >
L1217" class="line" namon>L1217">12176/a>static void 6a href="+code=e752x_init_sysbus_parity_mask" class="sref">e752x_init_sysbus_parity_mask6/a>(struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>)
L1218" class="line" namon>L1218">12186/a>{
L1219" class="line" namon>L1219">12196/a>        char *6a href="+code=cpu_id" class="sref">cpu_id6/a> = 6a href="+code=cpu_data" class="sref">cpu_data6/a>(0).6a href="+code=x86_model_id" class="sref">x86_model_id6/a>;
L1220" class="line" namon>L1220">12206/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev" class="sref">dev6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>;
L1221" class="line" namon>L1221">12216/a>        int.6a href="+code=enable" class="sref">enable6/a> = 1;
L1222" class="line" namon>L1222">12226/a>
L1223" class="line" namon>L1223">12236/a>        6spa  class="comment">/* Allow module paramoter override, else see if CPU supports parity */6/spa >
L1224" class="line" namon>L1224">12246/a>        if (6a href="+code=sysbus_parity" class="sref">sysbus_parity6/a> != -1) {
L1225" class="line" namon>L1225">12256/a>                6a href="+code=enable" class="sref">enable6/a> = 6a href="+code=sysbus_parity" class="sref">sysbus_parity6/a>;
L1226" class="line" namon>L1226">12266/a>        } else if (6a href="+code=cpu_id" class="sref">cpu_id6/a>[0] && !6a href="+code=strstr" class="sref">strstr6/a>(6a href="+code=cpu_id" class="sref">cpu_id6/a>, 6spa  class="string">"Xeon"6/spa >)) {
L1227" class="line" namon>L1227">12276/a>                6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_INFO" class="sref">KERN_INFO6/a>, 6spa  class="string">"System Bus Parity not "6/spa >
L1228" class="line" namon>L1228">12286/a>                             6spa  class="string">"supported by CPU, disabling\n"6/spa >);
L1229" class="line" namon>L1229">12296/a>                6a href="+code=enable" class="sref">enable6/a> = 0;
L1230" class="line" namon>L1230">12306/a>        }
L1231" class="line" namon>L1231">12316/a>
L1232" class="line" namon>L1232">12326/a>        if (6a href="+code=enable" class="sref">enable6/a>)
L1233" class="line" namon>L1233">12336/a>                6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_ERRMASK" class="sref">E752X_SYSBUS_ERRMASK6/a>, 0x0000);
L1234" class="line" namon>L1234">12346/a>        else
L1235" class="line" namon>L1235">12356/a>                6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_ERRMASK" class="sref">E752X_SYSBUS_ERRMASK6/a>, 0x0309);
L1236" class="line" namon>L1236">12366/a>}
L1237" class="line" namon>L1237">12376/a>
L1238" class="line" namon>L1238">12386/a>static void 6a href="+code=e752x_init_error_reporting_regs" class="sref">e752x_init_error_reporting_regs6/a>(struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>)
L1239" class="line" namon>L1239">12396/a>{
L1240" class="line" namon>L1240">12406/a>        struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=dev" class="sref">dev6/a>;
L1241" class="line" namon>L1241">12416/a>
L1242" class="line" namon>L1242">12426/a>        6a href="+code=dev" class="sref">dev6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>;
L1243" class="line" namon>L1243">12436/a>        6spa  class="comment">/* Turn.off error disable & SMI in case the BIOS turned it on */6/spa >
L1244" class="line" namon>L1244">12446/a>        if (6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=err_dev" class="sref">err_dev6/a> == 6a href="+code=PCI_DEVICE_ID_INTEL_3100_1_ERR" class="sref">PCI_DEVICE_ID_INTEL_3100_1_ERR6/a>) {
L1245" class="line" namon>L1245">12456/a>                6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_EMASK" class="sref">I3100_NSI_EMASK6/a>, 0);
L1246" class="line" namon>L1246">12466/a>                6a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=I3100_NSI_SMICMD" class="sref">I3100_NSI_SMICMD6/a>, 0);
L1247" class="line" namon>L1247">12476/a>        } else {
L1248" class="line" namon>L1248">12486/a>                6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_ERRMASK" class="sref">E752X_HI_ERRMASK6/a>, 0x00);
L1249" class="line" namon>L1249">12496/a>                6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_HI_SMICMD" class="sref">E752X_HI_SMICMD6/a>, 0x00);
L1250" class="line" namon>L1250">12506/a>        }
L1251" class="line" namon>L1251">12516/a>
L1252" class="line" namon>L1252">12526/a>        6a href="+code=e752x_init_sysbus_parity_mask" class="sref">e752x_init_sysbus_parity_mask6/a>(6a href="+code=pvt" class="sref">pvt6/a>);
L1253" class="line" namon>L1253">12536/a>
L1254" class="line" namon>L1254">12546/a>        6a href="+code=pci_write_config_word" class="sref">pci_write_config_word6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_SYSBUS_SMICMD" class="sref">E752X_SYSBUS_SMICMD6/a>, 0x00);
L1255" class="line" namon>L1255">12556/a>        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_ERRMASK" class="sref">E752X_BUF_ERRMASK6/a>, 0x00);
L1256" class="line" namon>L1256">12566/a>        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_BUF_SMICMD" class="sref">E752X_BUF_SMICMD6/a>, 0x00);
L1257" class="line" namon>L1257">12576/a>        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_ERRMASK" class="sref">E752X_DRAM_ERRMASK6/a>, 0x00);
L1258" class="line" namon>L1258">12586/a>        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=E752X_DRAM_SMICMD" class="sref">E752X_DRAM_SMICMD6/a>, 0x00);
L1259" class="line" namon>L1259">12596/a>}
L1260" class="line" namon>L1260">12606/a>
L1261" class="line" namon>L1261">12616/a>static int.6a href="+code=e752x_probe1" class="sref">e752x_probe16/a>(struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>, int.6a href="+code=dev_idx" class="sref">dev_idx6/a>)
L1262" class="line" namon>L1262">12626/a>{
L1263" class="line" namon>L1263">12636/a>        6a href="+code=u16" class="sref">u166/a>.6a href="+code=pci_data" class="sref">pci_data6/a>;
L1264" class="line" namon>L1264">12646/a>        6a href="+code=u8" class="sref">u86/a> 6a href="+code=stat8" class="sref">stat86/a>;
L1265" class="line" namon>L1265">12656/a>        struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>;
L1266" class="line" namon>L1266">12666/a>        struct.6a href="+code=edac_mc_layer" class="sref">edac_mc_layer6/a> 6a href="+code=layers" class="sref">layers6/a>[2];
L1267" class="line" namon>L1267">12676/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>;
L1268" class="line" namon>L1268">12686/a>        6a href="+code=u16" class="sref">u166/a>.6a href="+code=ddrcsr" class="sref">ddrcsr6/a>;
L1269" class="line" namon>L1269">12696/a>        int.6a href="+code=drc_chan" class="sref">drc_chan6/a>;.          6spa  class="comment">/* Number of channels 0=1chan,1=2chan */6/spa >
L1270" class="line" namon>L1270">12706/a>        struct.6a href="+code=e752x_error_info" class="sref">e752x_error_info6/a>.6a href="+code=discard" class="sref">discard6/a>;
L1271" class="line" namon>L1271">12716/a>
L1272" class="line" namon>L1272">12726/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(0, 6spa  class="string">"mci\n"6/spa >);
L1273" class="line" namon>L1273">12736/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(0, 6spa  class="string">"Starting Probe1\n"6/spa >);
L1274" class="line" namon>L1274">12746/a>
L1275" class="line" namon>L1275">12756/a>        6spa  class="comment">/* check to see if device 0 function 1 is enabled; if it isn't, we6/spa >
L1276" class="line" namon>L1276">12766/a>6spa  class="comment">         * assume the BIOS has reserved it for a reason and is expecting6/spa >
L1277" class="line" namon>L1277">12776/a>6spa  class="comment">         * exclusive access, we take care not to violate that assumption and6/spa >
L1278" class="line" namon>L1278">12786/a>6spa  class="comment">         * fail the probe. */6/spa >
L1279" class="line" namon>L1279">12796/a>        6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DEVPRES1" class="sref">E752X_DEVPRES16/a>, &6a href="+code=stat8" class="sref">stat86/a>);
L1280" class="line" namon>L1280">12806/a>        if (!6a href="+code=force_function_unhide" class="sref">force_function_unhide6/a> && !(6a href="+code=stat8" class="sref">stat86/a> & (1 << 5))) {
L1281" class="line" namon>L1281">12816/a>                6a href="+code=printk" class="sref">printk6/a>(6a href="+code=KERN_INFO" class="sref">KERN_INFO6/a> 6spa  class="string">"Contact.your BIOS vendor to see if the "6/spa >
L1282" class="line" namon>L1282">12826/a>                        6spa  class="string">"E752x error registers can be safely un-hidden\n"6/spa >);
L1283" class="line" namon>L1283">12836/a>                return.-6a href="+code=ENODEV" class="sref">ENODEV6/a>;
L1284" class="line" namon>L1284">12846/a>        }
L1285" class="line" namon>L1285">12856/a>        6a href="+code=stat8" class="sref">stat86/a> |= (1 << 5);
L1286" class="line" namon>L1286">12866/a>        6a href="+code=pci_write_config_byte" class="sref">pci_write_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DEVPRES1" class="sref">E752X_DEVPRES16/a>, 6a href="+code=stat8" class="sref">stat86/a>);
L1287" class="line" namon>L1287">12876/a>
L1288" class="line" namon>L1288">12886/a>        6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DDRCSR" class="sref">E752X_DDRCSR6/a>, &6a href="+code=ddrcsr" class="sref">ddrcsr6/a>);
L1289" class="line" namon>L1289">12896/a>        6spa  class="comment">/* FIXME: should check >>12 or 0xf, true for all? */6/spa >
L1290" class="line" namon>L1290">12906/a>        6spa  class="comment">/* Dual channel = 1, Single channel = 0 */6/spa >
L1291" class="line" namon>L1291">12916/a>        6a href="+code=drc_chan" class="sref">drc_chan6/a> = 6a href="+code=dual_channel_active" class="sref">dual_channel_active6/a>(6a href="+code=ddrcsr" class="sref">ddrcsr6/a>);
L1292" class="line" namon>L1292">12926/a>
L1293" class="line" namon>L1293">12936/a>        6a href="+code=layers" class="sref">layers6/a>[0].6a href="+code=type" class="sref">type6/a> = 6a href="+code=EDAC_MC_LAYER_CHIP_SELECT" class="sref">EDAC_MC_LAYER_CHIP_SELECT6/a>;
L1294" class="line" namon>L1294">12946/a>        6a href="+code=layers" class="sref">layers6/a>[0].6a href="+code=size" class="sref">size6/a> = 6a href="+code=E752X_NR_CSROWS" class="sref">E752X_NR_CSROWS6/a>;
L1295" class="line" namon>L1295">12956/a>        6a href="+code=layers" class="sref">layers6/a>[0].6a href="+code=is_virt_csrow" class="sref">is_virt_csrow6/a> = 6a href="+code=true" class="sref">true6/a>;
L1296" class="line" namon>L1296">12966/a>        6a href="+code=layers" class="sref">layers6/a>[1].6a href="+code=type" class="sref">type6/a> = 6a href="+code=EDAC_MC_LAYER_CHANNEL" class="sref">EDAC_MC_LAYER_CHANNEL6/a>;
L1297" class="line" namon>L1297">12976/a>        6a href="+code=layers" class="sref">layers6/a>[1].6a href="+code=size" class="sref">size6/a> = 6a href="+code=drc_chan" class="sref">drc_chan6/a> + 1;
L1298" class="line" namon>L1298">12986/a>        6a href="+code=layers" class="sref">layers6/a>[1].6a href="+code=is_virt_csrow" class="sref">is_virt_csrow6/a> = 6a href="+code=false" class="sref">false6/a>;
L1299" class="line" namon>L1299">12996/a>        6a href="+code=mci" class="sref">mci6/a> = 6a href="+code=edac_mc_alloc" class="sref">edac_mc_alloc6/a>(0, 6a href="+code=ARRAY_SIZE" class="sref">ARRAY_SIZE6/a>(6a href="+code=layers" class="sref">layers6/a>), 6a href="+code=layers" class="sref">layers6/a>, sizeof(*6a href="+code=pvt" class="sref">pvt6/a>));
L1300" class="line" namon>L1300">13006/a>        if (6a href="+code=mci" class="sref">mci6/a> == 6a href="+code=NULL" class="sref">NULL6/a>)
L1301" class="line" namon>L1301">13016/a>                return.-6a href="+code=ENOMEM" class="sref">ENOMEM6/a>;
L1302" class="line" namon>L1302">13026/a>
L1303" class="line" namon>L1303">13036/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"init mci\n"6/spa >);
L1304" class="line" namon>L1304">13046/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=mtype_cap" class="sref">mtype_cap6/a> = 6a href="+code=MEM_FLAG_RDDR" class="sref">MEM_FLAG_RDDR6/a>;
L1305" class="line" namon>L1305">13056/a>        6spa  class="comment">/* 3100 IMCH supports SECDEC only */6/spa >
L1306" class="line" namon>L1306">13066/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_ctl_cap" class="sref">edac_ctl_cap6/a> = (6a href="+code=dev_idx" class="sref">dev_idx6/a> == 6a href="+code=I3100" class="sref">I31006/a>) ? 6a href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDED6/a> :
L1307" class="line" namon>L1307">13076/a>                (6a href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONE6/a> | 6a href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDED6/a> | 6a href="+code=EDAC_FLAG_S4ECD4ED" class="sref">EDAC_FLAG_S4ECD4ED6/a>);
L1308" class="line" namon>L1308">13086/a>        6spa  class="comment">/* FIXME - what if different memory types are in different csrows? */6/spa >
L1309" class="line" namon>L1309">13096/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=mod_namo" class="sref">mod_namo6/a> = 6a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR6/a>;
L1310" class="line" namon>L1310">13106/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=mod_ver" class="sref">mod_ver6/a> = 6a href="+code=E752X_REVISION" class="sref">E752X_REVISION6/a>;
L1311" class="line" namon>L1311">13116/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pdev" class="sref">pdev6/a> = &6a href="+code=pdev" class="sref">pdev6/a>->6a href="+code=dev" class="sref">dev6/a>;
L1312" class="line" namon>L1312">13126/a>
L1313" class="line" namon>L1313">13136/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"init pvt\n"6/spa >);
L1314" class="line" namon>L1314">13146/a>        6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L1315" class="line" namon>L1315">13156/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a> = &6a href="+code=e752x_devs" class="sref">e752x_devs6/a>[6a href="+code=dev_idx" class="sref">dev_idx6/a>];
L1316" class="line" namon>L1316">13166/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=mc_symmetric" class="sref">mc_symmetric6/a> = ((6a href="+code=ddrcsr" class="sref">ddrcsr6/a> & 0x10) != 0);
L1317" class="line" namon>L1317">13176/a>
L1318" class="line" namon>L1318">13186/a>        if (6a href="+code=e752x_get_devs" class="sref">e752x_get_devs6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=dev_idx" class="sref">dev_idx6/a>, 6a href="+code=pvt" class="sref">pvt6/a>)) {
L1319" class="line" namon>L1319">13196/a>                6a href="+code=edac_mc_free" class="sref">edac_mc_free6/a>(6a href="+code=mci" class="sref">mci6/a>);
L1320" class="line" namon>L1320">13206/a>                return.-6a href="+code=ENODEV" class="sref">ENODEV6/a>;
L1321" class="line" namon>L1321">13216/a>        }
L1322" class="line" namon>L1322">13226/a>
L1323" class="line" namon>L1323">13236/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"more mci init\n"6/spa >);
L1324" class="line" namon>L1324">13246/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=ctl_namo" class="sref">ctl_namo6/a> = 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_info" class="sref">dev_info6/a>->6a href="+code=ctl_namo" class="sref">ctl_namo6/a>;
L1325" class="line" namon>L1325">13256/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=dev_namo" class="sref">dev_namo6/a> = 6a href="+code=pci_namo" class="sref">pci_namo6/a>(6a href="+code=pdev" class="sref">pdev6/a>);
L1326" class="line" namon>L1326">13266/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_check" class="sref">edac_check6/a> = 6a href="+code=e752x_check" class="sref">e752x_check6/a>;
L1327" class="line" namon>L1327">13276/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=ctl_page_to_phys" class="sref">ctl_page_to_phys6/a> = 6a href="+code=ctl_page_to_phys" class="sref">ctl_page_to_phys6/a>;
L1328" class="line" namon>L1328">13286/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=set_sdram_scrub_rate" class="sref">set_sdram_scrub_rate6/a> = 6a href="+code=set_sdram_scrub_rate" class="sref">set_sdram_scrub_rate6/a>;
L1329" class="line" namon>L1329">13296/a>        6a href="+code=mci" class="sref">mci6/a>->6a href="+code=get_sdram_scrub_rate" class="sref">get_sdram_scrub_rate6/a> = 6a href="+code=get_sdram_scrub_rate" class="sref">get_sdram_scrub_rate6/a>;
L1330" class="line" namon>L1330">13306/a>
L1331" class="line" namon>L1331">13316/a>        6spa  class="comment">/* set the map type.  1 = normal, 0 = reversed6/spa >
L1332" class="line" namon>L1332">13326/a>6spa  class="comment">         * Must be set before e752x_init_csrows in case csrow mapping6/spa >
L1333" class="line" namon>L1333">13336/a>6spa  class="comment">         * is reversed.6/spa >
L1334" class="line" namon>L1334">13346/a>6spa  class="comment">         */6/spa >
L1335" class="line" namon>L1335">13356/a>        6a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_DRM" class="sref">E752X_DRM6/a>, &6a href="+code=stat8" class="sref">stat86/a>);
L1336" class="line" namon>L1336">13366/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=map_type" class="sref">map_type6/a> = ((6a href="+code=stat8" class="sref">stat86/a> & 0x0f) > ((6a href="+code=stat8" class="sref">stat86/a> >> 4) & 0x0f));
L1337" class="line" namon>L1337">13376/a>
L1338" class="line" namon>L1338">13386/a>        6a href="+code=e752x_init_csrows" class="sref">e752x_init_csrows6/a>(6a href="+code=mci" class="sref">mci6/a>, 6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=ddrcsr" class="sref">ddrcsr6/a>);
L1339" class="line" namon>L1339">13396/a>        6a href="+code=e752x_init_mem_map_table" class="sref">e752x_init_mem_map_table6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=pvt" class="sref">pvt6/a>);
L1340" class="line" namon>L1340">13406/a>
L1341" class="line" namon>L1341">13416/a>        if (6a href="+code=dev_idx" class="sref">dev_idx6/a> == 6a href="+code=I3100" class="sref">I31006/a>)
L1342" class="line" namon>L1342">13426/a>                6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_cap" class="sref">edac_cap6/a> = 6a href="+code=EDAC_FLAG_SECDED" class="sref">EDAC_FLAG_SECDED6/a>; 6spa  class="comment">/* the only mode supported */6/spa >
L1343" class="line" namon>L1343">13436/a>        else
L1344" class="line" namon>L1344">13446/a>                6a href="+code=mci" class="sref">mci6/a>->6a href="+code=edac_cap" class="sref">edac_cap6/a> |= 6a href="+code=EDAC_FLAG_NONE" class="sref">EDAC_FLAG_NONE6/a>;
L1345" class="line" namon>L1345">13456/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"tolm, remapbase, remaplimit\n"6/spa >);
L1346" class="line" namon>L1346">13466/a>
L1347" class="line" namon>L1347">13476/a>        6spa  class="comment">/* load the top of low memory, remap base, and remap limit vars */6/spa >
L1348" class="line" namon>L1348">13486/a>        6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_TOLM" class="sref">E752X_TOLM6/a>, &6a href="+code=pci_data" class="sref">pci_data6/a>);
L1349" class="line" namon>L1349">13496/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=tolm" class="sref">tolm6/a> = ((6a href="+code=u32" class="sref">u326/a>).6a href="+code=pci_data" class="sref">pci_data6/a>) << 4;
L1350" class="line" namon>L1350">13506/a>        6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_REMAPBASE" class="sref">E752X_REMAPBASE6/a>, &6a href="+code=pci_data" class="sref">pci_data6/a>);
L1351" class="line" namon>L1351">13516/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remapbase" class="sref">remapbase6/a> = ((6a href="+code=u32" class="sref">u326/a>).6a href="+code=pci_data" class="sref">pci_data6/a>) << 14;
L1352" class="line" namon>L1352">13526/a>        6a href="+code=pci_read_config_word" class="sref">pci_read_config_word6/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=E752X_REMAPLIMIT" class="sref">E752X_REMAPLIMIT6/a>, &6a href="+code=pci_data" class="sref">pci_data6/a>);
L1353" class="line" namon>L1353">13536/a>        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remaplimit" class="sref">remaplimit6/a> = ((6a href="+code=u32" class="sref">u326/a>).6a href="+code=pci_data" class="sref">pci_data6/a>) << 14;
L1354" class="line" namon>L1354">13546/a>        6a href="+code=e752x_printk" class="sref">e752x_printk6/a>(6a href="+code=KERN_INFO" class="sref">KERN_INFO6/a>,
L1355" class="line" namon>L1355">13556/a>                        6spa  class="string">"tolm = %x, remapbase = %x, remaplimit = %x\n"6/spa >,
L1356" class="line" namon>L1356">13566/a>                        6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=tolm" class="sref">tolm6/a>, 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remapbase" class="sref">remapbase6/a>, 6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=remaplimit" class="sref">remaplimit6/a>);
L1357" class="line" namon>L1357">13576/a>
L1358" class="line" namon>L1358">13586/a>        6spa  class="comment">/* Here we assume that we will never see multiple instances of this6/spa >
L1359" class="line" namon>L1359">13596/a>6spa  class="comment">         * type of memory controller.  The ID is therefore hardcoded to 0.6/spa >
L1360" class="line" namon>L1360">13606/a>6spa  class="comment">         */6/spa >
L1361" class="line" namon>L1361">13616/a>        if (6a href="+code=edac_mc_add_mc" class="sref">edac_mc_add_mc6/a>(6a href="+code=mci" class="sref">mci6/a>)) {
L1362" class="line" namon>L1362">13626/a>                6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"failed edac_mc_add_mc()\n"6/spa >);
L1363" class="line" namon>L1363">13636/a>                goto 6a href="+code=fail" class="sref">fail6/a>;
L1364" class="line" namon>L1364">13646/a>        }
L1365" class="line" namon>L1365">13656/a>
L1366" class="line" namon>L1366">13666/a>        6a href="+code=e752x_init_error_reporting_regs" class="sref">e752x_init_error_reporting_regs6/a>(6a href="+code=pvt" class="sref">pvt6/a>);
L1367" class="line" namon>L1367">13676/a>        6a href="+code=e752x_get_error_info" class="sref">e752x_get_error_info6/a>(6a href="+code=mci" class="sref">mci6/a>, &6a href="+code=discard" class="sref">discard6/a>);    6spa  class="comment">/* clear other MCH errors */6/spa >
L1368" class="line" namon>L1368">13686/a>
L1369" class="line" namon>L1369">13696/a>        6spa  class="comment">/* allocating generic PCI control info */6/spa >
L1370" class="line" namon>L1370">13706/a>        6a href="+code=e752x_pci" class="sref">e752x_pci6/a> = 6a href="+code=edac_pci_create_generic_ctl" class="sref">edac_pci_create_generic_ctl6/a>(&6a href="+code=pdev" class="sref">pdev6/a>->6a href="+code=dev" class="sref">dev6/a>, 6a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR6/a>);
L1371" class="line" namon>L1371">13716/a>        if (!6a href="+code=e752x_pci" class="sref">e752x_pci6/a>) {
L1372" class="line" namon>L1372">13726/a>                6a href="+code=printk" class="sref">printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>
L1373" class="line" namon>L1373">13736/a>                        6spa  class="string">"%s(): Unable to create PCI control\n"6/spa >, 6a href="+code=__func__" class="sref">__func__6/a>);
L1374" class="line" namon>L1374">13746/a>                6a href="+code=printk" class="sref">printk6/a>(6a href="+code=KERN_WARNING" class="sref">KERN_WARNING6/a>
L1375" class="line" namon>L1375">13756/a>                        6spa  class="string">"%s(): PCI error report via EDAC not setup\n"6/spa >,
L1376" class="line" namon>L1376">13766/a>                        6a href="+code=__func__" class="sref">__func__6/a>);
L1377" class="line" namon>L1377">13776/a>        }
L1378" class="line" namon>L1378">13786/a>
L1379" class="line" namon>L1379">13796/a>        6spa  class="comment">/* get this far and it's successful */6/spa >
L1380" class="line" namon>L1380">13806/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"success\n"6/spa >);
L1381" class="line" namon>L1381">13816/a>        return.0;
L1382" class="line" namon>L1382">13826/a>
L1383" class="line" namon>L1383">13836/a>6a href="+code=fail" class="sref">fail6/a>:
L1384" class="line" namon>L1384">13846/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f0" class="sref">dev_d0f06/a>);
L1385" class="line" namon>L1385">13856/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>);
L1386" class="line" namon>L1386">13866/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>);
L1387" class="line" namon>L1387">13876/a>        6a href="+code=edac_mc_free" class="sref">edac_mc_free6/a>(6a href="+code=mci" class="sref">mci6/a>);
L1388" class="line" namon>L1388">13886/a>
L1389" class="line" namon>L1389">13896/a>        return.-6a href="+code=ENODEV" class="sref">ENODEV6/a>;
L1390" class="line" namon>L1390">13906/a>}
L1391" class="line" namon>L1391">13916/a>
L1392" class="line" namon>L1392">13926/a>6spa  class="comment">/* returns count (>= 0), or negative on error */6/spa >
L1393" class="line" namon>L1393">13936/a>static int.6a href="+code=__devinit" class="sref">__devinit6/a> 6a href="+code=e752x_init_one" class="sref">e752x_init_one6/a>(struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>,
L1394" class="line" namon>L1394">13946/a>                                const struct.6a href="+code=pci_device_id" class="sref">pci_device_id6/a> *6a href="+code=ent" class="sref">ent6/a>)
L1395" class="line" namon>L1395">13956/a>{
L1396" class="line" namon>L1396">13966/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(0, 6spa  class="string">"\n"6/spa >);
L1397" class="line" namon>L1397">13976/a>
L1398" class="line" namon>L1398">13986/a>        6spa  class="comment">/* wake up and enable device */6/spa >
L1399" class="line" namon>L1399">13996/a>        if (6a href="+code=pci_enable_device" class="sref">pci_enable_device6/a>(6a href="+code=pdev" class="sref">pdev6/a>) < 0)
L1400" class="line" namon>L1400">14006/a>                return.-6a href="+code=EIO" class="sref">EIO6/a>;
L1401" class="line" namon>L1401">14016/a>
L1402" class="line" namon>L1402">14026/a>        return.6a href="+code=e752x_probe1" class="sref">e752x_probe16/a>(6a href="+code=pdev" class="sref">pdev6/a>, 6a href="+code=ent" class="sref">ent6/a>->6a href="+code=driver_data" class="sref">driver_data6/a>);
L1403" class="line" namon>L1403">14036/a>}
L1404" class="line" namon>L1404">14046/a>
L1405" class="line" namon>L1405">14056/a>static void.6a href="+code=__devexit" class="sref">__devexit6/a> 6a href="+code=e752x_remove_one" class="sref">e752x_remove_one6/a>(struct.6a href="+code=pci_dev" class="sref">pci_dev6/a> *6a href="+code=pdev" class="sref">pdev6/a>)
L1406" class="line" namon>L1406">14066/a>{
L1407" class="line" namon>L1407">14076/a>        struct.6a href="+code=mem_ctl_info" class="sref">mem_ctl_info6/a> *6a href="+code=mci" class="sref">mci6/a>;
L1408" class="line" namon>L1408">14086/a>        struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *6a href="+code=pvt" class="sref">pvt6/a>;
L1409" class="line" namon>L1409">14096/a>
L1410" class="line" namon>L1410">14106/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(0, 6spa  class="string">"\n"6/spa >);
L1411" class="line" namon>L1411">14116/a>
L1412" class="line" namon>L1412">14126/a>        if (6a href="+code=e752x_pci" class="sref">e752x_pci6/a>)
L1413" class="line" namon>L1413">14136/a>                6a href="+code=edac_pci_release_generic_ctl" class="sref">edac_pci_release_generic_ctl6/a>(6a href="+code=e752x_pci" class="sref">e752x_pci6/a>);
L1414" class="line" namon>L1414">14146/a>
L1415" class="line" namon>L1415">14156/a>        if ((6a href="+code=mci" class="sref">mci6/a> = 6a href="+code=edac_mc_del_mc" class="sref">edac_mc_del_mc6/a>(&6a href="+code=pdev" class="sref">pdev6/a>->6a href="+code=dev" class="sref">dev6/a>)) == 6a href="+code=NULL" class="sref">NULL6/a>)
L1416" class="line" namon>L1416">14166/a>                return;
L1417" class="line" namon>L1417">14176/a>
L1418" class="line" namon>L1418">14186/a>        6a href="+code=pvt" class="sref">pvt6/a> = (struct.6a href="+code=e752x_pvt" class="sref">e752x_pvt6/a> *)6a href="+code=mci" class="sref">mci6/a>->6a href="+code=pvt_info" class="sref">pvt_info6/a>;
L1419" class="line" namon>L1419">14196/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f0" class="sref">dev_d0f06/a>);
L1420" class="line" namon>L1420">14206/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=dev_d0f1" class="sref">dev_d0f16/a>);
L1421" class="line" namon>L1421">14216/a>        6a href="+code=pci_dev_put" class="sref">pci_dev_put6/a>(6a href="+code=pvt" class="sref">pvt6/a>->6a href="+code=bridge_ck" class="sref">bridge_ck6/a>);
L1422" class="line" namon>L1422">14226/a>        6a href="+code=edac_mc_free" class="sref">edac_mc_free6/a>(6a href="+code=mci" class="sref">mci6/a>);
L1423" class="line" namon>L1423">14236/a>}
L1424" class="line" namon>L1424">14246/a>
L1425" class="line" namon>L1425">14256/a>static 6a href="+code=DEFINE_PCI_DEVICE_TABLE" class="sref">DEFINE_PCI_DEVICE_TABLE6/a>(6a href="+code=e752x_pci_tbl" class="sref">e752x_pci_tbl6/a>) = {
L1426" class="line" namon>L1426">14266/a>        {
L1427" class="line" namon>L1427">14276/a>         6a href="+code=PCI_VEND_DEV" class="sref">PCI_VEND_DEV6/a>(6a href="+code=INTEL" class="sref">INTEL6/a>, 7520_0), 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 0, 0,
L1428" class="line" namon>L1428">14286/a>         6a href="+code=E7520" class="sref">E75206/a>},
L1429" class="line" namon>L1429">14296/a>        {
L1430" class="line" namon>L1430">14306/a>         6a href="+code=PCI_VEND_DEV" class="sref">PCI_VEND_DEV6/a>(6a href="+code=INTEL" class="sref">INTEL6/a>, 7525_0), 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 0, 0,
L1431" class="line" namon>L1431">14316/a>         6a href="+code=E7525" class="sref">E75256/a>},
L1432" class="line" namon>L1432">14326/a>        {
L1433" class="line" namon>L1433">14336/a>         6a href="+code=PCI_VEND_DEV" class="sref">PCI_VEND_DEV6/a>(6a href="+code=INTEL" class="sref">INTEL6/a>, 7320_0), 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 0, 0,
L1434" class="line" namon>L1434">14346/a>         6a href="+code=E7320" class="sref">E73206/a>},
L1435" class="line" namon>L1435">14356/a>        {
L1436" class="line" namon>L1436">14366/a>         6a href="+code=PCI_VEND_DEV" class="sref">PCI_VEND_DEV6/a>(6a href="+code=INTEL" class="sref">INTEL6/a>, 3100_0), 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 6a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID6/a>, 0, 0,
L1437" class="line" namon>L1437">14376/a>         6a href="+code=I3100" class="sref">I31006/a>},
L1438" class="line" namon>L1438">14386/a>        {
L1439" class="line" namon>L1439">14396/a>         0,
L1440" class="line" namon>L1440">14406/a>         }                      6spa  class="comment">/* 0 terminated list. */6/spa >
L1441" class="line" namon>L1441">14416/a>};
L1442" class="line" namon>L1442">14426/a>
L1443" class="line" namon>L1443">14436/a>6a href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLE6/a>(6a href="+code=pci" class="sref">pci6/a>, 6a href="+code=e752x_pci_tbl" class="sref">e752x_pci_tbl6/a>);
L1444" class="line" namon>L1444">14446/a>
L1445" class="line" namon>L1445">14456/a>static struct.6a href="+code=pci_driver" class="sref">pci_driver6/a> 6a href="+code=e752x_driver" class="sref">e752x_driver6/a> = {
L1446" class="line" namon>L1446">14466/a>        .6a href="+code=namo" class="sref">namo6/a> = 6a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR6/a>,
L1447" class="line" namon>L1447">14476/a>        .6a href="+code=probe" class="sref">probe6/a> = 6a href="+code=e752x_init_one" class="sref">e752x_init_one6/a>,
L1448" class="line" namon>L1448">14486/a>        .6a href="+code=remove" class="sref">remove6/a> = 6a href="+code=__devexit_p" class="sref">__devexit_p6/a>(6a href="+code=e752x_remove_one" class="sref">e752x_remove_one6/a>),
L1449" class="line" namon>L1449">14496/a>        .6a href="+code=id_table" class="sref">id_table6/a> = 6a href="+code=e752x_pci_tbl" class="sref">e752x_pci_tbl6/a>,
L1450" class="line" namon>L1450">14506/a>};
L1451" class="line" namon>L1451">14516/a>
L1452" class="line" namon>L1452">14526/a>static int.6a href="+code=__init" class="sref">__init6/a> 6a href="+code=e752x_init" class="sref">e752x_init6/a>(void)
L1453" class="line" namon>L1453">14536/a>{
L1454" class="line" namon>L1454">14546/a>        int.6a href="+code=pci_rc" class="sref">pci_rc6/a>;
L1455" class="line" namon>L1455">14556/a>
L1456" class="line" namon>L1456">14566/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L1457" class="line" namon>L1457">14576/a>
L1458" class="line" namon>L1458">14586/a>       6spa  class="comment">/* Ensure that the OPSTATE is set correctly for POLL or NMI */6/spa >
L1459" class="line" namon>L1459">14596/a>       6a href="+code=opstate_init" class="sref">opstate_init6/a>();
L1460" class="line" namon>L1460">14606/a>
L1461" class="line" namon>L1461">14616/a>        6a href="+code=pci_rc" class="sref">pci_rc6/a> = 6a href="+code=pci_register_driver" class="sref">pci_register_driver6/a>(&6a href="+code=e752x_driver" class="sref">e752x_driver6/a>);
L1462" class="line" namon>L1462">14626/a>        return.(6a href="+code=pci_rc" class="sref">pci_rc6/a> < 0) ? 6a href="+code=pci_rc" class="sref">pci_rc6/a> :.0;
L1463" class="line" namon>L1463">14636/a>}
L1464" class="line" namon>L1464">14646/a>
L1465" class="line" namon>L1465">14656/a>static void.6a href="+code=__exit" class="sref">__exit6/a> 6a href="+code=e752x_exit" class="sref">e752x_exit6/a>(void)
L1466" class="line" namon>L1466">14666/a>{
L1467" class="line" namon>L1467">14676/a>        6a href="+code=edac_dbg" class="sref">edac_dbg6/a>(3, 6spa  class="string">"\n"6/spa >);
L1468" class="line" namon>L1468">14686/a>        6a href="+code=pci_unregister_driver" class="sref">pci_unregister_driver6/a>(&6a href="+code=e752x_driver" class="sref">e752x_driver6/a>);
L1469" class="line" namon>L1469">14696/a>}
L1470" class="line" namon>L1470">14706/a>
L1471" class="line" namon>L1471">14716/a>6a href="+code=module_init" class="sref">module_init6/a>(6a href="+code=e752x_init" class="sref">e752x_init6/a>);
L1472" class="line" namon>L1472">14726/a>6a href="+code=module_exit" class="sref">module_exit6/a>(6a href="+code=e752x_exit" class="sref">e752x_exit6/a>);
L1473" class="line" namon>L1473">14736/a>
L1474" class="line" namon>L1474">14746/a>6a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE6/a>(6spa  class="string">"GPL"6/spa >);
L1475" class="line" namon>L1475">14756/a>6a href="+code=MODULE_AUTHOR" class="sref">MODULE_AUTHOR6/a>(6spa  class="string">"Linux Networx (http://lnxi.com) Tom Zimmerman\n"6/spa >);
L1476" class="line" namon>L1476">14766/a>6a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION6/a>(6spa  class="string">"MC support for Intel e752x/3100 memory controllers"6/spa >);
L1477" class="line" namon>L1477">14776/a>
L1478" class="line" namon>L1478">14786/a>6a href="+code=module_param" class="sref">module_param6/a>(6a href="+code=force_function_unhide" class="sref">force_function_unhide6/a>, int, 0444);
L1479" class="line" namon>L1479">14796/a>6a href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESC6/a>(6a href="+code=force_function_unhide" class="sref">force_function_unhide6/a>, 6spa  class="string">"if BIOS sets Dev0:Fun1 up as hidden:"6/spa >
L1480" class="line" namon>L1480">14806/a>                 6spa  class="string">" 1=force unhide and hope BIOS doesn't fight driver for "6/spa >
L1481" class="line" namon>L1481">14816/a>                6spa  class="string">"Dev0:Fun1 access"6/spa >);
L1482" class="line" namon>L1482">14826/a>
L1483" class="line" namon>L1483">14836/a>6a href="+code=module_param" class="sref">module_param6/a>(6a href="+code=edac_op_state" class="sref">edac_op_state6/a>, int, 0444);
L1484" class="line" namon>L1484">14846/a>6a href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESC6/a>(6a href="+code=edac_op_state" class="sref">edac_op_state6/a>, 6spa  class="string">"EDAC Error Reporting state:.0=Poll,1=NMI"6/spa >);
L1485" class="line" namon>L1485">14856/a>
L1486" class="line" namon>L1486">14866/a>6a href="+code=module_param" class="sref">module_param6/a>(6a href="+code=sysbus_parity" class="sref">sysbus_parity6/a>, int, 0444);
L1487" class="line" namon>L1487">14876/a>6a href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESC6/a>(6a href="+code=sysbus_parity" class="sref">sysbus_parity6/a>, 6spa  class="string">"0=disable system bus parity checking,"6/spa >
L1488" class="line" namon>L1488">14886/a>                6spa  class="string">" 1=enable system bus parity checking, default=auto-detect"6/spa >);
L1489" class="line" namon>L1489">14896/a>6a href="+code=module_param" class="sref">module_param6/a>(6a href="+code=report_non_memory_errors" class="sref">report_non_memory_errors6/a>, int, 0644);
L1490" class="line" namon>L1490">14906/a>6a href="+code=MODULE_PARM_DESC" class="sref">MODULE_PARM_DESC6/a>(6a href="+code=report_non_memory_errors" class="sref">report_non_memory_errors6/a>, 6spa  class="string">"0=disable non-memory error "6/spa >
L1491" class="line" namon>L1491">14916/a>                6spa  class="string">"reporting, 1=enable non-memory error reporting"6/spa >);
L1492" class="line" namon>L1492">14926/a>6/pre>6/div>


6/div>