linux/drivers/dma/ste_dma40_ll.h
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   1/*
   2 * Copyright (C) ST-Ericsson SA 2007-2010
   3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
   4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
   5 * License terms: GNU General Public License (GPL) version 2
   6 */
   7#ifndef STE_DMA40_LL_H
   8#define STE_DMA40_LL_H
   9
  10#define D40_DREG_PCBASE         0x400
  11#define D40_DREG_PCDELTA        (8 * 4)
  12#define D40_LLI_ALIGN           16 /* LLI alignment must be 16 bytes. */
  13
  14#define D40_LCPA_CHAN_SIZE 32
  15#define D40_LCPA_CHAN_DST_DELTA 16
  16
  17#define D40_TYPE_TO_GROUP(type) (type / 16)
  18#define D40_TYPE_TO_EVENT(type) (type % 16)
  19#define D40_GROUP_SIZE 8
  20#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
  21
  22/* Most bits of the CFG register are the same in log as in phy mode */
  23#define D40_SREG_CFG_MST_POS            15
  24#define D40_SREG_CFG_TIM_POS            14
  25#define D40_SREG_CFG_EIM_POS            13
  26#define D40_SREG_CFG_LOG_INCR_POS       12
  27#define D40_SREG_CFG_PHY_PEN_POS        12
  28#define D40_SREG_CFG_PSIZE_POS          10
  29#define D40_SREG_CFG_ESIZE_POS           8
  30#define D40_SREG_CFG_PRI_POS             7
  31#define D40_SREG_CFG_LBE_POS             6
  32#define D40_SREG_CFG_LOG_GIM_POS         5
  33#define D40_SREG_CFG_LOG_MFU_POS         4
  34#define D40_SREG_CFG_PHY_TM_POS          4
  35#define D40_SREG_CFG_PHY_EVTL_POS        0
  36
  37
  38/* Standard channel parameters - basic mode (element register) */
  39#define D40_SREG_ELEM_PHY_ECNT_POS      16
  40#define D40_SREG_ELEM_PHY_EIDX_POS       0
  41
  42#define D40_SREG_ELEM_PHY_ECNT_MASK     (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
  43
  44/* Standard channel parameters - basic mode (Link register) */
  45#define D40_SREG_LNK_PHY_TCP_POS        0
  46#define D40_SREG_LNK_PHY_LMP_POS        1
  47#define D40_SREG_LNK_PHY_PRE_POS        2
  48/*
  49 * Source  destination link address. Contains the
  50 * 29-bit byte word aligned address of the reload area.
  51 */
  52#define D40_SREG_LNK_PHYS_LNK_MASK      0xFFFFFFF8UL
  53
  54/* Standard basic channel logical mode */
  55
  56/* Element register */
  57#define D40_SREG_ELEM_LOG_ECNT_POS      16
  58#define D40_SREG_ELEM_LOG_LIDX_POS       8
  59#define D40_SREG_ELEM_LOG_LOS_POS        1
  60#define D40_SREG_ELEM_LOG_TCP_POS        0
  61
  62#define D40_SREG_ELEM_LOG_LIDX_MASK     (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
  63
  64/* Link register */
  65#define D40_EVENTLINE_POS(i)            (2 * i)
  66#define D40_EVENTLINE_MASK(i)           (0x3 << D40_EVENTLINE_POS(i))
  67
  68/* Standard basic channel logical params in memory */
  69
  70/* LCSP0 */
  71#define D40_MEM_LCSP0_ECNT_POS          16
  72#define D40_MEM_LCSP0_SPTR_POS           0
  73
  74#define D40_MEM_LCSP0_ECNT_MASK         (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
  75#define D40_MEM_LCSP0_SPTR_MASK         (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
  76
  77/* LCSP1 */
  78#define D40_MEM_LCSP1_SPTR_POS          16
  79#define D40_MEM_LCSP1_SCFG_MST_POS      15
  80#define D40_MEM_LCSP1_SCFG_TIM_POS      14
  81#define D40_MEM_LCSP1_SCFG_EIM_POS      13
  82#define D40_MEM_LCSP1_SCFG_INCR_POS     12
  83#define D40_MEM_LCSP1_SCFG_PSIZE_POS    10
  84#define D40_MEM_LCSP1_SCFG_ESIZE_POS     8
  85#define D40_MEM_LCSP1_SLOS_POS           1
  86#define D40_MEM_LCSP1_STCP_POS           0
  87
  88#define D40_MEM_LCSP1_SPTR_MASK         (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
  89#define D40_MEM_LCSP1_SCFG_TIM_MASK     (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
  90#define D40_MEM_LCSP1_SCFG_INCR_MASK    (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
  91#define D40_MEM_LCSP1_SCFG_PSIZE_MASK   (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
  92#define D40_MEM_LCSP1_SLOS_MASK         (0x7F << D40_MEM_LCSP1_SLOS_POS)
  93#define D40_MEM_LCSP1_STCP_MASK         (0x1 << D40_MEM_LCSP1_STCP_POS)
  94
  95/* LCSP2 */
  96#define D40_MEM_LCSP2_ECNT_POS          16
  97
  98#define D40_MEM_LCSP2_ECNT_MASK         (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
  99
 100/* LCSP3 */
 101#define D40_MEM_LCSP3_DCFG_MST_POS      15
 102#define D40_MEM_LCSP3_DCFG_TIM_POS      14
 103#define D40_MEM_LCSP3_DCFG_EIM_POS      13
 104#define D40_MEM_LCSP3_DCFG_INCR_POS     12
 105#define D40_MEM_LCSP3_DCFG_PSIZE_POS    10
 106#define D40_MEM_LCSP3_DCFG_ESIZE_POS     8
 107#define D40_MEM_LCSP3_DLOS_POS           1
 108#define D40_MEM_LCSP3_DTCP_POS           0
 109
 110#define D40_MEM_LCSP3_DLOS_MASK         (0x7F << D40_MEM_LCSP3_DLOS_POS)
 111#define D40_MEM_LCSP3_DTCP_MASK         (0x1 << D40_MEM_LCSP3_DTCP_POS)
 112
 113
 114/* Standard channel parameter register offsets */
 115#define D40_CHAN_REG_SSCFG      0x00
 116#define D40_CHAN_REG_SSELT      0x04
 117#define D40_CHAN_REG_SSPTR      0x08
 118#define D40_CHAN_REG_SSLNK      0x0C
 119#define D40_CHAN_REG_SDCFG      0x10
 120#define D40_CHAN_REG_SDELT      0x14
 121#define D40_CHAN_REG_SDPTR      0x18
 122#define D40_CHAN_REG_SDLNK      0x1C
 123
 124/* DMA Register Offsets */
 125#define D40_DREG_GCC            0x000
 126#define D40_DREG_GCC_ENA        0x1
 127/* This assumes that there are only 4 event groups */
 128#define D40_DREG_GCC_ENABLE_ALL 0xff01
 129#define D40_DREG_GCC_EVTGRP_POS 8
 130#define D40_DREG_GCC_SRC 0
 131#define D40_DREG_GCC_DST 1
 132#define D40_DREG_GCC_EVTGRP_ENA(x, y) \
 133        (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
 134
 135#define D40_DREG_PRTYP          0x004
 136#define D40_DREG_PRSME          0x008
 137#define D40_DREG_PRSMO          0x00C
 138#define D40_DREG_PRMSE          0x010
 139#define D40_DREG_PRMSO          0x014
 140#define D40_DREG_PRMOE          0x018
 141#define D40_DREG_PRMOO          0x01C
 142#define D40_DREG_PRMO_PCHAN_BASIC               0x1
 143#define D40_DREG_PRMO_PCHAN_MODULO              0x2
 144#define D40_DREG_PRMO_PCHAN_DOUBLE_DST          0x3
 145#define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG     0x1
 146#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY     0x2
 147#define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG     0x3
 148
 149#define D40_DREG_LCPA           0x020
 150#define D40_DREG_LCLA           0x024
 151#define D40_DREG_ACTIVE         0x050
 152#define D40_DREG_ACTIVO         0x054
 153#define D40_DREG_FSEB1          0x058
 154#define D40_DREG_FSEB2          0x05C
 155#define D40_DREG_PCMIS          0x060
 156#define D40_DREG_PCICR          0x064
 157#define D40_DREG_PCTIS          0x068
 158#define D40_DREG_PCEIS          0x06C
 159#define D40_DREG_LCMIS0         0x080
 160#define D40_DREG_LCMIS1         0x084
 161#define D40_DREG_LCMIS2         0x088
 162#define D40_DREG_LCMIS3         0x08C
 163#define D40_DREG_LCICR0         0x090
 164#define D40_DREG_LCICR1         0x094
 165#define D40_DREG_LCICR2         0x098
 166#define D40_DREG_LCICR3         0x09C
 167#define D40_DREG_LCTIS0         0x0A0
 168#define D40_DREG_LCTIS1         0x0A4
 169#define D40_DREG_LCTIS2         0x0A8
 170#define D40_DREG_LCTIS3         0x0AC
 171#define D40_DREG_LCEIS0         0x0B0
 172#define D40_DREG_LCEIS1         0x0B4
 173#define D40_DREG_LCEIS2         0x0B8
 174#define D40_DREG_LCEIS3         0x0BC
 175#define D40_DREG_PSEG1          0x110
 176#define D40_DREG_PSEG2          0x114
 177#define D40_DREG_PSEG3          0x118
 178#define D40_DREG_PSEG4          0x11C
 179#define D40_DREG_PCEG1          0x120
 180#define D40_DREG_PCEG2          0x124
 181#define D40_DREG_PCEG3          0x128
 182#define D40_DREG_PCEG4          0x12C
 183#define D40_DREG_RSEG1          0x130
 184#define D40_DREG_RSEG2          0x134
 185#define D40_DREG_RSEG3          0x138
 186#define D40_DREG_RSEG4          0x13C
 187#define D40_DREG_RCEG1          0x140
 188#define D40_DREG_RCEG2          0x144
 189#define D40_DREG_RCEG3          0x148
 190#define D40_DREG_RCEG4          0x14C
 191#define D40_DREG_STFU           0xFC8
 192#define D40_DREG_ICFG           0xFCC
 193#define D40_DREG_PERIPHID0      0xFE0
 194#define D40_DREG_PERIPHID1      0xFE4
 195#define D40_DREG_PERIPHID2      0xFE8
 196#define D40_DREG_PERIPHID3      0xFEC
 197#define D40_DREG_CELLID0        0xFF0
 198#define D40_DREG_CELLID1        0xFF4
 199#define D40_DREG_CELLID2        0xFF8
 200#define D40_DREG_CELLID3        0xFFC
 201
 202/* LLI related structures */
 203
 204/**
 205 * struct d40_phy_lli - The basic configration register for each physical
 206 * channel.
 207 *
 208 * @reg_cfg: The configuration register.
 209 * @reg_elt: The element register.
 210 * @reg_ptr: The pointer register.
 211 * @reg_lnk: The link register.
 212 *
 213 * These registers are set up for both physical and logical transfers
 214 * Note that the bit in each register means differently in logical and
 215 * physical(standard) mode.
 216 *
 217 * This struct must be 16 bytes aligned, and only contain physical registers
 218 * since it will be directly accessed by the DMA.
 219 */
 220struct d40_phy_lli {
 221        u32 reg_cfg;
 222        u32 reg_elt;
 223        u32 reg_ptr;
 224        u32 reg_lnk;
 225};
 226
 227/**
 228 * struct d40_phy_lli_bidir - struct for a transfer.
 229 *
 230 * @src: Register settings for src channel.
 231 * @dst: Register settings for dst channel.
 232 *
 233 * All DMA transfers have a source and a destination.
 234 */
 235
 236struct d40_phy_lli_bidir {
 237        struct d40_phy_lli      *src;
 238        struct d40_phy_lli      *dst;
 239};
 240
 241
 242/**
 243 * struct d40_log_lli - logical lli configuration
 244 *
 245 * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
 246 * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
 247 *
 248 * This struct must be 8 bytes aligned since it will be accessed directy by
 249 * the DMA. Never add any none hw mapped registers to this struct.
 250 */
 251
 252struct d40_log_lli {
 253        u32 lcsp02;
 254        u32 lcsp13;
 255};
 256
 257/**
 258 * struct d40_log_lli_bidir - For both src and dst
 259 *
 260 * @src: pointer to src lli configuration.
 261 * @dst: pointer to dst lli configuration.
 262 *
 263 * You always have a src and a dst when doing DMA transfers.
 264 */
 265
 266struct d40_log_lli_bidir {
 267        struct d40_log_lli *src;
 268        struct d40_log_lli *dst;
 269};
 270
 271/**
 272 * struct d40_log_lli_full - LCPA layout
 273 *
 274 * @lcsp0: Logical Channel Standard Param 0 - Src.
 275 * @lcsp1: Logical Channel Standard Param 1 - Src.
 276 * @lcsp2: Logical Channel Standard Param 2 - Dst.
 277 * @lcsp3: Logical Channel Standard Param 3 - Dst.
 278 *
 279 * This struct maps to LCPA physical memory layout. Must map to
 280 * the hw.
 281 */
 282struct d40_log_lli_full {
 283        u32 lcsp0;
 284        u32 lcsp1;
 285        u32 lcsp2;
 286        u32 lcsp3;
 287};
 288
 289/**
 290 * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
 291 *
 292 * @lcsp3: The default configuration for dst.
 293 * @lcsp1: The default configuration for src.
 294 */
 295struct d40_def_lcsp {
 296        u32 lcsp3;
 297        u32 lcsp1;
 298};
 299
 300/* Physical channels */
 301
 302enum d40_lli_flags {
 303        LLI_ADDR_INC    = 1 << 0,
 304        LLI_TERM_INT    = 1 << 1,
 305        LLI_CYCLIC      = 1 << 2,
 306        LLI_LAST_LINK   = 1 << 3,
 307};
 308
 309void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 310                 u32 *src_cfg,
 311                 u32 *dst_cfg,
 312                 bool is_log);
 313
 314void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 315                 u32 *lcsp1,
 316                 u32 *lcsp2);
 317
 318int d40_phy_sg_to_lli(struct scatterlist *sg,
 319                      int sg_len,
 320                      dma_addr_t target,
 321                      struct d40_phy_lli *lli,
 322                      dma_addr_t lli_phys,
 323                      u32 reg_cfg,
 324                      struct stedma40_half_channel_info *info,
 325                      struct stedma40_half_channel_info *otherinfo,
 326                      unsigned long flags);
 327
 328/* Logical channels */
 329
 330int d40_log_sg_to_lli(struct scatterlist *sg,
 331                      int sg_len,
 332                      dma_addr_t dev_addr,
 333                      struct d40_log_lli *lli_sg,
 334                      u32 lcsp13, /* src or dst*/
 335                      u32 data_width1, u32 data_width2);
 336
 337void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
 338                            struct d40_log_lli *lli_dst,
 339                            struct d40_log_lli *lli_src,
 340                            int next, unsigned int flags);
 341
 342void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
 343                            struct d40_log_lli *lli_dst,
 344                            struct d40_log_lli *lli_src,
 345                            int next, unsigned int flags);
 346
 347#endif /* STE_DMA40_LLI_H */
 348
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