linux/drivers/clocksource/dw_apb_timer.c
<<
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/a>
spa1 class="comment">/*
/spa15"> >2
/a>
spa1 class="comment"> * (C) Copyright 2009 Intel Corpora.4.1
/spa15"> >3
/a>
spa1 class="comment"> * Author: Jacob Pa1 (jacob.jun.pa1@intel.com)
/spa15"> >4
/a>
spa1 class="comment"> *
/spa15"> >5
/a>
spa1 class="comment"> * Shared with ARM platforms, Jamie Iles, Picochip 201 ="spa15"> >6
/a>
spa1 class="comment"> *
/spa15"> >7
/a>
spa1 class="comment"> * This program is free software; you ca1 redistribute it and/or modify
/spa15"> >8
/a>
spa1 class="comment"> * it under the terms of the GNU General Public License vers3.4.2 as
/spa15"> >9
/a>
spa1 class="comment"> * published by the Free Software Founda.4.1.
/spa15"> ue="a>
spa1 class="comment"> *
/spa15"> 11
/a>
spa1 class="comment"> * Support for the Synopsys DesignWare APB Timers.
/spa15"> 12
/a>
spa1 class="comment"> */
/spa15"> 13
/a>#include <linux/dw_apb_timer.h
/a>>"> 14
/a>#include <linux/delay.h
/a>>"> 15
/a>#include <linux/kernel.h
/a>>"> 16
/a>#include <linux/interrupt.h
/a>>"> 17
/a>#include <linux/irq.h
/a>>"> 18
/a>#include <linux/io.h
/a>>"> 19
/a>#include <linux/slab.h
/a>>"> 2e="a>"> 21
/a>#define>
a href="+code=APBT_MIN_PERIOD" class="sref">APBT_MIN_PERIOD
/a>                 4"> 22
/a>#define>
a href="+code=APBT_MIN_DELTA_USEC" class="sref">APBT_MIN_DELTA_USEC
/a>             200"> 23="a>"> 24
/a>#define>
a href="+code=APBTMR_N_LOAD_COUNT" class="sref">APBTMR_N_LOAD_COUNT
/a>             0x00"> 25
/a>#define>
a href="+code=APBTMR_N_CURRENT_VALUE" class="sref">APBTMR_N_CURRENT_VALUE
/a>          0x04"> 26
/a>#define>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>                0x08"> 27
/a>#define>
a href="+code=APBTMR_N_EOI" class="sref">APBTMR_N_EOI
/a>                    0x0c"> 28
/a>#define>
a href="+code=APBTMR_N_INT_STATUS" class="sref">APBTMR_N_INT_STATUS
/a>             0x10"> 29="a>"> 30
/a>#define>
a href="+code=APBTMRS_INT_STATUS" class="sref">APBTMRS_INT_STATUS
/a>              0xa0"> 31
/a>#define>
a href="+code=APBTMRS_EOI" class="sref">APBTMRS_EOI
/a>                     0xa4"> 32
/a>#define>
a href="+code=APBTMRS_RAW_INT_STATUS" class="sref">APBTMRS_RAW_INT_STATUS
/a>          0xa8"> 33
/a>#define>
a href="+code=APBTMRS_COMP_VERSION" class="sref">APBTMRS_COMP_VERSION
/a>            0xac"> 34="a>"> 35
/a>#define>
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>           (1 << 0)"> 36
/a>
spa1 class="comment">/* 1: periodic, 0:free running. */
/spa15"> 37
/a>#define>
a href="+code=APBTMR_CONTROL_MODE_PERIODIC" class="sref">APBTMR_CONTROL_MODE_PERIODIC
/a>    (1 << 1)"> 38
/a>#define>
a href="+code=APBTMR_CONTROL_INT" class="sref">APBTMR_CONTROL_INT
/a>              (1 << 2)"> 39="a>"> 40
/a>static>
a href="+code=inline" class="sref">inline
/a> struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *"> 41
/a>
a href="+code=ced_to_dw_apb_ced" class="sref">ced_to_dw_apb_ced
/a>(struct>
a href="+code=clock_event_device" class="sref">clock_event_device
/a> *
a href="+code=evt" class="sref">evt
/a>)"> 42
/a>{"> 43
/a>        return 
a href="+code=container_of" class="sref">container_of
/a>(
a href="+code=evt" class="sref">evt
/a>, struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a>, 
a href="+code=ced" class="sref">ced
/a>);"> 44="a>}"> 45="a>"> 46
/a>static>
a href="+code=inline" class="sref">inline
/a> struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *"> 47
/a>
a href="+code=clocksource_to_dw_apb_clocksource" class="sref">clocksource_to_dw_apb_clocksource
/a>(struct>
a href="+code=clocksource" class="sref">clocksource
/a> *
a href="+code=cs" class="sref">cs
/a>)"> 48
/a>{"> 49
/a>        return 
a href="+code=container_of" class="sref">container_of
/a>(
a href="+code=cs" class="sref">cs
/a>, struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a>, 
a href="+code=cs" class="sref">cs
/a>);"> 50="a>}"> 51="a>"> 52
/a>static>unsigned long 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(struct>
a href="+code=dw_apb_timer" class="sref">dw_apb_timer
/a> *
a href="+code=timer" class="sref">timer
/a>,>unsigned long 
a href="+code=offs" class="sref">offs
/a>)"> 53
/a>{"> 54
/a>        return 
a href="+code=readl" class="sref">readl
/a>(
a href="+code=timer" class="sref">timer
/a>->
a href="+code=base" class="sref">base
/a> + 
a href="+code=offs" class="sref">offs
/a>);"> 55="a>}"> 56="a>"> 57
/a>static>void 
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(struct>
a href="+code=dw_apb_timer" class="sref">dw_apb_timer
/a> *
a href="+code=timer" class="sref">timer
/a>,>unsigned long 
a href="+code=val" class="sref">val
/a>,"> 58
/a>                 unsigned long 
a href="+code=offs" class="sref">offs
/a>)"> 59
/a>{"> 60
/a>        
a href="+code=writel" class="sref">writel
/a>(
a href="+code=val" class="sref">val
/a>, 
a href="+code=timer" class="sref">timer
/a>->
a href="+code=base" class="sref">base
/a> + 
a href="+code=offs" class="sref">offs
/a>);"> 61="a>}"> 62="a>"> 63
/a>static>void 
a href="+code=apbt_disable_int" class="sref">apbt_disable_int
/a>(struct>
a href="+code=dw_apb_timer" class="sref">dw_apb_timer
/a> *
a href="+code=timer" class="sref">timer
/a>)"> 64
/a>{"> 65
/a>        unsigned long 
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);"> 66="a>"> 67
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> |= 
a href="+code=APBTMR_CONTROL_INT" class="sref">APBTMR_CONTROL_INT
/a>;"> 68
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);"> 69="a>}"> 7e="a>"> 71
/a>
spa1 class="comment">/**
/spa15"> 72
/a>
spa1 class="comment"> * dw_apb_clockevent_pause() - stop the clock_event_device from running
/spa15"> 73
/a>
spa1 class="comment"> *
/spa15"> 74
/a>
spa1 class="comment"> * @dw_ced:     The APB clock to stop generating events.
/spa15"> 75
/a>
spa1 class="comment"> */
/spa15"> 76="a>void 
a href="+code=dw_apb_clockevent_pause" class="sref">dw_apb_clockevent_pause
/a>(struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a>)"> 77
/a>{"> 78
/a>        
a href="+code=disable_irq" class="sref">disable_irq
/a>(
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=irq" class="sref">irq
/a>);"> 79
/a>        
a href="+code=apbt_disable_int" class="sref">apbt_disable_int
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>);"> 80="a>}"> 81="a>"> 82
/a>static>void 
a href="+code=apbt_eoi" class="sref">apbt_eoi
/a>(struct>
a href="+code=dw_apb_timer" class="sref">dw_apb_timer
/a> *
a href="+code=timer" class="sref">timer
/a>)"> 83
/a>{"> 84
/a>        
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_EOI" class="sref">APBTMR_N_EOI
/a>);"> 85="a>}"> 86="a>"> 87
/a>static>
a href="+code=irqreturn_t" class="sref">irqreturn_t
/a> 
a href="+code=dw_apb_clockevent_irq" class="sref">dw_apb_clockevent_irq
/a>(int>
a href="+code=irq" class="sref">irq
/a>,>void *
a href="+code=data" class="sref">data
/a>)"> 88
/a>{"> 89
/a>        struct>
a href="+code=clock_event_device" class="sref">clock_event_device
/a> *
a href="+code=evt" class="sref">evt
/a> = 
a href="+code=data" class="sref">data
/a>;"> 90
/a>        struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a> = 
a href="+code=ced_to_dw_apb_ced" class="sref">ced_to_dw_apb_ced
/a>(
a href="+code=evt" class="sref">evt
/a>);"> 91="a>"> 92
/a>        if (!
a href="+code=evt" class="sref">evt
/a>->
a href="+code=event_handler" class="sref">event_handler
/a>) {"> 93
/a>                
a href="+code=pr_info" class="sref">pr_info
/a>(
spa1 class="string">"Spurious APBT timer interrupt %d"
/spa15,>
a href="+code=irq" class="sref">irq
/a>);"> 94
/a>                return 
a href="+code=IRQ_NONE" class="sref">IRQ_NONE
/a>;"> 95
/a>        }"> 96="a>"> 97
/a>        if (
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=eoi" class="sref">eoi
/a>)"> 98
/a>                
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=eoi" class="sref">eoi
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>);"> 99="a>">100
/a>        
a href="+code=evt" class="sref">evt
/a>->
a href="+code=event_handler" class="sref">event_handler
/a>(
a href="+code=evt" class="sref">evt
/a>);">101
/a>        return 
a href="+code=IRQ_HANDLED" class="sref">IRQ_HANDLED
/a>;">102="a>}">103="a>">104
/a>static>void 
a href="+code=apbt_enable_int" class="sref">apbt_enable_int
/a>(struct>
a href="+code=dw_apb_timer" class="sref">dw_apb_timer
/a> *
a href="+code=timer" class="sref">timer
/a>)">105
/a>{">106
/a>        unsigned long 
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">107
/a>        
spa1 class="comment">/* clear pending intr */
/spa15">108
/a>        
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_EOI" class="sref">APBTMR_N_EOI
/a>);">109
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_INT" class="sref">APBTMR_CONTROL_INT
/a>;">110
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">111="a>}">112="a>">113
/a>static>void 
a href="+code=apbt_set_mode" class="sref">apbt_set_mode
/a>(enum>
a href="+code=clock_event_mode" class="sref">clock_event_mode
/a> 
a href="+code=mode" class="sref">mode
/a>,">114
/a>                          struct>
a href="+code=clock_event_device" class="sref">clock_event_device
/a> *
a href="+code=evt" class="sref">evt
/a>)">115
/a>{">116
/a>        unsigned long 
a href="+code=ctrl" class="sref">ctrl
/a>;">117
/a>        unsigned long 
a href="+code=period" class="sref">period
/a>;">118
/a>        struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a> = 
a href="+code=ced_to_dw_apb_ced" class="sref">ced_to_dw_apb_ced
/a>(
a href="+code=evt" class="sref">evt
/a>);">119="a>">120
/a>        
a href="+code=pr_debug" class="sref">pr_debug
/a>(
spa1 class="string">"%s CPU %d mode=%d\n"
/spa15,>
a href="+code=__func__" class="sref">__func__
/a>,>
a href="+code=first_cpu" class="sref">first_cpu
/a>(*
a href="+code=evt" class="sref">evt
/a>->
a href="+code=cpumask" class="sref">cpumask
/a>),">121
/a>                 
a href="+code=mode" class="sref">mode
/a>);">122="a>">123
/a>        switch (
a href="+code=mode" class="sref">mode
/a>) {">124
/a>        case>
a href="+code=CLOCK_EVT_MODE_PERIODIC" class="sref">CLOCK_EVT_MODE_PERIODIC
/a>:">125
/a>                
a href="+code=period" class="sref">period
/a> = 
a href="+code=DIV_ROUND_UP" class="sref">DIV_ROUND_UP
/a>(
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=freq" class="sref">freq
/a>,>
a href="+code=HZ" class="sref">HZ
/a>);">126
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">127
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> |= 
a href="+code=APBTMR_CONTROL_MODE_PERIODIC" class="sref">APBTMR_CONTROL_MODE_PERIODIC
/a>;">128
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">129
/a>                
spa1 class="comment">/*
/spa15">13e="a>
spa1 class="comment">                 * DW APB p. 46, have to disable timer before load counter,
/spa15">131
/a>
spa1 class="comment">                 * may cause>sync problem.
/spa15">132
/a>
spa1 class="comment">                 */
/spa15">133
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">134
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">135
/a>                
a href="+code=udelay" class="sref">udelay
/a>(1);">136
/a>                
a href="+code=pr_debug" class="sref">pr_debug
/a>(
spa1 class="string">"Setting clock period %lu for HZ %d\n"
/spa15,>
a href="+code=period" class="sref">period
/a>,>
a href="+code=HZ" class="sref">HZ
/a>);">137
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=period" class="sref">period
/a>,>
a href="+code=APBTMR_N_LOAD_COUNT" class="sref">APBTMR_N_LOAD_COUNT
/a>);">138
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> |= 
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">139
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">140
/a>                break;">14>"> 142">>142
/a>        case>
a href="+code=CLOCK_EVT_MODE_ONESHOT" class="sref">CLOCK_EVT_MODE_ONESHOT
/a>:">143
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">144
/a>                
spa1 class="comment">/*
/spa15">145
/a>
spa1 class="comment">                 * set free running mode, this mode will let timer reload max
/spa15">146
/a>
spa1 class="comment">                 * timeout which will give time (3min .4.25MHz clock) to rearm
/spa15">147
/a>
spa1 class="comment">                 * the next event, therefore emulate the one-shot mode.
/spa15">148
/a>
spa1 class="comment">                 */
/spa15">149
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">150
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_MODE_PERIODIC" class="sref">APBTMR_CONTROL_MODE_PERIODIC
/a>;">151="a>">152
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">153
/a>                
spa1 class="comment">/* write again to set free running mode */
/spa15">154
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">155="a>">156
/a>                
spa1 class="comment">/*
/spa15">157
/a>
spa1 class="comment">                 * DW APB p. 46, load counter with all 1s before starting free
/spa15">158
/a>
spa1 class="comment">                 * running mode.
/spa15">159
/a>
spa1 class="comment">                 */
/spa15">160
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>~0,>
a href="+code=APBTMR_N_LOAD_COUNT" class="sref">APBTMR_N_LOAD_COUNT
/a>);">161
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_INT" class="sref">APBTMR_CONTROL_INT
/a>;">162
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> |= 
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">163
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">164
/a>                break;">165="a>">166
/a>        case>
a href="+code=CLOCK_EVT_MODE_UNUSED" class="sref">CLOCK_EVT_MODE_UNUSED
/a>:">167
/a>        case>
a href="+code=CLOCK_EVT_MODE_SHUTDOWN" class="sref">CLOCK_EVT_MODE_SHUTDOWN
/a>:">168
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">169
/a>                
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">170
/a>                
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">171
/a>                break;">172="a>">173
/a>        case>
a href="+code=CLOCK_EVT_MODE_RESUME" class="sref">CLOCK_EVT_MODE_RESUME
/a>:">174
/a>                
a href="+code=apbt_enable_int" class="sref">apbt_enable_int
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>);">175
/a>                break;">176
/a>        }">177
/a>}">178
/a>">179
/a>static>int>
a href="+code=apbt_next_event" class="sref">apbt_next_event
/a>(unsigned long 
a href="+code=delta" class="sref">delta
/a>,">180
/a>                           struct>
a href="+code=clock_event_device" class="sref">clock_event_device
/a> *
a href="+code=evt" class="sref">evt
/a>)">181="a>{">182
/a>        unsigned long 
a href="+code=ctrl" class="sref">ctrl
/a>;">183
/a>        struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a> = 
a href="+code=ced_to_dw_apb_ced" class="sref">ced_to_dw_apb_ced
/a>(
a href="+code=evt" class="sref">evt
/a>);">184="a>">185
/a>        
spa1 class="comment">/* Disable timer */
/spa15">186
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">187
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">188
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">189
/a>        
spa1 class="comment">/* write new count */
/spa15">190
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=delta" class="sref">delta
/a>,>
a href="+code=APBTMR_N_LOAD_COUNT" class="sref">APBTMR_N_LOAD_COUNT
/a>);">191
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> |= 
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">192
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">193="a>">194
/a>        return 0;">195="a>}">196="a>">197
/a>
spa1 class="comment">/**
/spa15">198
/a>
spa1 class="comment"> * dw_apb_clockevent_init() - use>a1 APB timer as a clock_event_device
/spa15">199
/a>
spa1 class="comment"> *
/spa15">20e="a>
spa1 class="comment"> * @cpu:        The CPU the events will be targeted at.
/spa15">201
/a>
spa1 class="comment"> * @namo:       The namo used for the timer and the IRQ for it.
/spa15">202
/a>
spa1 class="comment"> * @rating:     The rating to give the timer.
/spa15">203
/a>
spa1 class="comment"> * @base:       I/O base for the timer registers.
/spa15">204
/a>
spa1 class="comment"> * @irq:        The interrupt number to use for the timer.
/spa15">205
/a>
spa1 class="comment"> * @freq:       The frequency that the timer counts at.
/spa15">206
/a>
spa1 class="comment"> *
/spa15">207
/a>
spa1 class="comment"> * This creates a clock_event_device for using with the generic clock layer
/spa15">208
/a>
spa1 class="comment"> * but does not start and register it.  This should be done with
/spa15">209
/a>
spa1 class="comment"> * dw_apb_clockevent_register() as the next step.  If this is the first time
/spa15">21e="a>
spa1 class="comment"> * it has bee1 called for a timer then the IRQ will be requested, if not it
/spa15">211
/a>
spa1 class="comment"> * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
/spa15">212
/a>
spa1 class="comment"> * releasing the IRQ.
/spa15">213
/a>
spa1 class="comment"> */
/spa15">214
/a>struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *">215
/a>
a href="+code=dw_apb_clockevent_init" class="sref">dw_apb_clockevent_init
/a>(int>
a href="+code=cpu" class="sref">cpu
/a>, const char *
a href="+code=namo" class="sref">namo
/a>, unsigned 
a href="+code=rating" class="sref">rating
/a>,">216
/a>                       void 
a href="+code=__iomem" class="sref">__iomem
/a> *
a href="+code=base" class="sref">base
/a>,>int>
a href="+code=irq" class="sref">irq
/a>,>unsigned long 
a href="+code=freq" class="sref">freq
/a>)">217
/a>{">218
/a>        struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a> =">219
/a>                
a href="+code=kzalloc" class="sref">kzalloc
/a>(sizeof(*
a href="+code=dw_ced" class="sref">dw_ced
/a>),>
a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL
/a>);">220
/a>        int>
a href="+code=err" class="sref">err
/a>;">221="a>">222
/a>        if (!
a href="+code=dw_ced" class="sref">dw_ced
/a>)">223
/a>                return 
a href="+code=NULL" class="sref">NULL
/a>;">224="a>">225
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=base" class="sref">base
/a> = 
a href="+code=base" class="sref">base
/a>;">226
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=irq" class="sref">irq
/a> = 
a href="+code=irq" class="sref">irq
/a>;">227
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=freq" class="sref">freq
/a> = 
a href="+code=freq" class="sref">freq
/a>;">228
/a>">229
/a>        
a href="+code=clockevents_calc_mult_shift" class="sref">clockevents_calc_mult_shift
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>,>
a href="+code=freq" class="sref">freq
/a>,>
a href="+code=APBT_MIN_PERIOD" class="sref">APBT_MIN_PERIOD
/a>);">230
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=max_delta_ns" class="sref">max_delta_ns
/a> = 
a href="+code=clockevent_delta2ns" class="sref">clockevent_delta2ns
/a>(0x7fffffff,">231
/a>                                                       &
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>);">232
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=min_delta_ns" class="sref">min_delta_ns
/a> = 
a href="+code=clockevent_delta2ns" class="sref">clockevent_delta2ns
/a>(5000, &
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>);">233
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=cpumask" class="sref">cpumask
/a> = 
a href="+code=cpumask_of" class="sref">cpumask_of
/a>(
a href="+code=cpu" class="sref">cpu
/a>);">234
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=features" class="sref">features
/a> = 
a href="+code=CLOCK_EVT_FEAT_PERIODIC" class="sref">CLOCK_EVT_FEAT_PERIODIC
/a> | 
a href="+code=CLOCK_EVT_FEAT_ONESHOT" class="sref">CLOCK_EVT_FEAT_ONESHOT
/a>;">235
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=set_mode" class="sref">set_mode
/a> = 
a href="+code=apbt_set_mode" class="sref">apbt_set_mode
/a>;">236
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=set_next_event" class="sref">set_next_event
/a> = 
a href="+code=apbt_next_event" class="sref">apbt_next_event
/a>;">237
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=irq" class="sref">irq
/a> = 
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=irq" class="sref">irq
/a>;">238
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=rating" class="sref">rating
/a> = 
a href="+code=rating" class="sref">rating
/a>;">239
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=namo" class="sref">namo
/a> = 
a href="+code=namo" class="sref">namo
/a>;">240
/a>">241
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>.
a href="+code=namo" class="sref">namo
/a>          = 
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>.
a href="+code=namo" class="sref">namo
/a>;"> 242">>242
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>.
a href="+code=handler" class="sref">handler
/a>       = 
a href="+code=dw_cksource/dw_apb_rq" class="sref">ode=dw_cksource/dw_apef">namo
/a>;">243
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>.
a href="+code=dev_id" class="sref">dev_id
/a>        = &
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>namo
/a>;">244
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>.
a href="+code=irq" class="sref">irq
/a>           = 
a href="+code=irq" class="sref">irq
/a>;">245
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>.
a href="+code=flags" class="sref">flags
/a>         = 
a href="+code=IRQF_TIMER" class="sref">IRQF_TIMER
/a> | 
a href="+code=IRQF_IRQPOLL" class="sref">IRQF_IRQPOLL
/a> |">246
/a>                                          
a href="+code=IRQF_NOBALANCING" class="sref">IRQF_NOBALANCING
/a> |">247
/a>                                          
a href="+code=IRQF_DISABLED" class="sref">IRQF_DISABLED
/a>;">248
/a>">249
/a>        
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=eoi" class="sref">eoi
/a> = 
a href="+code=apbt_eoi" class="sref">apbt_eoi
/a>;">250
/a>        
a href="+code=err" class="sref">err
/a> = 
a href="+code=setupb_rq" class="sref">setupb_rq
/a>(
a href="+code=irq" class="sref">irq
/a>,>&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=irqaction" class="sref">irqaction
/a>);">251
/a>        if (
a href="+code=err" class="sref">err
/a>) {">252
/a>                
a href="+code=pr_err" class="sref">pr_err
/a>(
spa1 class="string">"failed to request timer irq\n"
/spa15);">253
/a>                
a href="+code=kfree" class="sref">kfree
/a>(
a href="+code=dw_ced" class="sref">dw_ced
/a>);">254
/a>                
a href="+code=dw_ced" class="sref">dw_ced
/a> = 
a href="+code=NULL" class="sref">NULL
/a>;">255
/a>        }">256="a>">257
/a>        return 
a href="+code=dw_ced" class="sref">dw_ced
/a>;">258
/a>}">259="a>">26e="a>
spa1 class="comment">/**
/spa15">261
/a>
spa1 class="comment"> * dw_apb_clockevent_resume() - resume a clock that has bee1 paused.
/spa15">262
/a>
spa1 class="comment"> *
/spa15">263
/a>
spa1 class="comment"> * @dw_ced:     The APB clock to resume.
/spa15">264
/a>
spa1 class="comment"> */
/spa15">265="a>void 
a href="+code=dw_apb_clockevent_resume" class="sref">ode=dw_cksource/dwresume
/a>(struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a>)">266
/a>{">267
/a>        
a href="+code=enable_irq" class="sref">enable_irq
/a>(
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=irq" class="sref">irq
/a>);">268
/a>}">269="a>">27e="a>
spa1 class="comment">/**
/spa15">271
/a>
spa1 class="comment"> * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
/spa15">272
/a>
spa1 class="comment"> *
/spa15">273
/a>
spa1 class="comment"> * @dw_ced:     The APB clock to stop generating the events.
/spa15">274
/a>
spa1 class="comment"> */
/spa15">275="a>void 
a href="+code=dw_apb_clockevent_stop" class="sref">ode=dw_cksource/dwstop
/a>(struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a>)">276
/a>{">277
/a>        
a href="+code=free_irq" class="sref">free_irq
/a>(
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=irq" class="sref">irq
/a>, &
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>);">278
/a>}">279="a>">28e="a>
spa1 class="comment">/**
/spa15">281
/a>
spa1 class="comment"> * dw_apb_clockevent_register() - register the clock with the generic layer
/spa15">282
/a>
spa1 class="comment"> *
/spa15">283
/a>
spa1 class="comment"> * @dw_ced:     The APB clock to register as a clock_event_device.
/spa15">284
/a>
spa1 class="comment"> */
/spa15">285="a>void 
a href="+code=dw_apb_clockevent_register" class="sref">ode=dw_cksource/dwregister
/a>(struct>
a href="+code=dw_apb_clock_event_device" class="sref">dw_apb_clock_event_device
/a> *
a href="+code=dw_ced" class="sref">dw_ced
/a>)">286
/a>{">287
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>,>0,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">288
/a>        
a href="+code=clockevents_register_device" class="sref">clockevents_register_device
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=ced" class="sref">ced
/a>);">289
/a>        
a href="+code=apbt_enable_int" class="sref">apbt_enable_int
/a>(&
a href="+code=dw_ced" class="sref">dw_ced
/a>->
a href="+code=timer" class="sref">timer
/a>);">290
/a>}">291="a>">292
/a>
spa1 class="comment">/**
/spa15">293
/a>
spa1 class="comment"> * dw_apb_clocksource_start() - start the clocksource counting.
/spa15">294
/a>
spa1 class="comment"> *
/spa15">295
/a>
spa1 class="comment"> * @dw_cs:      The clocksource to start.
/spa15">296
/a>
spa1 class="comment"> *
/spa15">297
/a>
spa1 class="comment"> * This is used to start the clocksource before registration and ca1 bo used
/spa15">298
/a>
spa1 class="comment"> * to enable calibration of timers.
/spa15">299
/a>
spa1 class="comment"> */
/spa15">30e="a>void 
a href="+code=dw_apb_clocksource_start" class="sref">dw_apb_clocksource_start
/a>(struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a>)">301="a>{">302
/a>        
spa1 class="comment">/*
/spa15">303
/a>
spa1 class="comment">         * start count down from 0xffff_ffff. this is done by toggling the
/spa15">304
/a>
spa1 class="comment">         * enable bit then load initial load count to ~0.
/spa15">305
/a>
spa1 class="comment">         */
/spa15">306
/a>        unsigned long 
a href="+code=ctrl" class="sref">ctrl
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">307
/a>">308
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a>;">309
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">310
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>~0,>
a href="+code=APBTMR_N_LOAD_COUNT" class="sref">APBTMR_N_LOAD_COUNT
/a>);">311
/a>        
spa1 class="comment">/* enable, mask interrupt */
/spa15">312
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> &= ~
a href="+code=APBTMR_CONTROL_MODE_PERIODIC" class="sref">APBTMR_CONTROL_MODE_PERIODIC
/a>;">313
/a>        
a href="+code=ctrl" class="sref">ctrl
/a> |= (
a href="+code=APBTMR_CONTROL_ENABLE" class="sref">APBTMR_CONTROL_ENABLE
/a> | 
a href="+code=APBTMR_CONTROL_INT" class="sref">APBTMR_CONTROL_INT
/a>);">314
/a>        
a href="+code=apbt_writel" class="sref">apbt_writel
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=ctrl" class="sref">ctrl
/a>,>
a href="+code=APBTMR_N_CONTROL" class="sref">APBTMR_N_CONTROL
/a>);">315
/a>        
spa1 class="comment">/* read it once to get cached counter value initialized */
/spa15">316
/a>        
a href="+code=dw_apb_clocksource_read" class="sref">dw_apb_clocksource_read
/a>(
a href="+code=dw_cs" class="sref">dw_cs
/a>);">317
/a>}">318
/a>">319
/a>static>
a href="+code=cycle_t" class="sref">cycle_t
/a> 
a href="+code=__apbt_read_clocksource" class="sref">__apbt_read_clocksource
/a>(struct>
a href="+code=clocksource" class="sref">clocksource
/a> *
a href="+code=cs" class="sref">cs
/a>)">320
/a>{">321
/a>        unsigned long 
a href="+code=current_count" class="sref">current_count
/a>;">322
/a>        struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a> =">323
/a>                
a href="+code=clocksource_to_dw_apb_clocksource" class="sref">clocksource_to_dw_apb_clocksource
/a>(
a href="+code=cs" class="sref">cs
/a>);">324="a>">325
/a>        
a href="+code=current_count" class="sref">current_count
/a> = 
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CURRENT_VALUE" class="sref">APBTMR_N_CURRENT_VALUE
/a>);">326="a>">327
/a>        return (
a href="+code=cycle_t" class="sref">cycle_t
/a>)~
a href="+code=current_count" class="sref">current_count
/a>;">328
/a>}">329="a>">330
/a>static>void 
a href="+code=apbt_restart_clocksource" class="sref">apbt_restart_clocksource
/a>(struct>
a href="+code=clocksource" class="sref">clocksource
/a> *
a href="+code=cs" class="sref">cs
/a>)">331="a>{">332
/a>        struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a> =">333
/a>                
a href="+code=clocksource_to_dw_apb_clocksource" class="sref">clocksource_to_dw_apb_clocksource
/a>(
a href="+code=cs" class="sref">cs
/a>);">334="a>">335
/a>        
a href="+code=dw_apb_clocksource_start" class="sref">dw_apb_clocksource_start
/a>(
a href="+code=dw_cs" class="sref">dw_cs
/a>);">336
/a>}">337
/a>">338
/a>
spa1 class="comment">/**
/spa15">339
/a>
spa1 class="comment"> * dw_apb_clocksource_init() - use>a1 APB timer as a clocksource.
/spa15">34e="a>
spa1 class="comment"> *
/spa15">341
/a>
spa1 class="comment"> * @rating:     The rating to give the clocksource.
/spa15"> 342">>342
/a>
spa1 class="comment"> * @L40":       The namo for the clocksource.
/spa15">343
/a>
spa1 class="comment"> * @base:       The I/O base for the timer registers.
/spa15">344
/a>
spa1 class="comment"> * @freq:       The frequency that the timer counts at.
/spa15">345
/a>
spa1 class="comment"> *
/spa15">346
/a>
spa1 class="comment"> * This creates a clocksource using a1 APB timer but does not yet register it
/spa15">347
/a>
spa1 class="comment"> * with the clocksource system.  This should be done with
/spa15">348
/a>
spa1 class="comment"> * dw_apb_clocksource_register() as the next step.
/spa15">349
/a>
spa1 class="comment"> */
/spa15">350
/a>struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *">351
/a>
a href="+code=dw_apb_clocksource_init" class="sref">dw_apb_clocksource_init
/a>(unsigned 
a href="+code=rating" class="sref">rating
/a>, const char *
a href="+code=namo" class="sref">namo
/a>, void 
a href="+code=__iomem" class="sref">__iomem
/a> *
a href="+code=base" class="sref">base
/a>,">352
/a>                        unsigned long 
a href="+code=freq" class="sref">freq
/a>)">353
/a>{">354
/a>        struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a> = 
a href="+code=kzalloc" class="sref">kzalloc
/a>(sizeof(*
a href="+code=dw_cs" class="sref">dw_cs
/a>),>
a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL
/a>);">355
/a>">356
/a>        if (!
a href="+code=dw_cs" class="sref">dw_cs
/a>)">357
/a>                return 
a href="+code=NULL" class="sref">NULL
/a>;">358
/a>">359
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=base" class="sref">base
/a> = 
a href="+code=base" class="sref">base
/a>;">360
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=freq" class="sref">freq
/a> = 
a href="+code=freq" class="sref">freq
/a>;">361
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=namo" class="sref">namo
/a> = 
a href="+code=namo" class="sref">namo
/a>;">362
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=rating" class="sref">rating
/a> = 
a href="+code=rating" class="sref">rating
/a>;">363
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=read" class="sref">read
/a> = 
a href="+code=__apbt_read_clocksource" class="sref">__apbt_read_clocksource
/a>;">364
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=mask" class="sref">mask
/a> = 
a href="+code=CLOCKSOURCE_MASK" class="sref">CLOCKSOURCE_MASK
/a>(32);">365
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=flags" class="sref">flags
/a> = 
a href="+code=CLOCK_SOURCE_IS_CONTINUOUS" class="sref">CLOCK_SOURCE_IS_CONTINUOUS
/a>;">366
/a>        
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>.
a href="+code=resume" class="sref">resume
/a> = 
a href="+code=apbt_restart_clocksource" class="sref">apbt_restart_clocksource
/a>;">367
/a>">368
/a>        return 
a href="+code=dw_cs" class="sref">dw_cs
/a>;">369="a>}">370
/a>">371
/a>
spa1 class="comment">/**
/spa15">372
/a>
spa1 class="comment"> * dw_apb_clocksource_register() - register the APB clocksource.
/spa15">373
/a>
spa1 class="comment"> *
/spa15">374
/a>
spa1 class="comment"> * @dw_cs:      The clocksource to register.
/spa15">375
/a>
spa1 class="comment"> */
/spa15">376
/a>void 
a href="+code=dw_apb_clocksource_register" class="sref">ode=dw_cksousource_register
/a>(struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a>)">377
/a>{">378
/a>        
a href="+code=clocksource_register_hz" class="sref">clocksource_register_hz
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>,>
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>.
a href="+code=freq" class="sref">freq
/a>);">379="a>}">380
/a>">381
/a>
spa1 class="comment">/**
/spa15">382
/a>
spa1 class="comment"> * dw_apb_clocksource_read() - read the current value of a clocksource.
/spa15">383
/a>
spa1 class="comment"> *
/spa15">384
/a>
spa1 class="comment"> * @dw_cs:      The clocksource to read.
/spa15">385
/a>
spa1 class="comment"> */
/spa15">386
/a>
a href="+code=cycle_t" class="sref">cycle_t
/a> 
a href="+code=dw_apb_clocksource_read" class="sref">dw_apb_clocksource_read
/a>(struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a>)">387
/a>{">388
/a>        return (
a href="+code=cycle_t" class="sref">cycle_t
/a>)~
a href="+code=apbt_readl" class="sref">apbt_readl
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=timer" class="sref">timer
/a>,>
a href="+code=APBTMR_N_CURRENT_VALUE" class="sref">APBTMR_N_CURRENT_VALUE
/a>);">389="a>}">390
/a>">391
/a>
spa1 class="comment">/**
/spa15">392
/a>
spa1 class="comment"> * dw_apb_clocksource_unregister() - unregister and free a clocksource.
/spa15">393
/a>
spa1 class="comment"> *
/spa15">394
/a>
spa1 class="comment"> * @dw_cs:      The clocksource to unregister/free.
/spa15">395
/a>
spa1 class="comment"> */
/spa15">396
/a>void 
a href="+code=dw_apb_clocksource_unregister" class="sref">dw_apb_clocksource_unregister
/a>(struct>
a href="+code=dw_apb_clocksource" class="sref">dw_apb_clocksource
/a> *
a href="+code=dw_cs" class="sref">dw_cs
/a>)">397
/a>{">398
/a>        
a href="+code=clocksource_unregister" class="sref">clocksource_unregister
/a>(&
a href="+code=dw_cs" class="sref">dw_cs
/a>->
a href="+code=cs" class="sref">cs
/a>);">399="a>">400
/a>        
a href="+code=kfree" class="sref">kfree
/a>(
a href="+code=dw_cs" class="sref">dw_cs
/a>);">401="a>}">402
/a>
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