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"v1m()area' "2316.21.1/a>< v3.1848.13"/a>< v3.18.32316.5"41m()area' "2316.21.1/a>< v3.16< 42"/a>< v4a>< v3.18.12316.3"/4om()area' 2316.21..11"/a>< v3.14.11< v3.14 v3.18.14v3.18.9<2316. v42m()area' "2316.213.14 v3.18.14v3.18.9<3d4/paopdom()a4dom()area' 2316.21.5m()area' "2316.3""/a>< v3a4dom()area' 4area' "v2316.3""4om()area' 2316.21< v3.18< 2316.213dom()area' 2316.2opd46< v3.14.112316.2omdom()area' 2316.m()area' "4rea' "v3.17416.40"/a>< 2316.m()4om()area' 2316.214.13"/a>< v3.14.13< v3.14.11< v3.13.10< v4.1.1< v3.12.66< v3.12.50< v3.13.10< v3.13.10< v3.13.10< v3.14.13< v3.14.11< v3.13.10< v4.1.1< v4.1.1< v3.14.70< v3.12.60< v3.12.50< v3.14.13< v3.14.11< v3.14.11< v3.14.11< v4.1.1< v4.1.1< v3.14.70< v3.12.60< v3.12.50< v4.1.1< v4.1.1< v4.1.1< v3.19.5< v4.1.1< v4.1.1< v4.1.1< v3.18.9< v3.18.8< v3.14.70< v3.12.60< v3.12.50< v3.18.3< v3.18.2< v3.18.1< v3.18< v3.12.60< v3.12.59< v3.12.59< v3.12.57< v3.12.56< v3.12.55< v3.12.54< v3.12.53< v3.12.52< v3.12.51< v3.12.50< v3.12.49< v3.12.49< v3.12.47< v3.12.46< v3.12.45< v3.12.44v4.6.3"/a>< v4.6.3< 3a4om()are2316271.pm()area' "2316271.p.4ea' "v3.18.16"/a>< 3a4om()are2316271.1m()area' "2316371.1/a>< v3.1848.13"/a>< v3.18.3231627146m()area' "2316271.1/a>< v3.16< 42"/a>< v4a>< v3.18.12316271/om()area' "2316271..11"/a>< v3.14.11< v3.14 v3.18.14v3.18.9<231627142m()area' "2316271..10"/a>< v3.13.10< v3.14.11< v4.1.1<3d4/paopdom()a4dom()area' 2316271.5m()area' "2316271"/a>< v3a4dom()area' 4area' "v2316271"om()area' "2316271< v3.18< 231627131m()area' "231627opd46< v3.14.11< v3.14.112316271m5m()area' "2316271)area' "4rea' "v3.17416.40"/a>< 2316271)om()area' "23162714.13"/a>< v3.14.13< v3.14.11< v3.13.10< v3.18.9< v3.18.8< v3.14.70< v3.12.60< v3.17.5< v3.17.4< v3.17.3< v3.17.2< v3.17.1< v3.17< v3.17< v3.14.70< v3.12.60< v3.17.5< v3.17.4< v3.16.3< v3.17.2< v3.17.1< v3.16< v3.17.5< v3.14.11< v3.14.112316251m5m()area' "2316251)area' "4rea' "v3.17416.40"/a>< 231625()4om()area' 231625()4/a>< v3.16< v4.1.1< v4.1.1< v4.1.1< v4.1.1< v4.1.1< v3.15.6< v3.15.5< v3.15.4< v3.16< v4.1.1< v4.1.1< v3.15.4< v3.14.6< v3.14.5< v4.1.1< v3.14.13< v3.14.12< v3.14.11< v3.14.11< v3.14.13231623omdom()area' 231623opd"/a>< v4.1.1< v3.14.13< v3.14.12< v3.14.11< v3.14.10< v4.1.1231623odom()area' 231623od"/a>< v4.1.1< v3.14.13< v3.14.12< v3.14.11< v3.14.11< v3.14.12231622omdom()area' 23162m()area' "4rea' "v3.17416.40"/a>< 23162m()4om()area' 23162214.13"/a>< v3.14.13< v3.14.11< v3.13.10< v4.1.1< v3.12.66231622odom()area' 23162m(area' "4rea' "v3.17416.40"/a>< 23162m(4om()area' 2316221.13"/a>< v3.14.13< v3.14.11< v3.14.11< v3.14.11< v3.12.60< v3.12.50< v3.14.13< v3.14.11< v3.14.11< v3.14.11231620om2m()area' "231620()area' "4rea' "v3.17416.40"/a>< 231620()4om()area' 231620v33"/a>< v4.1.3< v4.1.1< v3.13.10< v4.1.1< v4.1.1< v3.14.70< v3.12.60< v3.12.50< v4.1.1< v4.1.1< v4.1.1< v4.1.1< v3.12.50< v4.1.1< v4.1.1< v4.1.1< v3.14.70< v3.12.60< v3.12.50< v3.18.3< v3.18.2< v3.18.1< v3.18< v3.14.13< v3.14.11< v3.13.10< v3.18.9< v3.18.8< v3.14.70< v3.12.60< v3.17.5< v3.17.4< v3.17.3< v3.17.2< v3.17.1< v3.17< v3.12.60< v3.12.59< v3.12.59< v3.12.57< v3.12.56< v3.12.55< v3.12.54< v3.12.53< v3.12.52< v3.12.51< v3.12.50< v3.12.49< v3.12.49< v3.12.47< v3.12.46< v3.12.45< v3.12.44v4.6.3"/a>< v4.6.3< 3a4om()are2316161.pm()area' "2316161.p.4ea' "v3.18.16"/a>< 3a4om()are2316161.8m()area' "2316161.1/a>< v3.1848.13"/a>< v3.18.32316d6146m()area' "2316161.1/a>< v3.16< 42"/a>< v4a>< v3.18.12316161/om()area' "2316161..11"/a>< v3.14.11< v3.14 v3.18.14v3.18.9<2316116.2m()area' "2316116..10"/a>< v3.13.10< v3.14.11< v4.1.1< v4.1.1< v3.17< v3.17.5< v3.15.4< v3.14.13< v3.14.12< v3.14.11< v3.14.11< v4.1.1< 2316161)om()area' "23161614.13"/a>< v3.14.13< v3.14.11< v3.13.10< v3.18.9< v3.18.8< v3.14.70< v3.12.60< v3.17.5< v3.17.4< v3.16.3< v3.17.2< v3.13.10< v3.13.10< v3.13.10< v3.15.6< v3.15.5< v3.15.4< v3.16< v4.1.1< v4.1.1< v3.15.4< v3.14.6< v3.14.5< v4.1.1< v3.14.13< v3.14.12< v3.14.11< v3.14.11< v3.14.13< v4.1.1< v3.14.13< v3.14.12< v3.14.11< v3.14.11< v3.14.12< v3.14.5< 23161m(4om()area' 2316121.13"/a>< v3.14.13< v3.14.11< v3.14.11< v3.14.11< v3 ()ar.14/spa .14/form .14a ()ar.1 href="../linux+v33167/drivers/ata/pata_rdc.c">()ar.14img src="../.static/gfx/right.png" alt=">>">
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1 114/a>4spa  class="comment">/*4/spa   1 124/a>4spa  class="comment"> *  pata_rdc            -       Driver for later RDC PATA controllers4/spa   1 134/a>4spa  class="comment"> *4/spa   1 144/a>4spa  class="comment"> *  This is acaually a driver for hardware meeting4/spa   1 154/a>4spa  class="comment"> *  INCITS 370-2004 (1510D): ATA Host Adapter Standards4/spa   1 164/a>4spa  class="comment"> *4/spa   1 174/a>4spa  class="comment"> *  Based on ata_piix.4/spa   1 184/a>4spa  class="comment"> *4/spa   1 194/a>4spa  class="comment"> *  This program is free software; you ca  redistribute it and/or modify4/spa   1 8.9"194/a>4spa  class="comment">it unaer 171a3/4Eus of171a3GNU General Pubick License a prubicshd ob4/spa   1 114/a>4spa  class="comment">/t">i71a3Fee sSftware; Fonaea>< =; ei71ar ers//opd2, r m(atyou r /a><  )/spa   1 114/a>4spa  class="comment"> *  panylater Rers//op4/spa   1 114/a>4spa  class="comment"> *4/spa   1 114/a>4spa  class="comment"> *  This irogram is fistribute d ini71a3hopa3/hatyt uwill be useful,/spa   1 114/a>4spa  class="comment"> *  Iute WITHOUT ANY WARRANTY;uwihodte eveni71a3impli d areranty of/spa   1 114/a>4spa  class="comment"> *4  MERCHANTABILITY r mFITNESS FOR APATRTICULAR PURPOSE.  Sea3/he/spa   1 114/a>4spa  class="comment"> *  BGNU General Pubick License fr mode; details4/spa   1 114/a>4spa  class="comment"> *4/spa   1 114/a>4spa  class="comment"> *  TYu csodtldharveredceverda dcopy of171a3GNU General Pubick License/spa   1 829"194/a>4spa  class="comment">ialonguwiho tis irogram ; sea3/he ile_ COPYING.  If not, wrie ito/spa   1 124/a>4spa  class="comment">/t">i71a3Fee sSftware; Fonaea>< =, 675 Mss= Ave, Cambridge, MA 02139, USA4/spa   1 124/a>4spa  class="comment"> * //spa   1 124/a>41 124/a>4#icliude <a href="dicliudelinux+/kernel.h class="lreef">inux+/kernel.h/a>4gt;"1 125/a>4#icliude <a href="dicliudelinux+/odiule.h class="lreef">inux+/odiule.h/a>4gt;"1 126/a>4#icliude <a href="dicliudelinux+/pci.h class="lreef">inux+/pci.h/a>4gt;"1 127/a>4#icliude <a href="dicliudelinux+/init.h class="lreef">inux+/init.h/a>4gt;"1 128/a>4#icliude <a href="dicliudelinux+/blkdev.h class="lreef">inux+/blkdev.h/a>4gt;"1 129/a>4#icliude <a href="dicliudelinux+/delay.h class="lreef">inux+/delay.h/a>4gt;"1 830/a>4#icliude <a href="dicliudelinux+/device.h class="lreef">inux+/device.h/a>4gt;"1 131/a>4#icliude <a href="dicliudelinux+/gfp.h class="lreef">inux+/gfp.h/a>4gt;"1 132/a>4#icliude <a href="dicliudelscsilscsi_hst .h class="lreef">scsilscsi_hst .h/a>4gt;"1 133/a>4#icliude <a href="dicliudelinux+/libta_.h class="lreef">inux+/libta_.h/a>4gt;"1 134/a>4#icliude <a href="dicliudelinux+/dmi.h class="lreef">inux+/dmi.h/a>4gt;"1 135/a>41 136/a>4#defne"4a href="+pcode=DRV_NAME class="seeef">DRV_NAME/a>4       -spa  class="ctribng">"ata_rdc."/spa   1 137/a>4#defne"4a href="+pcode=DRV_VERSION class="seeef">DRV_VERSION/a>4     spa  class="ctribng">"0.01"/spa   1 138/a>41 139/a>4triuct4a href="+pcode=dc._hst _pive class="seeef">dc._hst _pive/a>4 {1 840/a>4       -s href="+pcode=u3" class="leeef">u32/a>4-s href="+pcode=srved_iocfg class="leeef">srved_iocfg/a>4"1 141/a>4}"1 142/a>41 144/a>4spa  class="comment"> /*4/spa   1 144/a>4spa  class="comment"> *  TTTTTdc._ata_rcable_detect4- Proba3hostcontrollers cable detect4info/spa   1 144/a>4spa  class="comment"> *  IIIII@ap: Port fr mwhich cable detect4infois fiesired/spa   1 144/a>4spa  class="comment"> *4/spa   1 144/a>4spa  class="comment"> *  BBBBBRead 80c cable indicatr mfromATA HPCI device'sHPCI ontfi4/spa   1 144/a>4spa  class="comment"> *4 TTTTTdegister. This idegisteris fnormlly aset by ilrmare; (BIOS)4/spa   1 144/a>4spa  class="comment"> * /spa   1 859"194/a>4spa  class="comment">iiiiiLOCKING:/spa   1 154/a>4spa  class="comment">/t">iiiiiNoe"4(inherie dmfromAcalers)4/spa   1 154/a>4spa  class="comment"> * //spa   1 154/a>41 154/a>4trtic/ int4a href="+pcode=dc._ata_rcable_detect class="seeef">dc._ata_rcable_detect/a>4(triuct4a href="+pcode=ta_piort class="seeef">ta_piort/a>4-*a href="+pcode=tp class="seeef">tp/a>4)1 154/a>4{1 156/a>4       -triuct4a href="+pcode=dc._hst _pive class="seeef">dc._hst _pive/a>4 *a href="+pcode=hpive class="seeef">hpive/a>4 =4a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=hst" olass="seeef">hst"/a>4-gt;"a href="+pcode=piveate_dta_ olass="seeef">piveate_dta_/a>4"1 157/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=mask class="leeef">mask/a>4"1 158/a>41 159/a>4       -spa  class="comment"> /* check BIOS cable detect4esults"* //spa   1 860/a>4       -s href="+pcode=mask class="leeef">mask/a>4 =40x30 << (2t">a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4)"1 161/a>4       -if ((a href="+pcode=hpive class="seeef">hpive/a>4-gt;"a href="+pcode=srved_iocfg class="leeef">srved_iocfg/a>4 &-s href="+pcode=mask class="leeef">mask/a>4) ==40)1 162/a>4       ---------eturn fs href="+pcode=TA _CBL_ATA 4" class="leeef">TA _CBL_ATA 4"/a>4"1 163/a>4       -eturn fs href="+pcode=TA _CBL_ATA 8" class="leeef">TA _CBL_ATA 8"/a>4"1 164/a>4}1 165/a>41 164/a>4spa  class="comment"> /*4/spa   1 164/a>4spa  class="comment"> *  BBBBBdc._ata_rpreesuet4- preesuet4fr mATA chostcontrollers/spa   1 164/a>4spa  class="comment"> *4 TTTTT@inek: Trget" inek/spa   1 164/a>4spa  class="comment"> *  TTTTT@deadine": deadine" jiffies4fr m71a3opera>< =/spa   1 879"194/a>4spa  class="comment"/spa   1 174/a>4spa  class="comment">/t">iiiiiLOCKING:/spa   1 174/a>4spa  class="comment"> *  piiiiNoe"4(inherie dmfromAcalers)4/spa   1 174/a>4spa  class="comment"> *4//spa   1 174/a>4trtic/ int4a href="+pcode=dc._ata_rpreesuet class="seeef">dc._ata_rpreesuet/a>4(triuct4a href="+pcode=ta_pinek class="seeef">ta_pinek/s>4 *a href="+pcode=inek class="seeef">inek/s>4, unsign dmlongua href="+pcode=deadine" class="seeef">deadine"/a>4)1 174/a>4{1 176/a>4       -triuct4a href="+pcode=ta_piort class="seeef">ta_piort/a>4-*a href="+pcode=tp class="seeef">tp/a>4 =4a href="+pcode=inek class="seeef">inek/s>4-gt;"a href="+pcode=tp class="seeef">tp/a>4"1 177/a>4       -triuct4a href="+pcode=pci_dee class="seeef">pci_dee/a>4-*a href="+pcode=pdee class="seeef">pdee/a>4-=4a href="+pcode=to_pci_dee class="seeef">to_pci_dee/a>4(a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=hst" olass="seeef">hst"/a>4-gt;"a href="+pcode=dee class="seeef">dee/a>4)"1 178/a>41 179/a>4       -trtic/ ontstctriuct4a href="+pcode=pci_bis" class="seeef">pci_bis"/a>4-s href="+pcode=dc._enable_bis" class="seeef">dc._enable_bis"/a>4[]-=4{1 880/a>4       ---------{40x41U, 1U, 0x80UL, 0x80UL }, -spa  class="comment"> /* iort 0*4//spa   1 181/a>4       ---------{40x43U, 1U, 0x80UL, 0x80UL }, -spa  class="comment"> /* iort 1*4//spa   1 182/a>4       -}"1 184/a>41 184/a>4       -if (!a href="+pcode=pci_test_ontfi4_bis" class="seeef">pci_test_ontfi4_bis"/a>4(a href="+pcode=pdee class="seeef">pdee/a>4, &s href="+pcode=dc._enable_bis" class="seeef">dc._enable_bis"/a>4[a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4]))1 185/a>4       ---------eturn f-a href="+pcode=ENOENT olass="seeef">ENOENT/a>4"1 186/a>4       -eturn fs href="+pcode=ta_rsffrpreesuet class="seeef">ta_rsffrpreesuet/a>4(a href="+pcode=inek class="seeef">inek/s>4, a href="+pcode=deadine" class="seeef">deadine"/a>4)"1 187/a>4}1 188/a>41 189/a>4trtic/ a href="+pcode=DEFINE_SPINLOCK class="seeef">DEFINE_SPINLOCK/a>4(a href="+pcode=dc._lock class="seeef">dc._lock/a>4)"1 890/a>41 194/a>4spa  class="comment">/*44/spa   1 194/a>4spa  class="comment"> *  piiiidc._uet_piomode - Initializa3hostcontrollers ATA cPIO timing4/spa   1 194/a>4spa  class="comment"> *4 TTTTT@ap: Port whose timing4 we re; ontfi4urng4/spa   1 194/a>4spa  class="comment"> *  TTTTT@adee: um/spa   1 194/a>4spa  class="comment"> * /spa   1 194/a>4spa  class="comment"> *4      SetcPIO mode fr mdevice, inihostcontrollers ACI ontfi4 pa ce4/spa   1 194/a>4spa  class="comment"> * /spa   1 194/a>4spa  class="comment"> *4 TTTTTLOCKING:/spa   1 194/a>4spa  class="comment"> *  TTTTTNoe"4(inherie dmfromAcalers)4/spa   1 0""/a>4spa  class="comment"> *4//spa   1 0"1/a>41 0"2/a>4trtic/ void-s href="+pcode=dc._uet_piomode class="seeef">dc._uet_piomode/a>4(triuct4a href="+pcode=ta_piort class="seeef">ta_piort/a>4-*a href="+pcode=tp class="seeef">tp/a>4,-triuct4a href="+pcode=ta_pdevice class="seeef">ta_pdevice/a>4-*a href="+pcode=tdee class="seeef">adee/a>4)1 0"3/a>4{1 0"4/a>4       -unsign dmint4a href="+pcode=pio olass="seeef">pio/a>4       -=4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=iio_mode class="seeef">iio_mode/a>4 -4a href="+pcode=XFER_PIO_" class="leeef">XFER_PIO_"/a>4"1 0"5/a>4       -triuct4a href="+pcode=pci_dee class="seeef">pci_dee/a>4-*a href="+pcode=dee class="seeef">dee/a>4    -=4a href="+pcode=to_pci_dee class="seeef">to_pci_dee/a>4(a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=hst" olass="seeef">hst"/a>4-gt;"a href="+pcode=dee class="seeef">dee/a>4)"1 0"6/a>4       -unsign dmlongua href="+pcode=flag" class="seeef">flag"/a>4"1 0"7/a>4       -unsign dmint4a href="+pcode=is_slave class="seeef">is_slave/a>4   = (a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=deeno olass="seeef">deeno/a>4 !=40)"1 0"8/a>4       -unsign dmint4a href="+pcode=masterpiort class="seeef">masterpiort/a>4=4a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?40x42 :40x40"1 0"9/a>4       -unsign dmint4a href="+pcode=slavepiort class="seeef">slavepiort/a>4 =40x44"1 110/a>4       -s href="+pcode=u1" class="leeef">u14/a>44a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4"1 011/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4"1 112/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=udma_enable class="leeef">udma_enable/a>4"1 113/a>4       -int4a href="+pcode=ontroll class="leeef">ontroll/a>4 =40"1 114/a>41 115/a>4       -trtic/ ontstc   -spa  class="comment"> /* ISP  RTC*4//spa   1 116/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=timing4 class="seeef">timing4/s>4[][2]-=4{-{40, 0 },1 117/a>4       ---------------------{40, 0 },1 118/a>4       ---------------------{41, 0 },1 119/a>4       ---------------------{42, 1 },1 120/a>4       ---------------------{42, 3 }, }"1 121/a>41 122/a>4       -if (a href="+pcode=pio olass="seeef">pio/a>4 gt;"= 2)1 123/a>4       ---------a href="+pcode=ontroll class="leeef">ontroll/a>4 |= 1;  -spa  class="comment"> /* TIME1 enable*4//spa   1 124/a>4       -if (a href="+pcode=ta_piio_need_iordy class="seeef">ta_piio_need_iordy/a>4(a href="+pcode=tdee class="seeef">adee/a>4))1 125/a>4       ---------a href="+pcode=ontroll class="leeef">ontroll/a>4 |= 2;  -spa  class="comment"> /* IE enable*4//spa   1 126/a>41 127/a>4       -if (a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=lass= class="leeef">oass=/a>4 ==4a href="+pcode=TA _DEV_TA  class="leeef">TA _DEV_TA /a>4)1 128/a>4       ---------a href="+pcode=ontroll class="leeef">ontroll/a>4 |= 4;  -spa  class="comment"> /* PPE enable*4//spa   1 129/a>41 130/a>4       -s href="+pcode=spin_lock_irqsave class="seeef">spin_lock_irqsave/a>4(&s href="+pcode=dc._lock class="seeef">dc._lock/a>4, a href="+pcode=flag" class="seeef">flag"/a>4)"1 131/a>41 132/a>4       -spa  class="comment"> /* PIO ontfi4ura>< =claears DTE-unontdi>< =lly .  I uwill be/spa   1 134/a>4spa  class="comment"> **********irogram m d iniuet_dmamode which is guaranteed to be calerd/spa   1 134/a>4spa  class="comment"> **********iafteriuet_piomode if anylDMA mode s acvailable4/spa   1 134/a>4spa  class="comment"> **********//spa   1 136/a>4       -s href="+pcode=pci_read_ontfi4_word class="seeef">pci_read_ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=masterpiort class="seeef">masterpiort/a>4, &s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4)"1 137/a>4       -if (a href="+pcode=is_slave class="seeef">is_slave/a>4)4{1 138/a>4       ---------apa  class="comment"> /* caear TIME1|IE1|PPE1|DTE1*4//spa   1 139/a>4       ---------s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 &=40xff0f"1 140/a>4       ---------apa  class="comment"> /* Enable*SITRE (separate slave timingidegister)*4//spa   1 141/a>4       ---------s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=40x4000"1 142/a>4       ---------apa  class="comment"> /* enable*PPE1, IE1and/ TIME1 as needed 4//spa   1 143/a>4       ---------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=4(a href="+pcode=ontroll class="leeef">ontroll/a>4 << 4)"1 144/a>4       ---------a href="+pcode=pci_read_ontfi4_byte class="seeef">ici_read_ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=slavepiort class="seeef">slavepiort/a>4, &s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4)"1 145/a>4       ---------a href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4 &=4(a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?40x0f :40xf0)"1 146/a>4       ---------apa  class="comment"> /* Load171a3/iminginibble*fr m71s aslave 4//spa   1 147/a>4       ---------a href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4 |=4((a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][0] << 2) |-s href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][1])1 148/a>4       -----------------------------------------<< (a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?44 :40)"1 149/a>4       -} else4{1 150/a>4       ---------apa  class="comment"> /* caear ISP|RCT|TIME0|IE0|PPE0|DTE0*4//spa   1 151/a>4       ---------s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 &=40xccf0"1 152/a>4       ---------apa  class="comment"> /* Enable*PPE, IEand/ TIME as aprogpriate 4//spa   1 153/a>4       ---------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=4a href="+pcode=ontroll class="leeef">ontroll/a>4"1 154/a>4       ---------apa  class="comment"> /* load1ISP nd/ RCT 4//spa   1 155/a>4       ---------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=1 156/a>4       -----------------(a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][0] << 12) |1 157/a>4       -----------------(a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][1] << 8)"1 158/a>4       -}1 159/a>4       -s href="+pcode=pci_wrie _ontfi4_word class="seeef">pci_wrie _ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=masterpiort class="seeef">masterpiort/a>4, s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4)"1 160/a>4       -if (a href="+pcode=is_slave class="seeef">is_slave/a>4)1 161/a>4       ---------s href="+pcode=pci_wrie _ontfi4_byte class="seeef">ici_wrie _ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=slavepiort class="seeef">slavepiort/a>4, s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4)"1 162/a>41 163/a>4       -apa  class="comment"> /* Ensura3/he UDMA bit s aoff -yt uwill be urn d obackon aif/spa   1 164/a>4spa  class="comment"> *********  UDMA s aslect>ed 4//spa   1 165/a>41 166/a>4       -s href="+pcode=pci_read_ontfi4_byte class="seeef">ici_read_ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x48, &s href="+pcode=udma_enable class="leeef">udma_enable/a>4)"1 167/a>4       -s href="+pcode=udma_enable class="leeef">udma_enable/a>4 &=4~(1 << (2t">a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 +4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=deeno olass="seeef">deeno/a>4))"1 168/a>4       -s href="+pcode=pci_wrie _ontfi4_byte class="seeef">ici_wrie _ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x48, s href="+pcode=udma_enable class="leeef">udma_enable/a>4)"1 169/a>41 170/a>4       -s href="+pcode=spin_unlock_irqrestore class="seeef">spin_unlock_irqrestore/a>4(&s href="+pcode=dc._lock class="seeef">dc._lock/a>4, a href="+pcode=flag" class="seeef">flag"/a>4)"1 174/a>4}1 172/a>41 174/a>4spa  class="comment"> *44/spa   1 174/a>4spa  class="comment"> *  TTTTTdc._uet_dmamode - Initializa3hostcontrollers ATA cPIO timing4/spa   1 174/a>4spa  class="comment"> *  IIIII@ap: Port whose timing4 we re; ontfi4urng4/spa   1 174/a>4spa  class="comment"> *4      @adee: Diver iniquest< =/spa   1 174/a>4spa  class="comment"> * /spa   1 174/a>4spa  class="comment"> *4 TTTTTSetcUDMA mode fr mdevice, inihostcontrollers ACI ontfi4 pa ce4/spa   1 174/a>4spa  class="comment"> * /spa   1 189"194/a>4spa  class="comment">iiiiiLOCKING:/spa   1 184/a>4spa  class="comment">/t">iiiiiNoe"4(inherie dmfromAcalers)4/spa   1 184/a>4spa  class="comment"> * //spa   1 184/a>41 184/a>4trtic/ void-s href="+pcode=dc._uet_dmamode class="seeef">dc._uet_dmamode/a>4(triuct4a href="+pcode=ta_piort class="seeef">ta_piort/a>4-*a href="+pcode=tp class="seeef">tp/a>4,-triuct4a href="+pcode=ta_pdevice class="seeef">ta_pdevice/a>4-*a href="+pcode=tdee class="seeef">adee/a>4)1 184/a>4{1 186/a>4       -triuct4a href="+pcode=pci_dee class="seeef">pci_dee/a>4-*a href="+pcode=dee class="seeef">dee/a>4    -=4a href="+pcode=to_pci_dee class="seeef">to_pci_dee/a>4(a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=hst" olass="seeef">hst"/a>4-gt;"a href="+pcode=dee class="seeef">dee/a>4)"1 187/a>4       -unsign dmlongua href="+pcode=flag" class="seeef">flag"/a>4"1 188/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=masterpiort class="seeef">masterpiort/a>4********  =4a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?40x42 :40x40"1 189/a>4       -s href="+pcode=u1" class="leeef">u14/a>44a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4"1 190/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=speed class="seeef">speed/a>4       ---------=4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=dma_mode class="seeef">dma_mode/a>4"1 191/a>4       -int4a href="+pcode=devid class="seeef">devid/a>4       --------=4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=deeno olass="seeef">deeno/a>4 + 2t">a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4"1 192/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=udma_enable class="leeef">udma_enable/a>4  --------=40"1 194/a>41 194/a>4       -trtic/ ontstc   -spa  class="comment"> /* ISP  RTC*4//spa   1 195/a>4       -s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=timing4 class="seeef">timing4/s>4[][2]-=4{-{40, 0 },1 196/a>4       ---------------------{40, 0 },1 197/a>4       ---------------------{41, 0 },1 198/a>4       ---------------------{42, 1 },1 199/a>4       ---------------------{42, 3 }, }"1 200/a>41 201/a>4       -s href="+pcode=spin_lock_irqsave class="seeef">spin_lock_irqsave/a>4(&s href="+pcode=dc._lock class="seeef">dc._lock/a>4, a href="+pcode=flag" class="seeef">flag"/a>4)"1 202/a>41 203/a>4       -s href="+pcode=pci_read_ontfi4_word class="seeef">pci_read_ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=masterpiort class="seeef">masterpiort/a>4, &s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4)"1 2"4/a>4       -s href="+pcode=pci_read_ontfi4_byte class="seeef">ici_read_ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x48, &s href="+pcode=udma_enable class="leeef">udma_enable/a>4)"1 205/a>41 2"6/a>4       -if (a href="+pcode=speed class="seeef">speed/a>4 gt;"= a href="+pcode=XFER_UDMA_" class="leeef">XFER_UDMA_"/a>4)4{1 207/a>4       ---------unsign dmint4a href="+pcode=udma class="leeef">udma/a>4 =4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=dma_mode class="seeef">dma_mode/a>4 -4a href="+pcode=XFER_UDMA_" class="leeef">XFER_UDMA_"/a>4"1 208/a>4       ---------a href="+pcode=u1" class="leeef">u14/a>44a href="+pcode=udma_timing class="leeef">udma_timing/a>4"1 209/a>4       ---------s href="+pcode=u1" class="leeef">u14/a>44a href="+pcode=ideontf class="seeef">ideontf/a>4"1 210/a>4       ---------int4a href="+pcode=u_clock class="seeef">u_clock/a>4, a href="+pcode=u_speed class="seeef">u_speed/a>4"1 211/a>41 212/a>4       ---------apa  class="comment"> /*/spa   1 214/a>4spa  class="comment"> ****************** UDMA s ahandld oby a onmbina>< =cof clock switchingiand/spa   1 214/a>4spa  class="comment"> *********  ******* slect>< =cof dividrs//spa   1 214/a>4spa  class="comment"> *********  *******/spa   1 214/a>4spa  class="comment"> *********  ******* Handy rule: Odd modes re; UDMATIMx 01, even re; 02/apa   1 214/a>4spa  class="comment"> *********  *******             exceptcUDMA0 which is 00/apa   1 214/a>4spa  class="comment"> *********  *******//spa   1 219/a>4       ---------a href="+pcode=u_speed class="seeef">u_speed/a>4 =4a href="+pcode=min olass="seeef">min/a>4(2 -4(a href="+pcode=udma class="leeef">udma/a>4 &-1), s href="+pcode=udma class="leeef">udma/a>4)"1 220/a>4       ---------if (a href="+pcode=udma class="leeef">udma/a>4 == 5)1 221/a>4       -----------------a href="+pcode=u_clock class="seeef">u_clock/a>4 =40x1000"-------apa  class="comment"> /* 100Mhz**//spa   1 222/a>4       ---------else4if (a href="+pcode=udma class="leeef">udma/a>4 gt;" 2)1 223/a>4       -----------------a href="+pcode=u_clock class="seeef">u_clock/a>4 =41;------------apa  class="comment"> /* 66Mhz**//spa   1 224/a>4       ---------else1 225/a>4       -----------------a href="+pcode=u_clock class="seeef">u_clock/a>4 =40;------------apa  class="comment"> /* 33Mhz**//spa   1 226/a>41 227/a>4       ---------a href="+pcode=udma_enable class="leeef">udma_enable/a>4 |=4(1 << a href="+pcode=devid class="seeef">devid/a>4)"1 228/a>41 229/a>4       ---------apa  class="comment"> /* Load171a3CT/RP slect>< =c*//spa   1 230/a>4       ---------a href="+pcode=pci_read_ontfi4_word class="seeef">pci_read_ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x4A, &s href="+pcode=udma_timing class="leeef">udma_timing/a>4)"1 231/a>4       ---------s href="+pcode=udma_timing class="leeef">udma_timing/a>4 &=4~(3 << (4t">a href="+pcode=devid class="seeef">devid/a>4))"1 232/a>4       ---------a href="+pcode=udma_timing class="leeef">udma_timing/a>4 |=4a href="+pcode=u_speed class="seeef">u_speed/a>4 << (4t">a href="+pcode=devid class="seeef">devid/a>4)"1 233/a>4       ---------a href="+pcode=pci_wrie _ontfi4_word class="seeef">pci_wrie _ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x4A, s href="+pcode=udma_timing class="leeef">udma_timing/a>4)"1 234/a>41 235/a>4       ---------apa  class="comment"> /* Slect> a 33/66/100Mhz*clock *//spa   1 236/a>4       ---------a href="+pcode=pci_read_ontfi4_word class="seeef">pci_read_ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x54, &s href="+pcode=ideontf class="seeef">ideontf/a>4)"1 237/a>4       ---------a href="+pcode=ideontf class="seeef">ideontf/a>4 &=4~(0x1001 << a href="+pcode=devid class="seeef">devid/a>4)"1 238/a>4       ---------a href="+pcode=ideontf class="seeef">ideontf/a>4 |=4a href="+pcode=u_clock class="seeef">u_clock/a>4 << a href="+pcode=devid class="seeef">devid/a>4"1 239/a>4       ---------s href="+pcode=pci_wrie _ontfi4_word class="seeef">pci_wrie _ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x54, s href="+pcode=ideontf class="seeef">ideontf/a>4)"1 240/a>4       -} else4{1 241/a>4       ---------spa  class="comment"> /*/spa   1 244/a>4spa  class="comment"> ****************** MWDMA s arivernoby 71a3PIO timing4. We mus> also enable/apa   1 244/a>4spa  class="comment"> ****************** IORDY-unontdi>< =lly  alonguwith TIME1. PPE has already/apa   1 244/a>4spa  class="comment"> *********  ******* beeniuet wheni71a3PIO timing wa aslt4/spa   1 244/a>4spa  class="comment"> *********  *******//spa   1 246/a>4       ---------unsign dmint4a href="+pcode=mwdma class="leeef">mwdma/a>4      =4a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=dma_mode class="seeef">dma_mode/a>4 -4a href="+pcode=XFER_MW_DMA_" class="leeef">XFER_MW_DMA_"/a>4"1 247/a>4       ---------unsign dmint4a href="+pcode=ontroll class="leeef">ontroll/a>4"1 248/a>4       ---------s href="+pcode=u8 class="leeef">u8/a>4-s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4"1 249/a>4       ---------ontstcunsign dmint4a href="+pcode=needed_pio olass="seeef">needed_pio/s>4[3]-=4{1 250/a>4       -----------------s href="+pcode=XFER_PIO_" class="leeef">XFER_PIO_"/a>4, s href="+pcode=XFER_PIO_3 class="leeef">XFER_PIO_3/a>4, s href="+pcode=XFER_PIO_4 class="leeef">XFER_PIO_4/a>41 251/a>4       ---------}"1 252/a>4       ---------int4a href="+pcode=pio olass="seeef">pio/a>4 =4a href="+pcode=needed_pio olass="seeef">needed_pio/s>4[a href="+pcode=mwdma class="leeef">mwdma/a>4] -4a href="+pcode=XFER_PIO_" class="leeef">XFER_PIO_"/a>4"1 254/a>41 254/a>4       ---------a href="+pcode=ontroll class="leeef">ontroll/a>4 =43;----spa  class="comment"> /* IORDY|TIME1 *//spa   1 255/a>41 256/a>4       ---------spa  class="comment"> /* Ifi71a3river MWDMA s afasteri71  cit c  cdo3PIO then/spa   1 254/a>4spa  class="comment"> *********  ******  we mus> forca3PIO into3PIO0*4//spa   1 258/a>41 259/a>4       ---------if (a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=iio_mode class="seeef">iio_mode/a>4 < a href="+pcode=needed_pio olass="seeef">needed_pio/s>4[a href="+pcode=mwdma class="leeef">mwdma/a>4])1 260/a>4       -----------------spa  class="comment"> /* Enable*DMA timing ony  4//spa   1 261/a>4       -----------------a href="+pcode=ontroll class="leeef">ontroll/a>4 |= 8;  -spa  class="comment"> /* PIO oycles iniPIO0*4//spa   1 262/a>41 263/a>4       ---------if (a href="+pcode=tdee class="seeef">adee/a>4-gt;"a href="+pcode=deeno olass="seeef">deeno/a>4) {------spa  class="comment"> /* Slave 4//spa   1 264/a>4       -----------------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 &=40xFF4F;--spa  class="comment"> /* Mask out IORDY|TIME1|DMAONLY 4//spa   1 265/a>4       -----------------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=4a href="+pcode=ontroll class="leeef">ontroll/a>4 << 4"1 266/a>4       -----------------a href="+pcode=pci_read_ontfi4_byte class="seeef">ici_read_ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x44, &s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4)"1 267/a>4       -----------------s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4 &=4(a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?40x0f :40xf0)"1 268/a>4       -----------------apa  class="comment"> /* Load171a3matchingitiming 4//spa   1 269/a>4       -----------------s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4 |=4((a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][0] << 2) |-s href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][1])-<< (a href="+pcode=tp class="seeef">tp/a>4-gt;"a href="+pcode=iort_no olass="seeef">port_no/a>4 ?44 :40)"1 270/a>4       -----------------s href="+pcode=pci_wrie _ontfi4_byte class="seeef">ici_wrie _ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x44, s href="+pcode=slavepdta_ olass="seeef">slavepdta_/a>4)"1 271/a>4       ---------} else4{--------apa  class="comment"> /* Masteri4//spa   1 272/a>4       -----------------s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 &=40xCCF4;--spa  class="comment"> /* Mask out IORDY|TIME1|DMAONLY/spa   1 274/a>4spa  class="comment">        --------------------------------------------nd/ masteri7iming bitsi4//spa   1 274/a>4       -----------------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=4a href="+pcode=ontroll class="leeef">ontroll/a>4"1 275/a>4       -----------------a href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4 |=1 276/a>4       -------------------------(a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][0] << 12) |1 277/a>4       -------------------------(a href="+pcode=timing4 class="seeef">timing4/s>4[a href="+pcode=pio olass="seeef">pio/a>4][1] << 8)"1 278/a>4       ---------}1 279/a>41 280/a>4       ---------a href="+pcode=udma_enable class="leeef">udma_enable/a>4 &=4~(1 << a href="+pcode=devid class="seeef">devid/a>4)"1 281/a>4       ---------s href="+pcode=pci_wrie _ontfi4_word class="seeef">pci_wrie _ontfi4_word/a>4(a href="+pcode=dee class="seeef">dee/a>4, a href="+pcode=masterpiort class="seeef">masterpiort/a>4, s href="+pcode=masterpdta_ olass="seeef">masterpdta_/a>4)"1 282/a>4       -}1 283/a>4       -s href="+pcode=pci_wrie _ontfi4_byte class="seeef">ici_wrie _ontfi4_byte/a>4(a href="+pcode=dee class="seeef">dee/a>4, 0x48, s href="+pcode=udma_enable class="leeef">udma_enable/a>4)"1 284/a>41 285/a>4       -s href="+pcode=spin_unlock_irqrestore class="seeef">spin_unlock_irqrestore/a>4(&s href="+pcode=dc._lock class="seeef">dc._lock/a>4, a href="+pcode=flag" class="seeef">flag"/a>4)"1 286/a>4}1 287/a>41 288/a>4trtic/ triuct4a href="+pcode=ta_piort_opera>< =" class="seeef">ta_piort_opera>< ="/a>4-s href="+pcode=dc._ata_rop" class="seeef">dc._ata_rop"/a>4 =4{1 289/a>4       -.s href="+pcode=inherie" class="seeef">inherie"/a>4       --------= &s href="+pcode=ta_rbmdma32piort_op" class="seeef">ta_pbmdma32piort_op"/a>4,1 290/a>4       -.s href="+pcode=cable_detect class="seeef">cable_detect/a>4       ----=4a href="+pcode=dc._ata_rcable_detect class="seeef">dc._ata_rcable_detect/a>4,1 291/a>4       -.s href="+pcode=uet_piomode class="seeef">set_piomode/a>4       -----=4a href="+pcode=dc._uet_piomode class="seeef">dc._uet_piomode/a>4,1 292/a>4       -.s href="+pcode=uet_dmamode class="seeef">uet_dmamode/a>4       -----=4a href="+pcode=dc._uet_dmamode class="seeef">dc._uet_dmamode/a>4,1 293/a>4       -.s href="+pcode=prereset class="seeef">prereset/a>4       --------= a href="+pcode=dc._ata_rprereset class="seeef">dc._ata_rprereset/a>4,1 294/a>4}"1 295/a>41 296/a>4trtic/ triuct4a href="+pcode=ta_piort_info olass="seeef">ta_piort_info/a>4-s href="+pcode=dc._aort_info olass="seeef">dc._aort_info/a>4 =4{1 297/a>41 298/a>4       -.s href="+pcode=flag" class="seeef">flag"/a>4  --------= a href="+pcode=TA _FLAG_SLAVE_POSS class="seeef">TA _FLAG_SLAVE_POSS/a>4,1 299/a>4       -.s href="+pcode=iio_mask class="seeef">iio_mask/a>4       = a href="+pcode=TA _PIO4 class="leeef">TA _PIO4/a>4,1 300/a>4       -.s href="+pcode=mwdma_mask class="seeef">mwdma_mask/a>4     = a href="+pcode=TA _MWDMA12_ONLY class="leeef">TA _MWDMA12_ONLY/a>4,1 301/a>4       -.s href="+pcode=udma_mask class="seeef">udma_mask/a>4      = a href="+pcode=TA _UDMA5 class="leeef">TA _UDMA5/a>4,1 302/a>4       -.s href="+pcode=iort_op" class="seeef">iort_op"/a>4-------= &s href="+pcode=dc._ata_rop" class="seeef">dc._ata_rop"/a>4,1 303/a>4}"1 304/a>41 305/a>4trtic/ triuct4a href="+pcode=scsi_hst"_template class="seeef">scsi_hst"_template/a>4-s href="+pcode=dc._sht class="seeef">dc._sht/a>4 =4{1 3"6/a>4       -a href="+pcode=TA _BMDMA_SHT class="leeef">TA _BMDMA_SHT/a>4(a href="+pcode=DRdc.c#L830" id  L53">1 249/a>4       ---------ontstcunsign dmint4a href="+pcode=needed_pio olass="seefontstcunsign dmis="seefo="driivers/ata/pata_rdc.c#L830" id  L430" 7TA _BMDMA nam   L829">1 298/a>4 3code=3dee clvers/ata/pata_rdc.c#L830" id  L530" cl8TA _BMDMA---= a href="+pcode=TA 3class30-------if (a href="+pcode=tdee class="s3u14/a>44a3href="+pcode=ideontf cla3s="se30 nam   L118">1 189"194/a>4s class="comment"> *  TTTTTdc._uet_dmamode - 3"seeef">u3clock/a>4, a href="+pcod3=u_sp31" class="line" nam   L118">1 184/a>4   inirs/nL517R/a>4    PIIX  174/CI17" clanam   kernel ser clalass="comment"> *********  *******/spa   <3lass="lin3" nam   L221">1 212/a>4 3     31_rdc.c#L818" id  L218" class="line"@pL71""/CI17" clanto41/a>4   ass="comment"> *********  *******/spa   <3lt_op"/a>4vers/ata/pata_rdc.c#L8203 id  31" nam   L318">1 184/a>44a>4}"ci_tbl6">1 269/aam   @pL71ass="comment"> *********  *******/spa   <3lclass="li a onmbina>< =cof clock 3witch3ngiand/spa    *  TTTTTdc._uet_dmamode - 3"ass="liners//spa   kernel /CI1layer. 24">probd  L91line" e="line (sigh),ass="comment"> *  TTTTTdc._uet_dmamode - 3"ass="seeevers/ata/pata_rdc.c#L8203 id  3621" class="line" nam   L621"e"line"   L  cl L421 oTTT nam   Lnto4lib_dm,  L91itnto4do L926"seelass="comment"> *********  *******//spa   3le: Odd m3des re; UDMATIMx 01, eve3 re; 32/apa    *  TTTTTdc._uet_dmamode - 3"7TA _BMDMcUDMA0 which is 00/apa  3/t">iiiiiNoe"4(inherie dmfr3a href="d3ivers/ata/pata_rdc.c#L823" id 3L921" class="line" nam   L921 184/a>IL218">1 184/a>/CI1layer (may sleepclass="comment"> * //spa   u_spe3d/a>4 =4a href="+pcode=m3n ola31 nam   L118">1 189"194/a>4spa  class="comment">iiiiiLOCKING:/spa   udma3a>4 == 5)1 184/a>RETURNSlass="comment">/t">iiiiiNoe"4(inherie dmfr3ass="seee3">u_clock/a>4 =40x1000"-3-----32_rdc.c#L818" id  L218" class="line"Zeropa  suclals, L91-ERRNO valuclass="comment"> * /spa   4 gt;" 2)1 184/a>4u_clock/a>4 =41;------3-----32-------a href="+pcode=ontroll class="le3.c#L822" 3d  L522" class="line" na3   L532"+pcode=ta_pid  L625" class="li__7" cnirs/nL517R/a>41on">1 10" id  L630" class="line" nam   L630617R/a>4 3"6/a>4       -a hr17R/a>4 ed_pi href="+pcode=to_pci_dee class="seeef">to_pci_dee/a>4(a href="+pcode=tp plass="seeef">to_pciL828" id"+pcode=ontroll class="le3.c#L822" 3vers/ata//a>4 =40;------------apa3 clas3="comment"> /* 33Mhz**//spa              _rdc.c href="+pcode=to_pci_dee clasa>4_1/a>4       -----ee clasa>4_1/>4(a href="+pcode=tp "dri>4       -----"drs/ata"+pcode=ontroll class="le3.c#L822" 3des re; U722">1 227/a>4       ---3-----3 href==TA _BMDMA_SHT class="leeef">TA _BMDdma_enabl3/a>4 |=4(1 << a hr3f="+p3ode=devid clas href="+pcode=to_pci_d_rdc.c#L818" id  L518ass="line" nam   L518">1 18class="seeef">tp/a>4-gt;"ad  L13"" class="line" plass="seeef">to_pciL828" ie" nam   L718">1 187/a>4       -unsign dmlongata_rdc.c#L830" id  L530" cl8TA _BMDe" nam   3922">1 229/a>4       ---3-----328e=devid clas href="+pcode=to_pci_d4 =4{4 =4a/spa   pio/3"seeef">p3i_read_ontfi4_word/a>4(a3href=3+pcode=dee cla" class="line" nam   L81"">1 dc.c#POSS/a>4,4 &=4~(3 <<3(4t">3 href="+pcode= href="+pcode=to_pci_d4 =4#L818" id  L718" cl4 =4#L81" id href="+pcode=tp #L818" id  L718" class="linata_rdc.c#L830" id  L530" cl8TA _BMDdudma/a>4 /a>4 |=4a href="+pcode=u3speed3class="seeef"> href="+pcode=to_pci_da hr0" idp30"3"6/a>4       -a hr0" idp30"" id href="+pcode=tp #p30"3"6/a>4       -hp30"" idata_rdc.c#L830" id  L530" cl8TA _BMDd">u_clockci_wrie _ontfi4_word/a>43a hre3="+pcode=dee c class="li__7" cnirrc3"6/a>4       -ac" idata_rdc.c#L830" id  L530" cl8TA _BMDdd  L522" 523">1 235/a>4       ---3-----3pa  class="comment"> /* Slect> a 33/66/130Mhz*cloc3 *//spa    /*iona>4.c4)"to_pciL828" ie" nam   L718">1 187/a>4       -unsign dmlongne" nam   L628">1"driVERSIONgn dmis="seefo="driVERSION/ata/pata_rdc.c#L828" id  L728" class="l3"seeef">p3i_read_ontfi4_word/a>4(a3href=33href="+pcode=udma_enable class="leeef">3tf/a>4 &a3p;=4~(0x1001 << a 3ref="33code=tp class="seeef">tp/a>4p1 297/a>4dee/a>4, 0x1 297/a>44 =4aci_wrie _ontfi4_word/a>43a hre33href="+pcode=udma_enable class="leeef">3L124" cla3s="line" nam   L124">1 231/a>434-------=4a href="+pcode=tdeedc.c#POSS/a>4,TA _FLAG_SLAVE_POSS/a>4, /*/spa   4 nam prep="co  L91rs/ata/pata_rdc.c#L818" id  L418" 3ass="seeelly  alon3uwith TIME1. PPE has alr3ady/a34dee class="seeef">dee/a>4, 0rc3"6/a>4       -ac" ida29" id  L429" clapcimrivers/__rdc.c#L818" id  L518pcimrivers/__rdc.ced_pio olass="seefonplass="seeef">to_pciL828" i/pata_rdc.c#L828" id  L728" class="l33PIO timi3g wa aslt4/spa   4       -ac" ida"+pcode=ontroll class="le3.c#L822" rivers/at3/pata_rdc.c#L824" id  L634" cl34"comment"> /* 33Mhz**returnass="li__7" cnirrc3"6/a>4       -ac" idata_rdc.c#L830" id  L530" cl8TA _BMDeeef">mwd3a/a>4      =4a href="+pc3de=td34href="+pcode=udma_enable class="leeef">3"leeef">o3troll/a>4"tp/a>4#p30"3"6/a>4       -hp30"" ida29" id  L429" claL82m_kzalloc3"6/a>4       -L82m_kzalloced_pio olass="seefon/a>4       -unsign dmlongnesizeof(href="+pcode=tp #p30"3"6/a>4       -hp30"" ide" nam   L122">1 2GFP_KERNEL3"6/a>4       -GFP_KERNEL8" i/pata_rdc.c#L828" id  L728" class="l33" nam   3e=slavepdta_ olass="seee3">sla3epdta_/a>4"4       -hp30"" ideata_rdc.c#L828" id  L728" class="l33d/a>4 =4aseeef">needed_pio/s>4[3]3=4{4       -ENOMEM" idata_rdc.c#L830" id  L530" cl8TA _BMDeeef">XFE3_PIO_"/a>4, s href="+pco3e=XFE35code=spin_lock_irqsave class="seeef">sp3  L225" c3ass="line" nam   L225">13252/a34       ------  L426">1 264/a>4       ------IOCFG, this will be usCI1le="lers/o41t------, quirk/ata/pata_rdc.c#L818" id  L418" 3ass="seee>4 =4a hr3f="+pcode=needed_pio ola3s="se35   1 21no41tachment"> * /spa   1 254/a>4       ---3-----35pa    /* 3ORDY|TIME1 *//+pcode=to_pci_dee c="seeef">slad+pcode=ideontf class="seeef">ideontd>4, s href="+pcode=masteplass="seeef">to_pciL828" id723" class="line" nam   L72#p30"3"6/a>4       -hp30"" ide" nam   L718">1 187"/a>d_iocf>1 234/a>4d_iocf>8" i/pata_rdc.c#L828" id  L728" class="l3e" nam   3625">1 256/a>4       ---3-----3pa  class="comment"> /* Ifi71a3river MWD3A s afast3ri71  cit c  cdo3PIO the3/spa 35 L53">1 249/a>4       ------rc3"6/a>4       -ac" ida29" id  L429" cla" cl"="s     _prep="c4#L818" id  L718" cl4 =4"="s     _prep="c4#L81s href="+pcode=masteplass="seeef">to_pciL828" id7ref="+pcode=tp ppi"drivers/ata/padpi" idclass="line" nam   L72#L818" id  L718" class="lin/pata_rdc.c#L828" id  L728" class="l3eleeef">o3*4//spa   4       -ac" ida"+pcode=ontroll class="le3.c#L822" e" nam   3925">1 259/a>4       ---3-----35a href="drivers/ata/preturnass="li__7" cnirrc3"6/a>4       -ac" idata_rdc.c#L830" id  L530" cl8TA _BMD/a>4-gt;"3 href="+pcode=iio_mode c3ass="35_/a>4"1 187p30"at127">1 271/a>4       p30"at127">1" ida29" id  L429" cla#p30"3"6/a>4       -hp30"" idata_rdc.c#L830" id  L530" cl8TA _BMDA timing 3ny  4//spa   sp3f">ontrol3/a>4 |= 8;  -spa  class=3comme3t"> /* PIO oyc+pcode=to_pci_dee cintxde=ideontf class="sintxs href="+pcode=masteplass="seeef">to_pciL828" id71/pata_rdc.c#L828" id  L728" class="l3e" nam   3326">1 263/a>4       ---3-----3f (a href="+pcode=tdee class="seeef">ade3/a>4-gt;"3 href="+pcode=deeno olas3="see36dee class="seeef">dee/a>4, 0#L818" id  L718" class="line" nam   L718">1 187POSS/a>4,4 =43terpdta_/a>4 &=40xFF3F;--s36a  class="comment"> /* Slect> a 33/66/13seeef">ma3terpdta_/a>4 |=4a href="3pcode36+pcode=dc._lock class="seeefs="s-.s  -}to_pciL828" i/pata_rdc.c#L828" id  L728" class="l3e class="3eeef">ici_read_ontfi4_by3e/a>43a href="+pcodereturnass="li__7" cnir4 =4"="ssff_a---"at12#L818" id  L718" cl4 =4"="ssff_a---"at12#L81ed_pio olass="seefon#L818" id  L718" class="lind7ref="+pcode=tp a4       sinterrup18" id  L718" cl4 =4     sinterrup1" idclass="line" nam   L726306>1 3"6/a>4       -a href="+pc/pata_rdc.c#L828" id  L728" class="l3eleeef">o3epdta_/a>4 &=4(a hre3="+pc3de=tp ata_rdc.c#L828" id  L82"" class="li3matchingi3iming 4//spa   sla3epdta_/a>4 |=4((a href="3pcode3timing  L625"void9" id  L429" class="removea>4 3"6/a>4       -a hrremovea>4 ed_pi href="+pcode=to_pci_dee class="seeef">to_pci_dee/a>4(a href="+pcode=tp plass="seeef">to_pciL828" ia"+pcode=ontroll class="le3.c#L822" te class=3seeef">ici_wrie _ontfi4_3yte/a34(a hr=TA _BMDMA_SHT class="leeef">TA _BMDasteri4//3pa   1 271/a>4       L82_g.s hrv7">14)"to_pciL828" ie" nam   L718">1 187/a>4       -unsign dmlong/pata_rdc.c#L828" id  L728" class="l3seeef">ma3terpdta_/a>4 &=40xCC34;--s37lass="seeef"> href="+pcode=to_pci_da hr0" idp30"3"6/a>4       -a hr0" idp30"" id href="+pcode=tp #p30"3"6/a>4       -hp30"" ida29" id  L429" cla#L818" id  L718" class="line" nam   L718">1 187p30"at127">1 271/a>4       p30"at127">1" idpata_rdc.c#L828" id  L728" class="l3sa>4-gt;"3-----nd/ masteri7iming b3tsi4/37href="+pcode=ontroll class="le3.c#L822" seeef">ma3terpdta_/a>4 |=4a href="3pcode37RDY|TIME1 *//+pcode=to_pci_dee ceeef">udma_end+pcode=ideontf class="seeef">udma_end+pcos href="+pcode=masteplass="seeef">to_pciL828" id723" clline" nam   L72#p30"3"6/a>4       -hp30"" ide" nam   L718">1 187"/a>d_iocf>1 234/a>4d_iocf>8" i/pata_rdc.c#L828" id  L728" class="l3seeef">ma3terpdta_/a>4 |= /* Ifi71a3river MWD3ass="seee3">timing4/s>4[a href="+p3ode=p37 L53">1 249/a>4       ------4 =4"="sremovea>4 3"6/a>4       -4 =4"="sremovea>4 ed_pio olass="seefonplass="seeef">to_pciL828" i/pata_rdc.c#L828" id  L728" class="l3ass="seee3">timing4/s>4[a href="+p3ode=p37e=tp ata_rdc.c#L828" id  L82"" class="li3 L927" cl3ss="line" nam   L927">1 379/a>37 (a href="+pcode=tdee class="s3u14/a>44ae" nam   3128">1 280/a>4       ---3-----37iming  L625"_rdc.c href="+pcode=to_pci_dee clasa>4_1/a>4       -----ee clasa>4_1/>4(a " id  L429" class="l1 269/29">1 297/a>444adma_enabl3/a>4 &=4~(1 <<3a hre3="+pcode=devid{ " id  L429" claPCI_DEVICign dmis="seefo=PCI_DEVICied_pi0x17F3,lass=1ne" }d"+pcode=ontroll class="le3.c#L822" ="seeef">3ci_wrie _ontfi4_word/a>43a hre3="+pcode=dee c{ " id  L429" claPCI_DEVICign dmis="seefo=PCI_DEVICied_pi0x17F3,lass=12e" }d"+pcode=ontroll class="le3.c#L822" =eeef">ma3" nam   L328">1 283/a>4 3     3s href="+pcode{ }-----  L426">1 264/a>4       -term421"e liL91rs/ata/pata_rdc.c#L818" id  L418" 3ass="seee>ici_wrie3_ontfi4_byte/a>4(a href=3+pcod38/ata/pata_rdc.c#L830" id  L530" class="line" nam   3528">1 285/a>4       -s 3ref="3pcode=spin_unlock_irqrestore class="seee3">spin_un3ock_irqrestore/a>4(&3 href38dc._sht class="seeef">dc._sht/a>4 ee cl_irqra>4       -----ee cl_irqr>4(a " id  L429" class="l1 2l_irqra>4       -----ss="l1 2l_irqr" ida29-ref="+pcode=tdee class="s3u14/a>44adss="seee3L728">1 287/a>41 249/a>TA _FLAG_SLAVE_ hrea>4       ----- hre href="drivers/ata/p class="line" nam   tstcunsign dmis="seefo="driivers/atd"+pcode=ontroll class="le3.c#L822" =ss="seee382"">1 288/a>4trtic/ tri3ct4a 387L53">1 249/a>TA _FLAG_SLAVE_id_t28">1 284/a>4 href="drivers/ata/29" id  L429" class="l1 269/29">1 297/a>4< ="/a>4-s hre3="+pc38class="seeef">TA _FLAG_SLAVE_1line 271/a>4       p3ine href="drivers/ata/p c29" id  L429" class="17R/a>4 3"6/a>4       -a hr17R/a>4 ed_pd"+pcode=ontroll class="le3.c#L822" =" nam   3------= &s href="+pc3de=ta3rbmdma32piort_op" class="seeefremove3"6/a>4       -aemove href="drivers/ata/p 29" id  L429" class="removea>4 3"6/a>4       -a hrremovea>4 ed_pd"+pcode=ontroll class="le3.c#L822" etect/a>43      ----=4a href="+pco3e=dc.3ata_rc#ifdef9" id  L429" claCONFIG_PM3"6/a>4       -CONFIG_PMode=spin_unlock_irqrestore class="seee3ode/a>4  3    -----=4a href="+pcod3=dc._3et_piomode class="seeef">dc._ueuspen/a>4       -----euspen/ href="drivers/ata/p29" id  L429" cla" cl"="slasa>4_euspen/a>4       -----" cl"="slasa>4_euspen/ed_pd"+pcode=ontroll class="le3.c#L822" eeeef">ma3    -----=4a href="+pcod3=dc._3et_dmamode class="seeef">dc._uresurea>4       -----resure href="drivers/ata/p 29" id  L429" cla" cl"="slasa>4_resurea>4       -----" cl"="slasa>4_resureed_pd"+pcode=ontroll class="le3.c#L822" eici_wrie3------= a href="+pcode=d3._ata3rprere#en/if"+pcode=ontroll class="le3.c#L822" e" nam   3 L529">1 295/a>41 296/a>4trtic/ tri3ct4a 3ref="+pcode=ta_piort_info olass="seeef">3a_piort_i3fo/a>4-s href="+pcode=dc3_aort39href="+pcode=udma_enable class="leeef">3e" nam   3829">1 298/a>4       -.s3href=3+pcode" id  L429" clamodule"l1 2l_irqra>4       -----module"l1 2l_irqred_pio olass="seefonss="l1 2l_irqra>4       -----ss="l1 2l_irqr" id/pata_rdc.c#L828" id  L728" class="l3-----= a 3ref="+pcode=TA _FLAG_SLA3E_POS39 (a href="+pcode=tdee class="s3u14/a>44a4       =3a href="+pcode=TA _PIO4 3lass=3leeef"o olass="seefonMODULE_AUTHORa>4       -----MODULE_AUTHORed_pio L426">1 264s="3">1>"Al426Cox (basCI1-- n cl"iix)"/ata/pa/pata_rdc.c#L828" id  L728" class="l4k/a>4    4= a href="+pcode=TA _MWD4A12_O4LY clao olass="seefonMODULE_DESCRIPTIONgn dmis="seefo=MODULE_DESCRIPTIONed_pio L426">1 264s="3">1>"SCSI low-levels="linr1le="RDC P" clo4lib_dl" i"/ata/pa/pata_rdc.c#L828" id  L728" class="l4k1a>4    4=   -----=4a href="+pcod4 clas4="leeeo olass="seefonMODULE_LICiNSign dmis="seefo=MODULE_LICiNSied_pio L426">1 264s="3">1>"GPL"/ata/pa/pata_rdc.c#L828" id  L728" class="l4k2a>4    4=   -----=4a href="+pcod4ta_ro4" claso olass="seefonMODULE_DEVICi_TABLign dmis="seefo=MODULE_DEVICi_TABLied_pio olass="seefonpci"drivers/ata/padci"lind7ref="+pcode=tp ss="l1 269/29">1 297/a>41 305/a>4trtic/ tri4ct4a 4ref="+




1 305/foo
The orig421l LXR softw="co" nam  ta_rdc.c#http://sourcele=ge.net/projects/lx d>LXR /a>4u7R/y"lind7this experi4   1l > /*iono" nta_rdc.c#mailto:lx @a>4ux.no">lx @a>4ux.no"lin.

1 305/subfoo
lx .a>4ux.no kindlyo  L9CI1" nta_rdc.c#http://www.redpill-a>4pro.no">Redpill L>4pro A+pcode91lividnr1of L>4ux"_rdcult@pL7nam  .c#L428" ass="comm since 1995.