linux/virt/kvm/ioapic.c
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   1/*
   2 *  Copyright (C) 2001  MandrakeSoft S.A.
   3 *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
   4 *
   5 *    MandrakeSoft S.A.
   6 *    43, rue d'Aboukir
   7 *    75002 Paris - France
   8 *    http://www.linux-mandrake.com/
   9 *    http://www.mandrakesoft.com/
  10 *
  11 *  This library is free software; you can redistribute it and/or
  12 *  modify it under the terms of the GNU Lesser General Public
  13 *  License as published by the Free Software Foundation; either
  14 *  version 2 of the License, or (at your option) any later version.
  15 *
  16 *  This library is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 *  Lesser General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU Lesser General Public
  22 *  License along with this library; if not, write to the Free Software
  23 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24 *
  25 *  Yunhong Jiang <yunhong.jiang@intel.com>
  26 *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27 *  Based on Xen 3.1 code.
  28 */
  29
  30#include <linux/kvm_host.h>
  31#include <linux/kvm.h>
  32#include <linux/mm.h>
  33#include <linux/highmem.h>
  34#include <linux/smp.h>
  35#include <linux/hrtimer.h>
  36#include <linux/io.h>
  37#include <linux/slab.h>
  38#include <asm/processor.h>
  39#include <asm/page.h>
  40#include <asm/current.h>
  41#include <trace/events/kvm.h>
  42
  43#include "ioapic.h"
  44#include "lapic.h"
  45#include "irq.h"
  46
  47#if 0
  48#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  49#else
  50#define ioapic_debug(fmt, arg...)
  51#endif
  52static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  53
  54static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  55                                          unsigned long addr,
  56                                          unsigned long length)
  57{
  58        unsigned long result = 0;
  59
  60        switch (ioapic->ioregsel) {
  61        case IOAPIC_REG_VERSION:
  62                result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  63                          | (IOAPIC_VERSION_ID & 0xff));
  64                break;
  65
  66        case IOAPIC_REG_APIC_ID:
  67        case IOAPIC_REG_ARB_ID:
  68                result = ((ioapic->id & 0xf) << 24);
  69                break;
  70
  71        default:
  72                {
  73                        u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  74                        u64 redir_content;
  75
  76                        ASSERT(redir_index < IOAPIC_NUM_PINS);
  77
  78                        redir_content = ioapic->redirtbl[redir_index].bits;
  79                        result = (ioapic->ioregsel & 0x1) ?
  80                            (redir_content >> 32) & 0xffffffff :
  81                            redir_content & 0xffffffff;
  82                        break;
  83                }
  84        }
  85
  86        return result;
  87}
  88
  89static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  90{
  91        union kvm_ioapic_redirect_entry *pent;
  92        int injected = -1;
  93
  94        pent = &ioapic->redirtbl[idx];
  95
  96        if (!pent->fields.mask) {
  97                injected = ioapic_deliver(ioapic, idx);
  98                if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  99                        pent->fields.remote_irr = 1;
 100        }
 101
 102        return injected;
 103}
 104
 105static void update_handled_vectors(struct kvm_ioapic *ioapic)
 106{
 107        DECLARE_BITMAP(handled_vectors, 256);
 108        int i;
 109
 110        memset(handled_vectors, 0, sizeof(handled_vectors));
 111        for (i = 0; i < IOAPIC_NUM_PINS; ++i)
 112                __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
 113        memcpy(ioapic->handled_vectors, handled_vectors,
 114               sizeof(handled_vectors));
 115        smp_wmb();
 116}
 117
 118static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 119{
 120        unsigned index;
 121        bool mask_before, mask_after;
 122        union kvm_ioapic_redirect_entry *e;
 123
 124        switch (ioapic->ioregsel) {
 125        case IOAPIC_REG_VERSION:
 126                /* Writes are ignored. */
 127                break;
 128
 129        case IOAPIC_REG_APIC_ID:
 130                ioapic->id = (val >> 24) & 0xf;
 131                break;
 132
 133        case IOAPIC_REG_ARB_ID:
 134                break;
 135
 136        default:
 137                index = (ioapic->ioregsel - 0x10) >> 1;
 138
 139                ioapic_debug("change redir index %x val %x\n", index, val);
 140                if (index >= IOAPIC_NUM_PINS)
 141                        return;
 142                e = &ioapic->redirtbl[index];
 143                mask_before = e->fields.mask;
 144                if (ioapic->ioregsel & 1) {
 145                        e->bits &= 0xffffffff;
 146                        e->bits |= (u64) val << 32;
 147                } else {
 148                        e->bits &= ~0xffffffffULL;
 149                        e->bits |= (u32) val;
 150                        e->fields.remote_irr = 0;
 151                }
 152                update_handled_vectors(ioapic);
 153                mask_after = e->fields.mask;
 154                if (mask_before != mask_after)
 155                        kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
 156                if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
 157                    && ioapic->irr & (1 << index))
 158                        ioapic_service(ioapic, index);
 159                break;
 160        }
 161}
 162
 163static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
 164{
 165        union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 166        struct kvm_lapic_irq irqe;
 167
 168        ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
 169                     "vector=%x trig_mode=%x\n",
 170                     entry->fields.dest_id, entry->fields.dest_mode,
 171                     entry->fields.delivery_mode, entry->fields.vector,
 172                     entry->fields.trig_mode);
 173
 174        irqe.dest_id = entry->fields.dest_id;
 175        irqe.vector = entry->fields.vector;
 176        irqe.dest_mode = entry->fields.dest_mode;
 177        irqe.trig_mode = entry->fields.trig_mode;
 178        irqe.delivery_mode = entry->fields.delivery_mode << 8;
 179        irqe.level = 1;
 180        irqe.shorthand = 0;
 181
 182#ifdef CONFIG_X86
 183        /* Always delivery PIT interrupt to vcpu 0 */
 184        if (irq == 0) {
 185                irqe.dest_mode = 0; /* Physical mode. */
 186                /* need to read apic_id from apic regiest since
 187                 * it can be rewritten */
 188                irqe.dest_id = ioapic->kvm->bsp_vcpu_id;
 189        }
 190#endif
 191        return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
 192}
 193
 194int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
 195                       int level)
 196{
 197        u32 old_irr;
 198        u32 mask = 1 << irq;
 199        union kvm_ioapic_redirect_entry entry;
 200        int ret = 1;
 201
 202        spin_lock(&ioapic->lock);
 203        old_irr = ioapic->irr;
 204        if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
 205                int irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
 206                                                     irq_source_id, level);
 207                entry = ioapic->redirtbl[irq];
 208                irq_level ^= entry.fields.polarity;
 209                if (!irq_level)
 210                        ioapic->irr &= ~mask;
 211                else {
 212                        int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 213                        ioapic->irr |= mask;
 214                        if ((edge && old_irr != ioapic->irr) ||
 215                            (!edge && !entry.fields.remote_irr))
 216                                ret = ioapic_service(ioapic, irq);
 217                        else
 218                                ret = 0; /* report coalesced interrupt */
 219                }
 220                trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
 221        }
 222        spin_unlock(&ioapic->lock);
 223
 224        return ret;
 225}
 226
 227void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
 228{
 229        int i;
 230
 231        spin_lock(&ioapic->lock);
 232        for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
 233                __clear_bit(irq_source_id, &ioapic->irq_states[i]);
 234        spin_unlock(&ioapic->lock);
 235}
 236
 237static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
 238                                     int trigger_mode)
 239{
 240        int i;
 241
 242        for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 243                union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 244
 245                if (ent->fields.vector != vector)
 246                        continue;
 247
 248                /*
 249                 * We are dropping lock while calling ack notifiers because ack
 250                 * notifier callbacks for assigned devices call into IOAPIC
 251                 * recursively. Since remote_irr is cleared only after call
 252                 * to notifiers if the same vector will be delivered while lock
 253                 * is dropped it will be put into irr and will be delivered
 254                 * after ack notifier returns.
 255                 */
 256                spin_unlock(&ioapic->lock);
 257                kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
 258                spin_lock(&ioapic->lock);
 259
 260                if (trigger_mode != IOAPIC_LEVEL_TRIG)
 261                        continue;
 262
 263                ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 264                ent->fields.remote_irr = 0;
 265                if (!ent->fields.mask && (ioapic->irr & (1 << i)))
 266                        ioapic_service(ioapic, i);
 267        }
 268}
 269
 270bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
 271{
 272        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 273        smp_rmb();
 274        return test_bit(vector, ioapic->handled_vectors);
 275}
 276
 277void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
 278{
 279        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 280
 281        spin_lock(&ioapic->lock);
 282        __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
 283        spin_unlock(&ioapic->lock);
 284}
 285
 286static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 287{
 288        return container_of(dev, struct kvm_ioapic, dev);
 289}
 290
 291static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
 292{
 293        return ((addr >= ioapic->base_address &&
 294                 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 295}
 296
 297static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
 298                            void *val)
 299{
 300        struct kvm_ioapic *ioapic = to_ioapic(this);
 301        u32 result;
 302        if (!ioapic_in_range(ioapic, addr))
 303                return -EOPNOTSUPP;
 304
 305        ioapic_debug("addr %lx\n", (unsigned long)addr);
 306        ASSERT(!(addr & 0xf));  /* check alignment */
 307
 308        addr &= 0xff;
 309        spin_lock(&ioapic->lock);
 310        switch (addr) {
 311        case IOAPIC_REG_SELECT:
 312                result = ioapic->ioregsel;
 313                break;
 314
 315        case IOAPIC_REG_WINDOW:
 316                result = ioapic_read_indirect(ioapic, addr, len);
 317                break;
 318
 319        default:
 320                result = 0;
 321                break;
 322        }
 323        spin_unlock(&ioapic->lock);
 324
 325        switch (len) {
 326        case 8:
 327                *(u64 *) val = result;
 328                break;
 329        case 1:
 330        case 2:
 331        case 4:
 332                memcpy(val, (char *)&result, len);
 333                break;
 334        default:
 335                printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 336        }
 337        return 0;
 338}
 339
 340static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
 341                             const void *val)
 342{
 343        struct kvm_ioapic *ioapic = to_ioapic(this);
 344        u32 data;
 345        if (!ioapic_in_range(ioapic, addr))
 346                return -EOPNOTSUPP;
 347
 348        ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
 349                     (void*)addr, len, val);
 350        ASSERT(!(addr & 0xf));  /* check alignment */
 351
 352        switch (len) {
 353        case 8:
 354        case 4:
 355                data = *(u32 *) val;
 356                break;
 357        case 2:
 358                data = *(u16 *) val;
 359                break;
 360        case 1:
 361                data = *(u8  *) val;
 362                break;
 363        default:
 364                printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 365                return 0;
 366        }
 367
 368        addr &= 0xff;
 369        spin_lock(&ioapic->lock);
 370        switch (addr) {
 371        case IOAPIC_REG_SELECT:
 372                ioapic->ioregsel = data & 0xFF; /* 8-bit register */
 373                break;
 374
 375        case IOAPIC_REG_WINDOW:
 376                ioapic_write_indirect(ioapic, data);
 377                break;
 378#ifdef  CONFIG_IA64
 379        case IOAPIC_REG_EOI:
 380                __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
 381                break;
 382#endif
 383
 384        default:
 385                break;
 386        }
 387        spin_unlock(&ioapic->lock);
 388        return 0;
 389}
 390
 391void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 392{
 393        int i;
 394
 395        for (i = 0; i < IOAPIC_NUM_PINS; i++)
 396                ioapic->redirtbl[i].fields.mask = 1;
 397        ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 398        ioapic->ioregsel = 0;
 399        ioapic->irr = 0;
 400        ioapic->id = 0;
 401        update_handled_vectors(ioapic);
 402}
 403
 404static const struct kvm_io_device_ops ioapic_mmio_ops = {
 405        .read     = ioapic_mmio_read,
 406        .write    = ioapic_mmio_write,
 407};
 408
 409int kvm_ioapic_init(struct kvm *kvm)
 410{
 411        struct kvm_ioapic *ioapic;
 412        int ret;
 413
 414        ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
 415        if (!ioapic)
 416                return -ENOMEM;
 417        spin_lock_init(&ioapic->lock);
 418        kvm->arch.vioapic = ioapic;
 419        kvm_ioapic_reset(ioapic);
 420        kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 421        ioapic->kvm = kvm;
 422        mutex_lock(&kvm->slots_lock);
 423        ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
 424                                      IOAPIC_MEM_LENGTH, &ioapic->dev);
 425        mutex_unlock(&kvm->slots_lock);
 426        if (ret < 0) {
 427                kvm->arch.vioapic = NULL;
 428                kfree(ioapic);
 429        }
 430
 431        return ret;
 432}
 433
 434void kvm_ioapic_destroy(struct kvm *kvm)
 435{
 436        struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 437
 438        if (ioapic) {
 439                kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
 440                kvm->arch.vioapic = NULL;
 441                kfree(ioapic);
 442        }
 443}
 444
 445int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 446{
 447        struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 448        if (!ioapic)
 449                return -EINVAL;
 450
 451        spin_lock(&ioapic->lock);
 452        memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
 453        spin_unlock(&ioapic->lock);
 454        return 0;
 455}
 456
 457int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 458{
 459        struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
 460        if (!ioapic)
 461                return -EINVAL;
 462
 463        spin_lock(&ioapic->lock);
 464        memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
 465        update_handled_vectors(ioapic);
 466        spin_unlock(&ioapic->lock);
 467        return 0;
 468}
 469
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