linux/drivers/watchdog/iTCO_wdt.c
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   1/*
   2 *      intel TCO Watchdog Driver
   3 *
   4 *      (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
   5 *
   6 *      This program is free software; you can redistribute it and/or
   7 *      modify it under the terms of the GNU General Public License
   8 *      as published by the Free Software Foundation; either version
   9 *      2 of the License, or (at your option) any later version.
  10 *
  11 *      Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12 *      provide warranty for any of this software. This material is
  13 *      provided "AS-IS" and at no charge.
  14 *
  15 *      The TCO watchdog is implemented in the following I/O controller hubs:
  16 *      (See the intel documentation on http://developer.intel.com.)
  17 *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  18 *      document number 290687-002, 298242-027: 82801BA (ICH2)
  19 *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  20 *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  21 *      document number 290744-001, 290745-025: 82801DB (ICH4)
  22 *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  23 *      document number 273599-001, 273645-002: 82801E (C-ICH)
  24 *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  25 *      document number 300641-004, 300884-013: 6300ESB
  26 *      document number 301473-002, 301474-026: 82801F (ICH6)
  27 *      document number 313082-001, 313075-006: 631xESB, 632xESB
  28 *      document number 307013-003, 307014-024: 82801G (ICH7)
  29 *      document number 322896-001, 322897-001: NM10
  30 *      document number 313056-003, 313057-017: 82801H (ICH8)
  31 *      document number 316972-004, 316973-012: 82801I (ICH9)
  32 *      document number 319973-002, 319974-002: 82801J (ICH10)
  33 *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  34 *      document number 320066-003, 320257-008: EP80597 (IICH)
  35 *      document number 324645-001, 324646-001: Cougar Point (CPT)
  36 *      document number TBD                   : Patsburg (PBG)
  37 *      document number TBD                   : DH89xxCC
  38 *      document number TBD                   : Panther Point
  39 *      document number TBD                   : Lynx Point
  40 */
  41
  42/*
  43 *      Includes, defines, variables, module parameters, ...
  44 */
  45
  46#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47
  48/* Module and version information */
  49#define DRV_NAME        "iTCO_wdt"
  50#define DRV_VERSION     "1.10"
  51
  52/* Includes */
  53#include <linux/module.h>               /* For module specific items */
  54#include <linux/moduleparam.h>          /* For new moduleparam's */
  55#include <linux/types.h>                /* For standard types (like size_t) */
  56#include <linux/errno.h>                /* For the -ENODEV/... values */
  57#include <linux/kernel.h>               /* For printk/panic/... */
  58#include <linux/miscdevice.h>           /* For MODULE_ALIAS_MISCDEV
  59                                                        (WATCHDOG_MINOR) */
  60#include <linux/watchdog.h>             /* For the watchdog specific items */
  61#include <linux/init.h>                 /* For __init/__exit/... */
  62#include <linux/fs.h>                   /* For file operations */
  63#include <linux/platform_device.h>      /* For platform_driver framework */
  64#include <linux/pci.h>                  /* For pci functions */
  65#include <linux/ioport.h>               /* For io-port access */
  66#include <linux/spinlock.h>             /* For spin_lock/spin_unlock/... */
  67#include <linux/uaccess.h>              /* For copy_to_user/put_user/... */
  68#include <linux/io.h>                   /* For inb/outb/... */
  69#include <linux/mfd/core.h>
  70#include <linux/mfd/lpc_ich.h>
  71
  72#include "iTCO_vendor.h"
  73
  74/* Address definitions for the TCO */
  75/* TCO base address */
  76#define TCOBASE         (iTCO_wdt_private.tco_res->start)
  77/* SMI Control and Enable Register */
  78#define SMI_EN          (iTCO_wdt_private.smi_res->start)
  79
  80#define TCO_RLD         (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
  81#define TCOv1_TMR       (TCOBASE + 0x01) /* TCOv1 Timer Initial Value   */
  82#define TCO_DAT_IN      (TCOBASE + 0x02) /* TCO Data In Register        */
  83#define TCO_DAT_OUT     (TCOBASE + 0x03) /* TCO Data Out Register       */
  84#define TCO1_STS        (TCOBASE + 0x04) /* TCO1 Status Register        */
  85#define TCO2_STS        (TCOBASE + 0x06) /* TCO2 Status Register        */
  86#define TCO1_CNT        (TCOBASE + 0x08) /* TCO1 Control Register       */
  87#define TCO2_CNT        (TCOBASE + 0x0a) /* TCO2 Control Register       */
  88#define TCOv2_TMR       (TCOBASE + 0x12) /* TCOv2 Timer Initial Value   */
  89
  90/* internal variables */
  91static struct {         /* this is private data for the iTCO_wdt device */
  92        /* TCO version/generation */
  93        unsigned int iTCO_version;
  94        struct resource *tco_res;
  95        struct resource *smi_res;
  96        struct resource *gcs_res;
  97        /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
  98        unsigned long __iomem *gcs;
  99        /* the lock for io operations */
 100        spinlock_t io_lock;
 101        struct platform_device *dev;
 102        /* the PCI-device */
 103        struct pci_dev *pdev;
 104} iTCO_wdt_private;
 105
 106/* module parameters */
 107#define WATCHDOG_TIMEOUT 30     /* 30 sec default heartbeat */
 108static int heartbeat = WATCHDOG_TIMEOUT;  /* in seconds */
 109module_param(heartbeat, int, 0);
 110MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
 111        "5..76 (TCO v1) or 3..614 (TCO v2), default="
 112                                __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 113
 114static bool nowayout = WATCHDOG_NOWAYOUT;
 115module_param(nowayout, bool, 0);
 116MODULE_PARM_DESC(nowayout,
 117        "Watchdog cannot be stopped once started (default="
 118                                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 119
 120static int turn_SMI_watchdog_clear_off = 1;
 121module_param(turn_SMI_watchdog_clear_off, int, 0);
 122MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
 123        "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
 124
 125/*
 126 * Some TCO specific functions
 127 */
 128
 129static inline unsigned int seconds_to_ticks(int seconds)
 130{
 131        /* the internal timer is stored as ticks which decrement
 132         * every 0.6 seconds */
 133        return (seconds * 10) / 6;
 134}
 135
 136static void iTCO_wdt_set_NO_REBOOT_bit(void)
 137{
 138        u32 val32;
 139
 140        /* Set the NO_REBOOT bit: this disables reboots */
 141        if (iTCO_wdt_private.iTCO_version == 2) {
 142                val32 = readl(iTCO_wdt_private.gcs);
 143                val32 |= 0x00000020;
 144                writel(val32, iTCO_wdt_private.gcs);
 145        } else if (iTCO_wdt_private.iTCO_version == 1) {
 146                pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 147                val32 |= 0x00000002;
 148                pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 149        }
 150}
 151
 152static int iTCO_wdt_unset_NO_REBOOT_bit(void)
 153{
 154        int ret = 0;
 155        u32 val32;
 156
 157        /* Unset the NO_REBOOT bit: this enables reboots */
 158        if (iTCO_wdt_private.iTCO_version == 2) {
 159                val32 = readl(iTCO_wdt_private.gcs);
 160                val32 &= 0xffffffdf;
 161                writel(val32, iTCO_wdt_private.gcs);
 162
 163                val32 = readl(iTCO_wdt_private.gcs);
 164                if (val32 & 0x00000020)
 165                        ret = -EIO;
 166        } else if (iTCO_wdt_private.iTCO_version == 1) {
 167                pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 168                val32 &= 0xfffffffd;
 169                pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 170
 171                pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 172                if (val32 & 0x00000002)
 173                        ret = -EIO;
 174        }
 175
 176        return ret; /* returns: 0 = OK, -EIO = Error */
 177}
 178
 179static int iTCO_wdt_start(struct watchdog_device *wd_dev)
 180{
 181        unsigned int val;
 182
 183        spin_lock(&iTCO_wdt_private.io_lock);
 184
 185        iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
 186
 187        /* disable chipset's NO_REBOOT bit */
 188        if (iTCO_wdt_unset_NO_REBOOT_bit()) {
 189                spin_unlock(&iTCO_wdt_private.io_lock);
 190                pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
 191                return -EIO;
 192        }
 193
 194        /* Force the timer to its reload value by writing to the TCO_RLD
 195           register */
 196        if (iTCO_wdt_private.iTCO_version == 2)
 197                outw(0x01, TCO_RLD);
 198        else if (iTCO_wdt_private.iTCO_version == 1)
 199                outb(0x01, TCO_RLD);
 200
 201        /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
 202        val = inw(TCO1_CNT);
 203        val &= 0xf7ff;
 204        outw(val, TCO1_CNT);
 205        val = inw(TCO1_CNT);
 206        spin_unlock(&iTCO_wdt_private.io_lock);
 207
 208        if (val & 0x0800)
 209                return -1;
 210        return 0;
 211}
 212
 213static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
 214{
 215        unsigned int val;
 216
 217        spin_lock(&iTCO_wdt_private.io_lock);
 218
 219        iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
 220
 221        /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
 222        val = inw(TCO1_CNT);
 223        val |= 0x0800;
 224        outw(val, TCO1_CNT);
 225        val = inw(TCO1_CNT);
 226
 227        /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 228        iTCO_wdt_set_NO_REBOOT_bit();
 229
 230        spin_unlock(&iTCO_wdt_private.io_lock);
 231
 232        if ((val & 0x0800) == 0)
 233                return -1;
 234        return 0;
 235}
 236
 237static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
 238{
 239        spin_lock(&iTCO_wdt_private.io_lock);
 240
 241        iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
 242
 243        /* Reload the timer by writing to the TCO Timer Counter register */
 244        if (iTCO_wdt_private.iTCO_version == 2)
 245                outw(0x01, TCO_RLD);
 246        else if (iTCO_wdt_private.iTCO_version == 1) {
 247                /* Reset the timeout status bit so that the timer
 248                 * needs to count down twice again before rebooting */
 249                outw(0x0008, TCO1_STS); /* write 1 to clear bit */
 250
 251                outb(0x01, TCO_RLD);
 252        }
 253
 254        spin_unlock(&iTCO_wdt_private.io_lock);
 255        return 0;
 256}
 257
 258static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
 259{
 260        unsigned int val16;
 261        unsigned char val8;
 262        unsigned int tmrval;
 263
 264        tmrval = seconds_to_ticks(t);
 265
 266        /* For TCO v1 the timer counts down twice before rebooting */
 267        if (iTCO_wdt_private.iTCO_version == 1)
 268                tmrval /= 2;
 269
 270        /* from the specs: */
 271        /* "Values of 0h-3h are ignored and should not be attempted" */
 272        if (tmrval < 0x04)
 273                return -EINVAL;
 274        if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
 275            ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
 276                return -EINVAL;
 277
 278        iTCO_vendor_pre_set_heartbeat(tmrval);
 279
 280        /* Write new heartbeat to watchdog */
 281        if (iTCO_wdt_private.iTCO_version == 2) {
 282                spin_lock(&iTCO_wdt_private.io_lock);
 283                val16 = inw(TCOv2_TMR);
 284                val16 &= 0xfc00;
 285                val16 |= tmrval;
 286                outw(val16, TCOv2_TMR);
 287                val16 = inw(TCOv2_TMR);
 288                spin_unlock(&iTCO_wdt_private.io_lock);
 289
 290                if ((val16 & 0x3ff) != tmrval)
 291                        return -EINVAL;
 292        } else if (iTCO_wdt_private.iTCO_version == 1) {
 293                spin_lock(&iTCO_wdt_private.io_lock);
 294                val8 = inb(TCOv1_TMR);
 295                val8 &= 0xc0;
 296                val8 |= (tmrval & 0xff);
 297                outb(val8, TCOv1_TMR);
 298                val8 = inb(TCOv1_TMR);
 299                spin_unlock(&iTCO_wdt_private.io_lock);
 300
 301                if ((val8 & 0x3f) != tmrval)
 302                        return -EINVAL;
 303        }
 304
 305        wd_dev->timeout = t;
 306        return 0;
 307}
 308
 309static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
 310{
 311        unsigned int val16;
 312        unsigned char val8;
 313        unsigned int time_left = 0;
 314
 315        /* read the TCO Timer */
 316        if (iTCO_wdt_private.iTCO_version == 2) {
 317                spin_lock(&iTCO_wdt_private.io_lock);
 318                val16 = inw(TCO_RLD);
 319                val16 &= 0x3ff;
 320                spin_unlock(&iTCO_wdt_private.io_lock);
 321
 322                time_left = (val16 * 6) / 10;
 323        } else if (iTCO_wdt_private.iTCO_version == 1) {
 324                spin_lock(&iTCO_wdt_private.io_lock);
 325                val8 = inb(TCO_RLD);
 326                val8 &= 0x3f;
 327                if (!(inw(TCO1_STS) & 0x0008))
 328                        val8 += (inb(TCOv1_TMR) & 0x3f);
 329                spin_unlock(&iTCO_wdt_private.io_lock);
 330
 331                time_left = (val8 * 6) / 10;
 332        }
 333        return time_left;
 334}
 335
 336/*
 337 *      Kernel Interfaces
 338 */
 339
 340static const struct watchdog_info ident = {
 341        .options =              WDIOF_SETTIMEOUT |
 342                                WDIOF_KEEPALIVEPING |
 343                                WDIOF_MAGICCLOSE,
 344        .firmware_version =     0,
 345        .identity =             DRV_NAME,
 346};
 347
 348static const struct watchdog_ops iTCO_wdt_ops = {
 349        .owner =                THIS_MODULE,
 350        .start =                iTCO_wdt_start,
 351        .stop =                 iTCO_wdt_stop,
 352        .ping =                 iTCO_wdt_ping,
 353        .set_timeout =          iTCO_wdt_set_timeout,
 354        .get_timeleft =         iTCO_wdt_get_timeleft,
 355};
 356
 357static struct watchdog_device iTCO_wdt_watchdog_dev = {
 358        .info =         &ident,
 359        .ops =          &iTCO_wdt_ops,
 360};
 361
 362/*
 363 *      Init & exit routines
 364 */
 365
 366static void __devexit iTCO_wdt_cleanup(void)
 367{
 368        /* Stop the timer before we leave */
 369        if (!nowayout)
 370                iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
 371
 372        /* Deregister */
 373        watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
 374
 375        /* release resources */
 376        release_region(iTCO_wdt_private.tco_res->start,
 377                        resource_size(iTCO_wdt_private.tco_res));
 378        release_region(iTCO_wdt_private.smi_res->start,
 379                        resource_size(iTCO_wdt_private.smi_res));
 380        if (iTCO_wdt_private.iTCO_version == 2) {
 381                iounmap(iTCO_wdt_private.gcs);
 382                release_mem_region(iTCO_wdt_private.gcs_res->start,
 383                                resource_size(iTCO_wdt_private.gcs_res));
 384        }
 385
 386        iTCO_wdt_private.tco_res = NULL;
 387        iTCO_wdt_private.smi_res = NULL;
 388        iTCO_wdt_private.gcs_res = NULL;
 389        iTCO_wdt_private.gcs = NULL;
 390}
 391
 392static int __devinit iTCO_wdt_probe(struct platform_device *dev)
 393{
 394        int ret = -ENODEV;
 395        unsigned long val32;
 396        struct lpc_ich_info *ich_info = dev->dev.platform_data;
 397
 398        if (!ich_info)
 399                goto out;
 400
 401        spin_lock_init(&iTCO_wdt_private.io_lock);
 402
 403        iTCO_wdt_private.tco_res =
 404                platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
 405        if (!iTCO_wdt_private.tco_res)
 406                goto out;
 407
 408        iTCO_wdt_private.smi_res =
 409                platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
 410        if (!iTCO_wdt_private.smi_res)
 411                goto out;
 412
 413        iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
 414        iTCO_wdt_private.dev = dev;
 415        iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
 416
 417        /*
 418         * Get the Memory-Mapped GCS register, we need it for the
 419         * NO_REBOOT flag (TCO v2).
 420         */
 421        if (iTCO_wdt_private.iTCO_version == 2) {
 422                iTCO_wdt_private.gcs_res = platform_get_resource(dev,
 423                                                        IORESOURCE_MEM,
 424                                                        ICH_RES_MEM_GCS);
 425
 426                if (!iTCO_wdt_private.gcs_res)
 427                        goto out;
 428
 429                if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
 430                        resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
 431                        ret = -EBUSY;
 432                        goto out;
 433                }
 434                iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
 435                        resource_size(iTCO_wdt_private.gcs_res));
 436                if (!iTCO_wdt_private.gcs) {
 437                        ret = -EIO;
 438                        goto unreg_gcs;
 439                }
 440        }
 441
 442        /* Check chipset's NO_REBOOT bit */
 443        if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
 444                pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
 445                ret = -ENODEV;  /* Cannot reset NO_REBOOT bit */
 446                goto unmap_gcs;
 447        }
 448
 449        /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 450        iTCO_wdt_set_NO_REBOOT_bit();
 451
 452        /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
 453        if (!request_region(iTCO_wdt_private.smi_res->start,
 454                        resource_size(iTCO_wdt_private.smi_res), dev->name)) {
 455                pr_err("I/O address 0x%04llx already in use, device disabled\n",
 456                       (u64)SMI_EN);
 457                ret = -EBUSY;
 458                goto unmap_gcs;
 459        }
 460        if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
 461                /*
 462                 * Bit 13: TCO_EN -> 0
 463                 * Disables TCO logic generating an SMI#
 464                 */
 465                val32 = inl(SMI_EN);
 466                val32 &= 0xffffdfff;    /* Turn off SMI clearing watchdog */
 467                outl(val32, SMI_EN);
 468        }
 469
 470        if (!request_region(iTCO_wdt_private.tco_res->start,
 471                        resource_size(iTCO_wdt_private.tco_res), dev->name)) {
 472                pr_err("I/O address 0x%04llx already in use, device disabled\n",
 473                       (u64)TCOBASE);
 474                ret = -EBUSY;
 475                goto unreg_smi;
 476        }
 477
 478        pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
 479                ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
 480
 481        /* Clear out the (probably old) status */
 482        outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
 483        outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
 484        outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
 485
 486        iTCO_wdt_watchdog_dev.bootstatus = 0;
 487        iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
 488        watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
 489        iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
 490
 491        /* Make sure the watchdog is not running */
 492        iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
 493
 494        /* Check that the heartbeat value is within it's range;
 495           if not reset to the default */
 496        if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
 497                iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
 498                pr_info("timeout value out of range, using %d\n",
 499                        WATCHDOG_TIMEOUT);
 500        }
 501
 502        ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
 503        if (ret != 0) {
 504                pr_err("cannot register watchdog device (err=%d)\n", ret);
 505                goto unreg_tco;
 506        }
 507
 508        pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
 509                heartbeat, nowayout);
 510
 511        return 0;
 512
 513unreg_tco:
 514        release_region(iTCO_wdt_private.tco_res->start,
 515                        resource_size(iTCO_wdt_private.tco_res));
 516unreg_smi:
 517        release_region(iTCO_wdt_private.smi_res->start,
 518                        resource_size(iTCO_wdt_private.smi_res));
 519unmap_gcs:
 520        if (iTCO_wdt_private.iTCO_version == 2)
 521                iounmap(iTCO_wdt_private.gcs);
 522unreg_gcs:
 523        if (iTCO_wdt_private.iTCO_version == 2)
 524                release_mem_region(iTCO_wdt_private.gcs_res->start,
 525                                resource_size(iTCO_wdt_private.gcs_res));
 526out:
 527        iTCO_wdt_private.tco_res = NULL;
 528        iTCO_wdt_private.smi_res = NULL;
 529        iTCO_wdt_private.gcs_res = NULL;
 530        iTCO_wdt_private.gcs = NULL;
 531
 532        return ret;
 533}
 534
 535static int __devexit iTCO_wdt_remove(struct platform_device *dev)
 536{
 537        if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
 538                iTCO_wdt_cleanup();
 539
 540        return 0;
 541}
 542
 543static void iTCO_wdt_shutdown(struct platform_device *dev)
 544{
 545        iTCO_wdt_stop(NULL);
 546}
 547
 548static struct platform_driver iTCO_wdt_driver = {
 549        .probe          = iTCO_wdt_probe,
 550        .remove         = __devexit_p(iTCO_wdt_remove),
 551        .shutdown       = iTCO_wdt_shutdown,
 552        .driver         = {
 553                .owner  = THIS_MODULE,
 554                .name   = DRV_NAME,
 555        },
 556};
 557
 558static int __init iTCO_wdt_init_module(void)
 559{
 560        int err;
 561
 562        pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
 563
 564        err = platform_driver_register(&iTCO_wdt_driver);
 565        if (err)
 566                return err;
 567
 568        return 0;
 569}
 570
 571static void __exit iTCO_wdt_cleanup_module(void)
 572{
 573        platform_driver_unregister(&iTCO_wdt_driver);
 574        pr_info("Watchdog Module Unloaded\n");
 575}
 576
 577module_init(iTCO_wdt_init_module);
 578module_exit(iTCO_wdt_cleanup_module);
 579
 580MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
 581MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
 582MODULE_VERSION(DRV_VERSION);
 583MODULE_LICENSE("GPL");
 584MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 585MODULE_ALIAS("platform:" DRV_NAME);
 586
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