linux/drivers/spi/spi-davinci.c
<<
>>
Prefs
   1/*
   2 * Copyright (C) 2009 Texas Instruments.
   3 * Copyright (C) 2010 EF Johnson Technologies
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 */
  19
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/gpio.h>
  23#include <linux/module.h>
  24#include <linux/delay.h>
  25#include <linux/platform_device.h>
  26#include <linux/err.h>
  27#include <linux/clk.h>
  28#include <linux/dma-mapping.h>
  29#include <linux/spi/spi.h>
  30#include <linux/spi/spi_bitbang.h>
  31#include <linux/slab.h>
  32
  33#include <mach/spi.h>
  34#include <mach/edma.h>
  35
  36#define SPI_NO_RESOURCE         ((resource_size_t)-1)
  37
  38#define SPI_MAX_CHIPSELECT      2
  39
  40#define CS_DEFAULT      0xFF
  41
  42#define SPIFMT_PHASE_MASK       BIT(16)
  43#define SPIFMT_POLARITY_MASK    BIT(17)
  44#define SPIFMT_DISTIMER_MASK    BIT(18)
  45#define SPIFMT_SHIFTDIR_MASK    BIT(20)
  46#define SPIFMT_WAITENA_MASK     BIT(21)
  47#define SPIFMT_PARITYENA_MASK   BIT(22)
  48#define SPIFMT_ODD_PARITY_MASK  BIT(23)
  49#define SPIFMT_WDELAY_MASK      0x3f000000u
  50#define SPIFMT_WDELAY_SHIFT     24
  51#define SPIFMT_PRESCALE_SHIFT   8
  52
  53/* SPIPC0 */
  54#define SPIPC0_DIFUN_MASK       BIT(11)         /* MISO */
  55#define SPIPC0_DOFUN_MASK       BIT(10)         /* MOSI */
  56#define SPIPC0_CLKFUN_MASK      BIT(9)          /* CLK */
  57#define SPIPC0_SPIENA_MASK      BIT(8)          /* nREADY */
  58
  59#define SPIINT_MASKALL          0x0101035F
  60#define SPIINT_MASKINT          0x0000015F
  61#define SPI_INTLVL_1            0x000001FF
  62#define SPI_INTLVL_0            0x00000000
  63
  64/* SPIDAT1 (upper 16 bit defines) */
  65#define SPIDAT1_CSHOLD_MASK     BIT(12)
  66
  67/* SPIGCR1 */
  68#define SPIGCR1_CLKMOD_MASK     BIT(1)
  69#define SPIGCR1_MASTER_MASK     BIT(0)
  70#define SPIGCR1_POWERDOWN_MASK  BIT(8)
  71#define SPIGCR1_LOOPBACK_MASK   BIT(16)
  72#define SPIGCR1_SPIENA_MASK     BIT(24)
  73
  74/* SPIBUF */
  75#define SPIBUF_TXFULL_MASK      BIT(29)
  76#define SPIBUF_RXEMPTY_MASK     BIT(31)
  77
  78/* SPIDELAY */
  79#define SPIDELAY_C2TDELAY_SHIFT 24
  80#define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
  81#define SPIDELAY_T2CDELAY_SHIFT 16
  82#define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
  83#define SPIDELAY_T2EDELAY_SHIFT 8
  84#define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
  85#define SPIDELAY_C2EDELAY_SHIFT 0
  86#define SPIDELAY_C2EDELAY_MASK  0xFF
  87
  88/* Error Masks */
  89#define SPIFLG_DLEN_ERR_MASK            BIT(0)
  90#define SPIFLG_TIMEOUT_MASK             BIT(1)
  91#define SPIFLG_PARERR_MASK              BIT(2)
  92#define SPIFLG_DESYNC_MASK              BIT(3)
  93#define SPIFLG_BITERR_MASK              BIT(4)
  94#define SPIFLG_OVRRUN_MASK              BIT(6)
  95#define SPIFLG_BUF_INIT_ACTIVE_MASK     BIT(24)
  96#define SPIFLG_ERROR_MASK               (SPIFLG_DLEN_ERR_MASK \
  97                                | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
  98                                | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
  99                                | SPIFLG_OVRRUN_MASK)
 100
 101#define SPIINT_DMA_REQ_EN       BIT(16)
 102
 103/* SPI Controller registers */
 104#define SPIGCR0         0x00
 105#define SPIGCR1         0x04
 106#define SPIINT          0x08
 107#define SPILVL          0x0c
 108#define SPIFLG          0x10
 109#define SPIPC0          0x14
 110#define SPIDAT1         0x3c
 111#define SPIBUF          0x40
 112#define SPIDELAY        0x48
 113#define SPIDEF          0x4c
 114#define SPIFMT0         0x50
 115
 116/* We have 2 DMA channels per CS, one for RX and one for TX */
 117struct davinci_spi_dma {
 118        int                     tx_channel;
 119        int                     rx_channel;
 120        int                     dummy_param_slot;
 121        enum dma_event_q        eventq;
 122};
 123
 124/* SPI Controller driver's private data. */
 125struct davinci_spi {
 126        struct spi_bitbang      bitbang;
 127        struct clk              *clk;
 128
 129        u8                      version;
 130        resource_size_t         pbase;
 131        void __iomem            *base;
 132        u32                     irq;
 133        struct completion       done;
 134
 135        const void              *tx;
 136        void                    *rx;
 137#define SPI_TMP_BUFSZ   (SMP_CACHE_BYTES + 1)
 138        u8                      rx_tmp_buf[SPI_TMP_BUFSZ];
 139        int                     rcount;
 140        int                     wcount;
 141        struct davinci_spi_dma  dma;
 142        struct davinci_spi_platform_data *pdata;
 143
 144        void                    (*get_rx)(u32 rx_data, struct davinci_spi *);
 145        u32                     (*get_tx)(struct davinci_spi *);
 146
 147        u8                      bytes_per_word[SPI_MAX_CHIPSELECT];
 148};
 149
 150static struct davinci_spi_config davinci_spi_default_cfg;
 151
 152static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
 153{
 154        if (dspi->rx) {
 155                u8 *rx = dspi->rx;
 156                *rx++ = (u8)data;
 157                dspi->rx = rx;
 158        }
 159}
 160
 161static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
 162{
 163        if (dspi->rx) {
 164                u16 *rx = dspi->rx;
 165                *rx++ = (u16)data;
 166                dspi->rx = rx;
 167        }
 168}
 169
 170static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
 171{
 172        u32 data = 0;
 173        if (dspi->tx) {
 174                const u8 *tx = dspi->tx;
 175                data = *tx++;
 176                dspi->tx = tx;
 177        }
 178        return data;
 179}
 180
 181static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
 182{
 183        u32 data = 0;
 184        if (dspi->tx) {
 185                const u16 *tx = dspi->tx;
 186                data = *tx++;
 187                dspi->tx = tx;
 188        }
 189        return data;
 190}
 191
 192static inline void set_io_bits(void __iomem *addr, u32 bits)
 193{
 194        u32 v = ioread32(addr);
 195
 196        v |= bits;
 197        iowrite32(v, addr);
 198}
 199
 200static inline void clear_io_bits(void __iomem *addr, u32 bits)
 201{
 202        u32 v = ioread32(addr);
 203
 204        v &= ~bits;
 205        iowrite32(v, addr);
 206}
 207
 208/*
 209 * Interface to control the chip select signal
 210 */
 211static void davinci_spi_chipselect(struct spi_device *spi, int value)
 212{
 213        struct davinci_spi *dspi;
 214        struct davinci_spi_platform_data *pdata;
 215        u8 chip_sel = spi->chip_select;
 216        u16 spidat1 = CS_DEFAULT;
 217        bool gpio_chipsel = false;
 218
 219        dspi = spi_master_get_devdata(spi->master);
 220        pdata = dspi->pdata;
 221
 222        if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
 223                                pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
 224                gpio_chipsel = true;
 225
 226        /*
 227         * Board specific chip select logic decides the polarity and cs
 228         * line for the controller
 229         */
 230        if (gpio_chipsel) {
 231                if (value == BITBANG_CS_ACTIVE)
 232                        gpio_set_value(pdata->chip_sel[chip_sel], 0);
 233                else
 234                        gpio_set_value(pdata->chip_sel[chip_sel], 1);
 235        } else {
 236                if (value == BITBANG_CS_ACTIVE) {
 237                        spidat1 |= SPIDAT1_CSHOLD_MASK;
 238                        spidat1 &= ~(0x1 << chip_sel);
 239                }
 240
 241                iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
 242        }
 243}
 244
 245/**
 246 * davinci_spi_get_prescale - Calculates the correct prescale value
 247 * @maxspeed_hz: the maximum rate the SPI clock can run at
 248 *
 249 * This function calculates the prescale value that generates a clock rate
 250 * less than or equal to the specified maximum.
 251 *
 252 * Returns: calculated prescale - 1 for easy programming into SPI registers
 253 * or negative error number if valid prescalar cannot be updated.
 254 */
 255static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
 256                                                        u32 max_speed_hz)
 257{
 258        int ret;
 259
 260        ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
 261
 262        if (ret < 3 || ret > 256)
 263                return -EINVAL;
 264
 265        return ret - 1;
 266}
 267
 268/**
 269 * davinci_spi_setup_transfer - This functions will determine transfer method
 270 * @spi: spi device on which data transfer to be done
 271 * @t: spi transfer in which transfer info is filled
 272 *
 273 * This function determines data transfer method (8/16/32 bit transfer).
 274 * It will also set the SPI Clock Control register according to
 275 * SPI slave device freq.
 276 */
 277static int davinci_spi_setup_transfer(struct spi_device *spi,
 278                struct spi_transfer *t)
 279{
 280
 281        struct davinci_spi *dspi;
 282        struct davinci_spi_config *spicfg;
 283        u8 bits_per_word = 0;
 284        u32 hz = 0, spifmt = 0, prescale = 0;
 285
 286        dspi = spi_master_get_devdata(spi->master);
 287        spicfg = (struct davinci_spi_config *)spi->controller_data;
 288        if (!spicfg)
 289                spicfg = &davinci_spi_default_cfg;
 290
 291        if (t) {
 292                bits_per_word = t->bits_per_word;
 293                hz = t->speed_hz;
 294        }
 295
 296        /* if bits_per_word is not set then set it default */
 297        if (!bits_per_word)
 298                bits_per_word = spi->bits_per_word;
 299
 300        /*
 301         * Assign function pointer to appropriate transfer method
 302         * 8bit, 16bit or 32bit transfer
 303         */
 304        if (bits_per_word <= 8 && bits_per_word >= 2) {
 305                dspi->get_rx = davinci_spi_rx_buf_u8;
 306                dspi->get_tx = davinci_spi_tx_buf_u8;
 307                dspi->bytes_per_word[spi->chip_select] = 1;
 308        } else if (bits_per_word <= 16 && bits_per_word >= 2) {
 309                dspi->get_rx = davinci_spi_rx_buf_u16;
 310                dspi->get_tx = davinci_spi_tx_buf_u16;
 311                dspi->bytes_per_word[spi->chip_select] = 2;
 312        } else
 313                return -EINVAL;
 314
 315        if (!hz)
 316                hz = spi->max_speed_hz;
 317
 318        /* Set up SPIFMTn register, unique to this chipselect. */
 319
 320        prescale = davinci_spi_get_prescale(dspi, hz);
 321        if (prescale < 0)
 322                return prescale;
 323
 324        spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
 325
 326        if (spi->mode & SPI_LSB_FIRST)
 327                spifmt |= SPIFMT_SHIFTDIR_MASK;
 328
 329        if (spi->mode & SPI_CPOL)
 330                spifmt |= SPIFMT_POLARITY_MASK;
 331
 332        if (!(spi->mode & SPI_CPHA))
 333                spifmt |= SPIFMT_PHASE_MASK;
 334
 335        /*
 336         * Version 1 hardware supports two basic SPI modes:
 337         *  - Standard SPI mode uses 4 pins, with chipselect
 338         *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
 339         *      (distinct from SPI_3WIRE, with just one data wire;
 340         *      or similar variants without MOSI or without MISO)
 341         *
 342         * Version 2 hardware supports an optional handshaking signal,
 343         * so it can support two more modes:
 344         *  - 5 pin SPI variant is standard SPI plus SPI_READY
 345         *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
 346         */
 347
 348        if (dspi->version == SPI_VERSION_2) {
 349
 350                u32 delay = 0;
 351
 352                spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
 353                                                        & SPIFMT_WDELAY_MASK);
 354
 355                if (spicfg->odd_parity)
 356                        spifmt |= SPIFMT_ODD_PARITY_MASK;
 357
 358                if (spicfg->parity_enable)
 359                        spifmt |= SPIFMT_PARITYENA_MASK;
 360
 361                if (spicfg->timer_disable) {
 362                        spifmt |= SPIFMT_DISTIMER_MASK;
 363                } else {
 364                        delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
 365                                                & SPIDELAY_C2TDELAY_MASK;
 366                        delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
 367                                                & SPIDELAY_T2CDELAY_MASK;
 368                }
 369
 370                if (spi->mode & SPI_READY) {
 371                        spifmt |= SPIFMT_WAITENA_MASK;
 372                        delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
 373                                                & SPIDELAY_T2EDELAY_MASK;
 374                        delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
 375                                                & SPIDELAY_C2EDELAY_MASK;
 376                }
 377
 378                iowrite32(delay, dspi->base + SPIDELAY);
 379        }
 380
 381        iowrite32(spifmt, dspi->base + SPIFMT0);
 382
 383        return 0;
 384}
 385
 386/**
 387 * davinci_spi_setup - This functions will set default transfer method
 388 * @spi: spi device on which data transfer to be done
 389 *
 390 * This functions sets the default transfer method.
 391 */
 392static int davinci_spi_setup(struct spi_device *spi)
 393{
 394        int retval = 0;
 395        struct davinci_spi *dspi;
 396        struct davinci_spi_platform_data *pdata;
 397
 398        dspi = spi_master_get_devdata(spi->master);
 399        pdata = dspi->pdata;
 400
 401        /* if bits per word length is zero then set it default 8 */
 402        if (!spi->bits_per_word)
 403                spi->bits_per_word = 8;
 404
 405        if (!(spi->mode & SPI_NO_CS)) {
 406                if ((pdata->chip_sel == NULL) ||
 407                    (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
 408                        set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
 409
 410        }
 411
 412        if (spi->mode & SPI_READY)
 413                set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
 414
 415        if (spi->mode & SPI_LOOP)
 416                set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
 417        else
 418                clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
 419
 420        return retval;
 421}
 422
 423static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
 424{
 425        struct device *sdev = dspi->bitbang.master->dev.parent;
 426
 427        if (int_status & SPIFLG_TIMEOUT_MASK) {
 428                dev_dbg(sdev, "SPI Time-out Error\n");
 429                return -ETIMEDOUT;
 430        }
 431        if (int_status & SPIFLG_DESYNC_MASK) {
 432                dev_dbg(sdev, "SPI Desynchronization Error\n");
 433                return -EIO;
 434        }
 435        if (int_status & SPIFLG_BITERR_MASK) {
 436                dev_dbg(sdev, "SPI Bit error\n");
 437                return -EIO;
 438        }
 439
 440        if (dspi->version == SPI_VERSION_2) {
 441                if (int_status & SPIFLG_DLEN_ERR_MASK) {
 442                        dev_dbg(sdev, "SPI Data Length Error\n");
 443                        return -EIO;
 444                }
 445                if (int_status & SPIFLG_PARERR_MASK) {
 446                        dev_dbg(sdev, "SPI Parity Error\n");
 447                        return -EIO;
 448                }
 449                if (int_status & SPIFLG_OVRRUN_MASK) {
 450                        dev_dbg(sdev, "SPI Data Overrun error\n");
 451                        return -EIO;
 452                }
 453                if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
 454                        dev_dbg(sdev, "SPI Buffer Init Active\n");
 455                        return -EBUSY;
 456                }
 457        }
 458
 459        return 0;
 460}
 461
 462/**
 463 * davinci_spi_process_events - check for and handle any SPI controller events
 464 * @dspi: the controller data
 465 *
 466 * This function will check the SPIFLG register and handle any events that are
 467 * detected there
 468 */
 469static int davinci_spi_process_events(struct davinci_spi *dspi)
 470{
 471        u32 buf, status, errors = 0, spidat1;
 472
 473        buf = ioread32(dspi->base + SPIBUF);
 474
 475        if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
 476                dspi->get_rx(buf & 0xFFFF, dspi);
 477                dspi->rcount--;
 478        }
 479
 480        status = ioread32(dspi->base + SPIFLG);
 481
 482        if (unlikely(status & SPIFLG_ERROR_MASK)) {
 483                errors = status & SPIFLG_ERROR_MASK;
 484                goto out;
 485        }
 486
 487        if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
 488                spidat1 = ioread32(dspi->base + SPIDAT1);
 489                dspi->wcount--;
 490                spidat1 &= ~0xFFFF;
 491                spidat1 |= 0xFFFF & dspi->get_tx(dspi);
 492                iowrite32(spidat1, dspi->base + SPIDAT1);
 493        }
 494
 495out:
 496        return errors;
 497}
 498
 499static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
 500{
 501        struct davinci_spi *dspi = data;
 502        struct davinci_spi_dma *dma = &dspi->dma;
 503
 504        edma_stop(lch);
 505
 506        if (status == DMA_COMPLETE) {
 507                if (lch == dma->rx_channel)
 508                        dspi->rcount = 0;
 509                if (lch == dma->tx_channel)
 510                        dspi->wcount = 0;
 511        }
 512
 513        if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
 514                complete(&dspi->done);
 515}
 516
 517/**
 518 * davinci_spi_bufs - functions which will handle transfer data
 519 * @spi: spi device on which data transfer to be done
 520 * @t: spi transfer in which transfer info is filled
 521 *
 522 * This function will put data to be transferred into data register
 523 * of SPI controller and then wait until the completion will be marked
 524 * by the IRQ Handler.
 525 */
 526static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 527{
 528        struct davinci_spi *dspi;
 529        int data_type, ret;
 530        u32 tx_data, spidat1;
 531        u32 errors = 0;
 532        struct davinci_spi_config *spicfg;
 533        struct davinci_spi_platform_data *pdata;
 534        unsigned uninitialized_var(rx_buf_count);
 535        struct device *sdev;
 536
 537        dspi = spi_master_get_devdata(spi->master);
 538        pdata = dspi->pdata;
 539        spicfg = (struct davinci_spi_config *)spi->controller_data;
 540        if (!spicfg)
 541                spicfg = &davinci_spi_default_cfg;
 542        sdev = dspi->bitbang.master->dev.parent;
 543
 544        /* convert len to words based on bits_per_word */
 545        data_type = dspi->bytes_per_word[spi->chip_select];
 546
 547        dspi->tx = t->tx_buf;
 548        dspi->rx = t->rx_buf;
 549        dspi->wcount = t->len / data_type;
 550        dspi->rcount = dspi->wcount;
 551
 552        spidat1 = ioread32(dspi->base + SPIDAT1);
 553
 554        clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
 555        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
 556
 557        INIT_COMPLETION(dspi->done);
 558
 559        if (spicfg->io_type == SPI_IO_TYPE_INTR)
 560                set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
 561
 562        if (spicfg->io_type != SPI_IO_TYPE_DMA) {
 563                /* start the transfer */
 564                dspi->wcount--;
 565                tx_data = dspi->get_tx(dspi);
 566                spidat1 &= 0xFFFF0000;
 567                spidat1 |= tx_data & 0xFFFF;
 568                iowrite32(spidat1, dspi->base + SPIDAT1);
 569        } else {
 570                struct davinci_spi_dma *dma;
 571                unsigned long tx_reg, rx_reg;
 572                struct edmacc_param param;
 573                void *rx_buf;
 574                int b, c;
 575
 576                dma = &dspi->dma;
 577
 578                tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
 579                rx_reg = (unsigned long)dspi->pbase + SPIBUF;
 580
 581                /*
 582                 * Transmit DMA setup
 583                 *
 584                 * If there is transmit data, map the transmit buffer, set it
 585                 * as the source of data and set the source B index to data
 586                 * size. If there is no transmit data, set the transmit register
 587                 * as the source of data, and set the source B index to zero.
 588                 *
 589                 * The destination is always the transmit register itself. And
 590                 * the destination never increments.
 591                 */
 592
 593                if (t->tx_buf) {
 594                        t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
 595                                                t->len, DMA_TO_DEVICE);
 596                        if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 597                                dev_dbg(sdev, "Unable to DMA map %d bytes"
 598                                                "TX buffer\n", t->len);
 599                                return -ENOMEM;
 600                        }
 601                }
 602
 603                /*
 604                 * If number of words is greater than 65535, then we need
 605                 * to configure a 3 dimension transfer.  Use the BCNTRLD
 606                 * feature to allow for transfers that aren't even multiples
 607                 * of 65535 (or any other possible b size) by first transferring
 608                 * the remainder amount then grabbing the next N blocks of
 609                 * 65535 words.
 610                 */
 611
 612                c = dspi->wcount / (SZ_64K - 1);        /* N 65535 Blocks */
 613                b = dspi->wcount - c * (SZ_64K - 1);    /* Remainder */
 614                if (b)
 615                        c++;
 616                else
 617                        b = SZ_64K - 1;
 618
 619                param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
 620                param.src = t->tx_buf ? t->tx_dma : tx_reg;
 621                param.a_b_cnt = b << 16 | data_type;
 622                param.dst = tx_reg;
 623                param.src_dst_bidx = t->tx_buf ? data_type : 0;
 624                param.link_bcntrld = 0xffffffff;
 625                param.src_dst_cidx = t->tx_buf ? data_type : 0;
 626                param.ccnt = c;
 627                edma_write_slot(dma->tx_channel, &param);
 628                edma_link(dma->tx_channel, dma->dummy_param_slot);
 629
 630                /*
 631                 * Receive DMA setup
 632                 *
 633                 * If there is receive buffer, use it to receive data. If there
 634                 * is none provided, use a temporary receive buffer. Set the
 635                 * destination B index to 0 so effectively only one byte is used
 636                 * in the temporary buffer (address does not increment).
 637                 *
 638                 * The source of receive data is the receive data register. The
 639                 * source address never increments.
 640                 */
 641
 642                if (t->rx_buf) {
 643                        rx_buf = t->rx_buf;
 644                        rx_buf_count = t->len;
 645                } else {
 646                        rx_buf = dspi->rx_tmp_buf;
 647                        rx_buf_count = sizeof(dspi->rx_tmp_buf);
 648                }
 649
 650                t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
 651                                                        DMA_FROM_DEVICE);
 652                if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 653                        dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
 654                                                                rx_buf_count);
 655                        if (t->tx_buf)
 656                                dma_unmap_single(&spi->dev, t->tx_dma, t->len,
 657                                                                DMA_TO_DEVICE);
 658                        return -ENOMEM;
 659                }
 660
 661                param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
 662                param.src = rx_reg;
 663                param.a_b_cnt = b << 16 | data_type;
 664                param.dst = t->rx_dma;
 665                param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
 666                param.link_bcntrld = 0xffffffff;
 667                param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16;
 668                param.ccnt = c;
 669                edma_write_slot(dma->rx_channel, &param);
 670
 671                if (pdata->cshold_bug)
 672                        iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
 673
 674                edma_start(dma->rx_channel);
 675                edma_start(dma->tx_channel);
 676                set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
 677        }
 678
 679        /* Wait for the transfer to complete */
 680        if (spicfg->io_type != SPI_IO_TYPE_POLL) {
 681                wait_for_completion_interruptible(&(dspi->done));
 682        } else {
 683                while (dspi->rcount > 0 || dspi->wcount > 0) {
 684                        errors = davinci_spi_process_events(dspi);
 685                        if (errors)
 686                                break;
 687                        cpu_relax();
 688                }
 689        }
 690
 691        clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
 692        if (spicfg->io_type == SPI_IO_TYPE_DMA) {
 693
 694                if (t->tx_buf)
 695                        dma_unmap_single(&spi->dev, t->tx_dma, t->len,
 696                                                                DMA_TO_DEVICE);
 697
 698                dma_unmap_single(&spi->dev, t->rx_dma, rx_buf_count,
 699                                                        DMA_FROM_DEVICE);
 700
 701                clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
 702        }
 703
 704        clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
 705        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
 706
 707        /*
 708         * Check for bit error, desync error,parity error,timeout error and
 709         * receive overflow errors
 710         */
 711        if (errors) {
 712                ret = davinci_spi_check_error(dspi, errors);
 713                WARN(!ret, "%s: error reported but no error found!\n",
 714                                                        dev_name(&spi->dev));
 715                return ret;
 716        }
 717
 718        if (dspi->rcount != 0 || dspi->wcount != 0) {
 719                dev_err(sdev, "SPI data transfer error\n");
 720                return -EIO;
 721        }
 722
 723        return t->len;
 724}
 725
 726/**
 727 * davinci_spi_irq - Interrupt handler for SPI Master Controller
 728 * @irq: IRQ number for this SPI Master
 729 * @context_data: structure for SPI Master controller davinci_spi
 730 *
 731 * ISR will determine that interrupt arrives either for READ or WRITE command.
 732 * According to command it will do the appropriate action. It will check
 733 * transfer length and if it is not zero then dispatch transfer command again.
 734 * If transfer length is zero then it will indicate the COMPLETION so that
 735 * davinci_spi_bufs function can go ahead.
 736 */
 737static irqreturn_t davinci_spi_irq(s32 irq, void *data)
 738{
 739        struct davinci_spi *dspi = data;
 740        int status;
 741
 742        status = davinci_spi_process_events(dspi);
 743        if (unlikely(status != 0))
 744                clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
 745
 746        if ((!dspi->rcount && !dspi->wcount) || status)
 747                complete(&dspi->done);
 748
 749        return IRQ_HANDLED;
 750}
 751
 752static int davinci_spi_request_dma(struct davinci_spi *dspi)
 753{
 754        int r;
 755        struct davinci_spi_dma *dma = &dspi->dma;
 756
 757        r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
 758                                                                dma->eventq);
 759        if (r < 0) {
 760                pr_err("Unable to request DMA channel for SPI RX\n");
 761                r = -EAGAIN;
 762                goto rx_dma_failed;
 763        }
 764
 765        r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
 766                                                                dma->eventq);
 767        if (r < 0) {
 768                pr_err("Unable to request DMA channel for SPI TX\n");
 769                r = -EAGAIN;
 770                goto tx_dma_failed;
 771        }
 772
 773        r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
 774        if (r < 0) {
 775                pr_err("Unable to request SPI TX DMA param slot\n");
 776                r = -EAGAIN;
 777                goto param_failed;
 778        }
 779        dma->dummy_param_slot = r;
 780        edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
 781
 782        return 0;
 783param_failed:
 784        edma_free_channel(dma->tx_channel);
 785tx_dma_failed:
 786        edma_free_channel(dma->rx_channel);
 787rx_dma_failed:
 788        return r;
 789}
 790
 791/**
 792 * davinci_spi_probe - probe function for SPI Master Controller
 793 * @pdev: platform_device structure which contains plateform specific data
 794 *
 795 * According to Linux Device Model this function will be invoked by Linux
 796 * with platform_device struct which contains the device specific info.
 797 * This function will map the SPI controller's memory, register IRQ,
 798 * Reset SPI controller and setting its registers to default value.
 799 * It will invoke spi_bitbang_start to create work queue so that client driver
 800 * can register transfer method to work queue.
 801 */
 802static int __devinit davinci_spi_probe(struct platform_device *pdev)
 803{
 804        struct spi_master *master;
 805        struct davinci_spi *dspi;
 806        struct davinci_spi_platform_data *pdata;
 807        struct resource *r, *mem;
 808        resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
 809        resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
 810        int i = 0, ret = 0;
 811        u32 spipc0;
 812
 813        pdata = pdev->dev.platform_data;
 814        if (pdata == NULL) {
 815                ret = -ENODEV;
 816                goto err;
 817        }
 818
 819        master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
 820        if (master == NULL) {
 821                ret = -ENOMEM;
 822                goto err;
 823        }
 824
 825        dev_set_drvdata(&pdev->dev, master);
 826
 827        dspi = spi_master_get_devdata(master);
 828        if (dspi == NULL) {
 829                ret = -ENOENT;
 830                goto free_master;
 831        }
 832
 833        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 834        if (r == NULL) {
 835                ret = -ENOENT;
 836                goto free_master;
 837        }
 838
 839        dspi->pbase = r->start;
 840        dspi->pdata = pdata;
 841
 842        mem = request_mem_region(r->start, resource_size(r), pdev->name);
 843        if (mem == NULL) {
 844                ret = -EBUSY;
 845                goto free_master;
 846        }
 847
 848        dspi->base = ioremap(r->start, resource_size(r));
 849        if (dspi->base == NULL) {
 850                ret = -ENOMEM;
 851                goto release_region;
 852        }
 853
 854        dspi->irq = platform_get_irq(pdev, 0);
 855        if (dspi->irq <= 0) {
 856                ret = -EINVAL;
 857                goto unmap_io;
 858        }
 859
 860        ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
 861                                                                        dspi);
 862        if (ret)
 863                goto unmap_io;
 864
 865        dspi->bitbang.master = spi_master_get(master);
 866        if (dspi->bitbang.master == NULL) {
 867                ret = -ENODEV;
 868                goto irq_free;
 869        }
 870
 871        dspi->clk = clk_get(&pdev->dev, NULL);
 872        if (IS_ERR(dspi->clk)) {
 873                ret = -ENODEV;
 874                goto put_master;
 875        }
 876        clk_enable(dspi->clk);
 877
 878        master->bus_num = pdev->id;
 879        master->num_chipselect = pdata->num_chipselect;
 880        master->setup = davinci_spi_setup;
 881
 882        dspi->bitbang.chipselect = davinci_spi_chipselect;
 883        dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
 884
 885        dspi->version = pdata->version;
 886
 887        dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
 888        if (dspi->version == SPI_VERSION_2)
 889                dspi->bitbang.flags |= SPI_READY;
 890
 891        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 892        if (r)
 893                dma_rx_chan = r->start;
 894        r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 895        if (r)
 896                dma_tx_chan = r->start;
 897
 898        dspi->bitbang.txrx_bufs = davinci_spi_bufs;
 899        if (dma_rx_chan != SPI_NO_RESOURCE &&
 900            dma_tx_chan != SPI_NO_RESOURCE) {
 901                dspi->dma.rx_channel = dma_rx_chan;
 902                dspi->dma.tx_channel = dma_tx_chan;
 903                dspi->dma.eventq = pdata->dma_event_q;
 904
 905                ret = davinci_spi_request_dma(dspi);
 906                if (ret)
 907                        goto free_clk;
 908
 909                dev_info(&pdev->dev, "DMA: supported\n");
 910                dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
 911                                "event queue: %d\n", dma_rx_chan, dma_tx_chan,
 912                                pdata->dma_event_q);
 913        }
 914
 915        dspi->get_rx = davinci_spi_rx_buf_u8;
 916        dspi->get_tx = davinci_spi_tx_buf_u8;
 917
 918        init_completion(&dspi->done);
 919
 920        /* Reset In/OUT SPI module */
 921        iowrite32(0, dspi->base + SPIGCR0);
 922        udelay(100);
 923        iowrite32(1, dspi->base + SPIGCR0);
 924
 925        /* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
 926        spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
 927        iowrite32(spipc0, dspi->base + SPIPC0);
 928
 929        /* initialize chip selects */
 930        if (pdata->chip_sel) {
 931                for (i = 0; i < pdata->num_chipselect; i++) {
 932                        if (pdata->chip_sel[i] != SPI_INTERN_CS)
 933                                gpio_direction_output(pdata->chip_sel[i], 1);
 934                }
 935        }
 936
 937        if (pdata->intr_line)
 938                iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
 939        else
 940                iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
 941
 942        iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
 943
 944        /* master mode default */
 945        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
 946        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
 947        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
 948
 949        ret = spi_bitbang_start(&dspi->bitbang);
 950        if (ret)
 951                goto free_dma;
 952
 953        dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
 954
 955        return ret;
 956
 957free_dma:
 958        edma_free_channel(dspi->dma.tx_channel);
 959        edma_free_channel(dspi->dma.rx_channel);
 960        edma_free_slot(dspi->dma.dummy_param_slot);
 961free_clk:
 962        clk_disable(dspi->clk);
 963        clk_put(dspi->clk);
 964put_master:
 965        spi_master_put(master);
 966irq_free:
 967        free_irq(dspi->irq, dspi);
 968unmap_io:
 969        iounmap(dspi->base);
 970release_region:
 971        release_mem_region(dspi->pbase, resource_size(r));
 972free_master:
 973        kfree(master);
 974err:
 975        return ret;
 976}
 977
 978/**
 979 * davinci_spi_remove - remove function for SPI Master Controller
 980 * @pdev: platform_device structure which contains plateform specific data
 981 *
 982 * This function will do the reverse action of davinci_spi_probe function
 983 * It will free the IRQ and SPI controller's memory region.
 984 * It will also call spi_bitbang_stop to destroy the work queue which was
 985 * created by spi_bitbang_start.
 986 */
 987static int __devexit davinci_spi_remove(struct platform_device *pdev)
 988{
 989        struct davinci_spi *dspi;
 990        struct spi_master *master;
 991        struct resource *r;
 992
 993        master = dev_get_drvdata(&pdev->dev);
 994        dspi = spi_master_get_devdata(master);
 995
 996        spi_bitbang_stop(&dspi->bitbang);
 997
 998        clk_disable(dspi->clk);
 999        clk_put(dspi->clk);
1000        spi_master_put(master);
1001        free_irq(dspi->irq, dspi);
1002        iounmap(dspi->base);
1003        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004        release_mem_region(dspi->pbase, resource_size(r));
1005
1006        return 0;
1007}
1008
1009static struct platform_driver davinci_spi_driver = {
1010        .driver = {
1011                .name = "spi_davinci",
1012                .owner = THIS_MODULE,
1013        },
1014        .probe = davinci_spi_probe,
1015        .remove = __devexit_p(davinci_spi_remove),
1016};
1017module_platform_driver(davinci_spi_driver);
1018
1019MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1020MODULE_LICENSE("GPL");
1021
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.