linux/drivers/scsi/qlogicfas408.h
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   1/* to be used by qlogicfas and qlogic_cs */
   2#ifndef __QLOGICFAS408_H
   3#define __QLOGICFAS408_H
   4
   5/*----------------------------------------------------------------*/
   6/* Configuration */
   7
   8/* Set the following to max out the speed of the PIO PseudoDMA transfers,
   9   again, 0 tends to be slower, but more stable.  */
  10
  11#define QL_TURBO_PDMA 1
  12
  13/* This should be 1 to enable parity detection */
  14
  15#define QL_ENABLE_PARITY 1
  16
  17/* This will reset all devices when the driver is initialized (during bootup).
  18   The other linux drivers don't do this, but the DOS drivers do, and after
  19   using DOS or some kind of crash or lockup this will bring things back
  20   without requiring a cold boot.  It does take some time to recover from a
  21   reset, so it is slower, and I have seen timeouts so that devices weren't
  22   recognized when this was set. */
  23
  24#define QL_RESET_AT_START 0
  25
  26/* crystal frequency in megahertz (for offset 5 and 9)
  27   Please set this for your card.  Most Qlogic cards are 40 Mhz.  The
  28   Control Concepts ISA (not VLB) is 24 Mhz */
  29
  30#define XTALFREQ        40
  31
  32/**********/
  33/* DANGER! modify these at your own risk */
  34/* SLOWCABLE can usually be reset to zero if you have a clean setup and
  35   proper termination.  The rest are for synchronous transfers and other
  36   advanced features if your device can transfer faster than 5Mb/sec.
  37   If you are really curious, email me for a quick howto until I have
  38   something official */
  39/**********/
  40
  41/*****/
  42/* config register 1 (offset 8) options */
  43/* This needs to be set to 1 if your cabling is long or noisy */
  44#define SLOWCABLE 1
  45
  46/*****/
  47/* offset 0xc */
  48/* This will set fast (10Mhz) synchronous timing when set to 1
  49   For this to have an effect, FASTCLK must also be 1 */
  50#define FASTSCSI 0
  51
  52/* This when set to 1 will set a faster sync transfer rate */
  53#define FASTCLK 0       /*(XTALFREQ>25?1:0)*/
  54
  55/*****/
  56/* offset 6 */
  57/* This is the sync transfer divisor, XTALFREQ/X will be the maximum
  58   achievable data rate (assuming the rest of the system is capable
  59   and set properly) */
  60#define SYNCXFRPD 5     /*(XTALFREQ/5)*/
  61
  62/*****/
  63/* offset 7 */
  64/* This is the count of how many synchronous transfers can take place
  65        i.e. how many reqs can occur before an ack is given.
  66        The maximum value for this is 15, the upper bits can modify
  67        REQ/ACK assertion and deassertion during synchronous transfers
  68        If this is 0, the bus will only transfer asynchronously */
  69#define SYNCOFFST 0
  70/* for the curious, bits 7&6 control the deassertion delay in 1/2 cycles
  71        of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will
  72        cause the deassertion to be early by 1/2 clock.  Bits 5&4 control
  73        the assertion delay, also in 1/2 clocks (FASTCLK is ignored here). */
  74
  75/*----------------------------------------------------------------*/
  76
  77struct qlogicfas408_priv {
  78        int qbase;              /* Port */
  79        int qinitid;            /* initiator ID */
  80        int qabort;             /* Flag to cause an abort */
  81        int qlirq;              /* IRQ being used */
  82        int int_type;           /* type of irq, 2 for ISA board, 0 for PCMCIA */
  83        char qinfo[80];         /* description */
  84        struct scsi_cmnd *qlcmd;        /* current command being processed */
  85        struct Scsi_Host *shost;        /* pointer back to host */
  86        struct qlogicfas408_priv *next; /* next private struct */
  87};
  88
  89/* The qlogic card uses two register maps - These macros select which one */
  90#define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))
  91#define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd ))
  92
  93/* following is watchdog timeout in microseconds */
  94#define WATCHDOG 5000000
  95
  96/*----------------------------------------------------------------*/
  97/* the following will set the monitor border color (useful to find
  98   where something crashed or gets stuck at and as a simple profiler) */
  99
 100#define rtrc(i) {}
 101
 102#define get_priv_by_cmd(x) (struct qlogicfas408_priv *)&((x)->device->host->hostdata[0])
 103#define get_priv_by_host(x) (struct qlogicfas408_priv *)&((x)->hostdata[0])
 104
 105irqreturn_t qlogicfas408_ihandl(int irq, void *dev_id);
 106int qlogicfas408_queuecommand(struct Scsi_Host *h, struct scsi_cmnd * cmd);
 107int qlogicfas408_biosparam(struct scsi_device * disk,
 108                           struct block_device *dev,
 109                           sector_t capacity, int ip[]);
 110int qlogicfas408_abort(struct scsi_cmnd * cmd);
 111int qlogicfas408_bus_reset(struct scsi_cmnd * cmd);
 112const char *qlogicfas408_info(struct Scsi_Host *host);
 113int qlogicfas408_get_chip_type(int qbase, int int_type);
 114void qlogicfas408_setup(int qbase, int id, int int_type);
 115int qlogicfas408_detect(int qbase, int int_type);
 116void qlogicfas408_disable_ints(struct qlogicfas408_priv *priv);
 117#endif  /* __QLOGICFAS408_H */
 118
 119
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