linux/drivers/scsi/advansys.c
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   1#define DRV_NAME "advansys"
   2#define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
   3
   4/*
   5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   6 *
   7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
   8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  10 * All Rights Reserved.
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License as published by
  14 * the Free Software Foundation; either version 2 of the License, or
  15 * (at your option) any later version.
  16 */
  17
  18/*
  19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  20 * changed its name to ConnectCom Solutions, Inc.
  21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/string.h>
  26#include <linux/kernel.h>
  27#include <linux/types.h>
  28#include <linux/ioport.h>
  29#include <linux/interrupt.h>
  30#include <linux/delay.h>
  31#include <linux/slab.h>
  32#include <linux/mm.h>
  33#include <linux/proc_fs.h>
  34#include <linux/init.h>
  35#include <linux/blkdev.h>
  36#include <linux/isa.h>
  37#include <linux/eisa.h>
  38#include <linux/pci.h>
  39#include <linux/spinlock.h>
  40#include <linux/dma-mapping.h>
  41#include <linux/firmware.h>
  42
  43#include <asm/io.h>
  44#include <asm/dma.h>
  45
  46#include <scsi/scsi_cmnd.h>
  47#include <scsi/scsi_device.h>
  48#include <scsi/scsi_tcq.h>
  49#include <scsi/scsi.h>
  50#include <scsi/scsi_host.h>
  51
  52/* FIXME:
  53 *
  54 *  1. Although all of the necessary command mapping places have the
  55 *     appropriate dma_map.. APIs, the driver still processes its internal
  56 *     queue using bus_to_virt() and virt_to_bus() which are illegal under
  57 *     the API.  The entire queue processing structure will need to be
  58 *     altered to fix this.
  59 *  2. Need to add memory mapping workaround. Test the memory mapping.
  60 *     If it doesn't work revert to I/O port access. Can a test be done
  61 *     safely?
  62 *  3. Handle an interrupt not working. Keep an interrupt counter in
  63 *     the interrupt handler. In the timeout function if the interrupt
  64 *     has not occurred then print a message and run in polled mode.
  65 *  4. Need to add support for target mode commands, cf. CAM XPT.
  66 *  5. check DMA mapping functions for failure
  67 *  6. Use scsi_transport_spi
  68 *  7. advansys_info is not safe against multiple simultaneous callers
  69 *  8. Add module_param to override ISA/VLB ioport array
  70 */
  71#warning this driver is still not properly converted to the DMA API
  72
  73/* Enable driver /proc statistics. */
  74#define ADVANSYS_STATS
  75
  76/* Enable driver tracing. */
  77#undef ADVANSYS_DEBUG
  78
  79/*
  80 * Portable Data Types
  81 *
  82 * Any instance where a 32-bit long or pointer type is assumed
  83 * for precision or HW defined structures, the following define
  84 * types must be used. In Linux the char, short, and int types
  85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
  86 * and long types are 64 bits on Alpha and UltraSPARC.
  87 */
  88#define ASC_PADDR __u32         /* Physical/Bus address data type. */
  89#define ASC_VADDR __u32         /* Virtual address data type. */
  90#define ASC_DCNT  __u32         /* Unsigned Data count type. */
  91#define ASC_SDCNT __s32         /* Signed Data count type. */
  92
  93typedef unsigned char uchar;
  94
  95#ifndef TRUE
  96#define TRUE     (1)
  97#endif
  98#ifndef FALSE
  99#define FALSE    (0)
 100#endif
 101
 102#define ERR      (-1)
 103#define UW_ERR   (uint)(0xFFFF)
 104#define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 105
 106#define PCI_VENDOR_ID_ASP               0x10cd
 107#define PCI_DEVICE_ID_ASP_1200A         0x1100
 108#define PCI_DEVICE_ID_ASP_ABP940        0x1200
 109#define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 110#define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 111#define PCI_DEVICE_ID_38C0800_REV1      0x2500
 112#define PCI_DEVICE_ID_38C1600_REV1      0x2700
 113
 114/*
 115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
 116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
 117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
 118 * SRB structure.
 119 */
 120#define CC_VERY_LONG_SG_LIST 0
 121#define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
 122
 123#define PortAddr                 unsigned int   /* port address size  */
 124#define inp(port)                inb(port)
 125#define outp(port, byte)         outb((byte), (port))
 126
 127#define inpw(port)               inw(port)
 128#define outpw(port, word)        outw((word), (port))
 129
 130#define ASC_MAX_SG_QUEUE    7
 131#define ASC_MAX_SG_LIST     255
 132
 133#define ASC_CS_TYPE  unsigned short
 134
 135#define ASC_IS_ISA          (0x0001)
 136#define ASC_IS_ISAPNP       (0x0081)
 137#define ASC_IS_EISA         (0x0002)
 138#define ASC_IS_PCI          (0x0004)
 139#define ASC_IS_PCI_ULTRA    (0x0104)
 140#define ASC_IS_PCMCIA       (0x0008)
 141#define ASC_IS_MCA          (0x0020)
 142#define ASC_IS_VL           (0x0040)
 143#define ASC_IS_WIDESCSI_16  (0x0100)
 144#define ASC_IS_WIDESCSI_32  (0x0200)
 145#define ASC_IS_BIG_ENDIAN   (0x8000)
 146
 147#define ASC_CHIP_MIN_VER_VL      (0x01)
 148#define ASC_CHIP_MAX_VER_VL      (0x07)
 149#define ASC_CHIP_MIN_VER_PCI     (0x09)
 150#define ASC_CHIP_MAX_VER_PCI     (0x0F)
 151#define ASC_CHIP_VER_PCI_BIT     (0x08)
 152#define ASC_CHIP_MIN_VER_ISA     (0x11)
 153#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
 154#define ASC_CHIP_MAX_VER_ISA     (0x27)
 155#define ASC_CHIP_VER_ISA_BIT     (0x30)
 156#define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
 157#define ASC_CHIP_VER_ASYN_BUG    (0x21)
 158#define ASC_CHIP_VER_PCI             0x08
 159#define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 160#define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 161#define ASC_CHIP_MIN_VER_EISA (0x41)
 162#define ASC_CHIP_MAX_VER_EISA (0x47)
 163#define ASC_CHIP_VER_EISA_BIT (0x40)
 164#define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 165#define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 166#define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 167#define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
 168
 169#define ASC_SCSI_ID_BITS  3
 170#define ASC_SCSI_TIX_TYPE     uchar
 171#define ASC_ALL_DEVICE_BIT_SET  0xFF
 172#define ASC_SCSI_BIT_ID_TYPE  uchar
 173#define ASC_MAX_TID       7
 174#define ASC_MAX_LUN       7
 175#define ASC_SCSI_WIDTH_BIT_SET  0xFF
 176#define ASC_MAX_SENSE_LEN   32
 177#define ASC_MIN_SENSE_LEN   14
 178#define ASC_SCSI_RESET_HOLD_TIME_US  60
 179
 180/*
 181 * Narrow boards only support 12-byte commands, while wide boards
 182 * extend to 16-byte commands.
 183 */
 184#define ASC_MAX_CDB_LEN     12
 185#define ADV_MAX_CDB_LEN     16
 186
 187#define MS_SDTR_LEN    0x03
 188#define MS_WDTR_LEN    0x02
 189
 190#define ASC_SG_LIST_PER_Q   7
 191#define QS_FREE        0x00
 192#define QS_READY       0x01
 193#define QS_DISC1       0x02
 194#define QS_DISC2       0x04
 195#define QS_BUSY        0x08
 196#define QS_ABORTED     0x40
 197#define QS_DONE        0x80
 198#define QC_NO_CALLBACK   0x01
 199#define QC_SG_SWAP_QUEUE 0x02
 200#define QC_SG_HEAD       0x04
 201#define QC_DATA_IN       0x08
 202#define QC_DATA_OUT      0x10
 203#define QC_URGENT        0x20
 204#define QC_MSG_OUT       0x40
 205#define QC_REQ_SENSE     0x80
 206#define QCSG_SG_XFER_LIST  0x02
 207#define QCSG_SG_XFER_MORE  0x04
 208#define QCSG_SG_XFER_END   0x08
 209#define QD_IN_PROGRESS       0x00
 210#define QD_NO_ERROR          0x01
 211#define QD_ABORTED_BY_HOST   0x02
 212#define QD_WITH_ERROR        0x04
 213#define QD_INVALID_REQUEST   0x80
 214#define QD_INVALID_HOST_NUM  0x81
 215#define QD_INVALID_DEVICE    0x82
 216#define QD_ERR_INTERNAL      0xFF
 217#define QHSTA_NO_ERROR               0x00
 218#define QHSTA_M_SEL_TIMEOUT          0x11
 219#define QHSTA_M_DATA_OVER_RUN        0x12
 220#define QHSTA_M_DATA_UNDER_RUN       0x12
 221#define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 222#define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 223#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 224#define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 225#define QHSTA_D_HOST_ABORT_FAILED       0x23
 226#define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 227#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 228#define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 229#define QHSTA_M_WTM_TIMEOUT         0x41
 230#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 231#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 232#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 233#define QHSTA_M_TARGET_STATUS_BUSY  0x45
 234#define QHSTA_M_BAD_TAG_CODE        0x46
 235#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 236#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 237#define QHSTA_D_LRAM_CMP_ERROR        0x81
 238#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 239#define ASC_FLAG_SCSIQ_REQ        0x01
 240#define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 241#define ASC_FLAG_BIOS_ASYNC_IO    0x04
 242#define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 243#define ASC_FLAG_WIN16            0x10
 244#define ASC_FLAG_WIN32            0x20
 245#define ASC_FLAG_ISA_OVER_16MB    0x40
 246#define ASC_FLAG_DOS_VM_CALLBACK  0x80
 247#define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 248#define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 249#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 250#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 251#define ASC_SCSIQ_CPY_BEG              4
 252#define ASC_SCSIQ_SGHD_CPY_BEG         2
 253#define ASC_SCSIQ_B_FWD                0
 254#define ASC_SCSIQ_B_BWD                1
 255#define ASC_SCSIQ_B_STATUS             2
 256#define ASC_SCSIQ_B_QNO                3
 257#define ASC_SCSIQ_B_CNTL               4
 258#define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 259#define ASC_SCSIQ_D_DATA_ADDR          8
 260#define ASC_SCSIQ_D_DATA_CNT          12
 261#define ASC_SCSIQ_B_SENSE_LEN         20
 262#define ASC_SCSIQ_DONE_INFO_BEG       22
 263#define ASC_SCSIQ_D_SRBPTR            22
 264#define ASC_SCSIQ_B_TARGET_IX         26
 265#define ASC_SCSIQ_B_CDB_LEN           28
 266#define ASC_SCSIQ_B_TAG_CODE          29
 267#define ASC_SCSIQ_W_VM_ID             30
 268#define ASC_SCSIQ_DONE_STATUS         32
 269#define ASC_SCSIQ_HOST_STATUS         33
 270#define ASC_SCSIQ_SCSI_STATUS         34
 271#define ASC_SCSIQ_CDB_BEG             36
 272#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 273#define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 274#define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 275#define ASC_SCSIQ_B_SG_WK_QP          49
 276#define ASC_SCSIQ_B_SG_WK_IX          50
 277#define ASC_SCSIQ_W_ALT_DC1           52
 278#define ASC_SCSIQ_B_LIST_CNT          6
 279#define ASC_SCSIQ_B_CUR_LIST_CNT      7
 280#define ASC_SGQ_B_SG_CNTL             4
 281#define ASC_SGQ_B_SG_HEAD_QP          5
 282#define ASC_SGQ_B_SG_LIST_CNT         6
 283#define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 284#define ASC_SGQ_LIST_BEG              8
 285#define ASC_DEF_SCSI1_QNG    4
 286#define ASC_MAX_SCSI1_QNG    4
 287#define ASC_DEF_SCSI2_QNG    16
 288#define ASC_MAX_SCSI2_QNG    32
 289#define ASC_TAG_CODE_MASK    0x23
 290#define ASC_STOP_REQ_RISC_STOP      0x01
 291#define ASC_STOP_ACK_RISC_STOP      0x03
 292#define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 293#define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 294#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 295#define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 296#define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 297#define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 298#define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 299#define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 300#define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 301#define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 302
 303typedef struct asc_scsiq_1 {
 304        uchar status;
 305        uchar q_no;
 306        uchar cntl;
 307        uchar sg_queue_cnt;
 308        uchar target_id;
 309        uchar target_lun;
 310        ASC_PADDR data_addr;
 311        ASC_DCNT data_cnt;
 312        ASC_PADDR sense_addr;
 313        uchar sense_len;
 314        uchar extra_bytes;
 315} ASC_SCSIQ_1;
 316
 317typedef struct asc_scsiq_2 {
 318        ASC_VADDR srb_ptr;
 319        uchar target_ix;
 320        uchar flag;
 321        uchar cdb_len;
 322        uchar tag_code;
 323        ushort vm_id;
 324} ASC_SCSIQ_2;
 325
 326typedef struct asc_scsiq_3 {
 327        uchar done_stat;
 328        uchar host_stat;
 329        uchar scsi_stat;
 330        uchar scsi_msg;
 331} ASC_SCSIQ_3;
 332
 333typedef struct asc_scsiq_4 {
 334        uchar cdb[ASC_MAX_CDB_LEN];
 335        uchar y_first_sg_list_qp;
 336        uchar y_working_sg_qp;
 337        uchar y_working_sg_ix;
 338        uchar y_res;
 339        ushort x_req_count;
 340        ushort x_reconnect_rtn;
 341        ASC_PADDR x_saved_data_addr;
 342        ASC_DCNT x_saved_data_cnt;
 343} ASC_SCSIQ_4;
 344
 345typedef struct asc_q_done_info {
 346        ASC_SCSIQ_2 d2;
 347        ASC_SCSIQ_3 d3;
 348        uchar q_status;
 349        uchar q_no;
 350        uchar cntl;
 351        uchar sense_len;
 352        uchar extra_bytes;
 353        uchar res;
 354        ASC_DCNT remain_bytes;
 355} ASC_QDONE_INFO;
 356
 357typedef struct asc_sg_list {
 358        ASC_PADDR addr;
 359        ASC_DCNT bytes;
 360} ASC_SG_LIST;
 361
 362typedef struct asc_sg_head {
 363        ushort entry_cnt;
 364        ushort queue_cnt;
 365        ushort entry_to_copy;
 366        ushort res;
 367        ASC_SG_LIST sg_list[0];
 368} ASC_SG_HEAD;
 369
 370typedef struct asc_scsi_q {
 371        ASC_SCSIQ_1 q1;
 372        ASC_SCSIQ_2 q2;
 373        uchar *cdbptr;
 374        ASC_SG_HEAD *sg_head;
 375        ushort remain_sg_entry_cnt;
 376        ushort next_sg_index;
 377} ASC_SCSI_Q;
 378
 379typedef struct asc_scsi_req_q {
 380        ASC_SCSIQ_1 r1;
 381        ASC_SCSIQ_2 r2;
 382        uchar *cdbptr;
 383        ASC_SG_HEAD *sg_head;
 384        uchar *sense_ptr;
 385        ASC_SCSIQ_3 r3;
 386        uchar cdb[ASC_MAX_CDB_LEN];
 387        uchar sense[ASC_MIN_SENSE_LEN];
 388} ASC_SCSI_REQ_Q;
 389
 390typedef struct asc_scsi_bios_req_q {
 391        ASC_SCSIQ_1 r1;
 392        ASC_SCSIQ_2 r2;
 393        uchar *cdbptr;
 394        ASC_SG_HEAD *sg_head;
 395        uchar *sense_ptr;
 396        ASC_SCSIQ_3 r3;
 397        uchar cdb[ASC_MAX_CDB_LEN];
 398        uchar sense[ASC_MIN_SENSE_LEN];
 399} ASC_SCSI_BIOS_REQ_Q;
 400
 401typedef struct asc_risc_q {
 402        uchar fwd;
 403        uchar bwd;
 404        ASC_SCSIQ_1 i1;
 405        ASC_SCSIQ_2 i2;
 406        ASC_SCSIQ_3 i3;
 407        ASC_SCSIQ_4 i4;
 408} ASC_RISC_Q;
 409
 410typedef struct asc_sg_list_q {
 411        uchar seq_no;
 412        uchar q_no;
 413        uchar cntl;
 414        uchar sg_head_qp;
 415        uchar sg_list_cnt;
 416        uchar sg_cur_list_cnt;
 417} ASC_SG_LIST_Q;
 418
 419typedef struct asc_risc_sg_list_q {
 420        uchar fwd;
 421        uchar bwd;
 422        ASC_SG_LIST_Q sg;
 423        ASC_SG_LIST sg_list[7];
 424} ASC_RISC_SG_LIST_Q;
 425
 426#define ASCQ_ERR_Q_STATUS             0x0D
 427#define ASCQ_ERR_CUR_QNG              0x17
 428#define ASCQ_ERR_SG_Q_LINKS           0x18
 429#define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 430#define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 431#define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 432
 433/*
 434 * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 435 */
 436#define ASC_WARN_NO_ERROR             0x0000
 437#define ASC_WARN_IO_PORT_ROTATE       0x0001
 438#define ASC_WARN_EEPROM_CHKSUM        0x0002
 439#define ASC_WARN_IRQ_MODIFIED         0x0004
 440#define ASC_WARN_AUTO_CONFIG          0x0008
 441#define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 442#define ASC_WARN_EEPROM_RECOVER       0x0020
 443#define ASC_WARN_CFG_MSW_RECOVER      0x0040
 444
 445/*
 446 * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 447 */
 448#define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 449#define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 450#define ASC_IERR_SET_PC_ADDR            0x0004
 451#define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 452#define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 453#define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 454#define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 455#define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 456#define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 457#define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 458#define ASC_IERR_NO_BUS_TYPE            0x0400
 459#define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 460#define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 461#define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 462
 463#define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 464#define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 465#define ASC_MIN_FREE_Q        (0x02)
 466#define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 467#define ASC_MAX_TOTAL_QNG 240
 468#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 469#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 470#define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 471#define ASC_MAX_INRAM_TAG_QNG   16
 472#define ASC_IOADR_GAP   0x10
 473#define ASC_SYN_MAX_OFFSET         0x0F
 474#define ASC_DEF_SDTR_OFFSET        0x0F
 475#define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 476#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 477
 478/* The narrow chip only supports a limited selection of transfer rates.
 479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
 480 * is Ultra-capable or not.  These tables let us convert from one to the other.
 481 */
 482static const unsigned char asc_syn_xfer_period[8] = {
 483        25, 30, 35, 40, 50, 60, 70, 85
 484};
 485
 486static const unsigned char asc_syn_ultra_xfer_period[16] = {
 487        12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 488};
 489
 490typedef struct ext_msg {
 491        uchar msg_type;
 492        uchar msg_len;
 493        uchar msg_req;
 494        union {
 495                struct {
 496                        uchar sdtr_xfer_period;
 497                        uchar sdtr_req_ack_offset;
 498                } sdtr;
 499                struct {
 500                        uchar wdtr_width;
 501                } wdtr;
 502                struct {
 503                        uchar mdp_b3;
 504                        uchar mdp_b2;
 505                        uchar mdp_b1;
 506                        uchar mdp_b0;
 507                } mdp;
 508        } u_ext_msg;
 509        uchar res;
 510} EXT_MSG;
 511
 512#define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 513#define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 514#define wdtr_width      u_ext_msg.wdtr.wdtr_width
 515#define mdp_b3          u_ext_msg.mdp_b3
 516#define mdp_b2          u_ext_msg.mdp_b2
 517#define mdp_b1          u_ext_msg.mdp_b1
 518#define mdp_b0          u_ext_msg.mdp_b0
 519
 520typedef struct asc_dvc_cfg {
 521        ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 522        ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 523        ASC_SCSI_BIT_ID_TYPE disc_enable;
 524        ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 525        uchar chip_scsi_id;
 526        uchar isa_dma_speed;
 527        uchar isa_dma_channel;
 528        uchar chip_version;
 529        ushort mcode_date;
 530        ushort mcode_version;
 531        uchar max_tag_qng[ASC_MAX_TID + 1];
 532        uchar sdtr_period_offset[ASC_MAX_TID + 1];
 533        uchar adapter_info[6];
 534} ASC_DVC_CFG;
 535
 536#define ASC_DEF_DVC_CNTL       0xFFFF
 537#define ASC_DEF_CHIP_SCSI_ID   7
 538#define ASC_DEF_ISA_DMA_SPEED  4
 539#define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 540#define ASC_INIT_STATE_END_GET_CFG   0x0002
 541#define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 542#define ASC_INIT_STATE_END_SET_CFG   0x0008
 543#define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 544#define ASC_INIT_STATE_END_LOAD_MC   0x0020
 545#define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 546#define ASC_INIT_STATE_END_INQUIRY   0x0080
 547#define ASC_INIT_RESET_SCSI_DONE     0x0100
 548#define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 549#define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 550#define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 551#define ASC_MIN_TAGGED_CMD  7
 552#define ASC_MAX_SCSI_RESET_WAIT      30
 553#define ASC_OVERRUN_BSIZE               64
 554
 555struct asc_dvc_var;             /* Forward Declaration. */
 556
 557typedef struct asc_dvc_var {
 558        PortAddr iop_base;
 559        ushort err_code;
 560        ushort dvc_cntl;
 561        ushort bug_fix_cntl;
 562        ushort bus_type;
 563        ASC_SCSI_BIT_ID_TYPE init_sdtr;
 564        ASC_SCSI_BIT_ID_TYPE sdtr_done;
 565        ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 566        ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 567        ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 568        ASC_SCSI_BIT_ID_TYPE start_motor;
 569        uchar *overrun_buf;
 570        dma_addr_t overrun_dma;
 571        uchar scsi_reset_wait;
 572        uchar chip_no;
 573        char is_in_int;
 574        uchar max_total_qng;
 575        uchar cur_total_qng;
 576        uchar in_critical_cnt;
 577        uchar last_q_shortage;
 578        ushort init_state;
 579        uchar cur_dvc_qng[ASC_MAX_TID + 1];
 580        uchar max_dvc_qng[ASC_MAX_TID + 1];
 581        ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 582        ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 583        const uchar *sdtr_period_tbl;
 584        ASC_DVC_CFG *cfg;
 585        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 586        char redo_scam;
 587        ushort res2;
 588        uchar dos_int13_table[ASC_MAX_TID + 1];
 589        ASC_DCNT max_dma_count;
 590        ASC_SCSI_BIT_ID_TYPE no_scam;
 591        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 592        uchar min_sdtr_index;
 593        uchar max_sdtr_index;
 594        struct asc_board *drv_ptr;
 595        int ptr_map_count;
 596        void **ptr_map;
 597        ASC_DCNT uc_break;
 598} ASC_DVC_VAR;
 599
 600typedef struct asc_dvc_inq_info {
 601        uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 602} ASC_DVC_INQ_INFO;
 603
 604typedef struct asc_cap_info {
 605        ASC_DCNT lba;
 606        ASC_DCNT blk_size;
 607} ASC_CAP_INFO;
 608
 609typedef struct asc_cap_info_array {
 610        ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 611} ASC_CAP_INFO_ARRAY;
 612
 613#define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 614#define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 615#define ASC_CNTL_INITIATOR         (ushort)0x0001
 616#define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 617#define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 618#define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 619#define ASC_CNTL_NO_SCAM           (ushort)0x0010
 620#define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 621#define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 622#define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 623#define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 624#define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 625#define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 626#define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 627#define ASC_CNTL_BURST_MODE        (ushort)0x2000
 628#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 629#define ASC_EEP_DVC_CFG_BEG_VL    2
 630#define ASC_EEP_MAX_DVC_ADDR_VL   15
 631#define ASC_EEP_DVC_CFG_BEG      32
 632#define ASC_EEP_MAX_DVC_ADDR     45
 633#define ASC_EEP_MAX_RETRY        20
 634
 635/*
 636 * These macros keep the chip SCSI id and ISA DMA speed
 637 * bitfields in board order. C bitfields aren't portable
 638 * between big and little-endian platforms so they are
 639 * not used.
 640 */
 641
 642#define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 643#define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 644#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 645   ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 646#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 647   ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 648
 649typedef struct asceep_config {
 650        ushort cfg_lsw;
 651        ushort cfg_msw;
 652        uchar init_sdtr;
 653        uchar disc_enable;
 654        uchar use_cmd_qng;
 655        uchar start_motor;
 656        uchar max_total_qng;
 657        uchar max_tag_qng;
 658        uchar bios_scan;
 659        uchar power_up_wait;
 660        uchar no_scam;
 661        uchar id_speed;         /* low order 4 bits is chip scsi id */
 662        /* high order 4 bits is isa dma speed */
 663        uchar dos_int13_table[ASC_MAX_TID + 1];
 664        uchar adapter_info[6];
 665        ushort cntl;
 666        ushort chksum;
 667} ASCEEP_CONFIG;
 668
 669#define ASC_EEP_CMD_READ          0x80
 670#define ASC_EEP_CMD_WRITE         0x40
 671#define ASC_EEP_CMD_WRITE_ABLE    0x30
 672#define ASC_EEP_CMD_WRITE_DISABLE 0x00
 673#define ASCV_MSGOUT_BEG         0x0000
 674#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 675#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 676#define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 677#define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 678#define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 679#define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 680#define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 681#define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 682#define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 683#define ASCV_BREAK_ADDR           (ushort)0x0028
 684#define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 685#define ASCV_BREAK_CONTROL        (ushort)0x002C
 686#define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 687
 688#define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 689#define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 690#define ASCV_MCODE_SIZE_W     (ushort)0x0034
 691#define ASCV_STOP_CODE_B      (ushort)0x0036
 692#define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 693#define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 694#define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 695#define ASCV_HALTCODE_W       (ushort)0x0040
 696#define ASCV_CHKSUM_W         (ushort)0x0042
 697#define ASCV_MC_DATE_W        (ushort)0x0044
 698#define ASCV_MC_VER_W         (ushort)0x0046
 699#define ASCV_NEXTRDY_B        (ushort)0x0048
 700#define ASCV_DONENEXT_B       (ushort)0x0049
 701#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 702#define ASCV_SCSIBUSY_B       (ushort)0x004B
 703#define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 704#define ASCV_CURCDB_B         (ushort)0x004D
 705#define ASCV_RCLUN_B          (ushort)0x004E
 706#define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 707#define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 708#define ASCV_DISC_ENABLE_B    (ushort)0x0052
 709#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 710#define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 711#define ASCV_MCODE_CNTL_B     (ushort)0x0056
 712#define ASCV_NULL_TARGET_B    (ushort)0x0057
 713#define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 714#define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 715#define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 716#define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 717#define ASCV_HOST_FLAG_B      (ushort)0x005D
 718#define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 719#define ASCV_VER_SERIAL_B     (ushort)0x0065
 720#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 721#define ASCV_WTM_FLAG_B       (ushort)0x0068
 722#define ASCV_RISC_FLAG_B      (ushort)0x006A
 723#define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 724#define ASC_HOST_FLAG_IN_ISR        0x01
 725#define ASC_HOST_FLAG_ACK_INT       0x02
 726#define ASC_RISC_FLAG_GEN_INT      0x01
 727#define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 728#define IOP_CTRL         (0x0F)
 729#define IOP_STATUS       (0x0E)
 730#define IOP_INT_ACK      IOP_STATUS
 731#define IOP_REG_IFC      (0x0D)
 732#define IOP_SYN_OFFSET    (0x0B)
 733#define IOP_EXTRA_CONTROL (0x0D)
 734#define IOP_REG_PC        (0x0C)
 735#define IOP_RAM_ADDR      (0x0A)
 736#define IOP_RAM_DATA      (0x08)
 737#define IOP_EEP_DATA      (0x06)
 738#define IOP_EEP_CMD       (0x07)
 739#define IOP_VERSION       (0x03)
 740#define IOP_CONFIG_HIGH   (0x04)
 741#define IOP_CONFIG_LOW    (0x02)
 742#define IOP_SIG_BYTE      (0x01)
 743#define IOP_SIG_WORD      (0x00)
 744#define IOP_REG_DC1      (0x0E)
 745#define IOP_REG_DC0      (0x0C)
 746#define IOP_REG_SB       (0x0B)
 747#define IOP_REG_DA1      (0x0A)
 748#define IOP_REG_DA0      (0x08)
 749#define IOP_REG_SC       (0x09)
 750#define IOP_DMA_SPEED    (0x07)
 751#define IOP_REG_FLAG     (0x07)
 752#define IOP_FIFO_H       (0x06)
 753#define IOP_FIFO_L       (0x04)
 754#define IOP_REG_ID       (0x05)
 755#define IOP_REG_QP       (0x03)
 756#define IOP_REG_IH       (0x02)
 757#define IOP_REG_IX       (0x01)
 758#define IOP_REG_AX       (0x00)
 759#define IFC_REG_LOCK      (0x00)
 760#define IFC_REG_UNLOCK    (0x09)
 761#define IFC_WR_EN_FILTER  (0x10)
 762#define IFC_RD_NO_EEPROM  (0x10)
 763#define IFC_SLEW_RATE     (0x20)
 764#define IFC_ACT_NEG       (0x40)
 765#define IFC_INP_FILTER    (0x80)
 766#define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 767#define SC_SEL   (uchar)(0x80)
 768#define SC_BSY   (uchar)(0x40)
 769#define SC_ACK   (uchar)(0x20)
 770#define SC_REQ   (uchar)(0x10)
 771#define SC_ATN   (uchar)(0x08)
 772#define SC_IO    (uchar)(0x04)
 773#define SC_CD    (uchar)(0x02)
 774#define SC_MSG   (uchar)(0x01)
 775#define SEC_SCSI_CTL         (uchar)(0x80)
 776#define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 777#define SEC_SLEW_RATE        (uchar)(0x20)
 778#define SEC_ENABLE_FILTER    (uchar)(0x10)
 779#define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 780#define ASC_HALT_CHK_CONDITION (ushort)0x8100
 781#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 782#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 783#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 784#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 785#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 786#define ASC_MAX_QNO        0xF8
 787#define ASC_DATA_SEC_BEG   (ushort)0x0080
 788#define ASC_DATA_SEC_END   (ushort)0x0080
 789#define ASC_CODE_SEC_BEG   (ushort)0x0080
 790#define ASC_CODE_SEC_END   (ushort)0x0080
 791#define ASC_QADR_BEG       (0x4000)
 792#define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 793#define ASC_QADR_END       (ushort)0x7FFF
 794#define ASC_QLAST_ADR      (ushort)0x7FC0
 795#define ASC_QBLK_SIZE      0x40
 796#define ASC_BIOS_DATA_QBEG 0xF8
 797#define ASC_MIN_ACTIVE_QNO 0x01
 798#define ASC_QLINK_END      0xFF
 799#define ASC_EEPROM_WORDS   0x10
 800#define ASC_MAX_MGS_LEN    0x10
 801#define ASC_BIOS_ADDR_DEF  0xDC00
 802#define ASC_BIOS_SIZE      0x3800
 803#define ASC_BIOS_RAM_OFF   0x3800
 804#define ASC_BIOS_RAM_SIZE  0x800
 805#define ASC_BIOS_MIN_ADDR  0xC000
 806#define ASC_BIOS_MAX_ADDR  0xEC00
 807#define ASC_BIOS_BANK_SIZE 0x0400
 808#define ASC_MCODE_START_ADDR  0x0080
 809#define ASC_CFG0_HOST_INT_ON    0x0020
 810#define ASC_CFG0_BIOS_ON        0x0040
 811#define ASC_CFG0_VERA_BURST_ON  0x0080
 812#define ASC_CFG0_SCSI_PARITY_ON 0x0800
 813#define ASC_CFG1_SCSI_TARGET_ON 0x0080
 814#define ASC_CFG1_LRAM_8BITS_ON  0x0800
 815#define ASC_CFG_MSW_CLR_MASK    0x3080
 816#define CSW_TEST1             (ASC_CS_TYPE)0x8000
 817#define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 818#define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 819#define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 820#define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 821#define CSW_TEST2             (ASC_CS_TYPE)0x0400
 822#define CSW_TEST3             (ASC_CS_TYPE)0x0200
 823#define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 824#define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 825#define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 826#define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 827#define CSW_HALTED            (ASC_CS_TYPE)0x0010
 828#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 829#define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 830#define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 831#define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 832#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 833#define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 834#define CIW_TEST1        (ASC_CS_TYPE)0x0200
 835#define CIW_TEST2        (ASC_CS_TYPE)0x0400
 836#define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 837#define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 838#define CC_CHIP_RESET   (uchar)0x80
 839#define CC_SCSI_RESET   (uchar)0x40
 840#define CC_HALT         (uchar)0x20
 841#define CC_SINGLE_STEP  (uchar)0x10
 842#define CC_DMA_ABLE     (uchar)0x08
 843#define CC_TEST         (uchar)0x04
 844#define CC_BANK_ONE     (uchar)0x02
 845#define CC_DIAG         (uchar)0x01
 846#define ASC_1000_ID0W      0x04C1
 847#define ASC_1000_ID0W_FIX  0x00C1
 848#define ASC_1000_ID1B      0x25
 849#define ASC_EISA_REV_IOP_MASK  (0x0C83)
 850#define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 851#define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 852#define INS_HALTINT        (ushort)0x6281
 853#define INS_HALT           (ushort)0x6280
 854#define INS_SINT           (ushort)0x6200
 855#define INS_RFLAG_WTM      (ushort)0x7380
 856#define ASC_MC_SAVE_CODE_WSIZE  0x500
 857#define ASC_MC_SAVE_DATA_WSIZE  0x40
 858
 859typedef struct asc_mc_saved {
 860        ushort data[ASC_MC_SAVE_DATA_WSIZE];
 861        ushort code[ASC_MC_SAVE_CODE_WSIZE];
 862} ASC_MC_SAVED;
 863
 864#define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 865#define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 866#define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 867#define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 868#define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 869#define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 870#define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 871#define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 872#define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 873#define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 874#define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 875#define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 876#define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 877#define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 878#define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 879#define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 880#define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 881#define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 882#define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 883#define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 884#define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 885#define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 886#define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 887#define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 888#define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 889#define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 890#define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 891#define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 892#define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 893#define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 894#define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 895#define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 896#define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 897#define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 898#define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 899#define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 900#define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 901#define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 902#define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 903#define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 904#define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 905#define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 906#define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 907#define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 908#define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 909#define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 910#define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 911#define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 912#define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 913#define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 914#define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 915#define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 916#define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 917#define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 918#define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 919#define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 920#define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 921#define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 922#define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 923#define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 924#define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 925#define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 926#define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 927#define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 928#define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 929#define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 930#define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 931
 932/*
 933 * Portable Data Types
 934 *
 935 * Any instance where a 32-bit long or pointer type is assumed
 936 * for precision or HW defined structures, the following define
 937 * types must be used. In Linux the char, short, and int types
 938 * are all consistent at 8, 16, and 32 bits respectively. Pointers
 939 * and long types are 64 bits on Alpha and UltraSPARC.
 940 */
 941#define ADV_PADDR __u32         /* Physical address data type. */
 942#define ADV_VADDR __u32         /* Virtual address data type. */
 943#define ADV_DCNT  __u32         /* Unsigned Data count type. */
 944#define ADV_SDCNT __s32         /* Signed Data count type. */
 945
 946/*
 947 * These macros are used to convert a virtual address to a
 948 * 32-bit value. This currently can be used on Linux Alpha
 949 * which uses 64-bit virtual address but a 32-bit bus address.
 950 * This is likely to break in the future, but doing this now
 951 * will give us time to change the HW and FW to handle 64-bit
 952 * addresses.
 953 */
 954#define ADV_VADDR_TO_U32   virt_to_bus
 955#define ADV_U32_TO_VADDR   bus_to_virt
 956
 957#define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 958
 959/*
 960 * Define Adv Library required memory access macros.
 961 */
 962#define ADV_MEM_READB(addr) readb(addr)
 963#define ADV_MEM_READW(addr) readw(addr)
 964#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 965#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 966#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 967
 968#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
 969
 970/*
 971 * Define total number of simultaneous maximum element scatter-gather
 972 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 973 * maximum number of outstanding commands per wide host adapter. Each
 974 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 975 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 976 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 977 * structures or 255 scatter-gather elements.
 978 */
 979#define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 980
 981/*
 982 * Define maximum number of scatter-gather elements per request.
 983 */
 984#define ADV_MAX_SG_LIST         255
 985#define NO_OF_SG_PER_BLOCK              15
 986
 987#define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 988#define ADV_EEP_DVC_CFG_END             (0x15)
 989#define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 990#define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 991
 992#define ADV_EEP_DELAY_MS                100
 993
 994#define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
 995#define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
 996/*
 997 * For the ASC3550 Bit 13 is Termination Polarity control bit.
 998 * For later ICs Bit 13 controls whether the CIS (Card Information
 999 * Service Section) is loaded from EEPROM.
1000 */
1001#define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1002#define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1003/*
1004 * ASC38C1600 Bit 11
1005 *
1006 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008 * Function 0 will specify INT B.
1009 *
1010 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012 * Function 1 will specify INT A.
1013 */
1014#define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1015
1016typedef struct adveep_3550_config {
1017        /* Word Offset, Description */
1018
1019        ushort cfg_lsw;         /* 00 power up initialization */
1020        /*  bit 13 set - Term Polarity Control */
1021        /*  bit 14 set - BIOS Enable */
1022        /*  bit 15 set - Big Endian Mode */
1023        ushort cfg_msw;         /* 01 unused      */
1024        ushort disc_enable;     /* 02 disconnect enable */
1025        ushort wdtr_able;       /* 03 Wide DTR able */
1026        ushort sdtr_able;       /* 04 Synchronous DTR able */
1027        ushort start_motor;     /* 05 send start up motor */
1028        ushort tagqng_able;     /* 06 tag queuing able */
1029        ushort bios_scan;       /* 07 BIOS device control */
1030        ushort scam_tolerant;   /* 08 no scam */
1031
1032        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1033        uchar bios_boot_delay;  /*    power up wait */
1034
1035        uchar scsi_reset_delay; /* 10 reset delay */
1036        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1037        /*    high nibble is lun */
1038        /*    low nibble is scsi id */
1039
1040        uchar termination;      /* 11 0 - automatic */
1041        /*    1 - low off / high off */
1042        /*    2 - low off / high on */
1043        /*    3 - low on  / high on */
1044        /*    There is no low on  / high off */
1045
1046        uchar reserved1;        /*    reserved byte (not used) */
1047
1048        ushort bios_ctrl;       /* 12 BIOS control bits */
1049        /*  bit 0  BIOS don't act as initiator. */
1050        /*  bit 1  BIOS > 1 GB support */
1051        /*  bit 2  BIOS > 2 Disk Support */
1052        /*  bit 3  BIOS don't support removables */
1053        /*  bit 4  BIOS support bootable CD */
1054        /*  bit 5  BIOS scan enabled */
1055        /*  bit 6  BIOS support multiple LUNs */
1056        /*  bit 7  BIOS display of message */
1057        /*  bit 8  SCAM disabled */
1058        /*  bit 9  Reset SCSI bus during init. */
1059        /*  bit 10 */
1060        /*  bit 11 No verbose initialization. */
1061        /*  bit 12 SCSI parity enabled */
1062        /*  bit 13 */
1063        /*  bit 14 */
1064        /*  bit 15 */
1065        ushort ultra_able;      /* 13 ULTRA speed able */
1066        ushort reserved2;       /* 14 reserved */
1067        uchar max_host_qng;     /* 15 maximum host queuing */
1068        uchar max_dvc_qng;      /*    maximum per device queuing */
1069        ushort dvc_cntl;        /* 16 control bit for driver */
1070        ushort bug_fix;         /* 17 control bit for bug fix */
1071        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1072        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1073        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1074        ushort check_sum;       /* 21 EEP check sum */
1075        uchar oem_name[16];     /* 22 OEM name */
1076        ushort dvc_err_code;    /* 30 last device driver error code */
1077        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1078        ushort adv_err_addr;    /* 32 last uc error address */
1079        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1080        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1081        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1082        ushort num_of_err;      /* 36 number of error */
1083} ADVEEP_3550_CONFIG;
1084
1085typedef struct adveep_38C0800_config {
1086        /* Word Offset, Description */
1087
1088        ushort cfg_lsw;         /* 00 power up initialization */
1089        /*  bit 13 set - Load CIS */
1090        /*  bit 14 set - BIOS Enable */
1091        /*  bit 15 set - Big Endian Mode */
1092        ushort cfg_msw;         /* 01 unused      */
1093        ushort disc_enable;     /* 02 disconnect enable */
1094        ushort wdtr_able;       /* 03 Wide DTR able */
1095        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1096        ushort start_motor;     /* 05 send start up motor */
1097        ushort tagqng_able;     /* 06 tag queuing able */
1098        ushort bios_scan;       /* 07 BIOS device control */
1099        ushort scam_tolerant;   /* 08 no scam */
1100
1101        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1102        uchar bios_boot_delay;  /*    power up wait */
1103
1104        uchar scsi_reset_delay; /* 10 reset delay */
1105        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1106        /*    high nibble is lun */
1107        /*    low nibble is scsi id */
1108
1109        uchar termination_se;   /* 11 0 - automatic */
1110        /*    1 - low off / high off */
1111        /*    2 - low off / high on */
1112        /*    3 - low on  / high on */
1113        /*    There is no low on  / high off */
1114
1115        uchar termination_lvd;  /* 11 0 - automatic */
1116        /*    1 - low off / high off */
1117        /*    2 - low off / high on */
1118        /*    3 - low on  / high on */
1119        /*    There is no low on  / high off */
1120
1121        ushort bios_ctrl;       /* 12 BIOS control bits */
1122        /*  bit 0  BIOS don't act as initiator. */
1123        /*  bit 1  BIOS > 1 GB support */
1124        /*  bit 2  BIOS > 2 Disk Support */
1125        /*  bit 3  BIOS don't support removables */
1126        /*  bit 4  BIOS support bootable CD */
1127        /*  bit 5  BIOS scan enabled */
1128        /*  bit 6  BIOS support multiple LUNs */
1129        /*  bit 7  BIOS display of message */
1130        /*  bit 8  SCAM disabled */
1131        /*  bit 9  Reset SCSI bus during init. */
1132        /*  bit 10 */
1133        /*  bit 11 No verbose initialization. */
1134        /*  bit 12 SCSI parity enabled */
1135        /*  bit 13 */
1136        /*  bit 14 */
1137        /*  bit 15 */
1138        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1139        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1140        uchar max_host_qng;     /* 15 maximum host queueing */
1141        uchar max_dvc_qng;      /*    maximum per device queuing */
1142        ushort dvc_cntl;        /* 16 control bit for driver */
1143        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1144        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1145        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1146        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1147        ushort check_sum;       /* 21 EEP check sum */
1148        uchar oem_name[16];     /* 22 OEM name */
1149        ushort dvc_err_code;    /* 30 last device driver error code */
1150        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1151        ushort adv_err_addr;    /* 32 last uc error address */
1152        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1153        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1154        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1155        ushort reserved36;      /* 36 reserved */
1156        ushort reserved37;      /* 37 reserved */
1157        ushort reserved38;      /* 38 reserved */
1158        ushort reserved39;      /* 39 reserved */
1159        ushort reserved40;      /* 40 reserved */
1160        ushort reserved41;      /* 41 reserved */
1161        ushort reserved42;      /* 42 reserved */
1162        ushort reserved43;      /* 43 reserved */
1163        ushort reserved44;      /* 44 reserved */
1164        ushort reserved45;      /* 45 reserved */
1165        ushort reserved46;      /* 46 reserved */
1166        ushort reserved47;      /* 47 reserved */
1167        ushort reserved48;      /* 48 reserved */
1168        ushort reserved49;      /* 49 reserved */
1169        ushort reserved50;      /* 50 reserved */
1170        ushort reserved51;      /* 51 reserved */
1171        ushort reserved52;      /* 52 reserved */
1172        ushort reserved53;      /* 53 reserved */
1173        ushort reserved54;      /* 54 reserved */
1174        ushort reserved55;      /* 55 reserved */
1175        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1176        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1177        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1178        ushort subsysid;        /* 59 SubSystem ID */
1179        ushort reserved60;      /* 60 reserved */
1180        ushort reserved61;      /* 61 reserved */
1181        ushort reserved62;      /* 62 reserved */
1182        ushort reserved63;      /* 63 reserved */
1183} ADVEEP_38C0800_CONFIG;
1184
1185typedef struct adveep_38C1600_config {
1186        /* Word Offset, Description */
1187
1188        ushort cfg_lsw;         /* 00 power up initialization */
1189        /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190        /*       clear - Func. 0 INTA, Func. 1 INTB */
1191        /*  bit 13 set - Load CIS */
1192        /*  bit 14 set - BIOS Enable */
1193        /*  bit 15 set - Big Endian Mode */
1194        ushort cfg_msw;         /* 01 unused */
1195        ushort disc_enable;     /* 02 disconnect enable */
1196        ushort wdtr_able;       /* 03 Wide DTR able */
1197        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1198        ushort start_motor;     /* 05 send start up motor */
1199        ushort tagqng_able;     /* 06 tag queuing able */
1200        ushort bios_scan;       /* 07 BIOS device control */
1201        ushort scam_tolerant;   /* 08 no scam */
1202
1203        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1204        uchar bios_boot_delay;  /*    power up wait */
1205
1206        uchar scsi_reset_delay; /* 10 reset delay */
1207        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1208        /*    high nibble is lun */
1209        /*    low nibble is scsi id */
1210
1211        uchar termination_se;   /* 11 0 - automatic */
1212        /*    1 - low off / high off */
1213        /*    2 - low off / high on */
1214        /*    3 - low on  / high on */
1215        /*    There is no low on  / high off */
1216
1217        uchar termination_lvd;  /* 11 0 - automatic */
1218        /*    1 - low off / high off */
1219        /*    2 - low off / high on */
1220        /*    3 - low on  / high on */
1221        /*    There is no low on  / high off */
1222
1223        ushort bios_ctrl;       /* 12 BIOS control bits */
1224        /*  bit 0  BIOS don't act as initiator. */
1225        /*  bit 1  BIOS > 1 GB support */
1226        /*  bit 2  BIOS > 2 Disk Support */
1227        /*  bit 3  BIOS don't support removables */
1228        /*  bit 4  BIOS support bootable CD */
1229        /*  bit 5  BIOS scan enabled */
1230        /*  bit 6  BIOS support multiple LUNs */
1231        /*  bit 7  BIOS display of message */
1232        /*  bit 8  SCAM disabled */
1233        /*  bit 9  Reset SCSI bus during init. */
1234        /*  bit 10 Basic Integrity Checking disabled */
1235        /*  bit 11 No verbose initialization. */
1236        /*  bit 12 SCSI parity enabled */
1237        /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238        /*  bit 14 */
1239        /*  bit 15 */
1240        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1241        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1242        uchar max_host_qng;     /* 15 maximum host queueing */
1243        uchar max_dvc_qng;      /*    maximum per device queuing */
1244        ushort dvc_cntl;        /* 16 control bit for driver */
1245        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1246        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1247        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1248        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1249        ushort check_sum;       /* 21 EEP check sum */
1250        uchar oem_name[16];     /* 22 OEM name */
1251        ushort dvc_err_code;    /* 30 last device driver error code */
1252        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1253        ushort adv_err_addr;    /* 32 last uc error address */
1254        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1255        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1256        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1257        ushort reserved36;      /* 36 reserved */
1258        ushort reserved37;      /* 37 reserved */
1259        ushort reserved38;      /* 38 reserved */
1260        ushort reserved39;      /* 39 reserved */
1261        ushort reserved40;      /* 40 reserved */
1262        ushort reserved41;      /* 41 reserved */
1263        ushort reserved42;      /* 42 reserved */
1264        ushort reserved43;      /* 43 reserved */
1265        ushort reserved44;      /* 44 reserved */
1266        ushort reserved45;      /* 45 reserved */
1267        ushort reserved46;      /* 46 reserved */
1268        ushort reserved47;      /* 47 reserved */
1269        ushort reserved48;      /* 48 reserved */
1270        ushort reserved49;      /* 49 reserved */
1271        ushort reserved50;      /* 50 reserved */
1272        ushort reserved51;      /* 51 reserved */
1273        ushort reserved52;      /* 52 reserved */
1274        ushort reserved53;      /* 53 reserved */
1275        ushort reserved54;      /* 54 reserved */
1276        ushort reserved55;      /* 55 reserved */
1277        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1278        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1279        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1280        ushort subsysid;        /* 59 SubSystem ID */
1281        ushort reserved60;      /* 60 reserved */
1282        ushort reserved61;      /* 61 reserved */
1283        ushort reserved62;      /* 62 reserved */
1284        ushort reserved63;      /* 63 reserved */
1285} ADVEEP_38C1600_CONFIG;
1286
1287/*
1288 * EEPROM Commands
1289 */
1290#define ASC_EEP_CMD_DONE             0x0200
1291
1292/* bios_ctrl */
1293#define BIOS_CTRL_BIOS               0x0001
1294#define BIOS_CTRL_EXTENDED_XLAT      0x0002
1295#define BIOS_CTRL_GT_2_DISK          0x0004
1296#define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1297#define BIOS_CTRL_BOOTABLE_CD        0x0010
1298#define BIOS_CTRL_MULTIPLE_LUN       0x0040
1299#define BIOS_CTRL_DISPLAY_MSG        0x0080
1300#define BIOS_CTRL_NO_SCAM            0x0100
1301#define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1302#define BIOS_CTRL_INIT_VERBOSE       0x0800
1303#define BIOS_CTRL_SCSI_PARITY        0x1000
1304#define BIOS_CTRL_AIPP_DIS           0x2000
1305
1306#define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1307
1308#define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1309
1310/*
1311 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312 * a special 16K Adv Library and Microcode version. After the issue is
1313 * resolved, should restore 32K support.
1314 *
1315 * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1316 */
1317#define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1318
1319/*
1320 * Byte I/O register address from base of 'iop_base'.
1321 */
1322#define IOPB_INTR_STATUS_REG    0x00
1323#define IOPB_CHIP_ID_1          0x01
1324#define IOPB_INTR_ENABLES       0x02
1325#define IOPB_CHIP_TYPE_REV      0x03
1326#define IOPB_RES_ADDR_4         0x04
1327#define IOPB_RES_ADDR_5         0x05
1328#define IOPB_RAM_DATA           0x06
1329#define IOPB_RES_ADDR_7         0x07
1330#define IOPB_FLAG_REG           0x08
1331#define IOPB_RES_ADDR_9         0x09
1332#define IOPB_RISC_CSR           0x0A
1333#define IOPB_RES_ADDR_B         0x0B
1334#define IOPB_RES_ADDR_C         0x0C
1335#define IOPB_RES_ADDR_D         0x0D
1336#define IOPB_SOFT_OVER_WR       0x0E
1337#define IOPB_RES_ADDR_F         0x0F
1338#define IOPB_MEM_CFG            0x10
1339#define IOPB_RES_ADDR_11        0x11
1340#define IOPB_GPIO_DATA          0x12
1341#define IOPB_RES_ADDR_13        0x13
1342#define IOPB_FLASH_PAGE         0x14
1343#define IOPB_RES_ADDR_15        0x15
1344#define IOPB_GPIO_CNTL          0x16
1345#define IOPB_RES_ADDR_17        0x17
1346#define IOPB_FLASH_DATA         0x18
1347#define IOPB_RES_ADDR_19        0x19
1348#define IOPB_RES_ADDR_1A        0x1A
1349#define IOPB_RES_ADDR_1B        0x1B
1350#define IOPB_RES_ADDR_1C        0x1C
1351#define IOPB_RES_ADDR_1D        0x1D
1352#define IOPB_RES_ADDR_1E        0x1E
1353#define IOPB_RES_ADDR_1F        0x1F
1354#define IOPB_DMA_CFG0           0x20
1355#define IOPB_DMA_CFG1           0x21
1356#define IOPB_TICKLE             0x22
1357#define IOPB_DMA_REG_WR         0x23
1358#define IOPB_SDMA_STATUS        0x24
1359#define IOPB_SCSI_BYTE_CNT      0x25
1360#define IOPB_HOST_BYTE_CNT      0x26
1361#define IOPB_BYTE_LEFT_TO_XFER  0x27
1362#define IOPB_BYTE_TO_XFER_0     0x28
1363#define IOPB_BYTE_TO_XFER_1     0x29
1364#define IOPB_BYTE_TO_XFER_2     0x2A
1365#define IOPB_BYTE_TO_XFER_3     0x2B
1366#define IOPB_ACC_GRP            0x2C
1367#define IOPB_RES_ADDR_2D        0x2D
1368#define IOPB_DEV_ID             0x2E
1369#define IOPB_RES_ADDR_2F        0x2F
1370#define IOPB_SCSI_DATA          0x30
1371#define IOPB_RES_ADDR_31        0x31
1372#define IOPB_RES_ADDR_32        0x32
1373#define IOPB_SCSI_DATA_HSHK     0x33
1374#define IOPB_SCSI_CTRL          0x34
1375#define IOPB_RES_ADDR_35        0x35
1376#define IOPB_RES_ADDR_36        0x36
1377#define IOPB_RES_ADDR_37        0x37
1378#define IOPB_RAM_BIST           0x38
1379#define IOPB_PLL_TEST           0x39
1380#define IOPB_PCI_INT_CFG        0x3A
1381#define IOPB_RES_ADDR_3B        0x3B
1382#define IOPB_RFIFO_CNT          0x3C
1383#define IOPB_RES_ADDR_3D        0x3D
1384#define IOPB_RES_ADDR_3E        0x3E
1385#define IOPB_RES_ADDR_3F        0x3F
1386
1387/*
1388 * Word I/O register address from base of 'iop_base'.
1389 */
1390#define IOPW_CHIP_ID_0          0x00    /* CID0  */
1391#define IOPW_CTRL_REG           0x02    /* CC    */
1392#define IOPW_RAM_ADDR           0x04    /* LA    */
1393#define IOPW_RAM_DATA           0x06    /* LD    */
1394#define IOPW_RES_ADDR_08        0x08
1395#define IOPW_RISC_CSR           0x0A    /* CSR   */
1396#define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1397#define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1398#define IOPW_RES_ADDR_10        0x10
1399#define IOPW_SEL_MASK           0x12    /* SM    */
1400#define IOPW_RES_ADDR_14        0x14
1401#define IOPW_FLASH_ADDR         0x16    /* FA    */
1402#define IOPW_RES_ADDR_18        0x18
1403#define IOPW_EE_CMD             0x1A    /* EC    */
1404#define IOPW_EE_DATA            0x1C    /* ED    */
1405#define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1406#define IOPW_RES_ADDR_20        0x20
1407#define IOPW_Q_BASE             0x22    /* QB    */
1408#define IOPW_QP                 0x24    /* QP    */
1409#define IOPW_IX                 0x26    /* IX    */
1410#define IOPW_SP                 0x28    /* SP    */
1411#define IOPW_PC                 0x2A    /* PC    */
1412#define IOPW_RES_ADDR_2C        0x2C
1413#define IOPW_RES_ADDR_2E        0x2E
1414#define IOPW_SCSI_DATA          0x30    /* SD    */
1415#define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1416#define IOPW_SCSI_CTRL          0x34    /* SC    */
1417#define IOPW_HSHK_CFG           0x36    /* HCFG  */
1418#define IOPW_SXFR_STATUS        0x36    /* SXS   */
1419#define IOPW_SXFR_CNTL          0x38    /* SXL   */
1420#define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1421#define IOPW_RES_ADDR_3C        0x3C
1422#define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1423
1424/*
1425 * Doubleword I/O register address from base of 'iop_base'.
1426 */
1427#define IOPDW_RES_ADDR_0         0x00
1428#define IOPDW_RAM_DATA           0x04
1429#define IOPDW_RES_ADDR_8         0x08
1430#define IOPDW_RES_ADDR_C         0x0C
1431#define IOPDW_RES_ADDR_10        0x10
1432#define IOPDW_COMMA              0x14
1433#define IOPDW_COMMB              0x18
1434#define IOPDW_RES_ADDR_1C        0x1C
1435#define IOPDW_SDMA_ADDR0         0x20
1436#define IOPDW_SDMA_ADDR1         0x24
1437#define IOPDW_SDMA_COUNT         0x28
1438#define IOPDW_SDMA_ERROR         0x2C
1439#define IOPDW_RDMA_ADDR0         0x30
1440#define IOPDW_RDMA_ADDR1         0x34
1441#define IOPDW_RDMA_COUNT         0x38
1442#define IOPDW_RDMA_ERROR         0x3C
1443
1444#define ADV_CHIP_ID_BYTE         0x25
1445#define ADV_CHIP_ID_WORD         0x04C1
1446
1447#define ADV_INTR_ENABLE_HOST_INTR                   0x01
1448#define ADV_INTR_ENABLE_SEL_INTR                    0x02
1449#define ADV_INTR_ENABLE_DPR_INTR                    0x04
1450#define ADV_INTR_ENABLE_RTA_INTR                    0x08
1451#define ADV_INTR_ENABLE_RMA_INTR                    0x10
1452#define ADV_INTR_ENABLE_RST_INTR                    0x20
1453#define ADV_INTR_ENABLE_DPE_INTR                    0x40
1454#define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1455
1456#define ADV_INTR_STATUS_INTRA            0x01
1457#define ADV_INTR_STATUS_INTRB            0x02
1458#define ADV_INTR_STATUS_INTRC            0x04
1459
1460#define ADV_RISC_CSR_STOP           (0x0000)
1461#define ADV_RISC_TEST_COND          (0x2000)
1462#define ADV_RISC_CSR_RUN            (0x4000)
1463#define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1464
1465#define ADV_CTRL_REG_HOST_INTR      0x0100
1466#define ADV_CTRL_REG_SEL_INTR       0x0200
1467#define ADV_CTRL_REG_DPR_INTR       0x0400
1468#define ADV_CTRL_REG_RTA_INTR       0x0800
1469#define ADV_CTRL_REG_RMA_INTR       0x1000
1470#define ADV_CTRL_REG_RES_BIT14      0x2000
1471#define ADV_CTRL_REG_DPE_INTR       0x4000
1472#define ADV_CTRL_REG_POWER_DONE     0x8000
1473#define ADV_CTRL_REG_ANY_INTR       0xFF00
1474
1475#define ADV_CTRL_REG_CMD_RESET             0x00C6
1476#define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1477#define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1478#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1479#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1480
1481#define ADV_TICKLE_NOP                      0x00
1482#define ADV_TICKLE_A                        0x01
1483#define ADV_TICKLE_B                        0x02
1484#define ADV_TICKLE_C                        0x03
1485
1486#define AdvIsIntPending(port) \
1487    (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488
1489/*
1490 * SCSI_CFG0 Register bit definitions
1491 */
1492#define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1493#define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1494#define EVEN_PARITY     0x1000  /* Select Even Parity */
1495#define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496#define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1497#define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1498#define SCAM_EN         0x0080  /* Enable SCAM selection */
1499#define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500#define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501#define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1502#define OUR_ID          0x000F  /* SCSI ID */
1503
1504/*
1505 * SCSI_CFG1 Register bit definitions
1506 */
1507#define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1508#define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509#define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1510#define FILTER_SEL      0x0C00  /* Filter Period Selection */
1511#define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1512#define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1513#define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1514#define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1515#define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1516#define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1517#define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1518#define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1519#define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1520#define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1521#define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1522
1523/*
1524 * Addendum for ASC-38C0800 Chip
1525 *
1526 * The ASC-38C1600 Chip uses the same definitions except that the
1527 * bus mode override bits [12:10] have been moved to byte register
1528 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533 */
1534#define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1535#define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1536#define  HVD             0x1000 /* HVD Device Detect */
1537#define  LVD             0x0800 /* LVD Device Detect */
1538#define  SE              0x0400 /* SE Device Detect */
1539#define TERM_LVD        0x00C0  /* LVD Termination Bits */
1540#define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1541#define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1542#define TERM_SE         0x0030  /* SE Termination Bits */
1543#define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1544#define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1545#define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1546#define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1547#define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1548#define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1549#define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1550#define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1551
1552#define CABLE_ILLEGAL_A 0x7
1553    /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1554
1555#define CABLE_ILLEGAL_B 0xB
1556    /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1557
1558/*
1559 * MEM_CFG Register bit definitions
1560 */
1561#define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1562#define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1563#define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1564#define  RAM_SZ_2KB      0x00   /* 2 KB */
1565#define  RAM_SZ_4KB      0x04   /* 4 KB */
1566#define  RAM_SZ_8KB      0x08   /* 8 KB */
1567#define  RAM_SZ_16KB     0x0C   /* 16 KB */
1568#define  RAM_SZ_32KB     0x10   /* 32 KB */
1569#define  RAM_SZ_64KB     0x14   /* 64 KB */
1570
1571/*
1572 * DMA_CFG0 Register bit definitions
1573 *
1574 * This register is only accessible to the host.
1575 */
1576#define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1577#define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1578#define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1579#define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1580#define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1581#define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1582#define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1583#define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1584#define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1585#define START_CTL       0x0C    /* DMA start conditions */
1586#define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1587#define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1588#define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1589#define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1590#define READ_CMD        0x03    /* Memory Read Method */
1591#define  READ_CMD_MR     0x00   /* Memory Read */
1592#define  READ_CMD_MRL    0x02   /* Memory Read Long */
1593#define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1594
1595/*
1596 * ASC-38C0800 RAM BIST Register bit definitions
1597 */
1598#define RAM_TEST_MODE         0x80
1599#define PRE_TEST_MODE         0x40
1600#define NORMAL_MODE           0x00
1601#define RAM_TEST_DONE         0x10
1602#define RAM_TEST_STATUS       0x0F
1603#define  RAM_TEST_HOST_ERROR   0x08
1604#define  RAM_TEST_INTRAM_ERROR 0x04
1605#define  RAM_TEST_RISC_ERROR   0x02
1606#define  RAM_TEST_SCSI_ERROR   0x01
1607#define  RAM_TEST_SUCCESS      0x00
1608#define PRE_TEST_VALUE        0x05
1609#define NORMAL_VALUE          0x00
1610
1611/*
1612 * ASC38C1600 Definitions
1613 *
1614 * IOPB_PCI_INT_CFG Bit Field Definitions
1615 */
1616
1617#define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1618
1619/*
1620 * Bit 1 can be set to change the interrupt for the Function to operate in
1621 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623 * mode, otherwise the operating mode is undefined.
1624 */
1625#define TOTEMPOLE       0x02
1626
1627/*
1628 * Bit 0 can be used to change the Int Pin for the Function. The value is
1629 * 0 by default for both Functions with Function 0 using INT A and Function
1630 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631 * INT A is used.
1632 *
1633 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634 * value specified in the PCI Configuration Space.
1635 */
1636#define INTAB           0x01
1637
1638/*
1639 * Adv Library Status Definitions
1640 */
1641#define ADV_TRUE        1
1642#define ADV_FALSE       0
1643#define ADV_SUCCESS     1
1644#define ADV_BUSY        0
1645#define ADV_ERROR       (-1)
1646
1647/*
1648 * ADV_DVC_VAR 'warn_code' values
1649 */
1650#define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1651#define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1652#define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1653#define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1654
1655#define ADV_MAX_TID                     15      /* max. target identifier */
1656#define ADV_MAX_LUN                     7       /* max. logical unit number */
1657
1658/*
1659 * Fixed locations of microcode operating variables.
1660 */
1661#define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1662#define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1663#define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1664#define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1665#define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1666#define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1667#define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1668#define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1669#define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1670#define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1671#define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1672#define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1673#define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1674#define ASC_MC_CHIP_TYPE                0x009A
1675#define ASC_MC_INTRB_CODE               0x009B
1676#define ASC_MC_WDTR_ABLE                0x009C
1677#define ASC_MC_SDTR_ABLE                0x009E
1678#define ASC_MC_TAGQNG_ABLE              0x00A0
1679#define ASC_MC_DISC_ENABLE              0x00A2
1680#define ASC_MC_IDLE_CMD_STATUS          0x00A4
1681#define ASC_MC_IDLE_CMD                 0x00A6
1682#define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1683#define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1684#define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1685#define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1686#define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1687#define ASC_MC_SDTR_DONE                0x00B6
1688#define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1689#define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1690#define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1691#define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1692#define ASC_MC_WDTR_DONE                0x0124
1693#define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1694#define ASC_MC_ICQ                      0x0160
1695#define ASC_MC_IRQ                      0x0164
1696#define ASC_MC_PPR_ABLE                 0x017A
1697
1698/*
1699 * BIOS LRAM variable absolute offsets.
1700 */
1701#define BIOS_CODESEG    0x54
1702#define BIOS_CODELEN    0x56
1703#define BIOS_SIGNATURE  0x58
1704#define BIOS_VERSION    0x5A
1705
1706/*
1707 * Microcode Control Flags
1708 *
1709 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710 * and handled by the microcode.
1711 */
1712#define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1713#define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1714
1715/*
1716 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717 */
1718#define HSHK_CFG_WIDE_XFR       0x8000
1719#define HSHK_CFG_RATE           0x0F00
1720#define HSHK_CFG_OFFSET         0x001F
1721
1722#define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1723#define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1724#define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1725#define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1726
1727#define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1728#define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1729#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1730#define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1731#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732
1733#define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1734#define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1735#define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1736#define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1737#define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1738/*
1739 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741 */
1742#define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1743#define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1744
1745/*
1746 * All fields here are accessed by the board microcode and need to be
1747 * little-endian.
1748 */
1749typedef struct adv_carr_t {
1750        ADV_VADDR carr_va;      /* Carrier Virtual Address */
1751        ADV_PADDR carr_pa;      /* Carrier Physical Address */
1752        ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753        /*
1754         * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1755         *
1756         * next_vpa [3:1]             Reserved Bits
1757         * next_vpa [0]               Done Flag set in Response Queue.
1758         */
1759        ADV_VADDR next_vpa;
1760} ADV_CARR_T;
1761
1762/*
1763 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764 */
1765#define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1766
1767#define ASC_RQ_DONE             0x00000001
1768#define ASC_RQ_GOOD             0x00000002
1769#define ASC_CQ_STOPPER          0x00000000
1770
1771#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772
1773#define ADV_CARRIER_NUM_PAGE_CROSSING \
1774    (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1775
1776#define ADV_CARRIER_BUFSIZE \
1777    ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778
1779/*
1780 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 *
1782 * The Adv Library should limit use to the lower nibble (4 bits) of
1783 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 */
1785#define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1786#define ADV_SCSIQ_DONE                  0x02    /* request done */
1787#define ADV_DONT_RETRY                  0x08    /* don't do retry */
1788
1789#define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1790#define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1791#define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1792
1793/*
1794 * Adapter temporary configuration structure
1795 *
1796 * This structure can be discarded after initialization. Don't add
1797 * fields here needed after initialization.
1798 *
1799 * Field naming convention:
1800 *
1801 *  *_enable indicates the field enables or disables a feature. The
1802 *  value of the field is never reset.
1803 */
1804typedef struct adv_dvc_cfg {
1805        ushort disc_enable;     /* enable disconnection */
1806        uchar chip_version;     /* chip version */
1807        uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1808        ushort control_flag;    /* Microcode Control Flag */
1809        ushort mcode_date;      /* Microcode date */
1810        ushort mcode_version;   /* Microcode version */
1811        ushort serial1;         /* EEPROM serial number word 1 */
1812        ushort serial2;         /* EEPROM serial number word 2 */
1813        ushort serial3;         /* EEPROM serial number word 3 */
1814} ADV_DVC_CFG;
1815
1816struct adv_dvc_var;
1817struct adv_scsi_req_q;
1818
1819typedef struct asc_sg_block {
1820        uchar reserved1;
1821        uchar reserved2;
1822        uchar reserved3;
1823        uchar sg_cnt;           /* Valid entries in block. */
1824        ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1825        struct {
1826                ADV_PADDR sg_addr;      /* SG element address. */
1827                ADV_DCNT sg_count;      /* SG element count. */
1828        } sg_list[NO_OF_SG_PER_BLOCK];
1829} ADV_SG_BLOCK;
1830
1831/*
1832 * ADV_SCSI_REQ_Q - microcode request structure
1833 *
1834 * All fields in this structure up to byte 60 are used by the microcode.
1835 * The microcode makes assumptions about the size and ordering of fields
1836 * in this structure. Do not change the structure definition here without
1837 * coordinating the change with the microcode.
1838 *
1839 * All fields accessed by microcode must be maintained in little_endian
1840 * order.
1841 */
1842typedef struct adv_scsi_req_q {
1843        uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1844        uchar target_cmd;
1845        uchar target_id;        /* Device target identifier. */
1846        uchar target_lun;       /* Device target logical unit number. */
1847        ADV_PADDR data_addr;    /* Data buffer physical address. */
1848        ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1849        ADV_PADDR sense_addr;
1850        ADV_PADDR carr_pa;
1851        uchar mflag;
1852        uchar sense_len;
1853        uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1854        uchar scsi_cntl;
1855        uchar done_status;      /* Completion status. */
1856        uchar scsi_status;      /* SCSI status byte. */
1857        uchar host_status;      /* Ucode host status. */
1858        uchar sg_working_ix;
1859        uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1860        ADV_PADDR sg_real_addr; /* SG list physical address. */
1861        ADV_PADDR scsiq_rptr;
1862        uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1863        ADV_VADDR scsiq_ptr;
1864        ADV_VADDR carr_va;
1865        /*
1866         * End of microcode structure - 60 bytes. The rest of the structure
1867         * is used by the Adv Library and ignored by the microcode.
1868         */
1869        ADV_VADDR srb_ptr;
1870        ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1871        char *vdata_addr;       /* Data buffer virtual address. */
1872        uchar a_flag;
1873        uchar pad[2];           /* Pad out to a word boundary. */
1874} ADV_SCSI_REQ_Q;
1875
1876/*
1877 * The following two structures are used to process Wide Board requests.
1878 *
1879 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882 * Mid-Level SCSI request structure.
1883 *
1884 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886 * up to 255 scatter-gather elements may be used per request or
1887 * ADV_SCSI_REQ_Q.
1888 *
1889 * Both structures must be 32 byte aligned.
1890 */
1891typedef struct adv_sgblk {
1892        ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1893        uchar align[32];        /* Sgblock structure padding. */
1894        struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1895} adv_sgblk_t;
1896
1897typedef struct adv_req {
1898        ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1899        uchar align[32];        /* Request structure padding. */
1900        struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1901        adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1902        struct adv_req *next_reqp;      /* Next Request Structure. */
1903} adv_req_t;
1904
1905/*
1906 * Adapter operation variable structure.
1907 *
1908 * One structure is required per host adapter.
1909 *
1910 * Field naming convention:
1911 *
1912 *  *_able indicates both whether a feature should be enabled or disabled
1913 *  and whether a device isi capable of the feature. At initialization
1914 *  this field may be set, but later if a device is found to be incapable
1915 *  of the feature, the field is cleared.
1916 */
1917typedef struct adv_dvc_var {
1918        AdvPortAddr iop_base;   /* I/O port address */
1919        ushort err_code;        /* fatal error code */
1920        ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1921        ushort wdtr_able;       /* try WDTR for a device */
1922        ushort sdtr_able;       /* try SDTR for a device */
1923        ushort ultra_able;      /* try SDTR Ultra speed for a device */
1924        ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1925        ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1926        ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1927        ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1928        ushort tagqng_able;     /* try tagged queuing with a device */
1929        ushort ppr_able;        /* PPR message capable per TID bitmask. */
1930        uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1931        ushort start_motor;     /* start motor command allowed */
1932        uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1933        uchar chip_no;          /* should be assigned by caller */
1934        uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1935        ushort no_scam;         /* scam_tolerant of EEPROM */
1936        struct asc_board *drv_ptr;      /* driver pointer to private structure */
1937        uchar chip_scsi_id;     /* chip SCSI target ID */
1938        uchar chip_type;
1939        uchar bist_err_code;
1940        ADV_CARR_T *carrier_buf;
1941        ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1942        ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1943        ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1944        ushort carr_pending_cnt;        /* Count of pending carriers. */
1945        struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1946        /*
1947         * Note: The following fields will not be used after initialization. The
1948         * driver may discard the buffer after initialization is done.
1949         */
1950        ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1951} ADV_DVC_VAR;
1952
1953/*
1954 * Microcode idle loop commands
1955 */
1956#define IDLE_CMD_COMPLETED           0
1957#define IDLE_CMD_STOP_CHIP           0x0001
1958#define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1959#define IDLE_CMD_SEND_INT            0x0004
1960#define IDLE_CMD_ABORT               0x0008
1961#define IDLE_CMD_DEVICE_RESET        0x0010
1962#define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1963#define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1964#define IDLE_CMD_SCSIREQ             0x0080
1965
1966#define IDLE_CMD_STATUS_SUCCESS      0x0001
1967#define IDLE_CMD_STATUS_FAILURE      0x0002
1968
1969/*
1970 * AdvSendIdleCmd() flag definitions.
1971 */
1972#define ADV_NOWAIT     0x01
1973
1974/*
1975 * Wait loop time out values.
1976 */
1977#define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1978#define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1979#define SCSI_MAX_RETRY               10 /* retry count */
1980
1981#define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1982#define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1983#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1984#define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1985
1986#define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1987
1988/* Read byte from a register. */
1989#define AdvReadByteRegister(iop_base, reg_off) \
1990     (ADV_MEM_READB((iop_base) + (reg_off)))
1991
1992/* Write byte to a register. */
1993#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994     (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995
1996/* Read word (2 bytes) from a register. */
1997#define AdvReadWordRegister(iop_base, reg_off) \
1998     (ADV_MEM_READW((iop_base) + (reg_off)))
1999
2000/* Write word (2 bytes) to a register. */
2001#define AdvWriteWordRegister(iop_base, reg_off, word) \
2002     (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003
2004/* Write dword (4 bytes) to a register. */
2005#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006     (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007
2008/* Read byte from LRAM. */
2009#define AdvReadByteLram(iop_base, addr, byte) \
2010do { \
2011    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012    (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013} while (0)
2014
2015/* Write byte to LRAM. */
2016#define AdvWriteByteLram(iop_base, addr, byte) \
2017    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018     ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019
2020/* Read word (2 bytes) from LRAM. */
2021#define AdvReadWordLram(iop_base, addr, word) \
2022do { \
2023    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024    (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025} while (0)
2026
2027/* Write word (2 bytes) to LRAM. */
2028#define AdvWriteWordLram(iop_base, addr, word) \
2029    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031
2032/* Write little-endian double word (4 bytes) to LRAM */
2033/* Because of unspecified C language ordering don't use auto-increment. */
2034#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035    ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037                     cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040                     cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041
2042/* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043#define AdvReadWordAutoIncLram(iop_base) \
2044     (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045
2046/* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047#define AdvWriteWordAutoIncLram(iop_base, word) \
2048     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049
2050/*
2051 * Define macro to check for Condor signature.
2052 *
2053 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055 */
2056#define AdvFindSignature(iop_base) \
2057    (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058    ADV_CHIP_ID_BYTE) && \
2059     (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060    ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2061
2062/*
2063 * Define macro to Return the version number of the chip at 'iop_base'.
2064 *
2065 * The second parameter 'bus_type' is currently unused.
2066 */
2067#define AdvGetChipVersion(iop_base, bus_type) \
2068    AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069
2070/*
2071 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073 *
2074 * If the request has not yet been sent to the device it will simply be
2075 * aborted from RISC memory. If the request is disconnected it will be
2076 * aborted on reselection by sending an Abort Message to the target ID.
2077 *
2078 * Return value:
2079 *      ADV_TRUE(1) - Queue was successfully aborted.
2080 *      ADV_FALSE(0) - Queue was not found on the active queue list.
2081 */
2082#define AdvAbortQueue(asc_dvc, scsiq) \
2083        AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084                       (ADV_DCNT) (scsiq))
2085
2086/*
2087 * Send a Bus Device Reset Message to the specified target ID.
2088 *
2089 * All outstanding commands will be purged if sending the
2090 * Bus Device Reset Message is successful.
2091 *
2092 * Return Value:
2093 *      ADV_TRUE(1) - All requests on the target are purged.
2094 *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095 *                     are not purged.
2096 */
2097#define AdvResetDevice(asc_dvc, target_id) \
2098        AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099                    (ADV_DCNT) (target_id))
2100
2101/*
2102 * SCSI Wide Type definition.
2103 */
2104#define ADV_SCSI_BIT_ID_TYPE   ushort
2105
2106/*
2107 * AdvInitScsiTarget() 'cntl_flag' options.
2108 */
2109#define ADV_SCAN_LUN           0x01
2110#define ADV_CAPINFO_NOLUN      0x02
2111
2112/*
2113 * Convert target id to target id bit mask.
2114 */
2115#define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2116
2117/*
2118 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119 */
2120
2121#define QD_NO_STATUS         0x00       /* Request not completed yet. */
2122#define QD_NO_ERROR          0x01
2123#define QD_ABORTED_BY_HOST   0x02
2124#define QD_WITH_ERROR        0x04
2125
2126#define QHSTA_NO_ERROR              0x00
2127#define QHSTA_M_SEL_TIMEOUT         0x11
2128#define QHSTA_M_DATA_OVER_RUN       0x12
2129#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130#define QHSTA_M_QUEUE_ABORTED       0x15
2131#define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2132#define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2133#define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2134#define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2135#define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2136#define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2137#define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2138/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2139#define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2140#define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2141#define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2142#define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2143#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2144#define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2145#define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2146#define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2147#define QHSTA_M_WTM_TIMEOUT         0x41
2148#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2149#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2150#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2151#define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2152#define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2153#define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2154
2155/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156#define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2157#define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2158#define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2159
2160/*
2161 * Total contiguous memory needed for driver SG blocks.
2162 *
2163 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164 * number of scatter-gather elements the driver supports in a
2165 * single request.
2166 */
2167
2168#define ADV_SG_LIST_MAX_BYTE_SIZE \
2169         (sizeof(ADV_SG_BLOCK) * \
2170          ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171
2172/* struct asc_board flags */
2173#define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2174
2175#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2176
2177#define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2178
2179#define ASC_INFO_SIZE           128     /* advansys_info() line size */
2180
2181#ifdef CONFIG_PROC_FS
2182/* /proc/scsi/advansys/[0...] related definitions */
2183#define ASC_PRTBUF_SIZE         2048
2184#define ASC_PRTLINE_SIZE        160
2185
2186#define ASC_PRT_NEXT() \
2187    if (cp) { \
2188        totlen += len; \
2189        leftlen -= len; \
2190        if (leftlen == 0) { \
2191            return totlen; \
2192        } \
2193        cp += len; \
2194    }
2195#endif /* CONFIG_PROC_FS */
2196
2197/* Asc Library return codes */
2198#define ASC_TRUE        1
2199#define ASC_FALSE       0
2200#define ASC_NOERROR     1
2201#define ASC_BUSY        0
2202#define ASC_ERROR       (-1)
2203
2204/* struct scsi_cmnd function return codes */
2205#define STATUS_BYTE(byte)   (byte)
2206#define MSG_BYTE(byte)      ((byte) << 8)
2207#define HOST_BYTE(byte)     ((byte) << 16)
2208#define DRIVER_BYTE(byte)   ((byte) << 24)
2209
2210#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2211#ifndef ADVANSYS_STATS
2212#define ASC_STATS_ADD(shost, counter, count)
2213#else /* ADVANSYS_STATS */
2214#define ASC_STATS_ADD(shost, counter, count) \
2215        (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2216#endif /* ADVANSYS_STATS */
2217
2218/* If the result wraps when calculating tenths, return 0. */
2219#define ASC_TENTHS(num, den) \
2220    (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2221    0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2222
2223/*
2224 * Display a message to the console.
2225 */
2226#define ASC_PRINT(s) \
2227    { \
2228        printk("advansys: "); \
2229        printk(s); \
2230    }
2231
2232#define ASC_PRINT1(s, a1) \
2233    { \
2234        printk("advansys: "); \
2235        printk((s), (a1)); \
2236    }
2237
2238#define ASC_PRINT2(s, a1, a2) \
2239    { \
2240        printk("advansys: "); \
2241        printk((s), (a1), (a2)); \
2242    }
2243
2244#define ASC_PRINT3(s, a1, a2, a3) \
2245    { \
2246        printk("advansys: "); \
2247        printk((s), (a1), (a2), (a3)); \
2248    }
2249
2250#define ASC_PRINT4(s, a1, a2, a3, a4) \
2251    { \
2252        printk("advansys: "); \
2253        printk((s), (a1), (a2), (a3), (a4)); \
2254    }
2255
2256#ifndef ADVANSYS_DEBUG
2257
2258#define ASC_DBG(lvl, s...)
2259#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2260#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2261#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2262#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2263#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2264#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2265#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2266#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2267#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2268
2269#else /* ADVANSYS_DEBUG */
2270
2271/*
2272 * Debugging Message Levels:
2273 * 0: Errors Only
2274 * 1: High-Level Tracing
2275 * 2-N: Verbose Tracing
2276 */
2277
2278#define ASC_DBG(lvl, format, arg...) {                                  \
2279        if (asc_dbglvl >= (lvl))                                        \
2280                printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2281                        __func__ , ## arg);                             \
2282}
2283
2284#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2285    { \
2286        if (asc_dbglvl >= (lvl)) { \
2287            asc_prt_scsi_host(s); \
2288        } \
2289    }
2290
2291#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2292    { \
2293        if (asc_dbglvl >= (lvl)) { \
2294            asc_prt_asc_scsi_q(scsiqp); \
2295        } \
2296    }
2297
2298#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2299    { \
2300        if (asc_dbglvl >= (lvl)) { \
2301            asc_prt_asc_qdone_info(qdone); \
2302        } \
2303    }
2304
2305#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2306    { \
2307        if (asc_dbglvl >= (lvl)) { \
2308            asc_prt_adv_scsi_req_q(scsiqp); \
2309        } \
2310    }
2311
2312#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2313    { \
2314        if (asc_dbglvl >= (lvl)) { \
2315            asc_prt_hex((name), (start), (length)); \
2316        } \
2317    }
2318
2319#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2320        ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2321
2322#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2323        ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2324
2325#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2326        ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2327#endif /* ADVANSYS_DEBUG */
2328
2329#ifdef ADVANSYS_STATS
2330
2331/* Per board statistics structure */
2332struct asc_stats {
2333        /* Driver Entrypoint Statistics */
2334        ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2335        ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2336        ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2337        ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2338        ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2339        ADV_DCNT done;          /* # calls to request's scsi_done function */
2340        ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2341        ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2342        ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2343        /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2344        ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2345        ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2346        ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2347        ADV_DCNT exe_unknown;   /* # unknown returns. */
2348        /* Data Transfer Statistics */
2349        ADV_DCNT xfer_cnt;      /* # I/O requests received */
2350        ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2351        ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2352};
2353#endif /* ADVANSYS_STATS */
2354
2355/*
2356 * Structure allocated for each board.
2357 *
2358 * This structure is allocated by scsi_host_alloc() at the end
2359 * of the 'Scsi_Host' structure starting at the 'hostdata'
2360 * field. It is guaranteed to be allocated from DMA-able memory.
2361 */
2362struct asc_board {
2363        struct device *dev;
2364        uint flags;             /* Board flags */
2365        unsigned int irq;
2366        union {
2367                ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2368                ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2369        } dvc_var;
2370        union {
2371                ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2372                ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2373        } dvc_cfg;
2374        ushort asc_n_io_port;   /* Number I/O ports. */
2375        ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2376        ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2377        ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2378        ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2379        union {
2380                ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2381                ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2382                ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2383                ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2384        } eep_config;
2385        ulong last_reset;       /* Saved last reset time */
2386        /* /proc/scsi/advansys/[0...] */
2387        char *prtbuf;           /* /proc print buffer */
2388#ifdef ADVANSYS_STATS
2389        struct asc_stats asc_stats;     /* Board statistics */
2390#endif                          /* ADVANSYS_STATS */
2391        /*
2392         * The following fields are used only for Narrow Boards.
2393         */
2394        uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2395        /*
2396         * The following fields are used only for Wide Boards.
2397         */
2398        void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2399        ushort ioport;          /* I/O Port address. */
2400        adv_req_t *adv_reqp;    /* Request structures. */
2401        adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2402        ushort bios_signature;  /* BIOS Signature. */
2403        ushort bios_version;    /* BIOS Version. */
2404        ushort bios_codeseg;    /* BIOS Code Segment. */
2405        ushort bios_codelen;    /* BIOS Code Segment Length. */
2406};
2407
2408#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2409                                                        dvc_var.asc_dvc_var)
2410#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2411                                                        dvc_var.adv_dvc_var)
2412#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2413
2414#ifdef ADVANSYS_DEBUG
2415static int asc_dbglvl = 3;
2416
2417/*
2418 * asc_prt_asc_dvc_var()
2419 */
2420static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2421{
2422        printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2423
2424        printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2425               "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2426
2427        printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2428                (unsigned)h->init_sdtr);
2429
2430        printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2431               "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2432               (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2433               (unsigned)h->chip_no);
2434
2435        printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2436               "%u,\n", (unsigned)h->queue_full_or_busy,
2437               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2438
2439        printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2440               "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2441               (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2442               (unsigned)h->in_critical_cnt);
2443
2444        printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2445               "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2446               (unsigned)h->init_state, (unsigned)h->no_scam,
2447               (unsigned)h->pci_fix_asyn_xfer);
2448
2449        printk(" cfg 0x%lx\n", (ulong)h->cfg);
2450}
2451
2452/*
2453 * asc_prt_asc_dvc_cfg()
2454 */
2455static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2456{
2457        printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2458
2459        printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2460               h->can_tagged_qng, h->cmd_qng_enabled);
2461        printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2462               h->disc_enable, h->sdtr_enable);
2463
2464        printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2465                "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2466                h->isa_dma_channel, h->chip_version);
2467
2468        printk(" mcode_date 0x%x, mcode_version %d\n",
2469                h->mcode_date, h->mcode_version);
2470}
2471
2472/*
2473 * asc_prt_adv_dvc_var()
2474 *
2475 * Display an ADV_DVC_VAR structure.
2476 */
2477static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2478{
2479        printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2480
2481        printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2482               (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2483
2484        printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2485               (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2486
2487        printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2488               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2489
2490        printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2491               (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2492               (ulong)h->carr_freelist);
2493
2494        printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2495               (ulong)h->icq_sp, (ulong)h->irq_sp);
2496
2497        printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2498               (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2499
2500        printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2501               (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2502}
2503
2504/*
2505 * asc_prt_adv_dvc_cfg()
2506 *
2507 * Display an ADV_DVC_CFG structure.
2508 */
2509static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2510{
2511        printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2512
2513        printk("  disc_enable 0x%x, termination 0x%x\n",
2514               h->disc_enable, h->termination);
2515
2516        printk("  chip_version 0x%x, mcode_date 0x%x\n",
2517               h->chip_version, h->mcode_date);
2518
2519        printk("  mcode_version 0x%x, control_flag 0x%x\n",
2520               h->mcode_version, h->control_flag);
2521}
2522
2523/*
2524 * asc_prt_scsi_host()
2525 */
2526static void asc_prt_scsi_host(struct Scsi_Host *s)
2527{
2528        struct asc_board *boardp = shost_priv(s);
2529
2530        printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2531        printk(" host_busy %u, host_no %d, last_reset %d,\n",
2532               s->host_busy, s->host_no, (unsigned)s->last_reset);
2533
2534        printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2535               (ulong)s->base, (ulong)s->io_port, boardp->irq);
2536
2537        printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2538               s->dma_channel, s->this_id, s->can_queue);
2539
2540        printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2541               s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2542
2543        if (ASC_NARROW_BOARD(boardp)) {
2544                asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2545                asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2546        } else {
2547                asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2548                asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2549        }
2550}
2551
2552/*
2553 * asc_prt_hex()
2554 *
2555 * Print hexadecimal output in 4 byte groupings 32 bytes
2556 * or 8 double-words per line.
2557 */
2558static void asc_prt_hex(char *f, uchar *s, int l)
2559{
2560        int i;
2561        int j;
2562        int k;
2563        int m;
2564
2565        printk("%s: (%d bytes)\n", f, l);
2566
2567        for (i = 0; i < l; i += 32) {
2568
2569                /* Display a maximum of 8 double-words per line. */
2570                if ((k = (l - i) / 4) >= 8) {
2571                        k = 8;
2572                        m = 0;
2573                } else {
2574                        m = (l - i) % 4;
2575                }
2576
2577                for (j = 0; j < k; j++) {
2578                        printk(" %2.2X%2.2X%2.2X%2.2X",
2579                               (unsigned)s[i + (j * 4)],
2580                               (unsigned)s[i + (j * 4) + 1],
2581                               (unsigned)s[i + (j * 4) + 2],
2582                               (unsigned)s[i + (j * 4) + 3]);
2583                }
2584
2585                switch (m) {
2586                case 0:
2587                default:
2588                        break;
2589                case 1:
2590                        printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2591                        break;
2592                case 2:
2593                        printk(" %2.2X%2.2X",
2594                               (unsigned)s[i + (j * 4)],
2595                               (unsigned)s[i + (j * 4) + 1]);
2596                        break;
2597                case 3:
2598                        printk(" %2.2X%2.2X%2.2X",
2599                               (unsigned)s[i + (j * 4) + 1],
2600                               (unsigned)s[i + (j * 4) + 2],
2601                               (unsigned)s[i + (j * 4) + 3]);
2602                        break;
2603                }
2604
2605                printk("\n");
2606        }
2607}
2608
2609/*
2610 * asc_prt_asc_scsi_q()
2611 */
2612static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2613{
2614        ASC_SG_HEAD *sgp;
2615        int i;
2616
2617        printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2618
2619        printk
2620            (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2621             q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2622             q->q2.tag_code);
2623
2624        printk
2625            (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2626             (ulong)le32_to_cpu(q->q1.data_addr),
2627             (ulong)le32_to_cpu(q->q1.data_cnt),
2628             (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2629
2630        printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2631               (ulong)q->cdbptr, q->q2.cdb_len,
2632               (ulong)q->sg_head, q->q1.sg_queue_cnt);
2633
2634        if (q->sg_head) {
2635                sgp = q->sg_head;
2636                printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2637                printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2638                       sgp->queue_cnt);
2639                for (i = 0; i < sgp->entry_cnt; i++) {
2640                        printk(" [%u]: addr 0x%lx, bytes %lu\n",
2641                               i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2642                               (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2643                }
2644
2645        }
2646}
2647
2648/*
2649 * asc_prt_asc_qdone_info()
2650 */
2651static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2652{
2653        printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2654        printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2655               (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2656               q->d2.tag_code);
2657        printk
2658            (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2659             q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2660}
2661
2662/*
2663 * asc_prt_adv_sgblock()
2664 *
2665 * Display an ADV_SG_BLOCK structure.
2666 */
2667static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2668{
2669        int i;
2670
2671        printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2672               (ulong)b, sgblockno);
2673        printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2674               b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2675        BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2676        if (b->sg_ptr != 0)
2677                BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2678        for (i = 0; i < b->sg_cnt; i++) {
2679                printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2680                       i, (ulong)b->sg_list[i].sg_addr,
2681                       (ulong)b->sg_list[i].sg_count);
2682        }
2683}
2684
2685/*
2686 * asc_prt_adv_scsi_req_q()
2687 *
2688 * Display an ADV_SCSI_REQ_Q structure.
2689 */
2690static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2691{
2692        int sg_blk_cnt;
2693        struct asc_sg_block *sg_ptr;
2694
2695        printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2696
2697        printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2698               q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2699
2700        printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2701               q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2702
2703        printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2704               (ulong)le32_to_cpu(q->data_cnt),
2705               (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2706
2707        printk
2708            ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2709             q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2710
2711        printk("  sg_working_ix 0x%x, target_cmd %u\n",
2712               q->sg_working_ix, q->target_cmd);
2713
2714        printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2715               (ulong)le32_to_cpu(q->scsiq_rptr),
2716               (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2717
2718        /* Display the request's ADV_SG_BLOCK structures. */
2719        if (q->sg_list_ptr != NULL) {
2720                sg_blk_cnt = 0;
2721                while (1) {
2722                        /*
2723                         * 'sg_ptr' is a physical address. Convert it to a virtual
2724                         * address by indexing 'sg_blk_cnt' into the virtual address
2725                         * array 'sg_list_ptr'.
2726                         *
2727                         * XXX - Assumes all SG physical blocks are virtually contiguous.
2728                         */
2729                        sg_ptr =
2730                            &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2731                        asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2732                        if (sg_ptr->sg_ptr == 0) {
2733                                break;
2734                        }
2735                        sg_blk_cnt++;
2736                }
2737        }
2738}
2739#endif /* ADVANSYS_DEBUG */
2740
2741/*
2742 * The advansys chip/microcode contains a 32-bit identifier for each command
2743 * known as the 'srb'.  I don't know what it stands for.  The driver used
2744 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2745 * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2746 * pointers.  It auto-expands when full, unless it can't allocate memory.
2747 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2748 * the return of i+1 in this routine, and the corresponding subtraction in
2749 * the inverse routine.
2750 */
2751#define BAD_SRB 0
2752static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2753{
2754        int i;
2755        void **new_ptr;
2756
2757        for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2758                if (!asc_dvc->ptr_map[i])
2759                        goto out;
2760        }
2761
2762        if (asc_dvc->ptr_map_count == 0)
2763                asc_dvc->ptr_map_count = 1;
2764        else
2765                asc_dvc->ptr_map_count *= 2;
2766
2767        new_ptr = krealloc(asc_dvc->ptr_map,
2768                        asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2769        if (!new_ptr)
2770                return BAD_SRB;
2771        asc_dvc->ptr_map = new_ptr;
2772 out:
2773        ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2774        asc_dvc->ptr_map[i] = ptr;
2775        return i + 1;
2776}
2777
2778static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2779{
2780        void *ptr;
2781
2782        srb--;
2783        if (srb >= asc_dvc->ptr_map_count) {
2784                printk("advansys: bad SRB %u, max %u\n", srb,
2785                                                        asc_dvc->ptr_map_count);
2786                return NULL;
2787        }
2788        ptr = asc_dvc->ptr_map[srb];
2789        asc_dvc->ptr_map[srb] = NULL;
2790        ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2791        return ptr;
2792}
2793
2794/*
2795 * advansys_info()
2796 *
2797 * Return suitable for printing on the console with the argument
2798 * adapter's configuration information.
2799 *
2800 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2801 * otherwise the static 'info' array will be overrun.
2802 */
2803static const char *advansys_info(struct Scsi_Host *shost)
2804{
2805        static char info[ASC_INFO_SIZE];
2806        struct asc_board *boardp = shost_priv(shost);
2807        ASC_DVC_VAR *asc_dvc_varp;
2808        ADV_DVC_VAR *adv_dvc_varp;
2809        char *busname;
2810        char *widename = NULL;
2811
2812        if (ASC_NARROW_BOARD(boardp)) {
2813                asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2814                ASC_DBG(1, "begin\n");
2815                if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2816                        if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2817                            ASC_IS_ISAPNP) {
2818                                busname = "ISA PnP";
2819                        } else {
2820                                busname = "ISA";
2821                        }
2822                        sprintf(info,
2823                                "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2824                                ASC_VERSION, busname,
2825                                (ulong)shost->io_port,
2826                                (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2827                                boardp->irq, shost->dma_channel);
2828                } else {
2829                        if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2830                                busname = "VL";
2831                        } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2832                                busname = "EISA";
2833                        } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2834                                if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2835                                    == ASC_IS_PCI_ULTRA) {
2836                                        busname = "PCI Ultra";
2837                                } else {
2838                                        busname = "PCI";
2839                                }
2840                        } else {
2841                                busname = "?";
2842                                shost_printk(KERN_ERR, shost, "unknown bus "
2843                                        "type %d\n", asc_dvc_varp->bus_type);
2844                        }
2845                        sprintf(info,
2846                                "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2847                                ASC_VERSION, busname, (ulong)shost->io_port,
2848                                (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2849                                boardp->irq);
2850                }
2851        } else {
2852                /*
2853                 * Wide Adapter Information
2854                 *
2855                 * Memory-mapped I/O is used instead of I/O space to access
2856                 * the adapter, but display the I/O Port range. The Memory
2857                 * I/O address is displayed through the driver /proc file.
2858                 */
2859                adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2860                if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2861                        widename = "Ultra-Wide";
2862                } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2863                        widename = "Ultra2-Wide";
2864                } else {
2865                        widename = "Ultra3-Wide";
2866                }
2867                sprintf(info,
2868                        "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2869                        ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2870                        (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2871        }
2872        BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2873        ASC_DBG(1, "end\n");
2874        return info;
2875}
2876
2877#ifdef CONFIG_PROC_FS
2878/*
2879 * asc_prt_line()
2880 *
2881 * If 'cp' is NULL print to the console, otherwise print to a buffer.
2882 *
2883 * Return 0 if printing to the console, otherwise return the number of
2884 * bytes written to the buffer.
2885 *
2886 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2887 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2888 */
2889static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2890{
2891        va_list args;
2892        int ret;
2893        char s[ASC_PRTLINE_SIZE];
2894
2895        va_start(args, fmt);
2896        ret = vsprintf(s, fmt, args);
2897        BUG_ON(ret >= ASC_PRTLINE_SIZE);
2898        if (buf == NULL) {
2899                (void)printk(s);
2900                ret = 0;
2901        } else {
2902                ret = min(buflen, ret);
2903                memcpy(buf, s, ret);
2904        }
2905        va_end(args);
2906        return ret;
2907}
2908
2909/*
2910 * asc_prt_board_devices()
2911 *
2912 * Print driver information for devices attached to the board.
2913 *
2914 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2915 * cf. asc_prt_line().
2916 *
2917 * Return the number of characters copied into 'cp'. No more than
2918 * 'cplen' characters will be copied to 'cp'.
2919 */
2920static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2921{
2922        struct asc_board *boardp = shost_priv(shost);
2923        int leftlen;
2924        int totlen;
2925        int len;
2926        int chip_scsi_id;
2927        int i;
2928
2929        leftlen = cplen;
2930        totlen = len = 0;
2931
2932        len = asc_prt_line(cp, leftlen,
2933                           "\nDevice Information for AdvanSys SCSI Host %d:\n",
2934                           shost->host_no);
2935        ASC_PRT_NEXT();
2936
2937        if (ASC_NARROW_BOARD(boardp)) {
2938                chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2939        } else {
2940                chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2941        }
2942
2943        len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2944        ASC_PRT_NEXT();
2945        for (i = 0; i <= ADV_MAX_TID; i++) {
2946                if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2947                        len = asc_prt_line(cp, leftlen, " %X,", i);
2948                        ASC_PRT_NEXT();
2949                }
2950        }
2951        len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2952        ASC_PRT_NEXT();
2953
2954        return totlen;
2955}
2956
2957/*
2958 * Display Wide Board BIOS Information.
2959 */
2960static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2961{
2962        struct asc_board *boardp = shost_priv(shost);
2963        int leftlen;
2964        int totlen;
2965        int len;
2966        ushort major, minor, letter;
2967
2968        leftlen = cplen;
2969        totlen = len = 0;
2970
2971        len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2972        ASC_PRT_NEXT();
2973
2974        /*
2975         * If the BIOS saved a valid signature, then fill in
2976         * the BIOS code segment base address.
2977         */
2978        if (boardp->bios_signature != 0x55AA) {
2979                len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2980                ASC_PRT_NEXT();
2981                len = asc_prt_line(cp, leftlen,
2982                                   "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2983                ASC_PRT_NEXT();
2984                len = asc_prt_line(cp, leftlen,
2985                                   "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2986                ASC_PRT_NEXT();
2987        } else {
2988                major = (boardp->bios_version >> 12) & 0xF;
2989                minor = (boardp->bios_version >> 8) & 0xF;
2990                letter = (boardp->bios_version & 0xFF);
2991
2992                len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2993                                   major, minor,
2994                                   letter >= 26 ? '?' : letter + 'A');
2995                ASC_PRT_NEXT();
2996
2997                /*
2998                 * Current available ROM BIOS release is 3.1I for UW
2999                 * and 3.2I for U2W. This code doesn't differentiate
3000                 * UW and U2W boards.
3001                 */
3002                if (major < 3 || (major <= 3 && minor < 1) ||
3003                    (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3004                        len = asc_prt_line(cp, leftlen,
3005                                           "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3006                        ASC_PRT_NEXT();
3007                        len = asc_prt_line(cp, leftlen,
3008                                           "ftp://ftp.connectcom.net/pub\n");
3009                        ASC_PRT_NEXT();
3010                }
3011        }
3012
3013        return totlen;
3014}
3015
3016/*
3017 * Add serial number to information bar if signature AAh
3018 * is found in at bit 15-9 (7 bits) of word 1.
3019 *
3020 * Serial Number consists fo 12 alpha-numeric digits.
3021 *
3022 *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
3023 *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
3024 *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
3025 *       5 - Product revision (A-J)    Word0:  "         "
3026 *
3027 *           Signature                 Word1: 15-9 (7 bits)
3028 *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3029 *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
3030 *
3031 *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3032 *
3033 * Note 1: Only production cards will have a serial number.
3034 *
3035 * Note 2: Signature is most significant 7 bits (0xFE).
3036 *
3037 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3038 */
3039static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3040{
3041        ushort w, num;
3042
3043        if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3044                return ASC_FALSE;
3045        } else {
3046                /*
3047                 * First word - 6 digits.
3048                 */
3049                w = serialnum[0];
3050
3051                /* Product type - 1st digit. */
3052                if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3053                        /* Product type is P=Prototype */
3054                        *cp += 0x8;
3055                }
3056                cp++;
3057
3058                /* Manufacturing location - 2nd digit. */
3059                *cp++ = 'A' + ((w & 0x1C00) >> 10);
3060
3061                /* Product ID - 3rd, 4th digits. */
3062                num = w & 0x3FF;
3063                *cp++ = '0' + (num / 100);
3064                num %= 100;
3065                *cp++ = '0' + (num / 10);
3066
3067                /* Product revision - 5th digit. */
3068                *cp++ = 'A' + (num % 10);
3069
3070                /*
3071                 * Second word
3072                 */
3073                w = serialnum[1];
3074
3075                /*
3076                 * Year - 6th digit.
3077                 *
3078                 * If bit 15 of third word is set, then the
3079                 * last digit of the year is greater than 7.
3080                 */
3081                if (serialnum[2] & 0x8000) {
3082                        *cp++ = '8' + ((w & 0x1C0) >> 6);
3083                } else {
3084                        *cp++ = '0' + ((w & 0x1C0) >> 6);
3085                }
3086
3087                /* Week of year - 7th, 8th digits. */
3088                num = w & 0x003F;
3089                *cp++ = '0' + num / 10;
3090                num %= 10;
3091                *cp++ = '0' + num;
3092
3093                /*
3094                 * Third word
3095                 */
3096                w = serialnum[2] & 0x7FFF;
3097
3098                /* Serial number - 9th digit. */
3099                *cp++ = 'A' + (w / 1000);
3100
3101                /* 10th, 11th, 12th digits. */
3102                num = w % 1000;
3103                *cp++ = '0' + num / 100;
3104                num %= 100;
3105                *cp++ = '0' + num / 10;
3106                num %= 10;
3107                *cp++ = '0' + num;
3108
3109                *cp = '\0';     /* Null Terminate the string. */
3110                return ASC_TRUE;
3111        }
3112}
3113
3114/*
3115 * asc_prt_asc_board_eeprom()
3116 *
3117 * Print board EEPROM configuration.
3118 *
3119 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3120 * cf. asc_prt_line().
3121 *
3122 * Return the number of characters copied into 'cp'. No more than
3123 * 'cplen' characters will be copied to 'cp'.
3124 */
3125static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3126{
3127        struct asc_board *boardp = shost_priv(shost);
3128        ASC_DVC_VAR *asc_dvc_varp;
3129        int leftlen;
3130        int totlen;
3131        int len;
3132        ASCEEP_CONFIG *ep;
3133        int i;
3134#ifdef CONFIG_ISA
3135        int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3136#endif /* CONFIG_ISA */
3137        uchar serialstr[13];
3138
3139        asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3140        ep = &boardp->eep_config.asc_eep;
3141
3142        leftlen = cplen;
3143        totlen = len = 0;
3144
3145        len = asc_prt_line(cp, leftlen,
3146                           "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3147                           shost->host_no);
3148        ASC_PRT_NEXT();
3149
3150        if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3151            == ASC_TRUE) {
3152                len =
3153                    asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3154                                 serialstr);
3155                ASC_PRT_NEXT();
3156        } else {
3157                if (ep->adapter_info[5] == 0xBB) {
3158                        len = asc_prt_line(cp, leftlen,
3159                                           " Default Settings Used for EEPROM-less Adapter.\n");
3160                        ASC_PRT_NEXT();
3161                } else {
3162                        len = asc_prt_line(cp, leftlen,
3163                                           " Serial Number Signature Not Present.\n");
3164                        ASC_PRT_NEXT();
3165                }
3166        }
3167
3168        len = asc_prt_line(cp, leftlen,
3169                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3170                           ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3171                           ep->max_tag_qng);
3172        ASC_PRT_NEXT();
3173
3174        len = asc_prt_line(cp, leftlen,
3175                           " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3176        ASC_PRT_NEXT();
3177
3178        len = asc_prt_line(cp, leftlen, " Target ID:           ");
3179        ASC_PRT_NEXT();
3180        for (i = 0; i <= ASC_MAX_TID; i++) {
3181                len = asc_prt_line(cp, leftlen, " %d", i);
3182                ASC_PRT_NEXT();
3183        }
3184        len = asc_prt_line(cp, leftlen, "\n");
3185        ASC_PRT_NEXT();
3186
3187        len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3188        ASC_PRT_NEXT();
3189        for (i = 0; i <= ASC_MAX_TID; i++) {
3190                len = asc_prt_line(cp, leftlen, " %c",
3191                                   (ep->
3192                                    disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3193                                   'N');
3194                ASC_PRT_NEXT();
3195        }
3196        len = asc_prt_line(cp, leftlen, "\n");
3197        ASC_PRT_NEXT();
3198
3199        len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3200        ASC_PRT_NEXT();
3201        for (i = 0; i <= ASC_MAX_TID; i++) {
3202                len = asc_prt_line(cp, leftlen, " %c",
3203                                   (ep->
3204                                    use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3205                                   'N');
3206                ASC_PRT_NEXT();
3207        }
3208        len = asc_prt_line(cp, leftlen, "\n");
3209        ASC_PRT_NEXT();
3210
3211        len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3212        ASC_PRT_NEXT();
3213        for (i = 0; i <= ASC_MAX_TID; i++) {
3214                len = asc_prt_line(cp, leftlen, " %c",
3215                                   (ep->
3216                                    start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3217                                   'N');
3218                ASC_PRT_NEXT();
3219        }
3220        len = asc_prt_line(cp, leftlen, "\n");
3221        ASC_PRT_NEXT();
3222
3223        len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3224        ASC_PRT_NEXT();
3225        for (i = 0; i <= ASC_MAX_TID; i++) {
3226                len = asc_prt_line(cp, leftlen, " %c",
3227                                   (ep->
3228                                    init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3229                                   'N');
3230                ASC_PRT_NEXT();
3231        }
3232        len = asc_prt_line(cp, leftlen, "\n");
3233        ASC_PRT_NEXT();
3234
3235#ifdef CONFIG_ISA
3236        if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3237                len = asc_prt_line(cp, leftlen,
3238                                   " Host ISA DMA speed:   %d MB/S\n",
3239                                   isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3240                ASC_PRT_NEXT();
3241        }
3242#endif /* CONFIG_ISA */
3243
3244        return totlen;
3245}
3246
3247/*
3248 * asc_prt_adv_board_eeprom()
3249 *
3250 * Print board EEPROM configuration.
3251 *
3252 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3253 * cf. asc_prt_line().
3254 *
3255 * Return the number of characters copied into 'cp'. No more than
3256 * 'cplen' characters will be copied to 'cp'.
3257 */
3258static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3259{
3260        struct asc_board *boardp = shost_priv(shost);
3261        ADV_DVC_VAR *adv_dvc_varp;
3262        int leftlen;
3263        int totlen;
3264        int len;
3265        int i;
3266        char *termstr;
3267        uchar serialstr[13];
3268        ADVEEP_3550_CONFIG *ep_3550 = NULL;
3269        ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3270        ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3271        ushort word;
3272        ushort *wordp;
3273        ushort sdtr_speed = 0;
3274
3275        adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3276        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3277                ep_3550 = &boardp->eep_config.adv_3550_eep;
3278        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3279                ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3280        } else {
3281                ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3282        }
3283
3284        leftlen = cplen;
3285        totlen = len = 0;
3286
3287        len = asc_prt_line(cp, leftlen,
3288                           "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3289                           shost->host_no);
3290        ASC_PRT_NEXT();
3291
3292        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3293                wordp = &ep_3550->serial_number_word1;
3294        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3295                wordp = &ep_38C0800->serial_number_word1;
3296        } else {
3297                wordp = &ep_38C1600->serial_number_word1;
3298        }
3299
3300        if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3301                len =
3302                    asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3303                                 serialstr);
3304                ASC_PRT_NEXT();
3305        } else {
3306                len = asc_prt_line(cp, leftlen,
3307                                   " Serial Number Signature Not Present.\n");
3308                ASC_PRT_NEXT();
3309        }
3310
3311        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3312                len = asc_prt_line(cp, leftlen,
3313                                   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3314                                   ep_3550->adapter_scsi_id,
3315                                   ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3316                ASC_PRT_NEXT();
3317        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3318                len = asc_prt_line(cp, leftlen,
3319                                   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3320                                   ep_38C0800->adapter_scsi_id,
3321                                   ep_38C0800->max_host_qng,
3322                                   ep_38C0800->max_dvc_qng);
3323                ASC_PRT_NEXT();
3324        } else {
3325                len = asc_prt_line(cp, leftlen,
3326                                   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3327                                   ep_38C1600->adapter_scsi_id,
3328                                   ep_38C1600->max_host_qng,
3329                                   ep_38C1600->max_dvc_qng);
3330                ASC_PRT_NEXT();
3331        }
3332        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3333                word = ep_3550->termination;
3334        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3335                word = ep_38C0800->termination_lvd;
3336        } else {
3337                word = ep_38C1600->termination_lvd;
3338        }
3339        switch (word) {
3340        case 1:
3341                termstr = "Low Off/High Off";
3342                break;
3343        case 2:
3344                termstr = "Low Off/High On";
3345                break;
3346        case 3:
3347                termstr = "Low On/High On";
3348                break;
3349        default:
3350        case 0:
3351                termstr = "Automatic";
3352                break;
3353        }
3354
3355        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3356                len = asc_prt_line(cp, leftlen,
3357                                   " termination: %u (%s), bios_ctrl: 0x%x\n",
3358                                   ep_3550->termination, termstr,
3359                                   ep_3550->bios_ctrl);
3360                ASC_PRT_NEXT();
3361        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3362                len = asc_prt_line(cp, leftlen,
3363                                   " termination: %u (%s), bios_ctrl: 0x%x\n",
3364                                   ep_38C0800->termination_lvd, termstr,
3365                                   ep_38C0800->bios_ctrl);
3366                ASC_PRT_NEXT();
3367        } else {
3368                len = asc_prt_line(cp, leftlen,
3369                                   " termination: %u (%s), bios_ctrl: 0x%x\n",
3370                                   ep_38C1600->termination_lvd, termstr,
3371                                   ep_38C1600->bios_ctrl);
3372                ASC_PRT_NEXT();
3373        }
3374
3375        len = asc_prt_line(cp, leftlen, " Target ID:           ");
3376        ASC_PRT_NEXT();
3377        for (i = 0; i <= ADV_MAX_TID; i++) {
3378                len = asc_prt_line(cp, leftlen, " %X", i);
3379                ASC_PRT_NEXT();
3380        }
3381        len = asc_prt_line(cp, leftlen, "\n");
3382        ASC_PRT_NEXT();
3383
3384        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3385                word = ep_3550->disc_enable;
3386        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3387                word = ep_38C0800->disc_enable;
3388        } else {
3389                word = ep_38C1600->disc_enable;
3390        }
3391        len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3392        ASC_PRT_NEXT();
3393        for (i = 0; i <= ADV_MAX_TID; i++) {
3394                len = asc_prt_line(cp, leftlen, " %c",
3395                                   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3396                ASC_PRT_NEXT();
3397        }
3398        len = asc_prt_line(cp, leftlen, "\n");
3399        ASC_PRT_NEXT();
3400
3401        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3402                word = ep_3550->tagqng_able;
3403        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3404                word = ep_38C0800->tagqng_able;
3405        } else {
3406                word = ep_38C1600->tagqng_able;
3407        }
3408        len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3409        ASC_PRT_NEXT();
3410        for (i = 0; i <= ADV_MAX_TID; i++) {
3411                len = asc_prt_line(cp, leftlen, " %c",
3412                                   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3413                ASC_PRT_NEXT();
3414        }
3415        len = asc_prt_line(cp, leftlen, "\n");
3416        ASC_PRT_NEXT();
3417
3418        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3419                word = ep_3550->start_motor;
3420        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3421                word = ep_38C0800->start_motor;
3422        } else {
3423                word = ep_38C1600->start_motor;
3424        }
3425        len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3426        ASC_PRT_NEXT();
3427        for (i = 0; i <= ADV_MAX_TID; i++) {
3428                len = asc_prt_line(cp, leftlen, " %c",
3429                                   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3430                ASC_PRT_NEXT();
3431        }
3432        len = asc_prt_line(cp, leftlen, "\n");
3433        ASC_PRT_NEXT();
3434
3435        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3436                len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3437                ASC_PRT_NEXT();
3438                for (i = 0; i <= ADV_MAX_TID; i++) {
3439                        len = asc_prt_line(cp, leftlen, " %c",
3440                                           (ep_3550->
3441                                            sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3442                                           'Y' : 'N');
3443                        ASC_PRT_NEXT();
3444                }
3445                len = asc_prt_line(cp, leftlen, "\n");
3446                ASC_PRT_NEXT();
3447        }
3448
3449        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3450                len = asc_prt_line(cp, leftlen, " Ultra Transfer:      ");
3451                ASC_PRT_NEXT();
3452                for (i = 0; i <= ADV_MAX_TID; i++) {
3453                        len = asc_prt_line(cp, leftlen, " %c",
3454                                           (ep_3550->
3455                                            ultra_able & ADV_TID_TO_TIDMASK(i))
3456                                           ? 'Y' : 'N');
3457                        ASC_PRT_NEXT();
3458                }
3459                len = asc_prt_line(cp, leftlen, "\n");
3460                ASC_PRT_NEXT();
3461        }
3462
3463        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3464                word = ep_3550->wdtr_able;
3465        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3466                word = ep_38C0800->wdtr_able;
3467        } else {
3468                word = ep_38C1600->wdtr_able;
3469        }
3470        len = asc_prt_line(cp, leftlen, " Wide Transfer:       ");
3471        ASC_PRT_NEXT();
3472        for (i = 0; i <= ADV_MAX_TID; i++) {
3473                len = asc_prt_line(cp, leftlen, " %c",
3474                                   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3475                ASC_PRT_NEXT();
3476        }
3477        len = asc_prt_line(cp, leftlen, "\n");
3478        ASC_PRT_NEXT();
3479
3480        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3481            adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3482                len = asc_prt_line(cp, leftlen,
3483                                   " Synchronous Transfer Speed (Mhz):\n  ");
3484                ASC_PRT_NEXT();
3485                for (i = 0; i <= ADV_MAX_TID; i++) {
3486                        char *speed_str;
3487
3488                        if (i == 0) {
3489                                sdtr_speed = adv_dvc_varp->sdtr_speed1;
3490                        } else if (i == 4) {
3491                                sdtr_speed = adv_dvc_varp->sdtr_speed2;
3492                        } else if (i == 8) {
3493                                sdtr_speed = adv_dvc_varp->sdtr_speed3;
3494                        } else if (i == 12) {
3495                                sdtr_speed = adv_dvc_varp->sdtr_speed4;
3496                        }
3497                        switch (sdtr_speed & ADV_MAX_TID) {
3498                        case 0:
3499                                speed_str = "Off";
3500                                break;
3501                        case 1:
3502                                speed_str = "  5";
3503                                break;
3504                        case 2:
3505                                speed_str = " 10";
3506                                break;
3507                        case 3:
3508                                speed_str = " 20";
3509                                break;
3510                        case 4:
3511                                speed_str = " 40";
3512                                break;
3513                        case 5:
3514                                speed_str = " 80";
3515                                break;
3516                        default:
3517                                speed_str = "Unk";
3518                                break;
3519                        }
3520                        len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3521                        ASC_PRT_NEXT();
3522                        if (i == 7) {
3523                                len = asc_prt_line(cp, leftlen, "\n  ");
3524                                ASC_PRT_NEXT();
3525                        }
3526                        sdtr_speed >>= 4;
3527                }
3528                len = asc_prt_line(cp, leftlen, "\n");
3529                ASC_PRT_NEXT();
3530        }
3531
3532        return totlen;
3533}
3534
3535/*
3536 * asc_prt_driver_conf()
3537 *
3538 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3539 * cf. asc_prt_line().
3540 *
3541 * Return the number of characters copied into 'cp'. No more than
3542 * 'cplen' characters will be copied to 'cp'.
3543 */
3544static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3545{
3546        struct asc_board *boardp = shost_priv(shost);
3547        int leftlen;
3548        int totlen;
3549        int len;
3550        int chip_scsi_id;
3551
3552        leftlen = cplen;
3553        totlen = len = 0;
3554
3555        len = asc_prt_line(cp, leftlen,
3556                           "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3557                           shost->host_no);
3558        ASC_PRT_NEXT();
3559
3560        len = asc_prt_line(cp, leftlen,
3561                           " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3562                           shost->host_busy, shost->last_reset, shost->max_id,
3563                           shost->max_lun, shost->max_channel);
3564        ASC_PRT_NEXT();
3565
3566        len = asc_prt_line(cp, leftlen,
3567                           " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3568                           shost->unique_id, shost->can_queue, shost->this_id,
3569                           shost->sg_tablesize, shost->cmd_per_lun);
3570        ASC_PRT_NEXT();
3571
3572        len = asc_prt_line(cp, leftlen,
3573                           " unchecked_isa_dma %d, use_clustering %d\n",
3574                           shost->unchecked_isa_dma, shost->use_clustering);
3575        ASC_PRT_NEXT();
3576
3577        len = asc_prt_line(cp, leftlen,
3578                           " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3579                           boardp->flags, boardp->last_reset, jiffies,
3580                           boardp->asc_n_io_port);
3581        ASC_PRT_NEXT();
3582
3583        len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3584        ASC_PRT_NEXT();
3585
3586        if (ASC_NARROW_BOARD(boardp)) {
3587                chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3588        } else {
3589                chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3590        }
3591
3592        return totlen;
3593}
3594
3595/*
3596 * asc_prt_asc_board_info()
3597 *
3598 * Print dynamic board configuration information.
3599 *
3600 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3601 * cf. asc_prt_line().
3602 *
3603 * Return the number of characters copied into 'cp'. No more than
3604 * 'cplen' characters will be copied to 'cp'.
3605 */
3606static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3607{
3608        struct asc_board *boardp = shost_priv(shost);
3609        int chip_scsi_id;
3610        int leftlen;
3611        int totlen;
3612        int len;
3613        ASC_DVC_VAR *v;
3614        ASC_DVC_CFG *c;
3615        int i;
3616        int renegotiate = 0;
3617
3618        v = &boardp->dvc_var.asc_dvc_var;
3619        c = &boardp->dvc_cfg.asc_dvc_cfg;
3620        chip_scsi_id = c->chip_scsi_id;
3621
3622        leftlen = cplen;
3623        totlen = len = 0;
3624
3625        len = asc_prt_line(cp, leftlen,
3626                           "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3627                           shost->host_no);
3628        ASC_PRT_NEXT();
3629
3630        len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3631                           "mcode_version 0x%x, err_code %u\n",
3632                           c->chip_version, c->mcode_date, c->mcode_version,
3633                           v->err_code);
3634        ASC_PRT_NEXT();
3635
3636        /* Current number of commands waiting for the host. */
3637        len = asc_prt_line(cp, leftlen,
3638                           " Total Command Pending: %d\n", v->cur_total_qng);
3639        ASC_PRT_NEXT();
3640
3641        len = asc_prt_line(cp, leftlen, " Command Queuing:");
3642        ASC_PRT_NEXT();
3643        for (i = 0; i <= ASC_MAX_TID; i++) {
3644                if ((chip_scsi_id == i) ||
3645                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3646                        continue;
3647                }
3648                len = asc_prt_line(cp, leftlen, " %X:%c",
3649                                   i,
3650                                   (v->
3651                                    use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3652                                   'Y' : 'N');
3653                ASC_PRT_NEXT();
3654        }
3655        len = asc_prt_line(cp, leftlen, "\n");
3656        ASC_PRT_NEXT();
3657
3658        /* Current number of commands waiting for a device. */
3659        len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3660        ASC_PRT_NEXT();
3661        for (i = 0; i <= ASC_MAX_TID; i++) {
3662                if ((chip_scsi_id == i) ||
3663                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3664                        continue;
3665                }
3666                len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3667                ASC_PRT_NEXT();
3668        }
3669        len = asc_prt_line(cp, leftlen, "\n");
3670        ASC_PRT_NEXT();
3671
3672        /* Current limit on number of commands that can be sent to a device. */
3673        len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3674        ASC_PRT_NEXT();
3675        for (i = 0; i <= ASC_MAX_TID; i++) {
3676                if ((chip_scsi_id == i) ||
3677                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3678                        continue;
3679                }
3680                len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3681                ASC_PRT_NEXT();
3682        }
3683        len = asc_prt_line(cp, leftlen, "\n");
3684        ASC_PRT_NEXT();
3685
3686        /* Indicate whether the device has returned queue full status. */
3687        len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3688        ASC_PRT_NEXT();
3689        for (i = 0; i <= ASC_MAX_TID; i++) {
3690                if ((chip_scsi_id == i) ||
3691                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3692                        continue;
3693                }
3694                if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3695                        len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3696                                           i, boardp->queue_full_cnt[i]);
3697                } else {
3698                        len = asc_prt_line(cp, leftlen, " %X:N", i);
3699                }
3700                ASC_PRT_NEXT();
3701        }
3702        len = asc_prt_line(cp, leftlen, "\n");
3703        ASC_PRT_NEXT();
3704
3705        len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3706        ASC_PRT_NEXT();
3707        for (i = 0; i <= ASC_MAX_TID; i++) {
3708                if ((chip_scsi_id == i) ||
3709                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3710                        continue;
3711                }
3712                len = asc_prt_line(cp, leftlen, " %X:%c",
3713                                   i,
3714                                   (v->
3715                                    sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3716                                   'N');
3717                ASC_PRT_NEXT();
3718        }
3719        len = asc_prt_line(cp, leftlen, "\n");
3720        ASC_PRT_NEXT();
3721
3722        for (i = 0; i <= ASC_MAX_TID; i++) {
3723                uchar syn_period_ix;
3724
3725                if ((chip_scsi_id == i) ||
3726                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3727                    ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3728                        continue;
3729                }
3730
3731                len = asc_prt_line(cp, leftlen, "  %X:", i);
3732                ASC_PRT_NEXT();
3733
3734                if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3735                        len = asc_prt_line(cp, leftlen, " Asynchronous");
3736                        ASC_PRT_NEXT();
3737                } else {
3738                        syn_period_ix =
3739                            (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3740                                                           1);
3741
3742                        len = asc_prt_line(cp, leftlen,
3743                                           " Transfer Period Factor: %d (%d.%d Mhz),",
3744                                           v->sdtr_period_tbl[syn_period_ix],
3745                                           250 /
3746                                           v->sdtr_period_tbl[syn_period_ix],
3747                                           ASC_TENTHS(250,
3748                                                      v->
3749                                                      sdtr_period_tbl
3750                                                      [syn_period_ix]));
3751                        ASC_PRT_NEXT();
3752
3753                        len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3754                                           boardp->
3755                                           sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3756                        ASC_PRT_NEXT();
3757                }
3758
3759                if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3760                        len = asc_prt_line(cp, leftlen, "*\n");
3761                        renegotiate = 1;
3762                } else {
3763                        len = asc_prt_line(cp, leftlen, "\n");
3764                }
3765                ASC_PRT_NEXT();
3766        }
3767
3768        if (renegotiate) {
3769                len = asc_prt_line(cp, leftlen,
3770                                   " * = Re-negotiation pending before next command.\n");
3771                ASC_PRT_NEXT();
3772        }
3773
3774        return totlen;
3775}
3776
3777/*
3778 * asc_prt_adv_board_info()
3779 *
3780 * Print dynamic board configuration information.
3781 *
3782 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3783 * cf. asc_prt_line().
3784 *
3785 * Return the number of characters copied into 'cp'. No more than
3786 * 'cplen' characters will be copied to 'cp'.
3787 */
3788static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3789{
3790        struct asc_board *boardp = shost_priv(shost);
3791        int leftlen;
3792        int totlen;
3793        int len;
3794        int i;
3795        ADV_DVC_VAR *v;
3796        ADV_DVC_CFG *c;
3797        AdvPortAddr iop_base;
3798        ushort chip_scsi_id;
3799        ushort lramword;
3800        uchar lrambyte;
3801        ushort tagqng_able;
3802        ushort sdtr_able, wdtr_able;
3803        ushort wdtr_done, sdtr_done;
3804        ushort period = 0;
3805        int renegotiate = 0;
3806
3807        v = &boardp->dvc_var.adv_dvc_var;
3808        c = &boardp->dvc_cfg.adv_dvc_cfg;
3809        iop_base = v->iop_base;
3810        chip_scsi_id = v->chip_scsi_id;
3811
3812        leftlen = cplen;
3813        totlen = len = 0;
3814
3815        len = asc_prt_line(cp, leftlen,
3816                           "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3817                           shost->host_no);
3818        ASC_PRT_NEXT();
3819
3820        len = asc_prt_line(cp, leftlen,
3821                           " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3822                           v->iop_base,
3823                           AdvReadWordRegister(iop_base,
3824                                               IOPW_SCSI_CFG1) & CABLE_DETECT,
3825                           v->err_code);
3826        ASC_PRT_NEXT();
3827
3828        len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3829                           "mcode_version 0x%x\n", c->chip_version,
3830                           c->mcode_date, c->mcode_version);
3831        ASC_PRT_NEXT();
3832
3833        AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3834        len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3835        ASC_PRT_NEXT();
3836        for (i = 0; i <= ADV_MAX_TID; i++) {
3837                if ((chip_scsi_id == i) ||
3838                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3839                        continue;
3840                }
3841
3842                len = asc_prt_line(cp, leftlen, " %X:%c",
3843                                   i,
3844                                   (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3845                                   'N');
3846                ASC_PRT_NEXT();
3847        }
3848        len = asc_prt_line(cp, leftlen, "\n");
3849        ASC_PRT_NEXT();
3850
3851        len = asc_prt_line(cp, leftlen, " Queue Limit:");
3852        ASC_PRT_NEXT();
3853        for (i = 0; i <= ADV_MAX_TID; i++) {
3854                if ((chip_scsi_id == i) ||
3855                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3856                        continue;
3857                }
3858
3859                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3860                                lrambyte);
3861
3862                len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3863                ASC_PRT_NEXT();
3864        }
3865        len = asc_prt_line(cp, leftlen, "\n");
3866        ASC_PRT_NEXT();
3867
3868        len = asc_prt_line(cp, leftlen, " Command Pending:");
3869        ASC_PRT_NEXT();
3870        for (i = 0; i <= ADV_MAX_TID; i++) {
3871                if ((chip_scsi_id == i) ||
3872                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3873                        continue;
3874                }
3875
3876                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3877                                lrambyte);
3878
3879                len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3880                ASC_PRT_NEXT();
3881        }
3882        len = asc_prt_line(cp, leftlen, "\n");
3883        ASC_PRT_NEXT();
3884
3885        AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3886        len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3887        ASC_PRT_NEXT();
3888        for (i = 0; i <= ADV_MAX_TID; i++) {
3889                if ((chip_scsi_id == i) ||
3890                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3891                        continue;
3892                }
3893
3894                len = asc_prt_line(cp, leftlen, " %X:%c",
3895                                   i,
3896                                   (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3897                                   'N');
3898                ASC_PRT_NEXT();
3899        }
3900        len = asc_prt_line(cp, leftlen, "\n");
3901        ASC_PRT_NEXT();
3902
3903        AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3904        len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3905        ASC_PRT_NEXT();
3906        for (i = 0; i <= ADV_MAX_TID; i++) {
3907                if ((chip_scsi_id == i) ||
3908                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3909                        continue;
3910                }
3911
3912                AdvReadWordLram(iop_base,
3913                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3914                                lramword);
3915
3916                len = asc_prt_line(cp, leftlen, " %X:%d",
3917                                   i, (lramword & 0x8000) ? 16 : 8);
3918                ASC_PRT_NEXT();
3919
3920                if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3921                    (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3922                        len = asc_prt_line(cp, leftlen, "*");
3923                        ASC_PRT_NEXT();
3924                        renegotiate = 1;
3925                }
3926        }
3927        len = asc_prt_line(cp, leftlen, "\n");
3928        ASC_PRT_NEXT();
3929
3930        AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3931        len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3932        ASC_PRT_NEXT();
3933        for (i = 0; i <= ADV_MAX_TID; i++) {
3934                if ((chip_scsi_id == i) ||
3935                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3936                        continue;
3937                }
3938
3939                len = asc_prt_line(cp, leftlen, " %X:%c",
3940                                   i,
3941                                   (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3942                                   'N');
3943                ASC_PRT_NEXT();
3944        }
3945        len = asc_prt_line(cp, leftlen, "\n");
3946        ASC_PRT_NEXT();
3947
3948        AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3949        for (i = 0; i <= ADV_MAX_TID; i++) {
3950
3951                AdvReadWordLram(iop_base,
3952                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3953                                lramword);
3954                lramword &= ~0x8000;
3955
3956                if ((chip_scsi_id == i) ||
3957                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3958                    ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3959                        continue;
3960                }
3961
3962                len = asc_prt_line(cp, leftlen, "  %X:", i);
3963                ASC_PRT_NEXT();
3964
3965                if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3966                        len = asc_prt_line(cp, leftlen, " Asynchronous");
3967                        ASC_PRT_NEXT();
3968                } else {
3969                        len =
3970                            asc_prt_line(cp, leftlen,
3971                                         " Transfer Period Factor: ");
3972                        ASC_PRT_NEXT();
3973
3974                        if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3975                                len =
3976                                    asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3977                                ASC_PRT_NEXT();
3978                        } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3979                                len =
3980                                    asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3981                                ASC_PRT_NEXT();
3982                        } else {        /* 20 Mhz or below. */
3983
3984                                period = (((lramword >> 8) * 25) + 50) / 4;
3985
3986                                if (period == 0) {      /* Should never happen. */
3987                                        len =
3988                                            asc_prt_line(cp, leftlen,
3989                                                         "%d (? Mhz), ");
3990                                        ASC_PRT_NEXT();
3991                                } else {
3992                                        len = asc_prt_line(cp, leftlen,
3993                                                           "%d (%d.%d Mhz),",
3994                                                           period, 250 / period,
3995                                                           ASC_TENTHS(250,
3996                                                                      period));
3997                                        ASC_PRT_NEXT();
3998                                }
3999                        }
4000
4001                        len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4002                                           lramword & 0x1F);
4003                        ASC_PRT_NEXT();
4004                }
4005
4006                if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4007                        len = asc_prt_line(cp, leftlen, "*\n");
4008                        renegotiate = 1;
4009                } else {
4010                        len = asc_prt_line(cp, leftlen, "\n");
4011                }
4012                ASC_PRT_NEXT();
4013        }
4014
4015        if (renegotiate) {
4016                len = asc_prt_line(cp, leftlen,
4017                                   " * = Re-negotiation pending before next command.\n");
4018                ASC_PRT_NEXT();
4019        }
4020
4021        return totlen;
4022}
4023
4024/*
4025 * asc_proc_copy()
4026 *
4027 * Copy proc information to a read buffer taking into account the current
4028 * read offset in the file and the remaining space in the read buffer.
4029 */
4030static int
4031asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4032              char *cp, int cplen)
4033{
4034        int cnt = 0;
4035
4036        ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4037                 (unsigned)offset, (unsigned)advoffset, cplen);
4038        if (offset <= advoffset) {
4039                /* Read offset below current offset, copy everything. */
4040                cnt = min(cplen, leftlen);
4041                ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4042                         (ulong)curbuf, (ulong)cp, cnt);
4043                memcpy(curbuf, cp, cnt);
4044        } else if (offset < advoffset + cplen) {
4045                /* Read offset within current range, partial copy. */
4046                cnt = (advoffset + cplen) - offset;
4047                cp = (cp + cplen) - cnt;
4048                cnt = min(cnt, leftlen);
4049                ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4050                         (ulong)curbuf, (ulong)cp, cnt);
4051                memcpy(curbuf, cp, cnt);
4052        }
4053        return cnt;
4054}
4055
4056#ifdef ADVANSYS_STATS
4057/*
4058 * asc_prt_board_stats()
4059 *
4060 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4061 * cf. asc_prt_line().
4062 *
4063 * Return the number of characters copied into 'cp'. No more than
4064 * 'cplen' characters will be copied to 'cp'.
4065 */
4066static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4067{
4068        struct asc_board *boardp = shost_priv(shost);
4069        struct asc_stats *s = &boardp->asc_stats;
4070
4071        int leftlen = cplen;
4072        int len, totlen = 0;
4073
4074        len = asc_prt_line(cp, leftlen,
4075                           "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4076                           shost->host_no);
4077        ASC_PRT_NEXT();
4078
4079        len = asc_prt_line(cp, leftlen,
4080                           " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4081                           s->queuecommand, s->reset, s->biosparam,
4082                           s->interrupt);
4083        ASC_PRT_NEXT();
4084
4085        len = asc_prt_line(cp, leftlen,
4086                           " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4087                           s->callback, s->done, s->build_error,
4088                           s->adv_build_noreq, s->adv_build_nosg);
4089        ASC_PRT_NEXT();
4090
4091        len = asc_prt_line(cp, leftlen,
4092                           " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4093                           s->exe_noerror, s->exe_busy, s->exe_error,
4094                           s->exe_unknown);
4095        ASC_PRT_NEXT();
4096
4097        /*
4098         * Display data transfer statistics.
4099         */
4100        if (s->xfer_cnt > 0) {
4101                len = asc_prt_line(cp, leftlen, " xfer_cnt %lu, xfer_elem %lu, ",
4102                                   s->xfer_cnt, s->xfer_elem);
4103                ASC_PRT_NEXT();
4104
4105                len = asc_prt_line(cp, leftlen, "xfer_bytes %lu.%01lu kb\n",
4106                                   s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
4107                ASC_PRT_NEXT();
4108
4109                /* Scatter gather transfer statistics */
4110                len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4111                                   s->xfer_elem / s->xfer_cnt,
4112                                   ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
4113                ASC_PRT_NEXT();
4114
4115                len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4116                                   (s->xfer_sect / 2) / s->xfer_elem,
4117                                   ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
4118                ASC_PRT_NEXT();
4119
4120                len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4121                                   (s->xfer_sect / 2) / s->xfer_cnt,
4122                                   ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
4123                ASC_PRT_NEXT();
4124        }
4125
4126        return totlen;
4127}
4128#endif /* ADVANSYS_STATS */
4129
4130/*
4131 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4132 *
4133 * *buffer: I/O buffer
4134 * **start: if inout == FALSE pointer into buffer where user read should start
4135 * offset: current offset into a /proc/scsi/advansys/[0...] file
4136 * length: length of buffer
4137 * hostno: Scsi_Host host_no
4138 * inout: TRUE - user is writing; FALSE - user is reading
4139 *
4140 * Return the number of bytes read from or written to a
4141 * /proc/scsi/advansys/[0...] file.
4142 *
4143 * Note: This function uses the per board buffer 'prtbuf' which is
4144 * allocated when the board is initialized in advansys_detect(). The
4145 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4146 * used to write to the buffer. The way asc_proc_copy() is written
4147 * if 'prtbuf' is too small it will not be overwritten. Instead the
4148 * user just won't get all the available statistics.
4149 */
4150static int
4151advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4152                   off_t offset, int length, int inout)
4153{
4154        struct asc_board *boardp = shost_priv(shost);
4155        char *cp;
4156        int cplen;
4157        int cnt;
4158        int totcnt;
4159        int leftlen;
4160        char *curbuf;
4161        off_t advoffset;
4162
4163        ASC_DBG(1, "begin\n");
4164
4165        /*
4166         * User write not supported.
4167         */
4168        if (inout == TRUE)
4169                return -ENOSYS;
4170
4171        /*
4172         * User read of /proc/scsi/advansys/[0...] file.
4173         */
4174
4175        /* Copy read data starting at the beginning of the buffer. */
4176        *start = buffer;
4177        curbuf = buffer;
4178        advoffset = 0;
4179        totcnt = 0;
4180        leftlen = length;
4181
4182        /*
4183         * Get board configuration information.
4184         *
4185         * advansys_info() returns the board string from its own static buffer.
4186         */
4187        cp = (char *)advansys_info(shost);
4188        strcat(cp, "\n");
4189        cplen = strlen(cp);
4190        /* Copy board information. */
4191        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4192        totcnt += cnt;
4193        leftlen -= cnt;
4194        if (leftlen == 0) {
4195                ASC_DBG(1, "totcnt %d\n", totcnt);
4196                return totcnt;
4197        }
4198        advoffset += cplen;
4199        curbuf += cnt;
4200
4201        /*
4202         * Display Wide Board BIOS Information.
4203         */
4204        if (!ASC_NARROW_BOARD(boardp)) {
4205                cp = boardp->prtbuf;
4206                cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4207                BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4208                cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4209                                  cplen);
4210                totcnt += cnt;
4211                leftlen -= cnt;
4212                if (leftlen == 0) {
4213                        ASC_DBG(1, "totcnt %d\n", totcnt);
4214                        return totcnt;
4215                }
4216                advoffset += cplen;
4217                curbuf += cnt;
4218        }
4219
4220        /*
4221         * Display driver information for each device attached to the board.
4222         */
4223        cp = boardp->prtbuf;
4224        cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4225        BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4226        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4227        totcnt += cnt;
4228        leftlen -= cnt;
4229        if (leftlen == 0) {
4230                ASC_DBG(1, "totcnt %d\n", totcnt);
4231                return totcnt;
4232        }
4233        advoffset += cplen;
4234        curbuf += cnt;
4235
4236        /*
4237         * Display EEPROM configuration for the board.
4238         */
4239        cp = boardp->prtbuf;
4240        if (ASC_NARROW_BOARD(boardp)) {
4241                cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4242        } else {
4243                cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4244        }
4245        BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4246        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4247        totcnt += cnt;
4248        leftlen -= cnt;
4249        if (leftlen == 0) {
4250                ASC_DBG(1, "totcnt %d\n", totcnt);
4251                return totcnt;
4252        }
4253        advoffset += cplen;
4254        curbuf += cnt;
4255
4256        /*
4257         * Display driver configuration and information for the board.
4258         */
4259        cp = boardp->prtbuf;
4260        cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4261        BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4262        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4263        totcnt += cnt;
4264        leftlen -= cnt;
4265        if (leftlen == 0) {
4266                ASC_DBG(1, "totcnt %d\n", totcnt);
4267                return totcnt;
4268        }
4269        advoffset += cplen;
4270        curbuf += cnt;
4271
4272#ifdef ADVANSYS_STATS
4273        /*
4274         * Display driver statistics for the board.
4275         */
4276        cp = boardp->prtbuf;
4277        cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4278        BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4279        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4280        totcnt += cnt;
4281        leftlen -= cnt;
4282        if (leftlen == 0) {
4283                ASC_DBG(1, "totcnt %d\n", totcnt);
4284                return totcnt;
4285        }
4286        advoffset += cplen;
4287        curbuf += cnt;
4288#endif /* ADVANSYS_STATS */
4289
4290        /*
4291         * Display Asc Library dynamic configuration information
4292         * for the board.
4293         */
4294        cp = boardp->prtbuf;
4295        if (ASC_NARROW_BOARD(boardp)) {
4296                cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4297        } else {
4298                cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4299        }
4300        BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4301        cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4302        totcnt += cnt;
4303        leftlen -= cnt;
4304        if (leftlen == 0) {
4305                ASC_DBG(1, "totcnt %d\n", totcnt);
4306                return totcnt;
4307        }
4308        advoffset += cplen;
4309        curbuf += cnt;
4310
4311        ASC_DBG(1, "totcnt %d\n", totcnt);
4312
4313        return totcnt;
4314}
4315#endif /* CONFIG_PROC_FS */
4316
4317static void asc_scsi_done(struct scsi_cmnd *scp)
4318{
4319        scsi_dma_unmap(scp);
4320        ASC_STATS(scp->device->host, done);
4321        scp->scsi_done(scp);
4322}
4323
4324static void AscSetBank(PortAddr iop_base, uchar bank)
4325{
4326        uchar val;
4327
4328        val = AscGetChipControl(iop_base) &
4329            (~
4330             (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4331              CC_CHIP_RESET));
4332        if (bank == 1) {
4333                val |= CC_BANK_ONE;
4334        } else if (bank == 2) {
4335                val |= CC_DIAG | CC_BANK_ONE;
4336        } else {
4337                val &= ~CC_BANK_ONE;
4338        }
4339        AscSetChipControl(iop_base, val);
4340}
4341
4342static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4343{
4344        AscSetBank(iop_base, 1);
4345        AscWriteChipIH(iop_base, ins_code);
4346        AscSetBank(iop_base, 0);
4347}
4348
4349static int AscStartChip(PortAddr iop_base)
4350{
4351        AscSetChipControl(iop_base, 0);
4352        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4353                return (0);
4354        }
4355        return (1);
4356}
4357
4358static int AscStopChip(PortAddr iop_base)
4359{
4360        uchar cc_val;
4361
4362        cc_val =
4363            AscGetChipControl(iop_base) &
4364            (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4365        AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4366        AscSetChipIH(iop_base, INS_HALT);
4367        AscSetChipIH(iop_base, INS_RFLAG_WTM);
4368        if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4369                return (0);
4370        }
4371        return (1);
4372}
4373
4374static int AscIsChipHalted(PortAddr iop_base)
4375{
4376        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4377                if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4378                        return (1);
4379                }
4380        }
4381        return (0);
4382}
4383
4384static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4385{
4386        PortAddr iop_base;
4387        int i = 10;
4388
4389        iop_base = asc_dvc->iop_base;
4390        while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4391               && (i-- > 0)) {
4392                mdelay(100);
4393        }
4394        AscStopChip(iop_base);
4395        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4396        udelay(60);
4397        AscSetChipIH(iop_base, INS_RFLAG_WTM);
4398        AscSetChipIH(iop_base, INS_HALT);
4399        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4400        AscSetChipControl(iop_base, CC_HALT);
4401        mdelay(200);
4402        AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4403        AscSetChipStatus(iop_base, 0);
4404        return (AscIsChipHalted(iop_base));
4405}
4406
4407static int AscFindSignature(PortAddr iop_base)
4408{
4409        ushort sig_word;
4410
4411        ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4412                 iop_base, AscGetChipSignatureByte(iop_base));
4413        if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4414                ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4415                         iop_base, AscGetChipSignatureWord(iop_base));
4416                sig_word = AscGetChipSignatureWord(iop_base);
4417                if ((sig_word == (ushort)ASC_1000_ID0W) ||
4418                    (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4419                        return (1);
4420                }
4421        }
4422        return (0);
4423}
4424
4425static void AscEnableInterrupt(PortAddr iop_base)
4426{
4427        ushort cfg;
4428
4429        cfg = AscGetChipCfgLsw(iop_base);
4430        AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4431}
4432
4433static void AscDisableInterrupt(PortAddr iop_base)
4434{
4435        ushort cfg;
4436
4437        cfg = AscGetChipCfgLsw(iop_base);
4438        AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4439}
4440
4441static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4442{
4443        unsigned char byte_data;
4444        unsigned short word_data;
4445
4446        if (isodd_word(addr)) {
4447                AscSetChipLramAddr(iop_base, addr - 1);
4448                word_data = AscGetChipLramData(iop_base);
4449                byte_data = (word_data >> 8) & 0xFF;
4450        } else {
4451                AscSetChipLramAddr(iop_base, addr);
4452                word_data = AscGetChipLramData(iop_base);
4453                byte_data = word_data & 0xFF;
4454        }
4455        return byte_data;
4456}
4457
4458static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4459{
4460        ushort word_data;
4461
4462        AscSetChipLramAddr(iop_base, addr);
4463        word_data = AscGetChipLramData(iop_base);
4464        return (word_data);
4465}
4466
4467#if CC_VERY_LONG_SG_LIST
4468static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4469{
4470        ushort val_low, val_high;
4471        ASC_DCNT dword_data;
4472
4473        AscSetChipLramAddr(iop_base, addr);
4474        val_low = AscGetChipLramData(iop_base);
4475        val_high = AscGetChipLramData(iop_base);
4476        dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4477        return (dword_data);
4478}
4479#endif /* CC_VERY_LONG_SG_LIST */
4480
4481static void
4482AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4483{
4484        int i;
4485
4486        AscSetChipLramAddr(iop_base, s_addr);
4487        for (i = 0; i < words; i++) {
4488                AscSetChipLramData(iop_base, set_wval);
4489        }
4490}
4491
4492static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4493{
4494        AscSetChipLramAddr(iop_base, addr);
4495        AscSetChipLramData(iop_base, word_val);
4496}
4497
4498static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4499{
4500        ushort word_data;
4501
4502        if (isodd_word(addr)) {
4503                addr--;
4504                word_data = AscReadLramWord(iop_base, addr);
4505                word_data &= 0x00FF;
4506                word_data |= (((ushort)byte_val << 8) & 0xFF00);
4507        } else {
4508                word_data = AscReadLramWord(iop_base, addr);
4509                word_data &= 0xFF00;
4510                word_data |= ((ushort)byte_val & 0x00FF);
4511        }
4512        AscWriteLramWord(iop_base, addr, word_data);
4513}
4514
4515/*
4516 * Copy 2 bytes to LRAM.
4517 *
4518 * The source data is assumed to be in little-endian order in memory
4519 * and is maintained in little-endian order when written to LRAM.
4520 */
4521static void
4522AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4523                        const uchar *s_buffer, int words)
4524{
4525        int i;
4526
4527        AscSetChipLramAddr(iop_base, s_addr);
4528        for (i = 0; i < 2 * words; i += 2) {
4529                /*
4530                 * On a little-endian system the second argument below
4531                 * produces a little-endian ushort which is written to
4532                 * LRAM in little-endian order. On a big-endian system
4533                 * the second argument produces a big-endian ushort which
4534                 * is "transparently" byte-swapped by outpw() and written
4535                 * in little-endian order to LRAM.
4536                 */
4537                outpw(iop_base + IOP_RAM_DATA,
4538                      ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4539        }
4540}
4541
4542/*
4543 * Copy 4 bytes to LRAM.
4544 *
4545 * The source data is assumed to be in little-endian order in memory
4546 * and is maintained in little-endian order when written to LRAM.
4547 */
4548static void
4549AscMemDWordCopyPtrToLram(PortAddr iop_base,
4550                         ushort s_addr, uchar *s_buffer, int dwords)
4551{
4552        int i;
4553
4554        AscSetChipLramAddr(iop_base, s_addr);
4555        for (i = 0; i < 4 * dwords; i += 4) {
4556                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4557                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4558        }
4559}
4560
4561/*
4562 * Copy 2 bytes from LRAM.
4563 *
4564 * The source data is assumed to be in little-endian order in LRAM
4565 * and is maintained in little-endian order when written to memory.
4566 */
4567static void
4568AscMemWordCopyPtrFromLram(PortAddr iop_base,
4569                          ushort s_addr, uchar *d_buffer, int words)
4570{
4571        int i;
4572        ushort word;
4573
4574        AscSetChipLramAddr(iop_base, s_addr);
4575        for (i = 0; i < 2 * words; i += 2) {
4576                word = inpw(iop_base + IOP_RAM_DATA);
4577                d_buffer[i] = word & 0xff;
4578                d_buffer[i + 1] = (word >> 8) & 0xff;
4579        }
4580}
4581
4582static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4583{
4584        ASC_DCNT sum;
4585        int i;
4586
4587        sum = 0L;
4588        for (i = 0; i < words; i++, s_addr += 2) {
4589                sum += AscReadLramWord(iop_base, s_addr);
4590        }
4591        return (sum);
4592}
4593
4594static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4595{
4596        uchar i;
4597        ushort s_addr;
4598        PortAddr iop_base;
4599        ushort warn_code;
4600
4601        iop_base = asc_dvc->iop_base;
4602        warn_code = 0;
4603        AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4604                          (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4605                                    64) >> 1));
4606        i = ASC_MIN_ACTIVE_QNO;
4607        s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4608        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4609                         (uchar)(i + 1));
4610        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4611                         (uchar)(asc_dvc->max_total_qng));
4612        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4613                         (uchar)i);
4614        i++;
4615        s_addr += ASC_QBLK_SIZE;
4616        for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4617                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4618                                 (uchar)(i + 1));
4619                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4620                                 (uchar)(i - 1));
4621                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4622                                 (uchar)i);
4623        }
4624        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4625                         (uchar)ASC_QLINK_END);
4626        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4627                         (uchar)(asc_dvc->max_total_qng - 1));
4628        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4629                         (uchar)asc_dvc->max_total_qng);
4630        i++;
4631        s_addr += ASC_QBLK_SIZE;
4632        for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4633             i++, s_addr += ASC_QBLK_SIZE) {
4634                AscWriteLramByte(iop_base,
4635                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4636                AscWriteLramByte(iop_base,
4637                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4638                AscWriteLramByte(iop_base,
4639                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4640        }
4641        return warn_code;
4642}
4643
4644static ASC_DCNT
4645AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4646                 const uchar *mcode_buf, ushort mcode_size)
4647{
4648        ASC_DCNT chksum;
4649        ushort mcode_word_size;
4650        ushort mcode_chksum;
4651
4652        /* Write the microcode buffer starting at LRAM address 0. */
4653        mcode_word_size = (ushort)(mcode_size >> 1);
4654        AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4655        AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4656
4657        chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4658        ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4659        mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4660                                                 (ushort)ASC_CODE_SEC_BEG,
4661                                                 (ushort)((mcode_size -
4662                                                           s_addr - (ushort)
4663                                                           ASC_CODE_SEC_BEG) /
4664                                                          2));
4665        ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4666        AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4667        AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4668        return chksum;
4669}
4670
4671static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4672{
4673        PortAddr iop_base;
4674        int i;
4675        ushort lram_addr;
4676
4677        iop_base = asc_dvc->iop_base;
4678        AscPutRiscVarFreeQHead(iop_base, 1);
4679        AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4680        AscPutVarFreeQHead(iop_base, 1);
4681        AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4682        AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4683                         (uchar)((int)asc_dvc->max_total_qng + 1));
4684        AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4685                         (uchar)((int)asc_dvc->max_total_qng + 2));
4686        AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4687                         asc_dvc->max_total_qng);
4688        AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4689        AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4690        AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4691        AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4692        AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4693        AscPutQDoneInProgress(iop_base, 0);
4694        lram_addr = ASC_QADR_BEG;
4695        for (i = 0; i < 32; i++, lram_addr += 2) {
4696                AscWriteLramWord(iop_base, lram_addr, 0);
4697        }
4698}
4699
4700static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4701{
4702        int i;
4703        ushort warn_code;
4704        PortAddr iop_base;
4705        ASC_PADDR phy_addr;
4706        ASC_DCNT phy_size;
4707        struct asc_board *board = asc_dvc_to_board(asc_dvc);
4708
4709        iop_base = asc_dvc->iop_base;
4710        warn_code = 0;
4711        for (i = 0; i <= ASC_MAX_TID; i++) {
4712                AscPutMCodeInitSDTRAtID(iop_base, i,
4713                                        asc_dvc->cfg->sdtr_period_offset[i]);
4714        }
4715
4716        AscInitQLinkVar(asc_dvc);
4717        AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4718                         asc_dvc->cfg->disc_enable);
4719        AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4720                         ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4721
4722        /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4723        BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4724        asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4725                                        ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4726        if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4727                warn_code = -ENOMEM;
4728                goto err_dma_map;
4729        }
4730        phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4731        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4732                                 (uchar *)&phy_addr, 1);
4733        phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4734        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4735                                 (uchar *)&phy_size, 1);
4736
4737        asc_dvc->cfg->mcode_date =
4738            AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4739        asc_dvc->cfg->mcode_version =
4740            AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4741
4742        AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4743        if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4744                asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4745                warn_code = UW_ERR;
4746                goto err_mcode_start;
4747        }
4748        if (AscStartChip(iop_base) != 1) {
4749                asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4750                warn_code = UW_ERR;
4751                goto err_mcode_start;
4752        }
4753
4754        return warn_code;
4755
4756err_mcode_start:
4757        dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4758                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4759err_dma_map:
4760        asc_dvc->overrun_dma = 0;
4761        return warn_code;
4762}
4763
4764static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4765{
4766        const struct firmware *fw;
4767        const char fwname[] = "advansys/mcode.bin";
4768        int err;
4769        unsigned long chksum;
4770        ushort warn_code;
4771        PortAddr iop_base;
4772
4773        iop_base = asc_dvc->iop_base;
4774        warn_code = 0;
4775        if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4776            !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4777                AscResetChipAndScsiBus(asc_dvc);
4778                mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4779        }
4780        asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4781        if (asc_dvc->err_code != 0)
4782                return UW_ERR;
4783        if (!AscFindSignature(asc_dvc->iop_base)) {
4784                asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4785                return warn_code;
4786        }
4787        AscDisableInterrupt(iop_base);
4788        warn_code |= AscInitLram(asc_dvc);
4789        if (asc_dvc->err_code != 0)
4790                return UW_ERR;
4791
4792        err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4793        if (err) {
4794                printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4795                       fwname, err);
4796                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4797                return err;
4798        }
4799        if (fw->size < 4) {
4800                printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4801                       fw->size, fwname);
4802                release_firmware(fw);
4803                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4804                return -EINVAL;
4805        }
4806        chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4807                 (fw->data[1] << 8) | fw->data[0];
4808        ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4809        if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4810                             fw->size - 4) != chksum) {
4811                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4812                release_firmware(fw);
4813                return warn_code;
4814        }
4815        release_firmware(fw);
4816        warn_code |= AscInitMicroCodeVar(asc_dvc);
4817        if (!asc_dvc->overrun_dma)
4818                return warn_code;
4819        asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4820        AscEnableInterrupt(iop_base);
4821        return warn_code;
4822}
4823
4824/*
4825 * Load the Microcode
4826 *
4827 * Write the microcode image to RISC memory starting at address 0.
4828 *
4829 * The microcode is stored compressed in the following format:
4830 *
4831 *  254 word (508 byte) table indexed by byte code followed
4832 *  by the following byte codes:
4833 *
4834 *    1-Byte Code:
4835 *      00: Emit word 0 in table.
4836 *      01: Emit word 1 in table.
4837 *      .
4838 *      FD: Emit word 253 in table.
4839 *
4840 *    Multi-Byte Code:
4841 *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4842 *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4843 *
4844 * Returns 0 or an error if the checksum doesn't match
4845 */
4846static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4847                            int size, int memsize, int chksum)
4848{
4849        int i, j, end, len = 0;
4850        ADV_DCNT sum;
4851
4852        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4853
4854        for (i = 253 * 2; i < size; i++) {
4855                if (buf[i] == 0xff) {
4856                        unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4857                        for (j = 0; j < buf[i + 1]; j++) {
4858                                AdvWriteWordAutoIncLram(iop_base, word);
4859                                len += 2;
4860                        }
4861                        i += 3;
4862                } else if (buf[i] == 0xfe) {
4863                        unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4864                        AdvWriteWordAutoIncLram(iop_base, word);
4865                        i += 2;
4866                        len += 2;
4867                } else {
4868                        unsigned int off = buf[i] * 2;
4869                        unsigned short word = (buf[off + 1] << 8) | buf[off];
4870                        AdvWriteWordAutoIncLram(iop_base, word);
4871                        len += 2;
4872                }
4873        }
4874
4875        end = len;
4876
4877        while (len < memsize) {
4878                AdvWriteWordAutoIncLram(iop_base, 0);
4879                len += 2;
4880        }
4881
4882        /* Verify the microcode checksum. */
4883        sum = 0;
4884        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4885
4886        for (len = 0; len < end; len += 2) {
4887                sum += AdvReadWordAutoIncLram(iop_base);
4888        }
4889
4890        if (sum != chksum)
4891                return ASC_IERR_MCODE_CHKSUM;
4892
4893        return 0;
4894}
4895
4896static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4897{
4898        ADV_CARR_T *carrp;
4899        ADV_SDCNT buf_size;
4900        ADV_PADDR carr_paddr;
4901
4902        carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4903        asc_dvc->carr_freelist = NULL;
4904        if (carrp == asc_dvc->carrier_buf) {
4905                buf_size = ADV_CARRIER_BUFSIZE;
4906        } else {
4907                buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4908        }
4909
4910        do {
4911                /* Get physical address of the carrier 'carrp'. */
4912                carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4913
4914                buf_size -= sizeof(ADV_CARR_T);
4915
4916                carrp->carr_pa = carr_paddr;
4917                carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4918
4919                /*
4920                 * Insert the carrier at the beginning of the freelist.
4921                 */
4922                carrp->next_vpa =
4923                        cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4924                asc_dvc->carr_freelist = carrp;
4925
4926                carrp++;
4927        } while (buf_size > 0);
4928}
4929
4930/*
4931 * Send an idle command to the chip and wait for completion.
4932 *
4933 * Command completion is polled for once per microsecond.
4934 *
4935 * The function can be called from anywhere including an interrupt handler.
4936 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4937 * functions to prevent reentrancy.
4938 *
4939 * Return Values:
4940 *   ADV_TRUE - command completed successfully
4941 *   ADV_FALSE - command failed
4942 *   ADV_ERROR - command timed out
4943 */
4944static int
4945AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4946               ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4947{
4948        int result;
4949        ADV_DCNT i, j;
4950        AdvPortAddr iop_base;
4951
4952        iop_base = asc_dvc->iop_base;
4953
4954        /*
4955         * Clear the idle command status which is set by the microcode
4956         * to a non-zero value to indicate when the command is completed.
4957         * The non-zero result is one of the IDLE_CMD_STATUS_* values
4958         */
4959        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4960
4961        /*
4962         * Write the idle command value after the idle command parameter
4963         * has been written to avoid a race condition. If the order is not
4964         * followed, the microcode may process the idle command before the
4965         * parameters have been written to LRAM.
4966         */
4967        AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4968                                cpu_to_le32(idle_cmd_parameter));
4969        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4970
4971        /*
4972         * Tickle the RISC to tell it to process the idle command.
4973         */
4974        AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4975        if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4976                /*
4977                 * Clear the tickle value. In the ASC-3550 the RISC flag
4978                 * command 'clr_tickle_b' does not work unless the host
4979                 * value is cleared.
4980                 */
4981                AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4982        }
4983
4984        /* Wait for up to 100 millisecond for the idle command to timeout. */
4985        for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4986                /* Poll once each microsecond for command completion. */
4987                for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4988                        AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4989                                        result);
4990                        if (result != 0)
4991                                return result;
4992                        udelay(1);
4993                }
4994        }
4995
4996        BUG();          /* The idle command should never timeout. */
4997        return ADV_ERROR;
4998}
4999
5000/*
5001 * Reset SCSI Bus and purge all outstanding requests.
5002 *
5003 * Return Value:
5004 *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
5005 *      ADV_FALSE(0) -  Microcode command failed.
5006 *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
5007 *                      may be hung which requires driver recovery.
5008 */
5009static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
5010{
5011        int status;
5012
5013        /*
5014         * Send the SCSI Bus Reset idle start idle command which asserts
5015         * the SCSI Bus Reset signal.
5016         */
5017        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
5018        if (status != ADV_TRUE) {
5019                return status;
5020        }
5021
5022        /*
5023         * Delay for the specified SCSI Bus Reset hold time.
5024         *
5025         * The hold time delay is done on the host because the RISC has no
5026         * microsecond accurate timer.
5027         */
5028        udelay(ASC_SCSI_RESET_HOLD_TIME_US);
5029
5030        /*
5031         * Send the SCSI Bus Reset end idle command which de-asserts
5032         * the SCSI Bus Reset signal and purges any pending requests.
5033         */
5034        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
5035        if (status != ADV_TRUE) {
5036                return status;
5037        }
5038
5039        mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
5040
5041        return status;
5042}
5043
5044/*
5045 * Initialize the ASC-3550.
5046 *
5047 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5048 *
5049 * For a non-fatal error return a warning code. If there are no warnings
5050 * then 0 is returned.
5051 *
5052 * Needed after initialization for error recovery.
5053 */
5054static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
5055{
5056        const struct firmware *fw;
5057        const char fwname[] = "advansys/3550.bin";
5058        AdvPortAddr iop_base;
5059        ushort warn_code;
5060        int begin_addr;
5061        int end_addr;
5062        ushort code_sum;
5063        int word;
5064        int i;
5065        int err;
5066        unsigned long chksum;
5067        ushort scsi_cfg1;
5068        uchar tid;
5069        ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5070        ushort wdtr_able = 0, sdtr_able, tagqng_able;
5071        uchar max_cmd[ADV_MAX_TID + 1];
5072
5073        /* If there is already an error, don't continue. */