linux/drivers/hwspinlock/u8500_hsem.c
<<
.5 2/drivers/hwspinlock/u8500_hsem.c">.5.53/spaval.53spav class="lxr_search">.5.5 hidden" nam> navtarget" > ">.5 text" nam> search" id search">.5 submit">Search.5.53/spaval.53input typ> hidden" nam> ajax_lookup" id ajax_lookup" > ">.l 3div id file_contents"a
 L1">v v13/a>3spav class="comment">/*3/spaval
 L2">v v23/a>3spav class="comment"> * u8500 HWSEM driver3/spaval
 L3">v v33/a>3spav class="comment"> *3/spaval
 L4">v v43/a>3spav class="comment"> * Copyright (C) 2010-2011 ST-Ericsson3/spaval
 L5">v v53/a>3spav class="comment"> *3/spaval
 L6">v v63/a>3spav class="comment"> * Implements u8500 semaphore handling for protocol 1, no interrupts.3/spaval
 L7">v v73/a>3spav class="comment"> *3/spaval
 L8">v v83/a>3spav class="comment"> * Author: Mathieu Poirier <mathieu.poirier@linaro.org>3/spaval
 L9">v v93/a>3spav class="comment"> * Heavily borrowed from the work of :3/spaval
 L10">v 
  3spav class="comment"> *   Sim12"Que <sque@ti.com>3/spaval
 L11">v 113/a>3spav class="comment"> *   Hari Kanigeri <h-kanigeri2@ti.com>3/spaval
 L12">v 123/a>3spav class="comment"> *   Ohad Ben-Cohen <ohad@wizery.com>3/spaval
 L13">v 133/a>3spav class="comment"> *3/spaval
 L14">v 143/a>3spav class="comment"> * This program is free software; you cav redistribute it and/or3/spaval
 L15">v 153/a>3spav class="comment"> * modify it under the terms of the GNU General Public License3/spaval
 L16">v 163/a>3spav class="comment"> * vers.12"2 as published by the Free Software Foundaon v.3/spaval
 L17">v 173/a>3spav class="comment"> *3/spaval
 L18">v 183/a>3spav class="comment"> * This program is distributed in the hope that it will be useful, but3/spaval
 L19">v 193/a>3spav class="comment"> * WITHOUT ANY WARRANTY; without even the implied warranty of3/spaval
 L20">v 2  3spav class="comment"> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU3/spaval
 L21">v 213/a>3spav class="comment"> * General Public License for more details.3/spaval
 L22">v 223/a>3spav class="comment"> */3/spaval
 L23">v 233/a>l
 L24">v 243/a>#include <linux/module.h3/a>>l
 L25">v 253/a>#include <linux/delay.h3/a>>l
 L26">v 263/a>#include <linux/io.h3/a>>l
 L27">v 273/a>#include <linux/pm_runtime.h3/a>>l
 L28">v 283/a>#include <linux/slab.h3/a>>l
 L29">v 293/a>#include <linux/spinlock.h3/a>>l
 L30">v 303/a>#include <linux/hwspinlock.h3/a>>l
 L31">v 313/a>#include <linux/platform_device.h3/a>>l
 L32">v 323/a>l
 L33">v 333/a>#include "hwspinlock_internal.h3/a>"l
 L34">v 343/a>l
 L35">v 353/a>3spav class="comment">/*3/spaval
 L36">v 363/a>3spav class="comment"> * Implementaon v of STE's HSem protocol 1 without interrutps.3/spaval
 L37">v 373/a>3spav class="comment"> * The only masterID we allow is '0x01' to force people to use3/spaval
 L38">v 383/a>3spav class="comment"> * HSems for synchronisaon v between processors rather than processes3/spaval
 L39">v 393/a>3spav class="comment"> * on the ARM core.3/spaval
 L40">v 4  3spav class="comment"> */3/spaval
 L41">v 413/a>l
 L42">v 423/a>#definev3a href="+code=U8500_MAX_SEMAPHORE" class="sref">U8500_MAX_SEMAPHORE3/a>             32/* a total of 32
 L43">v 433/a>#definev3a href="+code=RESET_SEMAPHORE" class="sref">RESET_SEMAPHORE3/a>                 (0)/"v v3spav class="comment">/* free */3/spaval
 L44">v 443/a>l
 L45">v 453/a>3spav class="comment">/*3/spaval
 L46">v 463/a>3spav class="comment"> * CPU ID for master running u8500 kernel.3/spaval
 L47">v 473/a>3spav class="comment"> * Hswpinlocks should only be used to synchonise operaon vs3/spaval
 L48">v 483/a>3spav class="comment"> * between the Cortex A9 core and the other CPUs.  Hence3/spaval
 L49">v 493/a>3spav class="comment"> * forcing the masterID to a preset 
	  >.3/spaval
 L50">v 5  3spav class="comment"> */3/spaval
 L51">v 513/a>#definev3a href="+code=HSEM_MASTER_ID" class="sref">HSEM_MASTER_ID3/a>                  0x01l
 L52">v 523/a>l
 L53">v 533/a>#definev3a href="+code=HSEM_REGISTER_OFFSET" class="sref">HSEM_REGISTER_OFFSET3/a>            0x08l
 L54">v 543/a>l
 L55">v 553/a>#definev3a href="+code=HSEM_CTRL_REG" class="sref">HSEM_CTRL_REG3/a>                   0x00l
 L56">v 563/a>#definev3a href="+code=HSEM_ICRALL" class="sref">HSEM_ICRALL3/a>                     0x90l
 L57">v 573/a>#definev3a href="+code=HSEM_PROTOCOL_1" class="sref">HSEM_PROTOCOL_13/a>                 0x01l
 L58">v 583/a>l
 L59">v 593/a>static intv3a href="+code=u8500_hsem_trylock" class="sref">u8500_hsem_trylock3/a>(structv3a href="+code=hwspinlock" class="sref">hwspinlock3/a> *3a href="+code=lock" class="sref">lock3/a>)l
 L60">v 6  {l
 L61">v 613/a>        voidv3a href="+code=__iomem" class="sref">__iomem3/a> *3a href="+code=lock_addr" class="sref">lock_addr3/a> =v3a href="+code=lock" class="sref">lock3/a>->3a href="+code=priv" class="sref">priv3/a>;l
 L62">v 623/a>l
 L63">v 633/a>        3a href="+code=writel" class="sref">writel3/a>(3a href="+code=HSEM_MASTER_ID" class="sref">HSEM_MASTER_ID3/a>,v3a href="+code=lock_addr" class="sref">lock_addr3/a>);l
 L64">v 643/a>l
 L65">v 653/a>        3spav class="comment">/* get only first 4 bit and compare to masterID.3/spaval
 L66">v 663/a>3spav class="comment">         * if equal, we have the semaphore, otherwise3/spaval
 L67">v 673/a>3spav class="comment">         * someonevelse has it.3/spaval
 L68">v 683/a>3spav class="comment">         */3/spaval
 L69">v 693/a>        return (3a href="+code=HSEM_MASTER_ID" class="sref">HSEM_MASTER_ID3/a> == (0x0F &v3a href="+code=readl" class="sref">readl3/a>(3a href="+code=lock_addr" class="sref">lock_addr3/a>)));l
 L70">v 7  }l
 L71">v 713/a>l
 L72">v 723/a>static voidv3a href="+code=u8500_hsem_unlock" class="sref">u8500_hsem_unlock3/a>(structv3a href="+code=hwspinlock" class="sref">hwspinlock3/a> *3a href="+code=lock" class="sref">lock3/a>)l
 L73">v 73 {l
 L74">v 743/a>        voidv3a href="+code=__iomem" class="sref">__iomem3/a> *3a href="+code=lock_addr" class="sref">lock_addr3/a> =v3a href="+code=lock" class="sref">lock3/a>->3a href="+code=priv" class="sref">priv3/a>;l
 L75">v 753/a>l
 L76">v 763/a>        3spav class="comment">/* release the lock by writing 0 to it */3/spaval
 L77">v 773/a>        3a href="+code=writel" class="sref">writel3/a>(3a href="+code=RESET_SEMAPHORE" class="sref">RESET_SEMAPHORE3/a>,v3a href="+code=lock_addr" class="sref">lock_addr3/a>);l
 L78">v 78 }l
 L79">v 793/a>l
 L80">v 8  3spav class="comment">/*3/spaval
 L81">v 813/a>3spav class="comment"> * u8500: what 
	  > is recommended here ?3/spaval
 L82">v 823/a>3spav class="comment"> */3/spaval
 L83">v 833/a>static voidv3a href="+code=u8500_hsem_relax" class="sref">u8500_hsem_relax3/a>(structv3a href="+code=hwspinlock" class="sref">hwspinlock3/a> *3a href="+code=lock" class="sref">lock3/a>)l
 L84">v 84 {l
 L85">v 853/a>        3a href="+code=ndelay" class="sref">ndelay3/a>(50);l
 L86">v 86 }l
 L87">v 873/a>l
 L88">v 883/a>static const structv3a href="+code=hwspinlock_ops" class="sref">hwspinlock_ops3/a> 3a href="+code=u8500_hwspinlock_ops" class="sref">u8500_hwspinlock_ops3/a> =v{l
 L89">v 893/a>        .3a href="+code=trylock" class="sref">trylock3/a>        =v3a href="+code=u8500_hsem_trylock" class="sref">u8500_hsem_trylock3/a>,l
 L90">v 903/a>        .3a href="+code=unlock" class="sref">unlock3/a>         =v3a href="+code=u8500_hsem_unlock" class="sref">u8500_hsem_unlock3/a>,l
 L91">v 913/a>        .3a href="+code=relax" class="sref">relax3/a>          =v3a href="+code=u8500_hsem_relax" class="sref">u8500_hsem_relax3/a>,l
 L92">v 923/a>};l
 L93">v 933/a>l
 L94">v 943/a>static intv3a href="+code=__devinit" class="sref">__devinit3/a> 3a href="+code=u8500_hsem_probe" class="sref">u8500_hsem_probe3/a>(structv3a href="+code=platform_device" class="sref">platform_device3/a> *3a href="+code=pdev" class="sref">pdev3/a>)l
 L95">v 95 {l
 L96">v 963/a>        structv3a href="+code=hwspinlock_pdata" class="sref">hwspinlock_pdata3/a> *3a href="+code=pdata" class="sref">pdata3/a> =v3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>.3a href="+code=platform_data" class="sref">platform_data3/a>;l
 L97">v 973/a>        structv3a href="+code=hwspinlock_device" class="sref">hwspinlock_device3/a> *3a href="+code=bank" class="sref">bank3/a>;l
 L98">v 983/a>        structv3a href="+code=hwspinlock" class="sref">hwspinlock3/a> *3a href="+code=hwlock" class="sref">hwlock3/a>;l
 L99">v 993/a>        structv3a href="+code=resource" class="sref">resource3/a> *3a href="+code=res" class="sref">res3/a>;l
 L100">v1003/a>        voidv3a href="+code=__iomem" class="sref">__iomem3/a> *3a href="+code=io_base" class="sref">io_base3/a>;l
 L101">v1013/a>        intv3a href="+code=i" class="sref">i3/a>,v3a href="+code=ret" class="sref">ret3/a>,v3a href="+code=num_locks" class="sref">num_locks3/a> =v3a href="+code=U8500_MAX_SEMAPHORE" class="sref">U8500_MAX_SEMAPHORE3/a>;l
 L102">v1023/a>        3a href="+code=ulong" class="sref">ulong3/a> 3a href="+code=
	 " class="sref">
	 3/a>;l
 L103">v1033/a>l
 L104">v1043/a>        if (!3a href="+code=pdata" class="sref">pdata3/a>)l
 L105">v1053/a>                return -3a href="+code=ENODEV" class="sref">ENODEV3/a>;l
 L106">v1063/a>l
 L107">v1073/a>        3a href="+code=res" class="sref">res3/a> =v3a href="+code=platform_get_resource" class="sref">platform_get_resource3/a>(3a href="+code=pdev" class="sref">pdev3/a>,v3a href="+code=IORESOURCE_MEM" class="sref">IORESOURCE_MEM3/a>,v0);l
 L108">v1083/a>        if (!3a href="+code=res" class="sref">res3/a>)l
 L109">v1093/a>                return -3a href="+code=ENODEV" class="sref">ENODEV3/a>;l
 L110">v1
  l
 L111">v1113/a>        3a href="+code=io_base" class="sref">io_base3/a> =v3a href="+code=ioremap" class="sref">ioremap3/a>(3a href="+code=res" class="sref">res3/a>->3a href="+code=start" class="sref">start3/a>,v3a href="+code=resource_size" class="sref">resource_size3/a>(3a href="+code=res" class="sref">res3/a>));l
 L112">v1123/a>        if (!3a href="+code=io_base" class="sref">io_base3/a>)l
 L113">v1133/a>                return -3a href="+code=ENOMEM" class="sref">ENOMEM3/a>;l
 L114">v1143/a>l
 L115">v1153/a>        3spav class="comment">/* make sure protocol 1 is selected */3/spaval
 L116">v1163/a>        3a href="+code=
	 " class="sref">
	 3/a> =v3a href="+code=readl" class="sref">readl3/a>(3a href="+code=io_base" class="sref">io_base3/a> +v3a href="+code=HSEM_CTRL_REG" class="sref">HSEM_CTRL_REG3/a>);l
 L117">v1173/a>        3a href="+code=writel" class="sref">writel3/a>((3a href="+code=
	 " class="sref">
	 3/a> &v~3a href="+code=HSEM_PROTOCOL_1" class="sref">HSEM_PROTOCOL_13/a>),v3a href="+code=io_base" class="sref">io_base3/a> +v3a href="+code=HSEM_CTRL_REG" class="sref">HSEM_CTRL_REG3/a>);l
 L118">v1183/a>l
 L119">v1193/a>        3spav class="comment">/* clear all interrupts */3/spaval
 L120">v1203/a>        3a href="+code=writel" class="sref">writel3/a>(0xFFFF,v3a href="+code=io_base" class="sref">io_base3/a> +v3a href="+code=HSEM_ICRALL" class="sref">HSEM_ICRALL3/a>);l
 L121">v1213/a>l
 L122">v1223/a>        3a href="+code=bank" class="sref">bank3/a> =v3a href="+code=kzalloc" class="sref">kzalloc3/a>(sizeof(*3a href="+code=bank" class="sref">bank3/a>) +v3a href="+code=num_locks" class="sref">num_locks3/a> * sizeof(*3a href="+code=hwlock" class="sref">hwlock3/a>),v3a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL3/a>);l
 L123">v1233/a>        if (!3a href="+code=bank" class="sref">bank3/a>) {l
 L124">v1243/a>                3a href="+code=ret" class="sref">ret3/a> =v-3a href="+code=ENOMEM" class="sref">ENOMEM3/a>;l
 L125">v1253/a>                gotov3a href="+code=iounmap_base" class="sref">iounmap_base3/a>;l
 L126">v1263/a>        }l
 L127">v1273/a>l
 L128">v1283/a>        3a href="+code=platform_set_drvdata" class="sref">platform_set_drvdata3/a>(3a href="+code=pdev" class="sref">pdev3/a>,v3a href="+code=bank" class="sref">bank3/a>);l
 L129">v1293/a>l
 L130">v1303/a>        for (3a href="+code=i" class="sref">i3/a> =v0,v3a href="+code=hwlock" class="sref">hwlock3/a> =v&3a href="+code=bank" class="sref">bank3/a>->3a href="+code=lock" class="sref">lock3/a>[0];v3a href="+code=i" class="sref">i3/a> <v3a href="+code=num_locks" class="sref">num_locks3/a>;v3a href="+code=i" class="sref">i3/a>++,v3a href="+code=hwlock" class="sref">hwlock3/a>++)l
 L131">v1313/a>                3a href="+code=hwlock" class="sref">hwlock3/a>->3a href="+code=priv" class="sref">priv3/a> =v3a href="+code=io_base" class="sref">io_base3/a> +v3a href="+code=HSEM_REGISTER_OFFSET" class="sref">HSEM_REGISTER_OFFSET3/a> + sizeof(3a href="+code=u32" class="sref">u323/a>) * 3a href="+code=i" class="sref">i3/a>;l
 L132">v1323/a>l
 L133">v1333/a>        3spav class="comment">/* no pm needed for HSem but required to comply with hwspilock core */3/spaval
 L134">v1343/a>        3a href="+code=pm_runtime_enable" class="sref">pm_runtime_enable3/a>(&3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>);l
 L135">v1353/a>l
 L136">v1363/a>        3a href="+code=ret" class="sref">ret3/a> =v3a href="+code=hwspin_lock_register" class="sref">hwspin_lock_register3/a>(3a href="+code=bank" class="sref">bank3/a>,v&3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>,v&3a href="+code=u8500_hwspinlock_ops" class="sref">u8500_hwspinlock_ops3/a>,l
 L137">v1373/a>                                                3a href="+code=pdata" class="sref">pdata3/a>->3a href="+code=base_id" class="sref">base_id3/a>,v3a href="+code=num_locks" class="sref">num_locks3/a>);l
 L138">v1383/a>        if (3a href="+code=ret" class="sref">ret3/a>)l
 L139">v1393/a>                gotov3a href="+code=reg_fail" class="sref">reg_fail3/a>;l
 L140">v14  l
 L141">v1413/a>        return 0;l
 L142">v1423/a>l
 L143">v1433/a>3a href="+code=reg_fail" class="sref">reg_fail3/a>:l
 L144">v1443/a>        3a href="+code=pm_runtime_disable" class="sref">pm_runtime_disable3/a>(&3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>);l
 L145">v1453/a>        3a href="+code=kfree" class="sref">kfree3/a>(3a href="+code=bank" class="sref">bank3/a>);l
 L146">v1463/a>3a href="+code=iounmap_base" class="sref">iounmap_base3/a>:l
 L147">v1473/a>        3a href="+code=iounmap" class="sref">iounmap3/a>(3a href="+code=io_base" class="sref">io_base3/a>);l
 L148">v1483/a>        return 3a href="+code=ret" class="sref">ret3/a>;l
 L149">v1493/a>}l
 L150">v15  l
 L151">v1513/a>static intv3a href="+code=__devexit" class="sref">__devexit3/a> 3a href="+code=u8500_hsem_remove" class="sref">u8500_hsem_remove3/a>(structv3a href="+code=platform_device" class="sref">platform_device3/a> *3a href="+code=pdev" class="sref">pdev3/a>)l
 L152">v1523/a>{l
 L153">v1533/a>        structv3a href="+code=hwspinlock_device" class="sref">hwspinlock_device3/a> *3a href="+code=bank" class="sref">bank3/a> =v3a href="+code=platform_get_drvdata" class="sref">platform_get_drvdata3/a>(3a href="+code=pdev" class="sref">pdev3/a>);l
 L154">v1543/a>        voidv3a href="+code=__iomem" class="sref">__iomem3/a> *3a href="+code=io_base" class="sref">io_base3/a> =v3a href="+code=bank" class="sref">bank3/a>->3a href="+code=lock" class="sref">lock3/a>[0].3a href="+code=priv" class="sref">priv3/a> -v3a href="+code=HSEM_REGISTER_OFFSET" class="sref">HSEM_REGISTER_OFFSET3/a>;l
 L155">v1553/a>        intv3a href="+code=ret" class="sref">ret3/a>;l
 L156">v1563/a>l
 L157">v1573/a>        3spav class="comment">/* clear all interrupts */3/spaval
 L158">v1583/a>        3a href="+code=writel" class="sref">writel3/a>(0xFFFF,v3a href="+code=io_base" class="sref">io_base3/a> +v3a href="+code=HSEM_ICRALL" class="sref">HSEM_ICRALL3/a>);l
 L159">v1593/a>l
 L160">v1603/a>        3a href="+code=ret" class="sref">ret3/a> =v3a href="+code=hwspin_lock_unregister" class="sref">hwspin_lock_unregister3/a>(3a href="+code=bank" class="sref">bank3/a>);l
 L161">v1613/a>        if (3a href="+code=ret" class="sref">ret3/a>) {l
 L162">v1623/a>                3a href="+code=dev_err" class="sref">dev_err3/a>(&3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>, 3spav class="string">"%s failed: %d\n"__func__3/a>,v3a href="+code=ret" class="sref">ret3/a>);l
 L163">v1633/a>                return 3a href="+code=ret" class="sref">ret3/a>;l
 L164">v1643/a>        }l
 L165">v1653/a>l
 L166">v1663/a>        3a href="+code=pm_runtime_disable" class="sref">pm_runtime_disable3/a>(&3a href="+code=pdev" class="sref">pdev3/a>->3a href="+code=dev" class="sref">dev3/a>);l
 L167">v1673/a>        3a href="+code=iounmap" class="sref">iounmap3/a>(3a href="+code=io_base" class="sref">io_base3/a>);l
 L168">v1683/a>        3a href="+code=kfree" class="sref">kfree3/a>(3a href="+code=bank" class="sref">bank3/a>);l
 L169">v1693/a>l
 L170">v1703/a>        return 0;l
 L171">v1713/a>}l
 L172">v1723/a>l
 L173">v1733/a>static structv3a href="+code=platform_driver" class="sref">platform_driver3/a> 3a href="+code=u8500_hsem_driver" class="sref">u8500_hsem_driver3/a> =v{l
 L174">v1743/a>        .3a href="+code=probe" class="sref">probe3/a>          =v3a href="+code=u8500_hsem_probe" class="sref">u8500_hsem_probe3/a>,l
 L175">v1753/a>        .3a href="+code=remove" class="sref">remove3/a>         =v3a href="+code=__devexit_p" class="sref">__devexit_p3/a>(3a href="+code=u8500_hsem_remove" class="sref">u8500_hsem_remove3/a>h165l135" class="line" nam>
 L135">v1353/a>lu8500_hsem_driver3/5">v1353/a>lbank3/a>);lpBv16wspinlock/u85k" cl65l135" class="lnk3/s3/a>);lv1353/a>l
 L78">v 78 }l
 L79">v 793/a>l
 1L80">v 8  3spav class1="com1ent">/pinlock/u8500_hsem.c#L93" id
 L93" class="lin1e" nam>
 1L81">v 813/a>3spav class1="com18hwspinlock/u8500_hsem.c#L122" id
 L122" class="lie" nam>
 1L82">v 823/a>3spav class1="com18f="+code=u85vexit" class="sref">_vinit3/a> 3a href="+c=u8500_hsem_probe" class="sref">u85vinit3/a> 3a href="="sref">u85vini00_hsomeminlock/u8500_hsem.c#L152" id
 L152" class="lie" nam>
 1L83">v 833/a>static void1v3a h18/hwspinlock/u8500_hsem.c#L74" id
 L74" class="lin1e" nam>
 1L84">v 84 {lplatform>hwspin_lock_register3/a"sref">platform>hwspin_le=pdev" class="sref">pdevs="sref">u8500_hsem_driver3/a> =v{l
 1L85">v 853/a>        3a 1href=1+code=inlock/u8500_hsem.c#L172" id
 L172" class="lie" nam>
 1L86">v 86 }l         * if equal, we/* boarill it >pde mricssuireck chrefrve #L172" id
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 L158" class="lie" nam>
 1L87">v 873/a>l(0xFFFF,v3a h"ost"dri5vinical/00_hsem_remove" class="sref">u8vinit3/a> 3a href="="sref">u85vini00_hpinlock/u8500_hsem.c#L169" id
 L169" class="lie" nam>
 L118">v 183/a>3spav class="rive18hwspinlock/u8500_hsem.c#L119" id
 L119" class="lie" nam>
 1L89">v 893/a>        .3a1 href18="+code=u850omem" class="sref">__ivexit3/a> 3a href="+c=u8500_hsem_remove" class="sref">u8vexit3/a> 3a href="s="sref">u8vexi00_hsomeminlock/u8500_hsem.c#L152" id
 L152" class="lie" nam>
 1L90">v 903/a>        .3a1 href19/hwspinlock/u8500_hsem.c#L61" id
 L61" class="lin1e" nam>
 1L91">v 913/a>        .3a1 href19code=io_base" class="sref">i"sref">platform>">hwspin_lock_unregister3"sref">platform>">hwspin_le=pdev" class="sref">pdevs="sref">u8500_hsem_driver3/a> =v{l
 1L92">v 923/a>};l
 1L93">v 933/a>lf="dri8vexit3/a> 3a href="f="dri8vexi00_hsem_remove" class="sref">u8vexit3/a> 3a href="s="sref">u8vexi00_hpinlock/u8500_hsem.c#L169" id
 L169" class="lie" nam>
 1L94">v 943/a>static intv13a hr19hwspinlock/u8500_hsem.c#L115" id
 L115" class="lie" nam>
 1L95">v 95 {lMODULA_LICENSA00_hseot;%s failed: %d\nGPL v2"+code=__funcpinlock/u8500_hsem.c#L169" id
 L169" class="lie" nam>
 1L96">v 963/a>        str1uctv319nmap_base" class="srMODULA_DESCRIPTIONX_SEMAPHORE3/a>MODULA_DESCRIPTION00_hseot;%s failed: %d\nHaril
 1L97">v 973/a>        str1uctv319hwspi_driver" class=MODULA_AUTHORX_SEMAPHORE3/a>MODULA_AUTHOR00_hseot;%s failed: %d\nMathieu Poirieme_locmathieu.poiriem@a> aro.org cla"+code=__funcpinlock/u8500_hsem.c#L169" id
 L169" class="lie" nam>
 LL98">v 983/a>        str1uctv31 href=


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