linux/drivers/edac/x38_edac.c
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   1 
a>/*
   2 
a> * Intel X38 Memory Controller kernel module
   3 
a> * Copyright (C) 2008 Cluster Computing, Inc.
   4 
a> *
   5 
a> * This file may be distributed under the terms of the
   6 
a> * GNU General Public License.
   7 
a> *
   8 
a> * This file is based on i3200_edac.c
   9 
a> *
  10 */
  11 
a>
  12 
a>#include <linux/module.h 
a>>
  13 
a>#include <linux/init.h 
a>>
  14 
a>#include <linux/pci.h 
a>>
  15 
a>#include <linux/pci_ids.h 
a>>
  16 
a>#include <linux/edac.h 
a>>
  17 
a>#include "edac_core.h 
a>"
  18 
a>
  19 
a>#define  a href="+code=X38_REVISION" class="sref">X38_REVISION 
a>            "1.1"
  20 
a>
  21 
a>#define  a href="+code=EDAC_MOD_STR" class="sref">EDAC_MOD_STR 
a>            "x38_edac"
  22 
a>
  23 
a>#define  a href="+code=PCI_DEVICE_ID_INTEL_X38_HB" class="sref">PCI_DEVICE_ID_INTEL_X38_HB 
a>      0x29e0
  24 
a>
  25 
a>#define  a href="+code=X38_RANKS" class="sref">X38_RANKS 
a>               8
  26 
a>#define  a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>   4
  27 
a>#define  a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>            2
  28 
a>
  29 
a>/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
  30 
a>
  31 
a>#define  a href="+code=X38_MCHBAR_LOW" class="sref">X38_MCHBAR_LOW 
a>  0x48    /* MCH Memory Mapped Register BAR */
  32 
a>#define  a href="+code=X38_MCHBAR_HIGH" class="sref">X38_MCHBAR_HIGH 
a> 0x4c
  33 
a>#define  a href="+code=X38_MCHBAR_MASK" class="sref">X38_MCHBAR_MASK 
a> 0xfffffc000ULL  /* bits 35:14 */
  34 
a>#define  a href="+code=X38_MMR_WINDOW_SIZE" class="sref">X38_MMR_WINDOW_SIZE 
a>     16384
  35 
a>
  36 
a>#define  a href="+code=X38_TOM" class="sref">X38_TOM 
a> 0xa0    /* Top of Memory (16b)
  37 
a>                                 *
  38 
a>                                 * 15:10 reserved
  39 
a>                                 *  9:0  total populated physical memory
  40                                 */
  41 
a>#define  a href="+code=X38_TOM_MASK" class="sref">X38_TOM_MASK 
a>    0x3ff   /* bits 9:0 */
  42 
a>#define  a href="+code=X38_TOM_SHIFT" class="sref">X38_TOM_SHIFT 
a> 26        /* 64MiB grain */
  43 
a>
  44 
a>#define  a href="+code=X38_ERRSTS" class="sref">X38_ERRSTS 
a>      0xc8    /* Error Status Register (16b)
  45 
a>                                 *
  46 
a>                                 * 15    reserved
  47 
a>                                 * 14    Isochronous TBWRR Run Behind FIFO Full
  48 
a>                                 *       (ITCV)
  49 
a>                                 * 13    Isochronous TBWRR Run Behind FIFO Put
  50                                 *       (ITSTV)
  51 
a>                                 * 12    reserved
  52 
a>                                 * 11    MCH Thermal Sensor Event
  53 
a>                                 *       for SMI/SCI/SERR (GTSE)
  54 
a>                                 * 10    reserved
  55 
a>                                 *  9    LOCK to non-DRAM Memory Flag (LCKF)
  56 
a>                                 *  8    reserved
  57 
a>                                 *  7    DRAM Throttle Flag (DTF)
  58 
a>                                 *  6:2  reserved
  59 
a>                                 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
  60                                 *  0    Single-bit DRAM ECC Error Flag (DSERR)
  61 
a>                                 */
  62 
a>#define  a href="+code=X38_ERRSTS_UE" class="sref">X38_ERRSTS_UE 
a>           0x0002
  63 
a>#define  a href="+code=X38_ERRSTS_CE" class="sref">X38_ERRSTS_CE 
a>           0x0001
  64 
a>#define  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a> ( a href="+code=X38_ERRSTS_UE" class="sref">X38_ERRSTS_UE 
a> |  a href="+code=X38_ERRSTS_CE" class="sref">X38_ERRSTS_CE 
a>)
  65 
a>
  66 
a>
  67 
a>/* Intel  MMIO register sptce - device 0 function 0 - MMR sptce */
  68 
a>
  69 
a>#define  a href="+code=X38_C0DRB" class="sref">X38_C0DRB 
a>       0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)
  70                                 *
  71 
a>                                 * 15:10 reserved
  72 
a>                                 *  9:0  Channel 0 DRAM Rank Boundary Address
  73 
a>                                 */
  74 
a>#define  a href="+code=X38_C1DRB" class="sref">X38_C1DRB 
a>       0x600   /* Channel 1 DRAM Rank Boundary (16b x 4) */
  75 
a>#define  a href="+code=X38_DRB_MASK" class="sref">X38_DRB_MASK 
a>    0x3ff   /* bits 9:0 */
  76 
a>#define  a href="+code=X38_DRB_SHIFT" class="sref">X38_DRB_SHIFT 
a> 26        /* 64MiB grain */
  77 
a>
  78 
a>#define  a href="+code=X38_C0ECCERRLOG" class="sref">X38_C0ECCERRLOG 
a> 0x280   /* Channel 0 ECC Error Log (64b)
  79 
a>                                 *
  80                                 * 63:48 Error Column Address (ERRCOL)
  81 
a>                                 * 47:32 Error Row Address (ERRROW)
  82 
a>                                 * 31:29 Error Bank Address (ERRBANK)
  83 
a>                                 * 28:27 Error Rank Address (ERRRANK)
  84 
a>                                 * 26:24 reserved
  85 
a>                                 * 23:16 Error Syndrome (ERRSYND)
  86 
a>                                 * 15: 2 reserved
  87 
a>                                 *    1  Multiple Bit Error Status (MERRSTS)
  88 
a>                                 *    0  Correctable Error Status (CERRSTS)
  89 
a>                                 */
  90 
a>#define  a href="+code=X38_C1ECCERRLOG" class="sref">X38_C1ECCERRLOG 
a> 0x680   /* Channel 1 ECC Error Log (64b) */
  91 
a>#define  a href="+code=X38_ECCERRLOG_CE" class="sref">X38_ECCERRLOG_CE 
a>        0x1
  92 
a>#define  a href="+code=X38_ECCERRLOG_UE" class="sref">X38_ECCERRLOG_UE 
a>        0x2
  93 
a>#define  a href="+code=X38_ECCERRLOG_RANK_BITS" class="sref">X38_ECCERRLOG_RANK_BITS 
a> 0x18000000
  94 
a>#define  a href="+code=X38_ECCERRLOG_SYNDROME_BITS" class="sref">X38_ECCERRLOG_SYNDROME_BITS 
a>     0xff0000
  95 
a>
  96 
a>#define  a href="+code=X38_CAPID0" class="sref">X38_CAPID0 
a> 0xe0 /* see P.94 of spec for details */
  97 
a>
  98 
a>static int  a href="+code=x38_channel_num" class="sref">x38_channel_num 
a>;
  99 
a>
 100 
a>static int  a href="+code=how_many_channel" class="sref">how_many_channel 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>)
 101 
a>{
 102 
a>        unsigned char  a href="+code=capid0_8b" class="sref">capid0_8b 
a>; /* 8th byte of CAPID0 */
 103 
a>
 104 
a>         a href="+code=pci_read_config_byte" class="sref">pci_read_config_byte 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_CAPID0" class="sref">X38_CAPID0 
a> + 8, & a href="+code=capid0_8b" class="sref">capid0_8b 
a>);
 105 
a>        if ( a href="+code=capid0_8b" class="sref">capid0_8b 
a> & 0x20) { /* check DCD: Dual Channel Disable */
 106 
a>                 a href="+code=edac_dbg" class="sref">edac_dbg 
a>(0, "In single channel mode\n");
 107 
a>                 a href="+code=x38_channel_num" class="sref">x38_channel_num 
a> = 1;
 108 
a>        } else {
 109 
a>                 a href="+code=edac_dbg" class="sref">edac_dbg 
a>(0, "In dual channel mode\n");
 110                 a href="+code=x38_channel_num" class="sref">x38_channel_num 
a> = 2;
 111 
a>        }
 112 
a>
 113 
a>        return  a href="+code=x38_channel_num" class="sref">x38_channel_num 
a>;
 114 
a>}
 115 
a>
 116 
a>static unsigned long  a href="+code=eccerrlog_syndrome" class="sref">eccerrlog_syndrome 
a>( a href="+code=u64" class="sref">u64 
a>  a href="+code=log" class="sref">log 
a>)
 117 
a>{
 118 
a>        return ( a href="+code=log" class="sref">log 
a> &  a href="+code=X38_ECCERRLOG_SYNDROME_BITS" class="sref">X38_ECCERRLOG_SYNDROME_BITS 
a>) >> 16;
 119 
a>}
 120 
a>
 121 
a>static int  a href="+code=eccerrlog_row" class="sref">eccerrlog_row 
a>(int  a href="+code=channel" class="sref">channel 
a>,  a href="+code=u64" class="sref">u64 
a>  a href="+code=log" class="sref">log 
a>)
 122 
a>{
 123 
a>        return (( a href="+code=log" class="sref">log 
a> &  a href="+code=X38_ECCERRLOG_RANK_BITS" class="sref">X38_ECCERRLOG_RANK_BITS 
a>) >> 27) |
 124                ( a href="+code=channel" class="sref">channel 
a> *  a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>);
 125 
a>}
 126 
a>
 127 
a>enum  a href="+code=x38_chips" class="sref">x38_chips 
a> {
 128 
a>         a href="+code=X38" class="sref">X38 
a> = 0,
 129 
a>};
 130 
a>
 131 
a>struct  a href="+code=x38_dev_info" class="sref">x38_dev_info 
a> {
 132 
a>        const char * a href="+code=ctl_name" class="sref">ctl_name 
a>;
 133 
a>};
 134 
a>
 135 
a>struct  a href="+code=x38_error_info" class="sref">x38_error_info 
a> {
 136 
a>         a href="+code=u16" class="sref">u16 
a>  a href="+code=errsts" class="sref">errsts 
a>;
 137 
a>         a href="+code=u16" class="sref">u16 
a>  a href="+code=errsts2" class="sref">errsts2 
a>;
 138 
a>         a href="+code=u64" class="sref">u64 
a>  a href="+code=eccerrlog" class="sref">eccerrlog 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>];
 139 
a>};
 140 
a>
 141 
a>static const struct  a href="+code=x38_dev_info" class="sref">x38_dev_info 
a>  a href="+code=x38_devs" class="sref">x38_devs 
a>[] = {
 142 
a>        [ a href="+code=X38" class="sref">X38 
a>] = {
 143 
a>                . a href="+code=ctl_name" class="sref">ctl_name 
a> = "x38"},
 144 
a>};
 145 
a>
 146 
a>static struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=mci_pdev" class="sref">mci_pdev 
a>;
 147 
a>static int  a href="+code=x38_registered" class="sref">x38_registered 
a> = 1;
 148 
a>
 149 
a>
 150 
a>static void  a href="+code=x38_clear_error_info" class="sref">x38_clear_error_info 
a>(struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a>)
 151 
a>{
 152 
a>        struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>;
 153 
a>
 154 
a>         a href="+code=pdev" class="sref">pdev 
a> = to_pci_dev 
a>( a href="+code=mci" class="sref">mci 
a>-> a href="+code=pdev" class="sref">pdev 
a>);
 155 
a>
 156 
a>         sptn class="comment">/*
 157 
a>         * Clear any error bits.
 158 
a>         * (Yes, we really clear bits by writing 1 to them.)
 159 
a>         */
 160 
a>         a href="+code=pci_write_bits16" class="sref">pci_write_bits16 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_ERRSTS" class="sref">X38_ERRSTS 
a>,  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>,
 161 
a>                          a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>);
 162 
a>}
 163 
a>
 164 
a>static  a href="+code=u64" class="sref">u64 
a>  a href="+code=x38_readq" class="sref">x38_readq 
a>(const void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=addr" class="sref">addr 
a>)
 165 
a>{
 166 
a>        return  a href="+code=readl" class="sref">readl 
a>( a href="+code=addr" class="sref">addr 
a>) | ((( a href="+code=u64" class="sref">u64 
a>) a href="+code=readl" class="sref">readl 
a>( a href="+code=addr" class="sref">addr 
a> + 4)) << 32);
 167 
a>}
 168 
a>
 169 
a>static void  a href="+code=x38_get_and_clear_error_info" class="sref">x38_get_and_clear_error_info 
a>(struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a>,
 170                                 struct  a href="+code=x38_error_info" class="sref">x38_error_info 
a> * a href="+code=info" class="sref">info 
a>)
 171 
a>{
 172 
a>        struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>;
 173 
a>        void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=window" class="sref">window 
a> = mci 
a>-> a href="+code=pvt_info" class="sref">pvt_info 
a>;
 174 
a>
 175 
a>         a href="+code=pdev" class="sref">pdev 
a> = to_pci_dev 
a>( a href="+code=mci" class="sref">mci 
a>-> a href="+code=pdev" class="sref">pdev 
a>);
 176 
a>
 177 
a>         sptn class="comment">/*
 178 
a>         * This is a mess because there is no atomic way to read all the
 179 
a>         * registers at once and the registers ctn transition from CE being
 180         * overwritten by UE.
 181 
a>         */
 182 
a>         a href="+code=pci_read_config_word" class="sref">pci_read_config_word 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_ERRSTS" class="sref">X38_ERRSTS 
a>, & a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a>);
 183 
a>        if (!( a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a> &  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>))
 184                return;
 185 
a>
 186 
a>         a href="+code=info" class="sref">info 
a>-> a href="+code=eccerrlog" class="sref">eccerrlog 
a>[0] = x38_readq 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C0ECCERRLOG" class="sref">X38_C0ECCERRLOG 
a>);
 187 
a>        if ( a href="+code=x38_channel_num" class="sref">x38_channel_num 
a> == 2)
 188                 a href="+code=info" class="sref">info 
a>-> a href="+code=eccerrlog" class="sref">eccerrlog 
a>[1] = x38_readq 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C1ECCERRLOG" class="sref">X38_C1ECCERRLOG 
a>);
 189 
a>
 190 
a>         a href="+code=pci_read_config_word" class="sref">pci_read_config_word 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_ERRSTS" class="sref">X38_ERRSTS 
a>, & a href="+code=info" class="sref">info 
a>-> a href="+code=errsts2" class="sref">errsts2 
a>);
 191 
a>
 192 
a>         sptn class="comment">/*
 193 
a>         * If the error is the same for both reads then the first set
 194 
a>         * of reads is valid.  If there is a change then there is a CE 
sptn>
 195 
a>         * with no info and the second set of reads is valid and 
sptn>
 196 
a>         * should be UE info.
 197 
a>         */
 198 
a>        if (( a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a> ^  a href="+code=info" class="sref">info 
a>-> a href="+code=errsts2" class="sref">errsts2 
a>) &  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>) {
 199 
a>                 a href="+code=info" class="sref">info 
a>-> a href="+code=eccerrlog" class="sref">eccerrlog 
a>[0] = x38_readq 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C0ECCERRLOG" class="sref">X38_C0ECCERRLOG 
a>);
 200                if ( a href="+code=x38_channel_num" class="sref">x38_channel_num 
a> == 2)
 201 
a>                         a href="+code=info" class="sref">info 
a>-> a href="+code=eccerrlog" class="sref">eccerrlog 
a>[1] =
 202 
a>                                 a href="+code=x38_readq" class="sref">x38_readq 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C1ECCERRLOG" class="sref">X38_C1ECCERRLOG 
a>);
 203 
a>        }
 204 
a>
 205 
a>         a href="+code=x38_clear_error_info" class="sref">x38_clear_error_info 
a>( a href="+code=mci" class="sref">mci 
a>);
 206 
a>}
 207 
a>
 208 
a>static void  a href="+code=x38_process_error_info" class="sref">x38_process_error_info 
a>(struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a>,
 209 
a>                                struct  a href="+code=x38_error_info" class="sref">x38_error_info 
a> * a href="+code=info" class="sref">info 
a>)
 210{
 211 
a>        int  a href="+code=channel" class="sref">channel 
a>;
 212 
a>         a href="+code=u64" class="sref">u64 
a>  a href="+code=log" class="sref">log 
a>;
 213 
a>
 214        if (!( a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a> &  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>))
 215 
a>                return;
 216 
a>
 217 
a>        if (( a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a> ^  a href="+code=info" class="sref">info 
a>-> a href="+code=errsts2" class="sref">errsts2 
a>) &  a href="+code=X38_ERRSTS_BITS" class="sref">X38_ERRSTS_BITS 
a>) {
 218                 a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error 
a>( a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED 
a>,  a href="+code=mci" class="sref">mci 
a>, 1, 0, 0, 0,
 219 
a>                                     -1, -1, -1,
 220                                      sptn class="string">"UE overwrote CE", "");
 221 
a>                 a href="+code=info" class="sref">info 
a>-> a href="+code=errsts" class="sref">errsts 
a> = info 
a>-> a href="+code=errsts2" class="sref">errsts2 
a>;
 222 
a>        }
 223 
a>
 224        for ( a href="+code=channel" class="sref">channel 
a> = 0;  a href="+code=channel" class="sref">channel 
a> <  a href="+code=x38_channel_num" class="sref">x38_channel_num 
a>;  a href="+code=channel" class="sref">channel 
a>++) {
 225 
a>                 a href="+code=log" class="sref">log 
a> = info 
a>-> a href="+code=eccerrlog" class="sref">eccerrlog 
a>[ a href="+code=channel" class="sref">channel 
a>];
 226 
a>                if ( a href="+code=log" class="sref">log 
a> &  a href="+code=X38_ECCERRLOG_UE" class="sref">X38_ECCERRLOG_UE 
a>) {
 227 
a>                         a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error 
a>( a href="+code=HW_EVENT_ERR_UNCORRECTED" class="sref">HW_EVENT_ERR_UNCORRECTED 
a>,  a href="+code=mci" class="sref">mci 
a>, 1,
 228                                             0, 0, 0,
 229 
a>                                              a href="+code=eccerrlog_row" class="sref">eccerrlog_row 
a>( a href="+code=channel" class="sref">channel 
a>,  a href="+code=log" class="sref">log 
a>),
 230                                             -1, -1,
 231 
a>                                              sptn class="string">"x38 UE", "");
 232 
a>                } else if ( a href="+code=log" class="sref">log 
a> &  a href="+code=X38_ECCERRLOG_CE" class="sref">X38_ECCERRLOG_CE 
a>) {
 233 
a>                         a href="+code=edac_mc_handle_error" class="sref">edac_mc_handle_error 
a>( a href="+code=HW_EVENT_ERR_CORRECTED" class="sref">HW_EVENT_ERR_CORRECTED 
a>,  a href="+code=mci" class="sref">mci 
a>, 1,
 234                                             0, 0,  a href="+code=eccerrlog_syndrome" class="sref">eccerrlog_syndrome 
a>( a href="+code=log" class="sref">log 
a>),
 235 
a>                                              a href="+code=eccerrlog_row" class="sref">eccerrlog_row 
a>( a href="+code=channel" class="sref">channel 
a>,  a href="+code=log" class="sref">log 
a>),
 236 
a>                                             -1, -1,
 237 
a>                                              sptn class="string">"x38 CE", "");
 238                }
 239 
a>        }
 240 
a>}
 241 
a>
 242 
a>static void  a href="+code=x38_check" class="sref">x38_check 
a>(struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a>)
 243 
a>{
 244        struct  a href="+code=x38_error_info" class="sref">x38_error_info 
a> info 
a>;
 245 
a>
 246 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(1, "MC%d\n",  a href="+code=mci" class="sref">mci 
a>-> a href="+code=mc_idx" class="sref">mc_idx 
a>);
 247 
a>         a href="+code=x38_get_and_clear_error_info" class="sref">x38_get_and_clear_error_info 
a>( a href="+code=mci" class="sref">mci 
a>, & a href="+code=info" class="sref">info 
a>);
 248 
a>         a href="+code=x38_process_error_info" class="sref">x38_process_error_info 
a>( a href="+code=mci" class="sref">mci 
a>, & a href="+code=info" class="sref">info 
a>);
 249 
a>}
 250 
a>
 251 
a>
 252 
a>void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=x38_map_mchbar" class="sref">x38_map_mchbar 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>)
 253 
a>{
 254 
a>        union {
 255 
a>                 a href="+code=u64" class="sref">u64 
a>  a href="+code=mchbar" class="sref">mchbar 
a>;
 256 
a>                struct {
 257 
a>                         a href="+code=u32" class="sref">u32 
a>  a href="+code=mchbar_low" class="sref">mchbar_low 
a>;
 258                         a href="+code=u32" class="sref">u32 
a>  a href="+code=mchbar_high" class="sref">mchbar_high 
a>;
 259 
a>                };
 260 
a>        }  a href="+code=u" class="sref">u 
a>;
 261 
a>        void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=window" class="sref">window 
a>;
 262 
a>
 263 
a>         a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_MCHBAR_LOW" class="sref">X38_MCHBAR_LOW 
a>, & a href="+code=u" class="sref">u 
a>. a href="+code=mchbar_low" class="sref">mchbar_low 
a>);
 264 
a>         a href="+code=pci_write_config_dword" class="sref">pci_write_config_dword 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_MCHBAR_LOW" class="sref">X38_MCHBAR_LOW 
a>,  a href="+code=u" class="sref">u 
a>. a href="+code=mchbar_low" class="sref">mchbar_low 
a> | 0x1);
 265 
a>         a href="+code=pci_read_config_dword" class="sref">pci_read_config_dword 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_MCHBAR_HIGH" class="sref">X38_MCHBAR_HIGH 
a>, & a href="+code=u" class="sref">u 
a>. a href="+code=mchbar_high" class="sref">mchbar_high 
a>);
 266 
a>         a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a> &= X38_MCHBAR_MASK 
a>;
 267 
a>
 268 
a>        if ( a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a> != ( a href="+code=resource_size_t" class="sref">resource_size_t 
a>) a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a>) {
 269 
a>                 a href="+code=printk" class="sref">printk 
a>( a href="+code=KERN_ERR" class="sref">KERN_ERR 
a>
 270                         sptn class="string">"x38: mmio sptce beyond accessible range (0x%llx)\n",
 271 
a>                        (unsigned long long) a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a>);
 272 
a>                return  a href="+code=NULL" class="sref">NULL 
a>;
 273 
a>        }
 274 
a>
 275 
a>         a href="+code=window" class="sref">window 
a> = ioremap_nocache 
a>( a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a>,  a href="+code=X38_MMR_WINDOW_SIZE" class="sref">X38_MMR_WINDOW_SIZE 
a>);
 276 
a>        if (! a href="+code=window" class="sref">window 
a>)
 277 
a>                 a href="+code=printk" class="sref">printk 
a>( a href="+code=KERN_ERR" class="sref">KERN_ERR 
a>  sptn class="string">"x38: cannot map mmio sptce at 0x%llx\n",
 278                        (unsigned long long) a href="+code=u" class="sref">u 
a>. a href="+code=mchbar" class="sref">mchbar 
a>);
 279 
a>
 280        return  a href="+code=window" class="sref">window 
a>;
 281 
a>}
 282 
a>
 283 
a>
 284 
a>static void  a href="+code=x38_get_drbs" class="sref">x38_get_drbs 
a>(void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=window" class="sref">window 
a>,
 285 
a>                         a href="+code=u16" class="sref">u16 
a>  a href="+code=drbs" class="sref">drbs 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>])
 286 
a>{
 287 
a>        int  a href="+code=i" class="sref">i 
a>;
 288 
a>
 289 
a>        for ( a href="+code=i" class="sref">i 
a> = 0;  a href="+code=i" class="sref">i 
a> <  a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>;  a href="+code=i" class="sref">i 
a>++) {
 290                 a href="+code=drbs" class="sref">drbs 
a>[0][ a href="+code=i" class="sref">i 
a>] = readw 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C0DRB" class="sref">X38_C0DRB 
a> + 2* a href="+code=i" class="sref">i 
a>) &  a href="+code=X38_DRB_MASK" class="sref">X38_DRB_MASK 
a>;
 291 
a>                 a href="+code=drbs" class="sref">drbs 
a>[1][ a href="+code=i" class="sref">i 
a>] = readw 
a>( a href="+code=window" class="sref">window 
a> +  a href="+code=X38_C1DRB" class="sref">X38_C1DRB 
a> + 2* a href="+code=i" class="sref">i 
a>) &  a href="+code=X38_DRB_MASK" class="sref">X38_DRB_MASK 
a>;
 292 
a>        }
 293 
a>}
 294 
a>
 295 
a>static  a href="+code=bool" class="sref">bool 
a>  a href="+code=x38_is_stacked" class="sref">x38_is_stacked 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>,
 296 
a>                         a href="+code=u16" class="sref">u16 
a>  a href="+code=drbs" class="sref">drbs 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>])
 297 
a>{
 298 
a>         a href="+code=u16" class="sref">u16 
a>  a href="+code=tom" class="sref">tom 
a>;
 299 
a>
 300 
a>         a href="+code=pci_read_config_word" class="sref">pci_read_config_word 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=X38_TOM" class="sref">X38_TOM 
a>, & a href="+code=tom" class="sref">tom 
a>);
 301 
a>         a href="+code=tom" class="sref">tom 
a> &= X38_TOM_MASK 
a>;
 302 
a>
 303 
a>        return  a href="+code=drbs" class="sref">drbs 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a> - 1][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a> - 1] ==  a href="+code=tom" class="sref">tom 
a>;
 304 
a>}
 305 
a>
 306 
a>static unsigned long  a href="+code=drb_to_nr_pages" class="sref">drb_to_nr_pages 
a>(
 307 
a>                         a href="+code=u16" class="sref">u16 
a>  a href="+code=drbs" class="sref">drbs 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>],
 308                         a href="+code=bool" class="sref">bool 
a>  a href="+code=stacked" class="sref">stacked 
a>, int  a href="+code=channel" class="sref">channel 
a>, int  a href="+code=rank" class="sref">rank 
a>)
 309 
a>{
 310 
a>        int  a href="+code=n" class="sref">n 
a>;
 311 
a>
 312 
a>         a href="+code=n" class="sref">n 
a> = drbs 
a>[ a href="+code=channel" class="sref">channel 
a>][ a href="+code=rank" class="sref">rank 
a>];
 313 
a>        if ( a href="+code=rank" class="sref">rank 
a> > 0)
 314                 a href="+code=n" class="sref">n 
a> -= drbs 
a>[ a href="+code=channel" class="sref">channel 
a>][ a href="+code=rank" class="sref">rank 
a> - 1];
 315 
a>        if ( a href="+code=stacked" class="sref">stacked 
a> && ( a href="+code=channel" class="sref">channel 
a> == 1) && drbs 
a>[ a href="+code=channel" class="sref">channel 
a>][ a href="+code=rank" class="sref">rank 
a>] ==
 316 
a>                                drbs 
a>[ a href="+code=channel" class="sref">channel 
a>][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a> - 1]) {
 317 
a>                 a href="+code=n" class="sref">n 
a> -= drbs 
a>[0][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a> - 1];
 318        }
 319 
a>
 320 
a>         a href="+code=n" class="sref">n 
a> <<= ( a href="+code=X38_DRB_SHIFT" class="sref">X38_DRB_SHIFT 
a> -  a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT 
a>);
 321 
a>        return  a href="+code=n" class="sref">n 
a>;
 322 
a>}
 323 
a>
 324 
a>static int  a href="+code=x38_probe1" class="sref">x38_probe1 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>, int  a href="+code=dev_idx" class="sref">dev_idx 
a>)
 325 
a>{
 326 
a>        int  a href="+code=rc" class="sref">rc 
a>;
 327 
a>        int  a href="+code=i" class="sref">i 
a>,  a href="+code=j" class="sref">j 
a>;
 328        struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a> = NULL 
a>;
 329 
a>        struct  a href="+code=edac_mc_layer" class="sref">edac_mc_layer 
a>  a href="+code=layers" class="sref">layers 
a>[2];
 330 
a>         a href="+code=u16" class="sref">u16 
a>  a href="+code=drbs" class="sref">drbs 
a>[ a href="+code=X38_CHANNELS" class="sref">X38_CHANNELS 
a>][ a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>];
 331 
a>         a href="+code=bool" class="sref">bool 
a>  a href="+code=stacked" class="sref">stacked 
a>;
 332 
a>        void  a href="+code=__iomem" class="sref">__iomem 
a> * a href="+code=window" class="sref">window 
a>;
 333 
a>
 334 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(0, "MC:\n");
 335 
a>
 336 
a>         a href="+code=window" class="sref">window 
a> = x38_map_mchbar 
a>( a href="+code=pdev" class="sref">pdev 
a>);
 337 
a>        if (! a href="+code=window" class="sref">window 
a>)
 338                return - a href="+code=ENODEV" class="sref">ENODEV 
a>;
 339 
a>
 340 
a>         a href="+code=x38_get_drbs" class="sref">x38_get_drbs 
a>( a href="+code=window" class="sref">window 
a>,  a href="+code=drbs" class="sref">drbs 
a>);
 341 
a>
 342 
a>         a href="+code=how_many_channel" class="sref">how_many_channel 
a>( a href="+code=pdev" class="sref">pdev 
a>);
 343 
a>
 344         sptn class="comment">/* FIXME: unconventional pvt_info usage */
 345 
a>         a href="+code=layers" class="sref">layers 
a>[0]. a href="+code=type" class="sref">type 
a> = EDAC_MC_LAYER_CHIP_SELECT 
a>;
 346 
a>         a href="+code=layers" class="sref">layers 
a>[0]. a href="+code=size" class="sref">size 
a> = X38_RANKS 
a>;
 347 
a>         a href="+code=layers" class="sref">layers 
a>[0]. a href="+code=is_virt_csrow" class="sref">is_virt_csrow 
a> = true 
a>;
 348 
a>         a href="+code=layers" class="sref">layers 
a>[1]. a href="+code=type" class="sref">type 
a> = EDAC_MC_LAYER_CHANNEL 
a>;
 349 
a>         a href="+code=layers" class="sref">layers 
a>[1]. a href="+code=size" class="sref">size 
a> = x38_channel_num 
a>;
 350 
a>         a href="+code=layers" class="sref">layers 
a>[1]. a href="+code=is_virt_csrow" class="sref">is_virt_csrow 
a> = false 
a>;
 351 
a>         a href="+code=mci" class="sref">mci 
a> = edac_mc_alloc 
a>(0, ARRAY_SIZE 
a>( a href="+code=layers" class="sref">layers 
a>),  a href="+code=layers" class="sref">layers 
a>, 0);
 352 
a>        if (! a href="+code=mci" class="sref">mci 
a>)
 353 
a>                return - a href="+code=ENOMEM" class="sref">ENOMEM 
a>;
 354 
a>
 355 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(3, "MC: init mci\n");
 356 
a>
 357 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=pdev" class="sref">pdev 
a> = & a href="+code=pdev" class="sref">pdev 
a>-> a href="+code=dev" class="sref">dev 
a>;
 358 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=mtype_cap" class="sref">mtype_cap 
a> = MEM_FLAG_DDR2 
a>;
 359 
a>
 360 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=edac_ctl_cap" class="sref">edac_ctl_cap 
a> = EDAC_FLAG_SECDED 
a>;
 361 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=edac_cap" class="sref">edac_cap 
a> = EDAC_FLAG_SECDED 
a>;
 362 
a>
 363 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=mod_name" class="sref">mod_name 
a> = EDAC_MOD_STR 
a>;
 364 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=mod_ver" class="sref">mod_ver 
a> = X38_REVISION 
a>;
 365 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=ctl_name" class="sref">ctl_name 
a> = x38_devs 
a>[ a href="+code=dev_idx" class="sref">dev_idx 
a>]. a href="+code=ctl_name" class="sref">ctl_name 
a>;
 366 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=dev_name" class="sref">dev_name 
a> = pci_name 
a>( a href="+code=pdev" class="sref">pdev 
a>);
 367 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=edac_check" class="sref">edac_check 
a> = x38_check 
a>;
 368 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=ctl_page_to_phys" class="sref">ctl_page_to_phys 
a> = NULL 
a>;
 369 
a>         a href="+code=mci" class="sref">mci 
a>-> a href="+code=pvt_info" class="sref">pvt_info 
a> = window 
a>;
 370 
a>
 371 
a>         a href="+code=stacked" class="sref">stacked 
a> = x38_is_stacked 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=drbs" class="sref">drbs 
a>);
 372 
a>
 373 
a>         sptn class="comment">/*
 374 
a> sptn class="comment">         * The dram rank boundary (DRB) reg values are boundary addresses 
sptn>
 375 
a> sptn class="comment">         * for each DRAM rank with a granularity of 64MB.  DRB regs are 
sptn>
 376 
a> sptn class="comment">         * cumulative; the last one will contain the total memory 
sptn>
 377 
a> sptn class="comment">         * contained in all ranks. 
sptn>
 378 sptn class="comment">         */
 379 
a>        for ( a href="+code=i" class="sref">i 
a> = 0;  a href="+code=i" class="sref">i 
a> <  a href="+code=mci" class="sref">mci 
a>-> a href="+code=nr_csrows" class="sref">nr_csrows 
a>;  a href="+code=i" class="sref">i 
a>++) {
 380                unsigned long  a href="+code=nr_pages" class="sref">nr_pages 
a>;
 381 
a>                struct  a href="+code=csrow_info" class="sref">csrow_info 
a> * a href="+code=csrow" class="sref">csrow 
a> = mci 
a>-> a href="+code=csrows" class="sref">csrows 
a>[ a href="+code=i" class="sref">i 
a>];
 382 
a>
 383 
a>                 a href="+code=nr_pages" class="sref">nr_pages 
a> = drb_to_nr_pages 
a>( a href="+code=drbs" class="sref">drbs 
a>,  a href="+code=stacked" class="sref">stacked 
a>,
 384                         a href="+code=i" class="sref">i 
a> /  a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>,
 385 
a>                         a href="+code=i" class="sref">i 
a> %  a href="+code=X38_RANKS_PER_CHANNEL" class="sref">X38_RANKS_PER_CHANNEL 
a>);
 386 
a>
 387 
a>                if ( a href="+code=nr_pages" class="sref">nr_pages 
a> == 0)
 388                        continue;
 389 
a>
 390                for ( a href="+code=j" class="sref">j 
a> = 0;  a href="+code=j" class="sref">j 
a> <  a href="+code=x38_channel_num" class="sref">x38_channel_num 
a>;  a href="+code=j" class="sref">j 
a>++) {
 391 
a>                        struct  a href="+code=dimm_info" class="sref">dimm_info 
a> * a href="+code=dimm" class="sref">dimm 
a> = csrow 
a>-> a href="+code=channels" class="sref">channels 
a>[ a href="+code=j" class="sref">j 
a>]-> a href="+code=dimm" class="sref">dimm 
a>;
 392 
a>
 393 
a>                         a href="+code=dimm" class="sref">dimm 
a>-> a href="+code=nr_pages" class="sref">nr_pages 
a> = nr_pages 
a> /  a href="+code=x38_channel_num" class="sref">x38_channel_num 
a>;
 394                         a href="+code=dimm" class="sref">dimm 
a>-> a href="+code=grain" class="sref">grain 
a> = nr_pages 
a> <<  a href="+code=PAGE_SHIFT" class="sref">PAGE_SHIFT 
a>;
 395 
a>                         a href="+code=dimm" class="sref">dimm 
a>-> a href="+code=mtype" class="sref">mtype 
a> = MEM_DDR2 
a>;
 396 
a>                         a href="+code=dimm" class="sref">dimm 
a>-> a href="+code=dtype" class="sref">dtype 
a> = DEV_UNKNOWN 
a>;
 397 
a>                         a href="+code=dimm" class="sref">dimm 
a>-> a href="+code=edac_mode" class="sref">edac_mode 
a> = EDAC_UNKNOWN 
a>;
 398                }
 399 
a>        }
 400 
a>
 401 
a>         a href="+code=x38_clear_error_info" class="sref">x38_clear_error_info 
a>( a href="+code=mci" class="sref">mci 
a>);
 402 
a>
 403 
a>         a href="+code=rc" class="sref">rc 
a> = - a href="+code=ENODEV" class="sref">ENODEV 
a>;
 404        if ( a href="+code=edac_mc_add_mc" class="sref">edac_mc_add_mc 
a>( a href="+code=mci" class="sref">mci 
a>)) {
 405 
a>                 a href="+code=edac_dbg" class="sref">edac_dbg 
a>(3, "MC: failed edac_mc_add_mc()\n");
 406 
a>                goto fail 
a>;
 407 
a>        }
 408 
a>
 409 
a>         sptn class="comment">/* get this far and it's successful */
 410 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(3, "MC: success\n");
 411 
a>        return 0;
 412 
a>
 413 
a>fail 
a>:
 414 
a>         a href="+code=iounmap" class="sref">iounmap 
a>( a href="+code=window" class="sref">window 
a>);
 415 
a>        if ( a href="+code=mci" class="sref">mci 
a>)
 416 
a>                 a href="+code=edac_mc_free" class="sref">edac_mc_free 
a>( a href="+code=mci" class="sref">mci 
a>);
 417 
a>
 418        return  a href="+code=rc" class="sref">rc 
a>;
 419 
a>}
 420 
a>
 421 
a>static int  a href="+code=__devinit" class="sref">__devinit x38_init_one 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>,
 422 
a>                                const struct  a href="+code=pci_device_id" class="sref">pci_device_id 
a> * a href="+code=ent" class="sref">ent 
a>)
 423 
a>{
 424        int  a href="+code=rc" class="sref">rc 
a>;
 425 
a>
 426 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(0, "MC:\n");
 427 
a>
 428 
a>        if ( a href="+code=pci_enable_device" class="sref">pci_enable_device 
a>( a href="+code=pdev" class="sref">pdev 
a>) < 0)
 429 
a>                return - a href="+code=EIO" class="sref">EIO 
a>;
 430 
a>
 431 
a>         a href="+code=rc" class="sref">rc 
a> = x38_probe1 
a>( a href="+code=pdev" class="sref">pdev 
a>,  a href="+code=ent" class="sref">ent 
a>-> a href="+code=driver_data" class="sref">driver_data 
a>);
 432 
a>        if (! a href="+code=mci_pdev" class="sref">mci_pdev 
a>)
 433 
a>                 a href="+code=mci_pdev" class="sref">mci_pdev 
a> = pci_dev_get 
a>( a href="+code=pdev" class="sref">pdev 
a>);
 434 
a>
 435 
a>        return  a href="+code=rc" class="sref">rc 
a>;
 436 
a>}
 437 
a>
 438static void  a href="+code=__devexit" class="sref">__devexit x38_remove_one 
a>(struct  a href="+code=pci_dev" class="sref">pci_dev 
a> * a href="+code=pdev" class="sref">pdev 
a>)
 439 
a>{
 440 
a>        struct  a href="+code=mem_ctl_info" class="sref">mem_ctl_info 
a> * a href="+code=mci" class="sref">mci 
a>;
 441 
a>
 442 
a>         a href="+code=edac_dbg" class="sref">edac_dbg 
a>(0, "\n");
 443 
a>
 444 
a>         a href="+code=mci" class="sref">mci 
a> = edac_mc_del_mc 
a>(& a href="+code=pdev" class="sref">pdev 
a>-> a href="+code=dev" class="sref">dev 
a>);
 445 
a>        if (! a href="+code=mci" class="sref">mci 
a>)
 446 
a>                return;
 447 
a>
 448 
a>         a href="+code=iounmap" class="sref">iounmap 
a>( a href="+code=mci" class="sref">mci 
a>-> a href="+code=pvt_info" class="sref">pvt_info 
a>);
 449 
a>
 450 
a>         a href="+code=edac_mc_free" class="sref">edac_mc_free 
a>( a href="+code=mci" class="sref">mci 
a>);
 451 
a>}
 452 
a>
 453 
a>static  a href="+code=DEFINE_PCI_DEVICE_TABLE" class="sref">DEFINE_PCI_DEVICE_TABLE 
a>( a href="+code=x38_pci_tbl" class="sref">x38_pci_tbl 
a>) = {
 454 
a>        {
 455 
a>          a href="+code=PCI_VEND_DEV" class="sref">PCI_VEND_DEV 
a>( a href="+code=INTEL" class="sref">INTEL 
a>,  a href="+code=X38_HB" class="sref">X38_HB 
a>),  a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID 
a>,  a href="+code=PCI_ANY_ID" class="sref">PCI_ANY_ID 
a>, 0, 0,
 456 
a>          a href="+code=X38" class="sref">X38 
a>},
 457 
a>        {
 458 
a>         0,
 459 
a>         }                       sptn class="comment">/* 0 terminated list. */
 460 
a>};
 461 
a>
 462 
a> a href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLE 
a>( a href="+code=pci" class="sref">pci 
a>,  a href="+code=x38_pci_tbl" class="sref">x38_pci_tbl 
a>);
 463 
a>
 464 
a>static struct  a href="+code=pci_driver" class="sref">pci_driver x38_driver 
a> = {
 465 
a>        . a href="+code=name" class="sref">name 
a> = EDAC_MOD_STR 
a>,
 466 
a>        . a href="+code=probe" class="sref">probe 
a> = x38_init_one 
a>,
 4 
a>         a. a href="+code=emove_de=PCI_ANY_ID" cef">mci 
a>-> a href="+B38_edac.c#L442" id="L442" class="line" nait mc1s="sref">2s/eda32" 6ac.ct mc1s="sref">2s/eda32" 6ac.ct mc1s="srt mc1s="sref">2s/eda32" 6ac.ct mc1s="st; a href="+B38_edac.c#L442" id="L442" c+code=iounmap" cla4code=mci" clascsrow" class="sred_t"+coa>( a href="+codd_t"+co8_probe1" class="sref">x38__pci_tbl 
a>);
 369 
a>         a 4ref="4code=m/x38_edac.c#L461" id="L461" class="line" name="4370"> 370 
a>
 371 
a>         a 4ref="47"+code=__devinit" class="sref">__init x38_ione 
a>,
 372 
a>
 373 
a>         sp4n cla4s="comment">/*init" class="sref">( a hdel_mc 
a>(&( a hddac/x38_edac.c#L441" id="L441" class="line" name="4374"> 374 
a> sptn class4"comm47dac/x38_edac.c#L435" id="L435" class="line" name="4375"> 375 
a> sptn class4"comm47ode=edac_dbg" class="sref">edac_dbg 
a>(3, "MC: init mci\n"f="drivers/edac/x38_edac.c#L443" id="L443" class="line" name="4376"> 376 
a> sptn class4"comm47dac/x38_edac.c#L387" id="L387" class="li4e" name="4377"> 377 
a> sptn class4"comm47ode=mci" class0 terminated list. */ 378 sptn class4"comm47ode=iounmap" class="sref">ioope=__ex38_ione 
a>,
/x38_edac.c#L443" id="L443" class="line" name="L379"> 379 
a>        for4( a h47dac/x38_edac.c#L450" id="L450" class="line" name="4380"> 380           4    u48ode=pci_read_config_word" class="del_mc 
a>(&( a hddac/v_get" class="sref">pcregdririvedriver pdev >x38_driver 
a> = {
 381 
a>           4    s4ruct  a href="nable_device" class="sr"del_mc 
a>(&( a hddac/v/edac/x38_edac.c#L429" id="L429" class="line" name="4382"> 382 
a>
fail 
a>;0el_mc 
a>(&
a>;0dac/x38_edac.c#L441" id="L441" class="line" name="4383"> 383 
a>           4     48dac/x38_edac.c#L464" id="L464" class="line" name="4384"> 384           4     48="+code=edac_mc_a" class="sref">mci_pdev 
a>)
 385 
a>           4     4       a href="+code=i6ac.ct mc1s="sref">2sgdriristacked 
a>( a href="2sgdriristdac/v_g/x38_edac.c#L412" id="L412" class="line" name="4386"> 386 
a>
pcode=wenable_device 
a>( a hreode=wenabla32" 6ac.ct mc1s="sr="+code=OR_ID_L 
a>,  a href="+cod="+code=OR_ID_L 
a>edaca32" 6ac.ct mc1s="st; a href="+B38_ede" name="4387"> 387 
a>           4    i4 ( a href="+code=nr_paaaaaaaaaaaaaaaaaaaaaaaaa6ac.ct mc1s="sr="+c="+codeID_L 
a>__HB 
a>),  a href="+c="+c="+codeID_L 
a>__HB 
a_pci_tbl" class="sref
a>;
 388           4     4      continue;
mci_pdev 
a>)
 389 
a>
"\n");
 390           4    f4r ( a href="+code=j" caaaaaaaa6ac.ct mc1s="srass="del_mc 
a>(&( a hddac/v_gclass="sref">ENODEV 
a>;
 391 
a>           4     4      struct  a href="+code=di" class="sref">fail 
a>;e1 
a>( a href="
a>;edac/x38_edac.c#L404" id="L404" class="line" name="4392"> 392 
a>
 393 
a>           4     49dac/x38_edac.c#L464" id="L464" class="line" name="4394"> 394           4     4       a href="+code=dconfig_word" class="del_mc 
a>(&( a hddac/v_get" class="sreff">x38_init_one 
a>(struct  a href="+code=pc class="sref">mci_pdev 
a>)
x38_pci_tbl 
a>);
 395 
a>           4     4       a href="+code=dnable_device" class="sr"del_mc 
a>(&( a hddac/v/edac/x/x38_edac.c#L465" id="L465" class="line" name="4396"> 396 
a>           4     4       a href="+code=dimm" class="sref">dimm dac_dbg 
a>(0, "\n");
 397 
a>           4     4       a href="+code=dimm" class="sref">dimm ass="del_mc 
a>(&( a hddac/v_gclass="sref">ENODEV 
a>;
 398           4    }4fail 
a>;e1 
a>( a href="
a>;edac/x38_edac.c#L404" id="L404" class="line" name="L399"> 399 
a>        }
<4 href49urn - a href="+code=Ex38_edac.c#L452" id="L452" class="li5e" name="5400"> 400 
a>
 391 
a>           5ref="50dac/x38_edac.c#L462" id="L462" class="li5e" name="5402"> 402 
a>
 403 
a>         a 5ref="50dac/x38_edac.c#L464" id="L464" class="li5e" name="5404"> 404        if 5 a hr5f="+coss="sref">fail 
a>;e1 
a>( a href="
a>;edac/x38_edac.c#L414" id="L414" class="li5e" name="5405"> 405 
a>           5     50ode=edac_dbg" class="sref">e( a unregdririvedriver pdev >x38_driver 
a> = {
 406 
a>           5    g50dac/x38_edac.c#L387" id="L387" class="li5e" name="5407"> 407 
a>        }
<5 href5"drivess="sref">fail 
a>;0el_mc 
a>(&
a>;0dac/x38_edac.c#L414" id="L414" class="li5e8 name="5498"> 398           5ivers50="+code=pci_enable_device" classci_pdev 
a>)
 409 
a>         sp5n cla50urn - a href="+code=Er" class="sref">pci_ev_puget 
a>( a href="+code=ppugde=pc class="sref">mci_pdev 
a>)
 410 
a>         a 5ref="51dac/x38_edac.c#L371" id="L371" class="li5e" name="5411"> 411 
a>        ret5rn 0;5( a hdel_mc 
a>(&( a hddac/x38_edac.c#L441" id="L441" class="li5e" name="5412"> 412 
a>
 413 
a> 414 
a>         a 5ref="51ef="+code=pcvexit" class="sref">__exit   415 
a>        if 5 a hr51edac/x38_edac.c#L326" id="L326" class="li5e" name="5416"> 416 
a>           5     51ode=edac_dbg" class="sref">edac_dbg 
a>(0, "MC: init mci\n"f="drivers/edac/x38_edac.c#L443" id="L443" class="li5e" name="5417"> 417 
a>
 418        ret5rn  a51ode=iounmap" class="sref">io( a unregdririvedriver pdev >x38_driver 
a> = {
 419 
a>}
mef">2sgdriristacked 
a>( a href="2sgdriristdac/x/x38_edac.c#L465" id="L465" class="li5e" name="5420"> 420 
a>
2s/eda32" 6ac.ct mc1s="srt mc1s="sref">2s/ec class="sref">mci_pdev 
a>)
 421 
a>static int 5a hre52     struct  a href="r" class="sref">pci_ev_puget 
a>( a href="+code=ppugde=pc class="sref">mci_pdev 
a>)
 422 
a>           5     5              x38_edac.c#L323" id="L323" class="li5e" name="5423"> 423 
a>{
 424        int5 a hr52dac/x38_edac.c#L435" id="L435" class="li5e" name="5425"> 425 
a>
mcodulex38_ione 
a>,
38_ione 
a>,
 426 
a>         a 5ref="5code=e class="sref">mcodulexexit exit  427 
a>
 428 
a>        if 5 a hr5f="+co6ac.ct mc1s="sr a hrefLICENSEVICE_TABLE 
a>( a hrefLICENSEa32" 6t;MC: init mci\n" 429 
a>           5    r5turn -6ac.ct mc1s="sr a hrefAUTHO_STR 
a>,
 430 
a>
;
 431 
a>         a 5ref="53dac/x38_edac.c#L462" id="L462" class="li5e" name="5432"> 432 
a>        if 5! a h53LE_DEVICE_TABLE" clacodulexpara-> a href="+ccodulexpara-a32" 6ac.ct mc1s="srass="op_e=__e
a>(0,  433 
a>           5     53" class="sref">fail  a hrefPARMfDESCION 
a>;
(0,  434 
a>
 434 
fooiri">
DRB)origiptn>LXR softwsptn>y
LXR  lisuiveydac/_tccessexperist. tn>3" iionn>y
8_edac.c#mailto:lxi@a>
ux.no">lxi@a>
ux.nodac/.

 434 
subfooiri">
lxi.a>
ux.no kindls hosref=>y
8_edac.c#http://www.istpill-a>
pro.no">Rstpill L>
pro ASdac/_tprovidri of L>
uxcode=ultn&q */