linux/drivers/edac/mpc85xx_edac.c
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   1/*
   2 * Freescale MPC85xx Memory Controller kenel module
   3 *
   4 * Author: Dave Jiang <djiang@mvista.com>
   5 *
   6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
   7 * the terms of the GNU General Public License version 2. This program
   8 * is licensed "as is" without any warranty of any kind, whether express
   9 * or implied.
  10 *
  11 */
  12#include <linux/module.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/ctype.h>
  16#include <linux/io.h>
  17#include <linux/mod_devicetable.h>
  18#include <linux/edac.h>
  19#include <linux/smp.h>
  20#include <linux/gfp.h>
  21
  22#include <linux/of_platform.h>
  23#include <linux/of_device.h>
  24#include "edac_module.h"
  25#include "edac_core.h"
  26#include "mpc85xx_edac.h"
  27
  28static int edac_dev_idx;
  29#ifdef CONFIG_PCI
  30static int edac_pci_idx;
  31#endif
  32static int edac_mc_idx;
  33
  34static u32 orig_ddr_err_disable;
  35static u32 orig_ddr_err_sbe;
  36
  37/*
  38 * PCI Err defines
  39 */
  40#ifdef CONFIG_PCI
  41static u32 orig_pci_err_cap_dr;
  42static u32 orig_pci_err_en;
  43#endif
  44
  45static u32 orig_l2_err_disable;
  46#ifdef CONFIG_FSL_SOC_BOOKE
  47static u32 orig_hid1[2];
  48#endif
  49
  50/************************ MC SYSFS parts ***********************************/
  51
  52#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  53
  54static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
  55                                              struct device_attribute *mattr,
  56                                              char *data)
  57{
  58        struct mem_ctl_info *mci = to_mci(dev);
  59        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  60        return sprintf(data, "0x%08x",
  61                       in_be32(pdata->mc_vbase +
  62                               MPC85XX_MC_DATA_ERR_INJECT_HI));
  63}
  64
  65static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
  66                                              struct device_attribute *mattr,
  67                                              char *data)
  68{
  69        struct mem_ctl_info *mci = to_mci(dev);
  70        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  71        return sprintf(data, "0x%08x",
  72                       in_be32(pdata->mc_vbase +
  73                               MPC85XX_MC_DATA_ERR_INJECT_LO));
  74}
  75
  76static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
  77                                           struct device_attribute *mattr,
  78                                           char *data)
  79{
  80        struct mem_ctl_info *mci = to_mci(dev);
  81        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  82        return sprintf(data, "0x%08x",
  83                       in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
  84}
  85
  86static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
  87                                               struct device_attribute *mattr,
  88                                               const char *data, size_t count)
  89{
  90        struct mem_ctl_info *mci = to_mci(dev);
  91        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
  92        if (isdigit(*data)) {
  93                out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
  94                         simple_strtoul(data, NULL, 0));
  95                return count;
  96        }
  97        return 0;
  98}
  99
 100static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
 101                                               struct device_attribute *mattr,
 102                                               const char *data, size_t count)
 103{
 104        struct mem_ctl_info *mci = to_mci(dev);
 105        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 106        if (isdigit(*data)) {
 107                out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
 108                         simple_strtoul(data, NULL, 0));
 109                return count;
 110        }
 111        return 0;
 112}
 113
 114static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
 115                                               struct device_attribute *mattr,
 116                                               const char *data, size_t count)
 117{
 118        struct mem_ctl_info *mci = to_mci(dev);
 119        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 120        if (isdigit(*data)) {
 121                out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
 122                         simple_strtoul(data, NULL, 0));
 123                return count;
 124        }
 125        return 0;
 126}
 127
 128DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
 129            mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
 130DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
 131            mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
 132DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
 133            mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
 134
 135static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci)
 136{
 137        int rc;
 138
 139        rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi);
 140        if (rc < 0)
 141                return rc;
 142        rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo);
 143        if (rc < 0)
 144                return rc;
 145        rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl);
 146        if (rc < 0)
 147                return rc;
 148
 149        return 0;
 150}
 151
 152static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci)
 153{
 154        device_remove_file(&mci->dev, &dev_attr_inject_data_hi);
 155        device_remove_file(&mci->dev, &dev_attr_inject_data_lo);
 156        device_remove_file(&mci->dev, &dev_attr_inject_ctrl);
 157}
 158
 159/**************************** PCI Err device ***************************/
 160#ifdef CONFIG_PCI
 161
 162static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
 163{
 164        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 165        u32 err_detect;
 166
 167        err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 168
 169        /* master aborts can happen during PCI config cycles */
 170        if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
 171                out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 172                return;
 173        }
 174
 175        printk(KERN_ERR "PCI error(s) detected\n");
 176        printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
 177
 178        printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
 179               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
 180        printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
 181               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
 182        printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
 183               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
 184        printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
 185               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
 186        printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
 187               in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
 188
 189        /* clear error bits */
 190        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
 191
 192        if (err_detect & PCI_EDE_PERR_MASK)
 193                edac_pci_handle_pe(pci, pci->ctl_name);
 194
 195        if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
 196                edac_pci_handle_npe(pci, pci->ctl_name);
 197}
 198
 199static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
 200{
 201        struct edac_pci_ctl_info *pci = dev_id;
 202        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 203        u32 err_detect;
 204
 205        err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
 206
 207        if (!err_detect)
 208                return IRQ_NONE;
 209
 210        mpc85xx_pci_check(pci);
 211
 212        return IRQ_HANDLED;
 213}
 214
 215static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
 216{
 217        struct edac_pci_ctl_info *pci;
 218        struct mpc85xx_pci_pdata *pdata;
 219        struct resource r;
 220        int res = 0;
 221
 222        if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
 223                return -ENOMEM;
 224
 225        pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
 226        if (!pci)
 227                return -ENOMEM;
 228
 229        pdata = pci->pvt_info;
 230        pdata->name = "mpc85xx_pci_err";
 231        pdata->irq = NO_IRQ;
 232        dev_set_drvdata(&op->dev, pci);
 233        pci->dev = &op->dev;
 234        pci->mod_name = EDAC_MOD_STR;
 235        pci->ctl_name = pdata->name;
 236        pci->dev_name = dev_name(&op->dev);
 237
 238        if (edac_op_state == EDAC_OPSTATE_POLL)
 239                pci->edac_check = mpc85xx_pci_check;
 240
 241        pdata->edac_idx = edac_pci_idx++;
 242
 243        res = of_address_to_resource(op->dev.of_node, 0, &r);
 244        if (res) {
 245                printk(KERN_ERR "%s: Unable to get resource for "
 246                       "PCI err regs\n", __func__);
 247                goto err;
 248        }
 249
 250        /* we only need the error registers */
 251        r.start += 0xe00;
 252
 253        if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
 254                                        pdata->name)) {
 255                printk(KERN_ERR "%s: Error while requesting mem region\n",
 256                       __func__);
 257                res = -EBUSY;
 258                goto err;
 259        }
 260
 261        pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
 262        if (!pdata->pci_vbase) {
 263                printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
 264                res = -ENOMEM;
 265                goto err;
 266        }
 267
 268        orig_pci_err_cap_dr =
 269            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
 270
 271        /* PCI master abort is expected during config cycles */
 272        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
 273
 274        orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
 275
 276        /* disable master abort reporting */
 277        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
 278
 279        /* clear error bits */
 280        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
 281
 282        if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
 283                edac_dbg(3, "failed edac_pci_add_device()\n");
 284                goto err;
 285        }
 286
 287        if (edac_op_state == EDAC_OPSTATE_INT) {
 288                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 289                res = devm_request_irq(&op->dev, pdata->irq,
 290                                       mpc85xx_pci_isr, IRQF_DISABLED,
 291                                       "[EDAC] PCI err", pci);
 292                if (res < 0) {
 293                        printk(KERN_ERR
 294                               "%s: Unable to requiest irq %d for "
 295                               "MPC85xx PCI err\n", __func__, pdata->irq);
 296                        irq_dispose_mapping(pdata->irq);
 297                        res = -ENODEV;
 298                        goto err2;
 299                }
 300
 301                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
 302                       pdata->irq);
 303        }
 304
 305        devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
 306        edac_dbg(3, "success\n");
 307        printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
 308
 309        return 0;
 310
 311err2:
 312        edac_pci_del_device(&op->dev);
 313err:
 314        edac_pci_free_ctl_info(pci);
 315        devres_release_group(&op->dev, mpc85xx_pci_err_probe);
 316        return res;
 317}
 318
 319static int mpc85xx_pci_err_remove(struct platform_device *op)
 320{
 321        struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
 322        struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
 323
 324        edac_dbg(0, "\n");
 325
 326        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
 327                 orig_pci_err_cap_dr);
 328
 329        out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
 330
 331        edac_pci_del_device(pci->dev);
 332
 333        if (edac_op_state == EDAC_OPSTATE_INT)
 334                irq_dispose_mapping(pdata->irq);
 335
 336        edac_pci_free_ctl_info(pci);
 337
 338        return 0;
 339}
 340
 341static struct of_device_id mpc85xx_pci_err_of_match[] = {
 342        {
 343         .compatible = "fsl,mpc8540-pcix",
 344         },
 345        {
 346         .compatible = "fsl,mpc8540-pci",
 347        },
 348        {},
 349};
 350MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
 351
 352static struct platform_driver mpc85xx_pci_err_driver = {
 353        .probe = mpc85xx_pci_err_probe,
 354        .remove = __devexit_p(mpc85xx_pci_err_remove),
 355        .driver = {
 356                .name = "mpc85xx_pci_err",
 357                .owner = THIS_MODULE,
 358                .of_match_table = mpc85xx_pci_err_of_match,
 359        },
 360};
 361
 362#endif                          /* CONFIG_PCI */
 363
 364/**************************** L2 Err device ***************************/
 365
 366/************************ L2 SYSFS parts ***********************************/
 367
 368static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
 369                                              *edac_dev, char *data)
 370{
 371        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 372        return sprintf(data, "0x%08x",
 373                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
 374}
 375
 376static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
 377                                              *edac_dev, char *data)
 378{
 379        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 380        return sprintf(data, "0x%08x",
 381                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
 382}
 383
 384static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
 385                                           *edac_dev, char *data)
 386{
 387        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 388        return sprintf(data, "0x%08x",
 389                       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
 390}
 391
 392static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
 393                                               *edac_dev, const char *data,
 394                                               size_t count)
 395{
 396        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 397        if (isdigit(*data)) {
 398                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
 399                         simple_strtoul(data, NULL, 0));
 400                return count;
 401        }
 402        return 0;
 403}
 404
 405static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
 406                                               *edac_dev, const char *data,
 407                                               size_t count)
 408{
 409        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 410        if (isdigit(*data)) {
 411                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
 412                         simple_strtoul(data, NULL, 0));
 413                return count;
 414        }
 415        return 0;
 416}
 417
 418static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
 419                                            *edac_dev, const char *data,
 420                                            size_t count)
 421{
 422        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 423        if (isdigit(*data)) {
 424                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
 425                         simple_strtoul(data, NULL, 0));
 426                return count;
 427        }
 428        return 0;
 429}
 430
 431static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
 432        {
 433         .attr = {
 434                  .name = "inject_data_hi",
 435                  .mode = (S_IRUGO | S_IWUSR)
 436                  },
 437         .show = mpc85xx_l2_inject_data_hi_show,
 438         .store = mpc85xx_l2_inject_data_hi_store},
 439        {
 440         .attr = {
 441                  .name = "inject_data_lo",
 442                  .mode = (S_IRUGO | S_IWUSR)
 443                  },
 444         .show = mpc85xx_l2_inject_data_lo_show,
 445         .store = mpc85xx_l2_inject_data_lo_store},
 446        {
 447         .attr = {
 448                  .name = "inject_ctrl",
 449                  .mode = (S_IRUGO | S_IWUSR)
 450                  },
 451         .show = mpc85xx_l2_inject_ctrl_show,
 452         .store = mpc85xx_l2_inject_ctrl_store},
 453
 454        /* End of list */
 455        {
 456         .attr = {.name = NULL}
 457         }
 458};
 459
 460static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
 461                                            *edac_dev)
 462{
 463        edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
 464}
 465
 466/***************************** L2 ops ***********************************/
 467
 468static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
 469{
 470        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 471        u32 err_detect;
 472
 473        err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 474
 475        if (!(err_detect & L2_EDE_MASK))
 476                return;
 477
 478        printk(KERN_ERR "ECC Error in CPU L2 cache\n");
 479        printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
 480        printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
 481               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
 482        printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
 483               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
 484        printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
 485               in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
 486        printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
 487               in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
 488        printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
 489               in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
 490
 491        /* clear error detect register */
 492        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
 493
 494        if (err_detect & L2_EDE_CE_MASK)
 495                edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
 496
 497        if (err_detect & L2_EDE_UE_MASK)
 498                edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
 499}
 500
 501static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
 502{
 503        struct edac_device_ctl_info *edac_dev = dev_id;
 504        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 505        u32 err_detect;
 506
 507        err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
 508
 509        if (!(err_detect & L2_EDE_MASK))
 510                return IRQ_NONE;
 511
 512        mpc85xx_l2_check(edac_dev);
 513
 514        return IRQ_HANDLED;
 515}
 516
 517static int __devinit mpc85xx_l2_err_probe(struct platform_device *op)
 518{
 519        struct edac_device_ctl_info *edac_dev;
 520        struct mpc85xx_l2_pdata *pdata;
 521        struct resource r;
 522        int res;
 523
 524        if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
 525                return -ENOMEM;
 526
 527        edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
 528                                              "cpu", 1, "L", 1, 2, NULL, 0,
 529                                              edac_dev_idx);
 530        if (!edac_dev) {
 531                devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 532                return -ENOMEM;
 533        }
 534
 535        pdata = edac_dev->pvt_info;
 536        pdata->name = "mpc85xx_l2_err";
 537        pdata->irq = NO_IRQ;
 538        edac_dev->dev = &op->dev;
 539        dev_set_drvdata(edac_dev->dev, edac_dev);
 540        edac_dev->ctl_name = pdata->name;
 541        edac_dev->dev_name = pdata->name;
 542
 543        res = of_address_to_resource(op->dev.of_node, 0, &r);
 544        if (res) {
 545                printk(KERN_ERR "%s: Unable to get resource for "
 546                       "L2 err regs\n", __func__);
 547                goto err;
 548        }
 549
 550        /* we only need the error registers */
 551        r.start += 0xe00;
 552
 553        if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
 554                                     pdata->name)) {
 555                printk(KERN_ERR "%s: Error while requesting mem region\n",
 556                       __func__);
 557                res = -EBUSY;
 558                goto err;
 559        }
 560
 561        pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
 562        if (!pdata->l2_vbase) {
 563                printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
 564                res = -ENOMEM;
 565                goto err;
 566        }
 567
 568        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
 569
 570        orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
 571
 572        /* clear the err_dis */
 573        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
 574
 575        edac_dev->mod_name = EDAC_MOD_STR;
 576
 577        if (edac_op_state == EDAC_OPSTATE_POLL)
 578                edac_dev->edac_check = mpc85xx_l2_check;
 579
 580        mpc85xx_set_l2_sysfs_attributes(edac_dev);
 581
 582        pdata->edac_idx = edac_dev_idx++;
 583
 584        if (edac_device_add_device(edac_dev) > 0) {
 585                edac_dbg(3, "failed edac_device_add_device()\n");
 586                goto err;
 587        }
 588
 589        if (edac_op_state == EDAC_OPSTATE_INT) {
 590                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 591                res = devm_request_irq(&op->dev, pdata->irq,
 592                                       mpc85xx_l2_isr, IRQF_DISABLED,
 593                                       "[EDAC] L2 err", edac_dev);
 594                if (res < 0) {
 595                        printk(KERN_ERR
 596                               "%s: Unable to requiest irq %d for "
 597                               "MPC85xx L2 err\n", __func__, pdata->irq);
 598                        irq_dispose_mapping(pdata->irq);
 599                        res = -ENODEV;
 600                        goto err2;
 601                }
 602
 603                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
 604                       pdata->irq);
 605
 606                edac_dev->op_state = OP_RUNNING_INTERRUPT;
 607
 608                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
 609        }
 610
 611        devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
 612
 613        edac_dbg(3, "success\n");
 614        printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
 615
 616        return 0;
 617
 618err2:
 619        edac_device_del_device(&op->dev);
 620err:
 621        devres_release_group(&op->dev, mpc85xx_l2_err_probe);
 622        edac_device_free_ctl_info(edac_dev);
 623        return res;
 624}
 625
 626static int mpc85xx_l2_err_remove(struct platform_device *op)
 627{
 628        struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
 629        struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
 630
 631        edac_dbg(0, "\n");
 632
 633        if (edac_op_state == EDAC_OPSTATE_INT) {
 634                out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
 635                irq_dispose_mapping(pdata->irq);
 636        }
 637
 638        out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
 639        edac_device_del_device(&op->dev);
 640        edac_device_free_ctl_info(edac_dev);
 641        return 0;
 642}
 643
 644static struct of_device_id mpc85xx_l2_err_of_match[] = {
 645/* deprecate the fsl,85.. forms in the future, 2.6.30? */
 646        { .compatible = "fsl,8540-l2-cache-controller", },
 647        { .compatible = "fsl,8541-l2-cache-controller", },
 648        { .compatible = "fsl,8544-l2-cache-controller", },
 649        { .compatible = "fsl,8548-l2-cache-controller", },
 650        { .compatible = "fsl,8555-l2-cache-controller", },
 651        { .compatible = "fsl,8568-l2-cache-controller", },
 652        { .compatible = "fsl,mpc8536-l2-cache-controller", },
 653        { .compatible = "fsl,mpc8540-l2-cache-controller", },
 654        { .compatible = "fsl,mpc8541-l2-cache-controller", },
 655        { .compatible = "fsl,mpc8544-l2-cache-controller", },
 656        { .compatible = "fsl,mpc8548-l2-cache-controller", },
 657        { .compatible = "fsl,mpc8555-l2-cache-controller", },
 658        { .compatible = "fsl,mpc8560-l2-cache-controller", },
 659        { .compatible = "fsl,mpc8568-l2-cache-controller", },
 660        { .compatible = "fsl,mpc8569-l2-cache-controller", },
 661        { .compatible = "fsl,mpc8572-l2-cache-controller", },
 662        { .compatible = "fsl,p1020-l2-cache-controller", },
 663        { .compatible = "fsl,p1021-l2-cache-controller", },
 664        { .compatible = "fsl,p2020-l2-cache-controller", },
 665        {},
 666};
 667MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
 668
 669static struct platform_driver mpc85xx_l2_err_driver = {
 670        .probe = mpc85xx_l2_err_probe,
 671        .remove = mpc85xx_l2_err_remove,
 672        .driver = {
 673                .name = "mpc85xx_l2_err",
 674                .owner = THIS_MODULE,
 675                .of_match_table = mpc85xx_l2_err_of_match,
 676        },
 677};
 678
 679/**************************** MC Err device ***************************/
 680
 681/*
 682 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
 683 * MPC8572 User's Manual.  Each line represents a syndrome bit column as a
 684 * 64-bit value, but split into an upper and lower 32-bit chunk.  The labels
 685 * below correspond to Freescale's manuals.
 686 */
 687static unsigned int ecc_table[16] = {
 688        /* MSB           LSB */
 689        /* [0:31]    [32:63] */
 690        0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
 691        0x00ff00ff, 0x00fff0ff,
 692        0x0f0f0f0f, 0x0f0fff00,
 693        0x11113333, 0x7777000f,
 694        0x22224444, 0x8888222f,
 695        0x44448888, 0xffff4441,
 696        0x8888ffff, 0x11118882,
 697        0xffff1111, 0x22221114, /* Syndrome bit 0 */
 698};
 699
 700/*
 701 * Calculate the correct ECC value for a 64-bit value specified by high:low
 702 */
 703static u8 calculate_ecc(u32 high, u32 low)
 704{
 705        u32 mask_low;
 706        u32 mask_high;
 707        int bit_cnt;
 708        u8 ecc = 0;
 709        int i;
 710        int j;
 711
 712        for (i = 0; i < 8; i++) {
 713                mask_high = ecc_table[i * 2];
 714                mask_low = ecc_table[i * 2 + 1];
 715                bit_cnt = 0;
 716
 717                for (j = 0; j < 32; j++) {
 718                        if ((mask_high >> j) & 1)
 719                                bit_cnt ^= (high >> j) & 1;
 720                        if ((mask_low >> j) & 1)
 721                                bit_cnt ^= (low >> j) & 1;
 722                }
 723
 724                ecc |= bit_cnt << i;
 725        }
 726
 727        return ecc;
 728}
 729
 730/*
 731 * Create the syndrome code which is generated if the data line specified by
 732 * 'bit' failed.  Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
 733 * User's Manual and 9-61 in the MPC8572 User's Manual.
 734 */
 735static u8 syndrome_from_bit(unsigned int bit) {
 736        int i;
 737        u8 syndrome = 0;
 738
 739        /*
 740         * Cycle through the upper or lower 32-bit portion of each value in
 741         * ecc_table depending on if 'bit' is in the upper or lower half of
 742         * 64-bit data.
 743         */
 744        for (i = bit < 32; i < 16; i += 2)
 745                syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
 746
 747        return syndrome;
 748}
 749
 750/*
 751 * Decode data and ecc syndrome to determine what went wrong
 752 * Note: This can only decode single-bit errors
 753 */
 754static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
 755                       int *bad_data_bit, int *bad_ecc_bit)
 756{
 757        int i;
 758        u8 syndrome;
 759
 760        *bad_data_bit = -1;
 761        *bad_ecc_bit = -1;
 762
 763        /*
 764         * Calculate the ECC of the captured data and XOR it with the captured
 765         * ECC to find an ECC syndrome value we can search for
 766         */
 767        syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
 768
 769        /* Check if a data line is stuck... */
 770        for (i = 0; i < 64; i++) {
 771                if (syndrome == syndrome_from_bit(i)) {
 772                        *bad_data_bit = i;
 773                        return;
 774                }
 775        }
 776
 777        /* If data is correct, check ECC bits for errors... */
 778        for (i = 0; i < 8; i++) {
 779                if ((syndrome >> i) & 0x1) {
 780                        *bad_ecc_bit = i;
 781                        return;
 782                }
 783        }
 784}
 785
 786static void mpc85xx_mc_check(struct mem_ctl_info *mci)
 787{
 788        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 789        struct csrow_info *csrow;
 790        u32 bus_width;
 791        u32 err_detect;
 792        u32 syndrome;
 793        u32 err_addr;
 794        u32 pfn;
 795        int row_index;
 796        u32 cap_high;
 797        u32 cap_low;
 798        int bad_data_bit;
 799        int bad_ecc_bit;
 800
 801        err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 802        if (!err_detect)
 803                return;
 804
 805        mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
 806                          err_detect);
 807
 808        /* no more processing if not ECC bit errors */
 809        if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
 810                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 811                return;
 812        }
 813
 814        syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
 815
 816        /* Mask off appropriate bits of syndrome based on bus width */
 817        bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
 818                        DSC_DBW_MASK) ? 32 : 64;
 819        if (bus_width == 64)
 820                syndrome &= 0xff;
 821        else
 822                syndrome &= 0xffff;
 823
 824        err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
 825        pfn = err_addr >> PAGE_SHIFT;
 826
 827        for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
 828                csrow = mci->csrows[row_index];
 829                if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
 830                        break;
 831        }
 832
 833        cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
 834        cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
 835
 836        /*
 837         * Analyze single-bit errors on 64-bit wide buses
 838         * TODO: Add support for 32-bit wide buses
 839         */
 840        if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
 841                sbe_ecc_decode(cap_high, cap_low, syndrome,
 842                                &bad_data_bit, &bad_ecc_bit);
 843
 844                if (bad_data_bit != -1)
 845                        mpc85xx_mc_printk(mci, KERN_ERR,
 846                                "Faulty Data bit: %d\n", bad_data_bit);
 847                if (bad_ecc_bit != -1)
 848                        mpc85xx_mc_printk(mci, KERN_ERR,
 849                                "Faulty ECC bit: %d\n", bad_ecc_bit);
 850
 851                mpc85xx_mc_printk(mci, KERN_ERR,
 852                        "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 853                        cap_high ^ (1 << (bad_data_bit - 32)),
 854                        cap_low ^ (1 << bad_data_bit),
 855                        syndrome ^ (1 << bad_ecc_bit));
 856        }
 857
 858        mpc85xx_mc_printk(mci, KERN_ERR,
 859                        "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
 860                        cap_high, cap_low, syndrome);
 861        mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
 862        mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
 863
 864        /* we are out of range */
 865        if (row_index == mci->nr_csrows)
 866                mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
 867
 868        if (err_detect & DDR_EDE_SBE)
 869                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 870                                     pfn, err_addr & ~PAGE_MASK, syndrome,
 871                                     row_index, 0, -1,
 872                                     mci->ctl_name, "");
 873
 874        if (err_detect & DDR_EDE_MBE)
 875                edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 876                                     pfn, err_addr & ~PAGE_MASK, syndrome,
 877                                     row_index, 0, -1,
 878                                     mci->ctl_name, "");
 879
 880        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
 881}
 882
 883static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
 884{
 885        struct mem_ctl_info *mci = dev_id;
 886        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 887        u32 err_detect;
 888
 889        err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
 890        if (!err_detect)
 891                return IRQ_NONE;
 892
 893        mpc85xx_mc_check(mci);
 894
 895        return IRQ_HANDLED;
 896}
 897
 898static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
 899{
 900        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
 901        struct csrow_info *csrow;
 902        struct dimm_info *dimm;
 903        u32 sdram_ctl;
 904        u32 sdtype;
 905        enum mem_type mtype;
 906        u32 cs_bnds;
 907        int index;
 908
 909        sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
 910
 911        sdtype = sdram_ctl & DSC_SDTYPE_MASK;
 912        if (sdram_ctl & DSC_RD_EN) {
 913                switch (sdtype) {
 914                case DSC_SDTYPE_DDR:
 915                        mtype = MEM_RDDR;
 916                        break;
 917                case DSC_SDTYPE_DDR2:
 918                        mtype = MEM_RDDR2;
 919                        break;
 920                case DSC_SDTYPE_DDR3:
 921                        mtype = MEM_RDDR3;
 922                        break;
 923                default:
 924                        mtype = MEM_UNKNOWN;
 925                        break;
 926                }
 927        } else {
 928                switch (sdtype) {
 929                case DSC_SDTYPE_DDR:
 930                        mtype = MEM_DDR;
 931                        break;
 932                case DSC_SDTYPE_DDR2:
 933                        mtype = MEM_DDR2;
 934                        break;
 935                case DSC_SDTYPE_DDR3:
 936                        mtype = MEM_DDR3;
 937                        break;
 938                default:
 939                        mtype = MEM_UNKNOWN;
 940                        break;
 941                }
 942        }
 943
 944        for (index = 0; index < mci->nr_csrows; index++) {
 945                u32 start;
 946                u32 end;
 947
 948                csrow = mci->csrows[index];
 949                dimm = csrow->channels[0]->dimm;
 950
 951                cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
 952                                  (index * MPC85XX_MC_CS_BNDS_OFS));
 953
 954                start = (cs_bnds & 0xffff0000) >> 16;
 955                end   = (cs_bnds & 0x0000ffff);
 956
 957                if (start == end)
 958                        continue;       /* not populated */
 959
 960                start <<= (24 - PAGE_SHIFT);
 961                end   <<= (24 - PAGE_SHIFT);
 962                end    |= (1 << (24 - PAGE_SHIFT)) - 1;
 963
 964                csrow->first_page = start;
 965                csrow->last_page = end;
 966
 967                dimm->nr_pages = end + 1 - start;
 968                dimm->grain = 8;
 969                dimm->mtype = mtype;
 970                dimm->dtype = DEV_UNKNOWN;
 971                if (sdram_ctl & DSC_X32_EN)
 972                        dimm->dtype = DEV_X32;
 973                dimm->edac_mode = EDAC_SECDED;
 974        }
 975}
 976
 977static int __devinit mpc85xx_mc_err_probe(struct platform_device *op)
 978{
 979        struct mem_ctl_info *mci;
 980        struct edac_mc_layer layers[2];
 981        struct mpc85xx_mc_pdata *pdata;
 982        struct resource r;
 983        u32 sdram_ctl;
 984        int res;
 985
 986        if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
 987                return -ENOMEM;
 988
 989        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 990        layers[0].size = 4;
 991        layers[0].is_virt_csrow = true;
 992        layers[1].type = EDAC_MC_LAYER_CHANNEL;
 993        layers[1].size = 1;
 994        layers[1].is_virt_csrow = false;
 995        mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
 996                            sizeof(*pdata));
 997        if (!mci) {
 998                devres_release_group(&op->dev, mpc85xx_mc_err_probe);
 999                return -ENOMEM;
1000        }
1001
1002        pdata = mci->pvt_info;
1003        pdata->name = "mpc85xx_mc_err";
1004        pdata->irq = NO_IRQ;
1005        mci->pdev = &op->dev;
1006        pdata->edac_idx = edac_mc_idx++;
1007        dev_set_drvdata(mci->pdev, mci);
1008        mci->ctl_name = pdata->name;
1009        mci->dev_name = pdata->name;
1010
1011        res = of_address_to_resource(op->dev.of_node, 0, &r);
1012        if (res) {
1013                printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
1014                       __func__);
1015                goto err;
1016        }
1017
1018        if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
1019                                     pdata->name)) {
1020                printk(KERN_ERR "%s: Error while requesting mem region\n",
1021                       __func__);
1022                res = -EBUSY;
1023                goto err;
1024        }
1025
1026        pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
1027        if (!pdata->mc_vbase) {
1028                printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1029                res = -ENOMEM;
1030                goto err;
1031        }
1032
1033        sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1034        if (!(sdram_ctl & DSC_ECC_EN)) {
1035                /* no ECC */
1036                printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1037                res = -ENODEV;
1038                goto err;
1039        }
1040
1041        edac_dbg(3, "init mci\n");
1042        mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1043            MEM_FLAG_DDR | MEM_FLAG_DDR2;
1044        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1045        mci->edac_cap = EDAC_FLAG_SECDED;
1046        mci->mod_name = EDAC_MOD_STR;
1047        mci->mod_ver = MPC85XX_REVISION;
1048
1049        if (edac_op_state == EDAC_OPSTATE_POLL)
1050                mci->edac_check = mpc85xx_mc_check;
1051
1052        mci->ctl_page_to_phys = NULL;
1053
1054        mci->scrub_mode = SCRUB_SW_SRC;
1055
1056        mpc85xx_init_csrows(mci);
1057
1058        /* store the original error disable bits */
1059        orig_ddr_err_disable =
1060            in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1061        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1062
1063        /* clear all error bits */
1064        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1065
1066        if (edac_mc_add_mc(mci)) {
1067                edac_dbg(3, "failed edac_mc_add_mc()\n");
1068                goto err;
1069        }
1070
1071        if (mpc85xx_create_sysfs_attributes(mci)) {
1072                edac_mc_del_mc(mci->pdev);
1073                edac_dbg(3, "failed edac_mc_add_mc()\n");
1074                goto err;
1075        }
1076
1077        if (edac_op_state == EDAC_OPSTATE_INT) {
1078                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1079                         DDR_EIE_MBEE | DDR_EIE_SBEE);
1080
1081                /* store the original error management threshold */
1082                orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1083                                           MPC85XX_MC_ERR_SBE) & 0xff0000;
1084
1085                /* set threshold to 1 error per interrupt */
1086                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1087
1088                /* register interrupts */
1089                pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1090                res = devm_request_irq(&op->dev, pdata->irq,
1091                                       mpc85xx_mc_isr,
1092                                        IRQF_DISABLED | IRQF_SHARED,
1093                                       "[EDAC] MC err", mci);
1094                if (res < 0) {
1095                        printk(KERN_ERR "%s: Unable to request irq %d for "
1096                               "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1097                        irq_dispose_mapping(pdata->irq);
1098                        res = -ENODEV;
1099                        goto err2;
1100                }
1101
1102                printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1103                       pdata->irq);
1104        }
1105
1106        devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1107        edac_dbg(3, "success\n");
1108        printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1109
1110        return 0;
1111
1112err2:
1113        edac_mc_del_mc(&op->dev);
1114err:
1115        devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1116        edac_mc_free(mci);
1117        return res;
1118}
1119
1120static int mpc85xx_mc_err_remove(struct platform_device *op)
1121{
1122        struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1123        struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1124
1125        edac_dbg(0, "\n");
1126
1127        if (edac_op_state == EDAC_OPSTATE_INT) {
1128                out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1129                irq_dispose_mapping(pdata->irq);
1130        }
1131
1132        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1133                 orig_ddr_err_disable);
1134        out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1135
1136        mpc85xx_remove_sysfs_attributes(mci);
1137        edac_mc_del_mc(&op->dev);
1138        edac_mc_free(mci);
1139        return 0;
1140}
1141
1142static struct of_device_id mpc85xx_mc_err_of_match[] = {
1143/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1144        { .compatible = "fsl,8540-memory-controller", },
1145        { .compatible = "fsl,8541-memory-controller", },
1146        { .compatible = "fsl,8544-memory-controller", },
1147        { .compatible = "fsl,8548-memory-controller", },
1148        { .compatible = "fsl,8555-memory-controller", },
1149        { .compatible = "fsl,8568-memory-controller", },
1150        { .compatible = "fsl,mpc8536-memory-controller", },
1151        { .compatible = "fsl,mpc8540-memory-controller", },
1152        { .compatible = "fsl,mpc8541-memory-controller", },
1153        { .compatible = "fsl,mpc8544-memory-controller", },
1154        { .compatible = "fsl,mpc8548-memory-controller", },
1155        { .compatible = "fsl,mpc8555-memory-controller", },
1156        { .compatible = "fsl,mpc8560-memory-controller", },
1157        { .compatible = "fsl,mpc8568-memory-controller", },
1158        { .compatible = "fsl,mpc8569-memory-controller", },
1159        { .compatible = "fsl,mpc8572-memory-controller", },
1160        { .compatible = "fsl,mpc8349-memory-controller", },
1161        { .compatible = "fsl,p1020-memory-controller", },
1162        { .compatible = "fsl,p1021-memory-controller", },
1163        { .compatible = "fsl,p2020-memory-controller", },
1164        { .compatible = "fsl,qoriq-memory-controller", },
1165        {},
1166};
1167MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
1168
1169static struct platform_driver mpc85xx_mc_err_driver = {
1170        .probe = mpc85xx_mc_err_probe,
1171        .remove = mpc85xx_mc_err_remove,
1172        .driver = {
1173                .name = "mpc85xx_mc_err",
1174                .owner = THIS_MODULE,
1175                .of_match_table = mpc85xx_mc_err_of_match,
1176        },
1177};
1178
1179#ifdef CONFIG_FSL_SOC_BOOKE
1180static void __init mpc85xx_mc_clear_rfxe(void *data)
1181{
1182        orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1183        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
1184}
1185#endif
1186
1187static int __init mpc85xx_mc_init(void)
1188{
1189        int res = 0;
1190        u32 pvr = 0;
1191
1192        printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1193               "(C) 2006 Montavista Software\n");
1194
1195        /* make sure error reporting method is sane */
1196        switch (edac_op_state) {
1197        case EDAC_OPSTATE_POLL:
1198        case EDAC_OPSTATE_INT:
1199                break;
1200        default:
1201                edac_op_state = EDAC_OPSTATE_INT;
1202                break;
1203        }
1204
1205        res = platform_driver_register(&mpc85xx_mc_err_driver);
1206        if (res)
1207                printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1208
1209        res = platform_driver_register(&mpc85xx_l2_err_driver);
1210        if (res)
1211                printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1212
1213#ifdef CONFIG_PCI
1214        res = platform_driver_register(&mpc85xx_pci_err_driver);
1215        if (res)
1216                printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1217#endif
1218
1219#ifdef CONFIG_FSL_SOC_BOOKE
1220        pvr = mfspr(SPRN_PVR);
1221
1222        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1223            (PVR_VER(pvr) == PVR_VER_E500V2)) {
1224                /*
1225                 * need to clear HID1[RFXE] to disable machine check int
1226                 * so we can catch it
1227                 */
1228                if (edac_op_state == EDAC_OPSTATE_INT)
1229                        on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1230        }
1231#endif
1232
1233        return 0;
1234}
1235
1236module_init(mpc85xx_mc_init);
1237
1238#ifdef CONFIG_FSL_SOC_BOOKE
1239static void __exit mpc85xx_mc_restore_hid1(void *data)
1240{
1241        mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1242}
1243#endif
1244
1245static void __exit mpc85xx_mc_exit(void)
1246{
1247#ifdef CONFIG_FSL_SOC_BOOKE
1248        u32 pvr = mfspr(SPRN_PVR);
1249
1250        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
1251            (PVR_VER(pvr) == PVR_VER_E500V2)) {
1252                on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1253        }
1254#endif
1255#ifdef CONFIG_PCI
1256        platform_driver_unregister(&mpc85xx_pci_err_driver);
1257#endif
1258        platform_driver_unregister(&mpc85xx_l2_err_driver);
1259        platform_driver_unregister(&mpc85xx_mc_err_driver);
1260}
1261
1262module_exit(mpc85xx_mc_exit);
1263
1264MODULE_LICENSE("GPL");
1265MODULE_AUTHOR("Montavista Software, Inc.");
1266module_param(edac_op_state, int, 0444);
1267MODULE_PARM_DESC(edac_op_state,
1268                 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
1269
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