linux/drivers/ata/ata_piix.c
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   1/*
   2 *    ata_piix.c - Intel PATA/SATA controllers
   3 *
   4 *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *
   9 *      Copyright 2003-2005 Red Hat Inc
  10 *      Copyright 2003-2005 Jeff Garzik
  11 *
  12 *
  13 *      Copyright header from piix.c:
  14 *
  15 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  16 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  17 *  Copyright (C) 2003 Red Hat Inc
  18 *
  19 *
  20 *  This program is free software; you can redistribute it and/or modify
  21 *  it under the terms of the GNU General Public License as published by
  22 *  the Free Software Foundation; either version 2, or (at your option)
  23 *  any later version.
  24 *
  25 *  This program is distributed in the hope that it will be useful,
  26 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28 *  GNU General Public License for more details.
  29 *
  30 *  You should have received a copy of the GNU General Public License
  31 *  along with this program; see the file COPYING.  If not, write to
  32 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  33 *
  34 *
  35 *  libata documentation is available via 'make {ps|pdf}docs',
  36 *  as Documentation/DocBook/libata.*
  37 *
  38 *  Hardware documentation available at http://developer.intel.com/
  39 *
  40 * Documentation
  41 *      Publicly available from Intel web site. Errata documentation
  42 * is also publicly available. As an aide to anyone hacking on this
  43 * driver the list of errata that are relevant is below, going back to
  44 * PIIX4. Older device documentation is now a bit tricky to find.
  45 *
  46 * The chipsets all follow very much the same design. The original Triton
  47 * series chipsets do _not_ support independent device timings, but this
  48 * is fixed in Triton II. With the odd mobile exception the chips then
  49 * change little except in gaining more modes until SATA arrives. This
  50 * driver supports only the chips with independent timing (that is those
  51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  52 * for the early chip drivers.
  53 *
  54 * Errata of note:
  55 *
  56 * Unfixable
  57 *      PIIX4    errata #9      - Only on ultra obscure hw
  58 *      ICH3     errata #13     - Not observed to affect real hw
  59 *                                by Intel
  60 *
  61 * Things we must deal with
  62 *      PIIX4   errata #10      - BM IDE hang with non UDMA
  63 *                                (must stop/start dma to recover)
  64 *      440MX   errata #15      - As PIIX4 errata #10
  65 *      PIIX4   errata #15      - Must not read control registers
  66 *                                during a PIO transfer
  67 *      440MX   errata #13      - As PIIX4 errata #15
  68 *      ICH2    errata #21      - DMA mode 0 doesn't work right
  69 *      ICH0/1  errata #55      - As ICH2 errata #21
  70 *      ICH2    spec c #9       - Extra operations needed to handle
  71 *                                drive hotswap [NOT YET SUPPORTED]
  72 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  73 *                                and must be dword aligned
  74 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  75 *      ICH7    errata #16      - MWDMA1 timings are incorrect
  76 *
  77 * Should have been BIOS fixed:
  78 *      450NX:  errata #19      - DMA hangs on old 450NX
  79 *      450NX:  errata #20      - DMA hangs on old 450NX
  80 *      450NX:  errata #25      - Corruption with DMA on old 450NX
  81 *      ICH3    errata #15      - IDE deadlock under high load
  82 *                                (BIOS must set dev 31 fn 0 bit 23)
  83 *      ICH3    errata #18      - Don't use native mode
  84 */
  85
  86#include <linux/kernel.h>
  87#include <linux/module.h>
  88#include <linux/pci.h>
  89#include <linux/init.h>
  90#include <linux/blkdev.h>
  91#include <linux/delay.h>
  92#include <linux/device.h>
  93#include <linux/gfp.h>
  94#include <scsi/scsi_host.h>
  95#include <linux/libata.h>
  96#include <linux/dmi.h>
  97
  98#define DRV_NAME        "ata_piix"
  99#define DRV_VERSION     "2.13"
 100
 101enum {
 102        PIIX_IOCFG              = 0x54, /* IDE I/O configuration register */
 103        ICH5_PMR                = 0x90, /* port mapping register */
 104        ICH5_PCS                = 0x92, /* port control and status */
 105        PIIX_SIDPR_BAR          = 5,
 106        PIIX_SIDPR_LEN          = 16,
 107        PIIX_SIDPR_IDX          = 0,
 108        PIIX_SIDPR_DATA         = 4,
 109
 110        PIIX_FLAG_CHECKINTR     = (1 << 28), /* make sure PCI INTx enabled */
 111        PIIX_FLAG_SIDPR         = (1 << 29), /* SATA idx/data pair regs */
 112
 113        PIIX_PATA_FLAGS         = ATA_FLAG_SLAVE_POSS,
 114        PIIX_SATA_FLAGS         = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
 115
 116        PIIX_FLAG_PIO16         = (1 << 30), /*support 16bit PIO only*/
 117
 118        PIIX_80C_PRI            = (1 << 5) | (1 << 4),
 119        PIIX_80C_SEC            = (1 << 7) | (1 << 6),
 120
 121        /* constants for mapping table */
 122        P0                      = 0,  /* port 0 */
 123        P1                      = 1,  /* port 1 */
 124        P2                      = 2,  /* port 2 */
 125        P3                      = 3,  /* port 3 */
 126        IDE                     = -1, /* IDE */
 127        NA                      = -2, /* not available */
 128        RV                      = -3, /* reserved */
 129
 130        PIIX_AHCI_DEVICE        = 6,
 131
 132        /* host->flags bits */
 133        PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
 134};
 135
 136enum piix_controller_ids {
 137        /* controller IDs */
 138        piix_pata_mwdma,        /* PIIX3 MWDMA only */
 139        piix_pata_33,           /* PIIX4 at 33Mhz */
 140        ich_pata_33,            /* ICH up to UDMA 33 only */
 141        ich_pata_66,            /* ICH up to 66 Mhz */
 142        ich_pata_100,           /* ICH up to UDMA 100 */
 143        ich_pata_100_nomwdma1,  /* ICH up to UDMA 100 but with no MWDMA1*/
 144        ich5_sata,
 145        ich6_sata,
 146        ich6m_sata,
 147        ich8_sata,
 148        ich8_2port_sata,
 149        ich8m_apple_sata,       /* locks up on second port enable */
 150        tolapai_sata,
 151        piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
 152        ich8_sata_snb,
 153};
 154
 155struct piix_map_db {
 156        const u32 mask;
 157        const u16 port_enable;
 158        const int map[][4];
 159};
 160
 161struct piix_host_priv {
 162        const int *map;
 163        u32 saved_iocfg;
 164        void __iomem *sidpr;
 165};
 166
 167static int piix_init_one(struct pci_dev *pdev,
 168                         const struct pci_device_id *ent);
 169static void piix_remove_one(struct pci_dev *pdev);
 170static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
 171static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
 172static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 173static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 174static int ich_pata_cable_detect(struct ata_port *ap);
 175static u8 piix_vmw_bmdma_status(struct ata_port *ap);
 176static int piix_sidpr_scr_read(struct ata_link *link,
 177                               unsigned int reg, u32 *val);
 178static int piix_sidpr_scr_write(struct ata_link *link,
 179                                unsigned int reg, u32 val);
 180static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 181                              unsigned hints);
 182static bool piix_irq_check(struct ata_port *ap);
 183static int piix_port_start(struct ata_port *ap);
 184#ifdef CONFIG_PM
 185static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 186static int piix_pci_device_resume(struct pci_dev *pdev);
 187#endif
 188
 189static unsigned int in_module_init = 1;
 190
 191static const struct pci_device_id piix_pci_tbl[] = {
 192        /* Intel PIIX3 for the 430HX etc */
 193        { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
 194        /* VMware ICH4 */
 195        { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
 196        /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
 197        /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
 198        { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 199        /* Intel PIIX4 */
 200        { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 201        /* Intel PIIX4 */
 202        { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 203        /* Intel PIIX */
 204        { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 205        /* Intel ICH (i810, i815, i840) UDMA 66*/
 206        { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
 207        /* Intel ICH0 : UDMA 33*/
 208        { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
 209        /* Intel ICH2M */
 210        { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 211        /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
 212        { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 213        /*  Intel ICH3M */
 214        { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 215        /* Intel ICH3 (E7500/1) UDMA 100 */
 216        { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 217        /* Intel ICH4-L */
 218        { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 219        /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
 220        { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 221        { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 222        /* Intel ICH5 */
 223        { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 224        /* C-ICH (i810E2) */
 225        { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 226        /* ESB (855GME/875P + 6300ESB) UDMA 100  */
 227        { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 228        /* ICH6 (and 6) (i915) UDMA 100 */
 229        { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 230        /* ICH7/7-R (i945, i975) UDMA 100*/
 231        { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 232        { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 233        /* ICH8 Mobile PATA Controller */
 234        { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 235
 236        /* SATA ports */
 237
 238        /* 82801EB (ICH5) */
 239        { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 240        /* 82801EB (ICH5) */
 241        { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 242        /* 6300ESB (ICH5 variant with broken PCS present bits) */
 243        { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 244        /* 6300ESB pretending RAID */
 245        { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 246        /* 82801FB/FW (ICH6/ICH6W) */
 247        { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 248        /* 82801FR/FRW (ICH6R/ICH6RW) */
 249        { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 250        /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
 251         * Attach iff the controller is in IDE mode. */
 252        { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
 253          PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
 254        /* 82801GB/GR/GH (ICH7, identical to ICH6) */
 255        { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 256        /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
 257        { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
 258        /* Enterprise Southbridge 2 (631xESB/632xESB) */
 259        { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 260        /* SATA Controller 1 IDE (ICH8) */
 261        { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 262        /* SATA Controller 2 IDE (ICH8) */
 263        { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 264        /* Mobile SATA Controller IDE (ICH8M), Apple */
 265        { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
 266        { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
 267        { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
 268        /* Mobile SATA Controller IDE (ICH8M) */
 269        { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 270        /* SATA Controller IDE (ICH9) */
 271        { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 272        /* SATA Controller IDE (ICH9) */
 273        { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 274        /* SATA Controller IDE (ICH9) */
 275        { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 276        /* SATA Controller IDE (ICH9M) */
 277        { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 278        /* SATA Controller IDE (ICH9M) */
 279        { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 280        /* SATA Controller IDE (ICH9M) */
 281        { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 282        /* SATA Controller IDE (Tolapai) */
 283        { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
 284        /* SATA Controller IDE (ICH10) */
 285        { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 286        /* SATA Controller IDE (ICH10) */
 287        { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 288        /* SATA Controller IDE (ICH10) */
 289        { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 290        /* SATA Controller IDE (ICH10) */
 291        { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 292        /* SATA Controller IDE (PCH) */
 293        { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 294        /* SATA Controller IDE (PCH) */
 295        { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 296        /* SATA Controller IDE (PCH) */
 297        { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 298        /* SATA Controller IDE (PCH) */
 299        { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 300        /* SATA Controller IDE (PCH) */
 301        { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 302        /* SATA Controller IDE (PCH) */
 303        { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 304        /* SATA Controller IDE (CPT) */
 305        { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 306        /* SATA Controller IDE (CPT) */
 307        { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 308        /* SATA Controller IDE (CPT) */
 309        { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 310        /* SATA Controller IDE (CPT) */
 311        { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 312        /* SATA Controller IDE (PBG) */
 313        { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 314        /* SATA Controller IDE (PBG) */
 315        { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 316        /* SATA Controller IDE (Panther Point) */
 317        { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 318        /* SATA Controller IDE (Panther Point) */
 319        { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 320        /* SATA Controller IDE (Panther Point) */
 321        { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 322        /* SATA Controller IDE (Panther Point) */
 323        { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 324        /* SATA Controller IDE (Lynx Point) */
 325        { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 326        /* SATA Controller IDE (Lynx Point) */
 327        { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 328        /* SATA Controller IDE (Lynx Point) */
 329        { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 330        /* SATA Controller IDE (Lynx Point) */
 331        { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 332        /* SATA Controller IDE (Lynx Point-LP) */
 333        { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 334        /* SATA Controller IDE (Lynx Point-LP) */
 335        { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 336        /* SATA Controller IDE (Lynx Point-LP) */
 337        { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 338        /* SATA Controller IDE (Lynx Point-LP) */
 339        { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 340        /* SATA Controller IDE (DH89xxCC) */
 341        { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 342        { }     /* terminate list */
 343};
 344
 345static struct pci_driver piix_pci_driver = {
 346        .name                   = DRV_NAME,
 347        .id_table               = piix_pci_tbl,
 348        .probe                  = piix_init_one,
 349        .remove                 = piix_remove_one,
 350#ifdef CONFIG_PM
 351        .suspend                = piix_pci_device_suspend,
 352        .resume                 = piix_pci_device_resume,
 353#endif
 354};
 355
 356static struct scsi_host_template piix_sht = {
 357        ATA_BMDMA_SHT(DRV_NAME),
 358};
 359
 360static struct ata_port_operations piix_sata_ops = {
 361        .inherits               = &ata_bmdma32_port_ops,
 362        .sff_irq_check          = piix_irq_check,
 363        .port_start             = piix_port_start,
 364};
 365
 366static struct ata_port_operations piix_pata_ops = {
 367        .inherits               = &piix_sata_ops,
 368        .cable_detect           = ata_cable_40wire,
 369        .set_piomode            = piix_set_piomode,
 370        .set_dmamode            = piix_set_dmamode,
 371        .prereset               = piix_pata_prereset,
 372};
 373
 374static struct ata_port_operations piix_vmw_ops = {
 375        .inherits               = &piix_pata_ops,
 376        .bmdma_status           = piix_vmw_bmdma_status,
 377};
 378
 379static struct ata_port_operations ich_pata_ops = {
 380        .inherits               = &piix_pata_ops,
 381        .cable_detect           = ich_pata_cable_detect,
 382        .set_dmamode            = ich_set_dmamode,
 383};
 384
 385static struct device_attribute *piix_sidpr_shost_attrs[] = {
 386        &dev_attr_link_power_management_policy,
 387        NULL
 388};
 389
 390static struct scsi_host_template piix_sidpr_sht = {
 391        ATA_BMDMA_SHT(DRV_NAME),
 392        .shost_attrs            = piix_sidpr_shost_attrs,
 393};
 394
 395static struct ata_port_operations piix_sidpr_sata_ops = {
 396        .inherits               = &piix_sata_ops,
 397        .hardreset              = sata_std_hardreset,
 398        .scr_read               = piix_sidpr_scr_read,
 399        .scr_write              = piix_sidpr_scr_write,
 400        .set_lpm                = piix_sidpr_set_lpm,
 401};
 402
 403static const struct piix_map_db ich5_map_db = {
 404        .mask = 0x7,
 405        .port_enable = 0x3,
 406        .map = {
 407                /* PM   PS   SM   SS       MAP  */
 408                {  P0,  NA,  P1,  NA }, /* 000b */
 409                {  P1,  NA,  P0,  NA }, /* 001b */
 410                {  RV,  RV,  RV,  RV },
 411                {  RV,  RV,  RV,  RV },
 412                {  P0,  P1, IDE, IDE }, /* 100b */
 413                {  P1,  P0, IDE, IDE }, /* 101b */
 414                { IDE, IDE,  P0,  P1 }, /* 110b */
 415                { IDE, IDE,  P1,  P0 }, /* 111b */
 416        },
 417};
 418
 419static const struct piix_map_db ich6_map_db = {
 420        .mask = 0x3,
 421        .port_enable = 0xf,
 422        .map = {
 423                /* PM   PS   SM   SS       MAP */
 424                {  P0,  P2,  P1,  P3 }, /* 00b */
 425                { IDE, IDE,  P1,  P3 }, /* 01b */
 426                {  P0,  P2, IDE, IDE }, /* 10b */
 427                {  RV,  RV,  RV,  RV },
 428        },
 429};
 430
 431static const struct piix_map_db ich6m_map_db = {
 432        .mask = 0x3,
 433        .port_enable = 0x5,
 434
 435        /* Map 01b isn't specified in the doc but some notebooks use
 436         * it anyway.  MAP 01b have been spotted on both ICH6M and
 437         * ICH7M.
 438         */
 439        .map = {
 440                /* PM   PS   SM   SS       MAP */
 441                {  P0,  P2,  NA,  NA }, /* 00b */
 442                { IDE, IDE,  P1,  P3 }, /* 01b */
 443                {  P0,  P2, IDE, IDE }, /* 10b */
 444                {  RV,  RV,  RV,  RV },
 445        },
 446};
 447
 448static const struct piix_map_db ich8_map_db = {
 449        .mask = 0x3,
 450        .port_enable = 0xf,
 451        .map = {
 452                /* PM   PS   SM   SS       MAP */
 453                {  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 454                {  RV,  RV,  RV,  RV },
 455                {  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 456                {  RV,  RV,  RV,  RV },
 457        },
 458};
 459
 460static const struct piix_map_db ich8_2port_map_db = {
 461        .mask = 0x3,
 462        .port_enable = 0x3,
 463        .map = {
 464                /* PM   PS   SM   SS       MAP */
 465                {  P0,  NA,  P1,  NA }, /* 00b */
 466                {  RV,  RV,  RV,  RV }, /* 01b */
 467                {  RV,  RV,  RV,  RV }, /* 10b */
 468                {  RV,  RV,  RV,  RV },
 469        },
 470};
 471
 472static const struct piix_map_db ich8m_apple_map_db = {
 473        .mask = 0x3,
 474        .port_enable = 0x1,
 475        .map = {
 476                /* PM   PS   SM   SS       MAP */
 477                {  P0,  NA,  NA,  NA }, /* 00b */
 478                {  RV,  RV,  RV,  RV },
 479                {  P0,  P2, IDE, IDE }, /* 10b */
 480                {  RV,  RV,  RV,  RV },
 481        },
 482};
 483
 484static const struct piix_map_db tolapai_map_db = {
 485        .mask = 0x3,
 486        .port_enable = 0x3,
 487        .map = {
 488                /* PM   PS   SM   SS       MAP */
 489                {  P0,  NA,  P1,  NA }, /* 00b */
 490                {  RV,  RV,  RV,  RV }, /* 01b */
 491                {  RV,  RV,  RV,  RV }, /* 10b */
 492                {  RV,  RV,  RV,  RV },
 493        },
 494};
 495
 496static const struct piix_map_db *piix_map_db_table[] = {
 497        [ich5_sata]             = &ich5_map_db,
 498        [ich6_sata]             = &ich6_map_db,
 499        [ich6m_sata]            = &ich6m_map_db,
 500        [ich8_sata]             = &ich8_map_db,
 501        [ich8_2port_sata]       = &ich8_2port_map_db,
 502        [ich8m_apple_sata]      = &ich8m_apple_map_db,
 503        [tolapai_sata]          = &tolapai_map_db,
 504        [ich8_sata_snb]         = &ich8_map_db,
 505};
 506
 507static struct ata_port_info piix_port_info[] = {
 508        [piix_pata_mwdma] =     /* PIIX3 MWDMA only */
 509        {
 510                .flags          = PIIX_PATA_FLAGS,
 511                .pio_mask       = ATA_PIO4,
 512                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 513                .port_ops       = &piix_pata_ops,
 514        },
 515
 516        [piix_pata_33] =        /* PIIX4 at 33MHz */
 517        {
 518                .flags          = PIIX_PATA_FLAGS,
 519                .pio_mask       = ATA_PIO4,
 520                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 521                .udma_mask      = ATA_UDMA2,
 522                .port_ops       = &piix_pata_ops,
 523        },
 524
 525        [ich_pata_33] =         /* ICH0 - ICH at 33Mhz*/
 526        {
 527                .flags          = PIIX_PATA_FLAGS,
 528                .pio_mask       = ATA_PIO4,
 529                .mwdma_mask     = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
 530                .udma_mask      = ATA_UDMA2,
 531                .port_ops       = &ich_pata_ops,
 532        },
 533
 534        [ich_pata_66] =         /* ICH controllers up to 66MHz */
 535        {
 536                .flags          = PIIX_PATA_FLAGS,
 537                .pio_mask       = ATA_PIO4,
 538                .mwdma_mask     = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
 539                .udma_mask      = ATA_UDMA4,
 540                .port_ops       = &ich_pata_ops,
 541        },
 542
 543        [ich_pata_100] =
 544        {
 545                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
 546                .pio_mask       = ATA_PIO4,
 547                .mwdma_mask     = ATA_MWDMA12_ONLY,
 548                .udma_mask      = ATA_UDMA5,
 549                .port_ops       = &ich_pata_ops,
 550        },
 551
 552        [ich_pata_100_nomwdma1] =
 553        {
 554                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
 555                .pio_mask       = ATA_PIO4,
 556                .mwdma_mask     = ATA_MWDMA2_ONLY,
 557                .udma_mask      = ATA_UDMA5,
 558                .port_ops       = &ich_pata_ops,
 559        },
 560
 561        [ich5_sata] =
 562        {
 563                .flags          = PIIX_SATA_FLAGS,
 564                .pio_mask       = ATA_PIO4,
 565                .mwdma_mask     = ATA_MWDMA2,
 566                .udma_mask      = ATA_UDMA6,
 567                .port_ops       = &piix_sata_ops,
 568        },
 569
 570        [ich6_sata] =
 571        {
 572                .flags          = PIIX_SATA_FLAGS,
 573                .pio_mask       = ATA_PIO4,
 574                .mwdma_mask     = ATA_MWDMA2,
 575                .udma_mask      = ATA_UDMA6,
 576                .port_ops       = &piix_sata_ops,
 577        },
 578
 579        [ich6m_sata] =
 580        {
 581                .flags          = PIIX_SATA_FLAGS,
 582                .pio_mask       = ATA_PIO4,
 583                .mwdma_mask     = ATA_MWDMA2,
 584                .udma_mask      = ATA_UDMA6,
 585                .port_ops       = &piix_sata_ops,
 586        },
 587
 588        [ich8_sata] =
 589        {
 590                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
 591                .pio_mask       = ATA_PIO4,
 592                .mwdma_mask     = ATA_MWDMA2,
 593                .udma_mask      = ATA_UDMA6,
 594                .port_ops       = &piix_sata_ops,
 595        },
 596
 597        [ich8_2port_sata] =
 598        {
 599                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
 600                .pio_mask       = ATA_PIO4,
 601                .mwdma_mask     = ATA_MWDMA2,
 602                .udma_mask      = ATA_UDMA6,
 603                .port_ops       = &piix_sata_ops,
 604        },
 605
 606        [tolapai_sata] =
 607        {
 608                .flags          = PIIX_SATA_FLAGS,
 609                .pio_mask       = ATA_PIO4,
 610                .mwdma_mask     = ATA_MWDMA2,
 611                .udma_mask      = ATA_UDMA6,
 612                .port_ops       = &piix_sata_ops,
 613        },
 614
 615        [ich8m_apple_sata] =
 616        {
 617                .flags          = PIIX_SATA_FLAGS,
 618                .pio_mask       = ATA_PIO4,
 619                .mwdma_mask     = ATA_MWDMA2,
 620                .udma_mask      = ATA_UDMA6,
 621                .port_ops       = &piix_sata_ops,
 622        },
 623
 624        [piix_pata_vmw] =
 625        {
 626                .flags          = PIIX_PATA_FLAGS,
 627                .pio_mask       = ATA_PIO4,
 628                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
 629                .udma_mask      = ATA_UDMA2,
 630                .port_ops       = &piix_vmw_ops,
 631        },
 632
 633        /*
 634         * some Sandybridge chipsets have broken 32 mode up to now,
 635         * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
 636         */
 637        [ich8_sata_snb] =
 638        {
 639                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
 640                .pio_mask       = ATA_PIO4,
 641                .mwdma_mask     = ATA_MWDMA2,
 642                .udma_mask      = ATA_UDMA6,
 643                .port_ops       = &piix_sata_ops,
 644        },
 645
 646};
 647
 648static struct pci_bits piix_enable_bits[] = {
 649        { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
 650        { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
 651};
 652
 653MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
 654MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
 655MODULE_LICENSE("GPL");
 656MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 657MODULE_VERSION(DRV_VERSION);
 658
 659struct ich_laptop {
 660        u16 device;
 661        u16 subvendor;
 662        u16 subdevice;
 663};
 664
 665/*
 666 *      List of laptops that use short cables rather than 80 wire
 667 */
 668
 669static const struct ich_laptop ich_laptop[] = {
 670        /* devid, subvendor, subdev */
 671        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 672        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 673        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 674        { 0x27DF, 0x1028, 0x02b0 },     /* ICH7 on unknown Dell */
 675        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 676        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 677        { 0x27DF, 0x103C, 0x361a },     /* ICH7 on unknown HP  */
 678        { 0x27DF, 0x1071, 0xD221 },     /* ICH7 on Hercules EC-900 */
 679        { 0x27DF, 0x152D, 0x0778 },     /* ICH7 on unknown Intel */
 680        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on ACER Aspire 2023WLMi */
 681        { 0x24CA, 0x1025, 0x003d },     /* ICH4 on ACER TM290 */
 682        { 0x266F, 0x1025, 0x0066 },     /* ICH6 on ACER Aspire 1694WLMi */
 683        { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
 684        { 0x27df, 0x104d, 0x900e },     /* ICH7 on Sony TZ-90 */
 685        /* end marker */
 686        { 0, }
 687};
 688
 689static int piix_port_start(struct ata_port *ap)
 690{
 691        if (!(ap->flags & PIIX_FLAG_PIO16))
 692                ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
 693
 694        return ata_bmdma_port_start(ap);
 695}
 696
 697/**
 698 *      ich_pata_cable_detect - Probe host controller cable detect info
 699 *      @ap: Port for which cable detect info is desired
 700 *
 701 *      Read 80c cable indicator from ATA PCI device's PCI config
 702 *      register.  This register is normally set by firmware (BIOS).
 703 *
 704 *      LOCKING:
 705 *      None (inherited from caller).
 706 */
 707
 708static int ich_pata_cable_detect(struct ata_port *ap)
 709{
 710        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 711        struct piix_host_priv *hpriv = ap->host->private_data;
 712        const struct ich_laptop *lap = &ich_laptop[0];
 713        u8 mask;
 714
 715        /* Check for specials - Acer Aspire 5602WLMi */
 716        while (lap->device) {
 717                if (lap->device == pdev->device &&
 718                    lap->subvendor == pdev->subsystem_vendor &&
 719                    lap->subdevice == pdev->subsystem_device)
 720                        return ATA_CBL_PATA40_SHORT;
 721
 722                lap++;
 723        }
 724
 725        /* check BIOS cable detect results */
 726        mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
 727        if ((hpriv->saved_iocfg & mask) == 0)
 728                return ATA_CBL_PATA40;
 729        return ATA_CBL_PATA80;
 730}
 731
 732/**
 733 *      piix_pata_prereset - prereset for PATA host controller
 734 *      @link: Target link
 735 *      @deadline: deadline jiffies for the operation
 736 *
 737 *      LOCKING:
 738 *      None (inherited from caller).
 739 */
 740static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
 741{
 742        struct ata_port *ap = link->ap;
 743        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 744
 745        if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
 746                return -ENOENT;
 747        return ata_sff_prereset(link, deadline);
 748}
 749
 750static DEFINE_SPINLOCK(piix_lock);
 751
 752static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
 753                             u8 pio)
 754{
 755        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 756        unsigned long flags;
 757        unsigned int is_slave   = (adev->devno != 0);
 758        unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 759        unsigned int slave_port = 0x44;
 760        u16 master_data;
 761        u8 slave_data;
 762        u8 udma_enable;
 763        int control = 0;
 764
 765        /*
 766         *      See Intel Document 298600-004 for the timing programing rules
 767         *      for ICH controllers.
 768         */
 769
 770        static const     /* ISP  RTC */
 771        u8 timings[][2] = { { 0, 0 },
 772                            { 0, 0 },
 773                            { 1, 0 },
 774                            { 2, 1 },
 775                            { 2, 3 }, };
 776
 777        if (pio >= 2)
 778                control |= 1;   /* TIME1 enable */
 779        if (ata_pio_need_iordy(adev))
 780                control |= 2;   /* IE enable */
 781        /* Intel specifies that the PPE functionality is for disk only */
 782        if (adev->class == ATA_DEV_ATA)
 783                control |= 4;   /* PPE enable */
 784        /*
 785         * If the drive MWDMA is faster than it can do PIO then
 786         * we must force PIO into PIO0
 787         */
 788        if (adev->pio_mode < XFER_PIO_0 + pio)
 789                /* Enable DMA timing only */
 790                control |= 8;   /* PIO cycles in PIO0 */
 791
 792        spin_lock_irqsave(&piix_lock, flags);
 793
 794        /* PIO configuration clears DTE unconditionally.  It will be
 795         * programmed in set_dmamode which is guaranteed to be called
 796         * after set_piomode if any DMA mode is available.
 797         */
 798        pci_read_config_word(dev, master_port, &master_data);
 799        if (is_slave) {
 800                /* clear TIME1|IE1|PPE1|DTE1 */
 801                master_data &= 0xff0f;
 802                /* enable PPE1, IE1 and TIME1 as needed */
 803                master_data |= (control << 4);
 804                pci_read_config_byte(dev, slave_port, &slave_data);
 805                slave_data &= (ap->port_no ? 0x0f : 0xf0);
 806                /* Load the timing nibble for this slave */
 807                slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 808                                                << (ap->port_no ? 4 : 0);
 809        } else {
 810                /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 811                master_data &= 0xccf0;
 812                /* Enable PPE, IE and TIME as appropriate */
 813                master_data |= control;
 814                /* load ISP and RCT */
 815                master_data |=
 816                        (timings[pio][0] << 12) |
 817                        (timings[pio][1] << 8);
 818        }
 819
 820        /* Enable SITRE (separate slave timing register) */
 821        master_data |= 0x4000;
 822        pci_write_config_word(dev, master_port, master_data);
 823        if (is_slave)
 824                pci_write_config_byte(dev, slave_port, slave_data);
 825
 826        /* Ensure the UDMA bit is off - it will be turned back on if
 827           UDMA is selected */
 828
 829        if (ap->udma_mask) {
 830                pci_read_config_byte(dev, 0x48, &udma_enable);
 831                udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 832                pci_write_config_byte(dev, 0x48, udma_enable);
 833        }
 834
 835        spin_unlock_irqrestore(&piix_lock, flags);
 836}
 837
 838/**
 839 *      piix_set_piomode - Initialize host controller PATA PIO timings
 840 *      @ap: Port whose timings we are configuring
 841 *      @adev: Drive in question
 842 *
 843 *      Set PIO mode for device, in host controller PCI config space.
 844 *
 845 *      LOCKING:
 846 *      None (inherited from caller).
 847 */
 848
 849static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 850{
 851        piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
 852}
 853
 854/**
 855 *      do_pata_set_dmamode - Initialize host controller PATA PIO timings
 856 *      @ap: Port whose timings we are configuring
 857 *      @adev: Drive in question
 858 *      @isich: set if the chip is an ICH device
 859 *
 860 *      Set UDMA mode for device, in host controller PCI config space.
 861 *
 862 *      LOCKING:
 863 *      None (inherited from caller).
 864 */
 865
 866static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
 867{
 868        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 869        unsigned long flags;
 870        u8 speed                = adev->dma_mode;
 871        int devid               = adev->devno + 2 * ap->port_no;
 872        u8 udma_enable          = 0;
 873
 874        if (speed >= XFER_UDMA_0) {
 875                unsigned int udma = speed - XFER_UDMA_0;
 876                u16 udma_timing;
 877                u16 ideconf;
 878                int u_clock, u_speed;
 879
 880                spin_lock_irqsave(&piix_lock, flags);
 881
 882                pci_read_config_byte(dev, 0x48, &udma_enable);
 883
 884                /*
 885                 * UDMA is handled by a combination of clock switching and
 886                 * selection of dividers
 887                 *
 888                 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 889                 *             except UDMA0 which is 00
 890                 */
 891                u_speed = min(2 - (udma & 1), udma);
 892                if (udma == 5)
 893                        u_clock = 0x1000;       /* 100Mhz */
 894                else if (udma > 2)
 895                        u_clock = 1;            /* 66Mhz */
 896                else
 897                        u_clock = 0;            /* 33Mhz */
 898
 899                udma_enable |= (1 << devid);
 900
 901                /* Load the CT/RP selection */
 902                pci_read_config_word(dev, 0x4A, &udma_timing);
 903                udma_timing &= ~(3 << (4 * devid));
 904                udma_timing |= u_speed << (4 * devid);
 905                pci_write_config_word(dev, 0x4A, udma_timing);
 906
 907                if (isich) {
 908                        /* Select a 33/66/100Mhz clock */
 909                        pci_read_config_word(dev, 0x54, &ideconf);
 910                        ideconf &= ~(0x1001 << devid);
 911                        ideconf |= u_clock << devid;
 912                        /* For ICH or later we should set bit 10 for better
 913                           performance (WR_PingPong_En) */
 914                        pci_write_config_word(dev, 0x54, ideconf);
 915                }
 916
 917                pci_write_config_byte(dev, 0x48, udma_enable);
 918
 919                spin_unlock_irqrestore(&piix_lock, flags);
 920        } else {
 921                /* MWDMA is driven by the PIO timings. */
 922                unsigned int mwdma = speed - XFER_MW_DMA_0;
 923                const unsigned int needed_pio[3] = {
 924                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 925                };
 926                int pio = needed_pio[mwdma] - XFER_PIO_0;
 927
 928                /* XFER_PIO_0 is never used currently */
 929                piix_set_timings(ap, adev, pio);
 930        }
 931}
 932
 933/**
 934 *      piix_set_dmamode - Initialize host controller PATA DMA timings
 935 *      @ap: Port whose timings we are configuring
 936 *      @adev: um
 937 *
 938 *      Set MW/UDMA mode for device, in host controller PCI config space.
 939 *
 940 *      LOCKING:
 941 *      None (inherited from caller).
 942 */
 943
 944static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 945{
 946        do_pata_set_dmamode(ap, adev, 0);
 947}
 948
 949/**
 950 *      ich_set_dmamode - Initialize host controller PATA DMA timings
 951 *      @ap: Port whose timings we are configuring
 952 *      @adev: um
 953 *
 954 *      Set MW/UDMA mode for device, in host controller PCI config space.
 955 *
 956 *      LOCKING:
 957 *      None (inherited from caller).
 958 */
 959
 960static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 961{
 962        do_pata_set_dmamode(ap, adev, 1);
 963}
 964
 965/*
 966 * Serial ATA Index/Data Pair Superset Registers access
 967 *
 968 * Beginning from ICH8, there's a sane way to access SCRs using index
 969 * and data register pair located at BAR5 which means that we have
 970 * separate SCRs for master and slave.  This is handled using libata
 971 * slave_link facility.
 972 */
 973static const int piix_sidx_map[] = {
 974        [SCR_STATUS]    = 0,
 975        [SCR_ERROR]     = 2,
 976        [SCR_CONTROL]   = 1,
 977};
 978
 979static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
 980{
 981        struct ata_port *ap = link->ap;
 982        struct piix_host_priv *hpriv = ap->host->private_data;
 983
 984        iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
 985                  hpriv->sidpr + PIIX_SIDPR_IDX);
 986}
 987
 988static int piix_sidpr_scr_read(struct ata_link *link,
 989                               unsigned int reg, u32 *val)
 990{
 991        struct piix_host_priv *hpriv = link->ap->host->private_data;
 992
 993        if (reg >= ARRAY_SIZE(piix_sidx_map))
 994                return -EINVAL;
 995
 996        piix_sidpr_sel(link, reg);
 997        *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
 998        return 0;
 999}
1000
1001static int piix_sidpr_scr_write(struct ata_link *link,
1002                                unsigned int reg, u32 val)
1003{
1004        struct piix_host_priv *hpriv = link->ap->host->private_data;
1005
1006        if (reg >= ARRAY_SIZE(piix_sidx_map))
1007                return -EINVAL;
1008
1009        piix_sidpr_sel(link, reg);
1010        iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1011        return 0;
1012}
1013
1014static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1015                              unsigned hints)
1016{
1017        return sata_link_scr_lpm(link, policy, false);
1018}
1019
1020static bool piix_irq_check(struct ata_port *ap)
1021{
1022        if (unlikely(!ap->ioaddr.bmdma_addr))
1023                return false;
1024
1025        return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1026}
1027
1028#ifdef CONFIG_PM
1029static int piix_broken_suspend(void)
1030{
1031        static const struct dmi_system_id sysids[] = {
1032                {
1033                        .ident = "TECRA M3",
1034                        .matches = {
1035                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1036                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1037                        },
1038                },
1039                {
1040                        .ident = "TECRA M3",
1041                        .matches = {
1042                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1043                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1044                        },
1045                },
1046                {
1047                        .ident = "TECRA M4",
1048                        .matches = {
1049                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1050                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1051                        },
1052                },
1053                {
1054                        .ident = "TECRA M4",
1055                        .matches = {
1056                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1057                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1058                        },
1059                },
1060                {
1061                        .ident = "TECRA M5",
1062                        .matches = {
1063                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1064                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1065                        },
1066                },
1067                {
1068                        .ident = "TECRA M6",
1069                        .matches = {
1070                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1071                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1072                        },
1073                },
1074                {
1075                        .ident = "TECRA M7",
1076                        .matches = {
1077                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1078                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1079                        },
1080                },
1081                {
1082                        .ident = "TECRA A8",
1083                        .matches = {
1084                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1085                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1086                        },
1087                },
1088                {
1089                        .ident = "Satellite R20",
1090                        .matches = {
1091                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1092                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1093                        },
1094                },
1095                {
1096                        .ident = "Satellite R25",
1097                        .matches = {
1098                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1099                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1100                        },
1101                },
1102                {
1103                        .ident = "Satellite U200",
1104                        .matches = {
1105                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1106                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1107                        },
1108                },
1109                {
1110                        .ident = "Satellite U200",
1111                        .matches = {
1112                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1113                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1114                        },
1115                },
1116                {
1117                        .ident = "Satellite Pro U200",
1118                        .matches = {
1119                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1120                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1121                        },
1122                },
1123                {
1124                        .ident = "Satellite U205",
1125                        .matches = {
1126                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1127                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1128                        },
1129                },
1130                {
1131                        .ident = "SATELLITE U205",
1132                        .matches = {
1133                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1134                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1135                        },
1136                },
1137                {
1138                        .ident = "Satellite Pro A120",
1139                        .matches = {
1140                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1141                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
1142                        },
1143                },
1144                {
1145                        .ident = "Portege M500",
1146                        .matches = {
1147                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1148                                DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1149                        },
1150                },
1151                {
1152                        .ident = "VGN-BX297XP",
1153                        .matches = {
1154                                DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1155                                DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1156                        },
1157                },
1158
1159                { }     /* terminate list */
1160        };
1161        static const char *oemstrs[] = {
1162                "Tecra M3,",
1163        };
1164        int i;
1165
1166        if (dmi_check_system(sysids))
1167                return 1;
1168
1169        for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1170                if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1171                        return 1;
1172
1173        /* TECRA M4 sometimes forgets its identify and reports bogus
1174         * DMI information.  As the bogus information is a bit
1175         * generic, match as many entries as possible.  This manual
1176         * matching is necessary because dmi_system_id.matches is
1177         * limited to four entries.
1178         */
1179        if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1180            dmi_match(DMI_PRODUCT_NAME, "000000") &&
1181            dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1182            dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1183            dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1184            dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1185            dmi_match(DMI_BOARD_VERSION, "Version A0"))
1186                return 1;
1187
1188        return 0;
1189}
1190
1191static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1192{
1193        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1194        unsigned long flags;
1195        int rc = 0;
1196
1197        rc = ata_host_suspend(host, mesg);
1198        if (rc)
1199                return rc;
1200
1201        /* Some braindamaged ACPI suspend implementations expect the
1202         * controller to be awake on entry; otherwise, it burns cpu
1203         * cycles and power trying to do something to the sleeping
1204         * beauty.
1205         */
1206        if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1207                pci_save_state(pdev);
1208
1209                /* mark its power state as "unknown", since we don't
1210                 * know if e.g. the BIOS will change its device state
1211                 * when we suspend.
1212                 */
1213                if (pdev->current_state == PCI_D0)
1214                        pdev->current_state = PCI_UNKNOWN;
1215
1216                /* tell resume that it's waking up from broken suspend */
1217                spin_lock_irqsave(&host->lock, flags);
1218                host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1219                spin_unlock_irqrestore(&host->lock, flags);
1220        } else
1221                ata_pci_device_do_suspend(pdev, mesg);
1222
1223        return 0;
1224}
1225
1226static int piix_pci_device_resume(struct pci_dev *pdev)
1227{
1228        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1229        unsigned long flags;
1230        int rc;
1231
1232        if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1233                spin_lock_irqsave(&host->lock, flags);
1234                host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1235                spin_unlock_irqrestore(&host->lock, flags);
1236
1237                pci_set_power_state(pdev, PCI_D0);
1238                pci_restore_state(pdev);
1239
1240                /* PCI device wasn't disabled during suspend.  Use
1241                 * pci_reenable_device() to avoid affecting the enable
1242                 * count.
1243                 */
1244                rc = pci_reenable_device(pdev);
1245                if (rc)
1246                        dev_err(&pdev->dev,
1247                                "failed to enable device after resume (%d)\n",
1248                                rc);
1249        } else
1250                rc = ata_pci_device_do_resume(pdev);
1251
1252        if (rc == 0)
1253                ata_host_resume(host);
1254
1255        return rc;
1256}
1257#endif
1258
1259static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1260{
1261        return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1262}
1263
1264#define AHCI_PCI_BAR 5
1265#define AHCI_GLOBAL_CTL 0x04
1266#define AHCI_ENABLE (1 << 31)
1267static int piix_disable_ahci(struct pci_dev *pdev)
1268{
1269        void __iomem *mmio;
1270        u32 tmp;
1271        int rc = 0;
1272
1273        /* BUG: pci_enable_device has not yet been called.  This
1274         * works because this device is usually set up by BIOS.
1275         */
1276
1277        if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1278            !pci_resource_len(pdev, AHCI_PCI_BAR))
1279                return 0;
1280
1281        mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1282        if (!mmio)
1283                return -ENOMEM;
1284
1285        tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1286        if (tmp & AHCI_ENABLE) {
1287                tmp &= ~AHCI_ENABLE;
1288                iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1289
1290                tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1291                if (tmp & AHCI_ENABLE)
1292                        rc = -EIO;
1293        }
1294
1295        pci_iounmap(pdev, mmio);
1296        return rc;
1297}
1298
1299/**
1300 *      piix_check_450nx_errata -       Check for problem 450NX setup
1301 *      @ata_dev: the PCI device to check
1302 *
1303 *      Check for the present of 450NX errata #19 and errata #25. If
1304 *      they are found return an error code so we can turn off DMA
1305 */
1306
1307static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1308{
1309        struct pci_dev *pdev = NULL;
1310        u16 cfg;
1311        int no_piix_dma = 0;
1312
1313        while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1314                /* Look for 450NX PXB. Check for problem configurations
1315                   A PCI quirk checks bit 6 already */
1316                pci_read_config_word(pdev, 0x41, &cfg);
1317                /* Only on the original revision: IDE DMA can hang */
1318                if (pdev->revision == 0x00)
1319                        no_piix_dma = 1;
1320                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1321                else if (cfg & (1<<14) && pdev->revision < 5)
1322                        no_piix_dma = 2;
1323        }
1324        if (no_piix_dma)
1325                dev_warn(&ata_dev->dev,
1326                         "450NX errata present, disabling IDE DMA%s\n",
1327                         no_piix_dma == 2 ? " - a BIOS update may resolve this"
1328                         : "");
1329
1330        return no_piix_dma;
1331}
1332
1333static void __devinit piix_init_pcs(struct ata_host *host,
1334                                    const struct piix_map_db *map_db)
1335{
1336        struct pci_dev *pdev = to_pci_dev(host->dev);
1337        u16 pcs, new_pcs;
1338
1339        pci_read_config_word(pdev, ICH5_PCS, &pcs);
1340
1341        new_pcs = pcs | map_db->port_enable;
1342
1343        if (new_pcs != pcs) {
1344                DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1345                pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1346                msleep(150);
1347        }
1348}
1349
1350static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1351                                               struct ata_port_info *pinfo,
1352                                               const struct piix_map_db *map_db)
1353{
1354        const int *map;
1355        int i, invalid_map = 0;
1356        u8 map_value;
1357
1358        pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1359
1360        map = map_db->map[map_value & map_db->mask];
1361
1362        dev_info(&pdev->dev, "MAP [");
1363        for (i = 0; i < 4; i++) {
1364                switch (map[i]) {
1365                case RV:
1366                        invalid_map = 1;
1367                        pr_cont(" XX");
1368                        break;
1369
1370                case NA:
1371                        pr_cont(" --");
1372                        break;
1373
1374                case IDE:
1375                        WARN_ON((i & 1) || map[i + 1] != IDE);
1376                        pinfo[i / 2] = piix_port_info[ich_pata_100];
1377                        i++;
1378                        pr_cont(" IDE IDE");
1379                        break;
1380
1381                default:
1382                        pr_cont(" P%d", map[i]);
1383                        if (i & 1)
1384                                pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1385                        break;
1386                }
1387        }
1388        pr_cont(" ]\n");
1389
1390        if (invalid_map)
1391                dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1392
1393        return map;
1394}
1395
1396static bool piix_no_sidpr(struct ata_host *host)
1397{
1398        struct pci_dev *pdev = to_pci_dev(host->dev);
1399
1400        /*
1401         * Samsung DB-P70 only has three ATA ports exposed and
1402         * curiously the unconnected first port reports link online
1403         * while not responding to SRST protocol causing excessive
1404         * detection delay.
1405         *
1406         * Unfortunately, the system doesn't carry enough DMI
1407         * information to identify the machine but does have subsystem
1408         * vendor and device set.  As it's unclear whether the
1409         * subsystem vendor/device is used only for this specific
1410         * board, the port can't be disabled solely with the
1411         * information; however, turning off SIDPR access works around
1412         * the problem.  Turn it off.
1413         *
1414         * This problem is reported in bnc#441240.
1415         *
1416         * https://bugzilla.novell.com/show_bug.cgi?id=441420
1417         */
1418        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1419            pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1420            pdev->subsystem_device == 0xb049) {
1421                dev_warn(host->dev,
1422                         "Samsung DB-P70 detected, disabling SIDPR\n");
1423                return true;
1424        }
1425
1426        return false;
1427}
1428
1429static int __devinit piix_init_sidpr(struct ata_host *host)
1430{
1431        struct pci_dev *pdev = to_pci_dev(host->dev);
1432        struct piix_host_priv *hpriv = host->private_data;
1433        struct ata_link *link0 = &host->ports[0]->link;
1434        u32 scontrol;
1435        int i, rc;
1436
1437        /* check for availability */
1438        for (i = 0; i < 4; i++)
1439                if (hpriv->map[i] == IDE)
1440                        return 0;
1441
1442        /* is it blacklisted? */
1443        if (piix_no_sidpr(host))
1444                return 0;
1445
1446        if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1447                return 0;
1448
1449        if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1450            pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1451                return 0;
1452
1453        if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1454                return 0;
1455
1456        hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1457
1458        /* SCR access via SIDPR doesn't work on some configurations.
1459         * Give it a test drive by inhibiting power save modes which
1460         * we'll do anyway.
1461         */
1462        piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1463
1464        /* if IPM is already 3, SCR access is probably working.  Don't
1465         * un-inhibit power save modes as BIOS might have inhibited
1466         * them for a reason.
1467         */
1468        if ((scontrol & 0xf00) != 0x300) {
1469                scontrol |= 0x300;
1470                piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1471                piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1472
1473                if ((scontrol & 0xf00) != 0x300) {
1474                        dev_info(host->dev,
1475                                 "SCR access via SIDPR is available but doesn't work\n");
1476                        return 0;
1477                }
1478        }
1479
1480        /* okay, SCRs available, set ops and ask libata for slave_link */
1481        for (i = 0; i < 2; i++) {
1482                struct ata_port *ap = host->ports[i];
1483
1484                ap->ops = &piix_sidpr_sata_ops;
1485
1486                if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1487                        rc = ata_slave_link_init(ap);
1488                        if (rc)
1489                                return rc;
1490                }
1491        }
1492
1493        return 0;
1494}
1495
1496static void piix_iocfg_bit18_quirk(struct ata_host *host)
1497{
1498        static const struct dmi_system_id sysids[] = {
1499                {
1500                        /* Clevo M570U sets IOCFG bit 18 if the cdrom
1501                         * isn't used to boot the system which
1502                         * disables the channel.
1503                         */
1504                        .ident = "M570U",
1505                        .matches = {
1506                                DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1507                                DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1508                        },
1509                },
1510
1511                { }     /* terminate list */
1512        };
1513        struct pci_dev *pdev = to_pci_dev(host->dev);
1514        struct piix_host_priv *hpriv = host->private_data;
1515
1516        if (!dmi_check_system(sysids))
1517                return;
1518
1519        /* The datasheet says that bit 18 is NOOP but certain systems
1520         * seem to use it to disable a channel.  Clear the bit on the
1521         * affected systems.
1522         */
1523        if (hpriv->saved_iocfg & (1 << 18)) {
1524                dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1525                pci_write_config_dword(pdev, PIIX_IOCFG,
1526                                       hpriv->saved_iocfg & ~(1 << 18));
1527        }
1528}
1529
1530static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1531{
1532        static const struct dmi_system_id broken_systems[] = {
1533                {
1534                        .ident = "HP Compaq 2510p",
1535                        .matches = {
1536                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1537                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1538                        },
1539                        /* PCI slot number of the controller */
1540                        .driver_data = (void *)0x1FUL,
1541                },
1542                {
1543                        .ident = "HP Compaq nc6000",
1544                        .matches = {
1545                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1546                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1547                        },
1548                        /* PCI slot number of the controller */
1549                        .driver_data = (void *)0x1FUL,
1550                },
1551
1552                { }     /* terminate list */
1553        };
1554        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1555
1556        if (dmi) {
1557                unsigned long slot = (unsigned long)dmi->driver_data;
1558                /* apply the quirk only to on-board controllers */
1559                return slot == PCI_SLOT(pdev->devfn);
1560        }
1561
1562        return false;
1563}
1564
1565static int prefer_ms_hyperv = 1;
1566module_param(prefer_ms_hyperv, int, 0);
1567
1568static void piix_ignore_devices_quirk(struct ata_host *host)
1569{
1570#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1571        static const struct dmi_system_id ignore_hyperv[] = {
1572                {
1573                        /* On Hyper-V hypervisors the disks are exposed on
1574                         * both the emulated SATA controller and on the
1575                         * paravirtualised drivers.  The CD/DVD devices
1576                         * are only exposed on the emulated controller.
1577                         * Request we ignore ATA devices on this host.
1578                         */
1579                        .ident = "Hyper-V Virtual Machine",
1580                        .matches = {
1581                                DMI_MATCH(DMI_SYS_VENDOR,
1582                                                "Microsoft Corporation"),
1583                                DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1584                        },
1585                },
1586                { }     /* terminate list */
1587        };
1588        const struct dmi_system_id *dmi = dmi_first_match(ignore_hyperv);
1589
1590        if (dmi && prefer_ms_hyperv) {
1591                host->flags |= ATA_HOST_IGNORE_ATA;
1592                dev_info(host->dev, "%s detected, ATA device ignore set\n",
1593                        dmi->ident);
1594        }
1595#endif
1596}
1597
1598/**
1599 *      piix_init_one - Register PIIX ATA PCI device with kernel services
1600 *      @pdev: PCI device to register
1601 *      @ent: Entry in piix_pci_tbl matching with @pdev
1602 *
1603 *      Called from kernel PCI layer.  We probe for combined mode (sigh),
1604 *      and then hand over control to libata, for it to do the rest.
1605 *
1606 *      LOCKING:
1607 *      Inherited from PCI layer (may sleep).
1608 *
1609 *      RETURNS:
1610 *      Zero on success, or -ERRNO value.
1611 */
1612
1613static int __devinit piix_init_one(struct pci_dev *pdev,
1614                                   const struct pci_device_id *ent)
1615{
1616        struct device *dev = &pdev->dev;
1617        struct ata_port_info port_info[2];
1618        const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1619        struct scsi_host_template *sht = &piix_sht;
1620        unsigned long port_flags;
1621        struct ata_host *host;
1622        struct piix_host_priv *hpriv;
1623        int rc;
1624
1625        ata_print_version_once(&pdev->dev, DRV_VERSION);
1626
1627        /* no hotplugging support for later devices (FIXME) */
1628        if (!in_module_init && ent->driver_data >= ich5_sata)
1629                return -ENODEV;
1630
1631        if (piix_broken_system_poweroff(pdev)) {
1632                piix_port_info[ent->driver_data].flags |=
1633                                ATA_FLAG_NO_POWEROFF_SPINDOWN |
1634                                        ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1635                dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1636                                "on poweroff and hibernation\n");
1637        }
1638
1639        port_info[0] = piix_port_info[ent->driver_data];
1640        port_info[1] = piix_port_info[ent->driver_data];
1641
1642        port_flags = port_info[0].flags;
1643
1644        /* enable device and prepare host */
1645        rc = pcim_enable_device(pdev);
1646        if (rc)
1647                return rc;
1648
1649        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1650        if (!hpriv)
1651                return -ENOMEM;
1652
1653        /* Save IOCFG, this will be used for cable detection, quirk
1654         * detection and restoration on detach.  This is necessary
1655         * because some ACPI implementations mess up cable related
1656         * bits on _STM.  Reported on kernel bz#11879.
1657         */
1658        pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1659
1660        /* ICH6R may be driven by either ata_piix or ahci driver
1661         * regardless of BIOS configuration.  Make sure AHCI mode is
1662         * off.
1663         */
1664        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1665                rc = piix_disable_ahci(pdev);
1666                if (rc)
1667                        return rc;
1668        }
1669
1670        /* SATA map init can change port_info, do it before prepping host */
1671        if (port_flags & ATA_FLAG_SATA)
1672                hpriv->map = piix_init_sata_map(pdev, port_info,
1673                                        piix_map_db_table[ent->driver_data]);
1674
1675        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1676        if (rc)
1677                return rc;
1678        host->private_data = hpriv;
1679
1680        /* initialize controller */
1681        if (port_flags & ATA_FLAG_SATA) {
1682                piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1683                rc = piix_init_sidpr(host);
1684                if (rc)
1685                        return rc;
1686                if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1687                        sht = &piix_sidpr_sht;
1688        }
1689
1690        /* apply IOCFG bit18 quirk */
1691        piix_iocfg_bit18_quirk(host);
1692
1693        /* On ICH5, some BIOSen disable the interrupt using the
1694         * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1695         * On ICH6, this bit has the same effect, but only when
1696         * MSI is disabled (and it is disabled, as we don't use
1697         * message-signalled interrupts currently).
1698         */
1699        if (port_flags & PIIX_FLAG_CHECKINTR)
1700                pci_intx(pdev, 1);
1701
1702        if (piix_check_450nx_errata(pdev)) {
1703                /* This writes into the master table but it does not
1704                   really matter for this errata as we will apply it to
1705                   all the PIIX devices on the board */
1706                host->ports[0]->mwdma_mask = 0;
1707                host->ports[0]->udma_mask = 0;
1708                host->ports[1]->mwdma_mask = 0;
1709                host->ports[1]->udma_mask = 0;
1710        }
1711        host->flags |= ATA_HOST_PARALLEL_SCAN;
1712
1713        /* Allow hosts to specify device types to ignore when scanning. */
1714        piix_ignore_devices_quirk(host);
1715
1716        pci_set_master(pdev);
1717        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1718}
1719
1720static void piix_remove_one(struct pci_dev *pdev)
1721{
1722        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1723        struct piix_host_priv *hpriv = host->private_data;
1724
1725        pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1726
1727        ata_pci_remove_one(pdev);
1728}
1729
1730static int __init piix_init(void)
1731{
1732        int rc;
1733
1734        DPRINTK("pci_register_driver\n");
1735        rc = pci_register_driver(&piix_pci_driver);
1736        if (rc)
1737                return rc;
1738
1739        in_module_init = 0;
1740
1741        DPRINTK("done\n");
1742        return 0;
1743}
1744
1745static void __exit piix_exit(void)
1746{
1747        pci_unregister_driver(&piix_pci_driver);
1748}
1749
1750module_init(piix_init);
1751module_exit(piix_exit);
1752
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