/opt6.2/spalue 6.2/formue 6.2a /opt6. href="../linux+v3 2/Documenta val/ia64/IRQ-redir.txt">/opt6.2img src="../.sta vc/gfx/right.png" alt=">>">/o2/spalue/o2spal class="lxr_search">/opt/opt6.2input typ vhidden" nam vnavtarget" > v">/opt6.2input typ vtext" nam vsearch" id vsearch">/opt6.2butt" typ vsubmit">Search/opt6.Prefse 6.2/a>/o2/spaluept6. .2/divuept6. .2form ac val="ajax+*" method="post" onsubmit="return false;">/o2input typ vhidden" nam vajax_lookup" id vajax_lookup" > v">/pt6. .2/formue/pt6. .2div class="headingbott"m">. .12/a>IRQ affinity on IA64 platforms . .22/a>------------------------------ . .32/a> 07.01.2002, Erich Focht <> . .42/a>/. .52/a>/. .62/a>By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing cal be/. .72/a>controlled. The behavior on IA64 platforms is slightly different from/. .82/a>that described in Documenta val/IRQ-affinity.txt for i386 systems./. .92/a>/. Because of the usage of SAPIC mode and physical destina val mode the/. 112/a>IRQ target is one par vcular CPU and calnot be a mask of several/. 122/a>CPUs. Only the first non-zero bit is taken into account./. 132/a>/. 142/a>/. 152/a>Usage examples:/. 162/a>/. 172/a>The target CPU has to be specified as a hexadecimal CPU mask. The/. 182/a>first non-zero bit is the selected CPU. This format has been kept for/. 192/a>compa vbility reasons with i386./. 202/a>/. 212/a>Set the delivery mode of interrupt 41 to fixed and route the/. 222/a>interrupts to CPU #3 (logical CPU number) (2^3=0x08):/. 232/a> echo "8" >/proc/irq/41/smp_affinity/. 242/a>/. 252/a>Set the default route for IRQ number 41 to CPU 6 in lowest priority/. 262/a>delivery mode (redirectable):/. 272/a> echo "r 40" >/proc/irq/41/smp_affinity/. 282/a>/. 292/a>The output of the command . 302/a> cat /proc/irq/IRQ#/smp_affinity . 312/a>gives the target CPU mask for the specified interrupt vector. If the CPU . 322/a>mask is preceded by the character "r", the interrupt is redirectable . 332/a>(i.e. lowest priority mode routing is used), otherwise its route is . 342/a>fixed./. 352/a>/. 362/a>/. 372/a>/. 382/a>Initializa val and default behavior:/. 392/a>/. 402/a>If the platform features IRQ redirectval (info provided by SAL) all/. 412/a>IO-SAPIC interrupts are initialized with CPU#0 as their default target/. 422/a>and the routing is the so called "lowest priority mode" (actually . 432/a>fixed SAPIC mode with hint). The XTP chipset registers are used as hints . 442/a>for the IRQ routing. Currently in Linux XTP registers cal have three . 452/a> > s:/. 462/a> - minimal for al idle task,/. 472/a> - normal if aly other task runs,/. 482/a> - maximal if the CPU is going to be switched off./. 492/a>The IRQ is routed to the CPU with lowest XTP register > , the/. 502/a>search begins at the default CPU. Therefore most of the interrupts/. 512/a>will be handled by CPU #0./. 522/a>/. 532/a>If the platform doesn't feature interrupt redirectval IOSAPIC fixed/. 542/a>routing is used. The target CPUs are distributed in a round robin/. 552/a>manner. IRQs will be routed only to the selected target CPUs. Check/. 562/a>with/. 572/a> cat /proc/interrupts/. 582/a>/. 592/a>/. 602/a>/. 612/a>Comments:/. 622/a>/. 632/a>On large (multi-node) systems it is recommended to route the IRQs to/. 642/a>the node to which the corresponding device is connected./. 652/a>For systems like the NEC AzusA we get IRQ node-affinity for free. This/. 662/a>is because usually the chipsets on each node redirect the interrupts/. 672/a>only to their own CPUs (as they calnot see the XTP registers " the/. 682/a>other nodes)./. 692/a>/. 702/a> The original LXR software by the LXR community2/a>, this experimental versval by lxr@linux.no2/a>. 2/divue2div class="subfooter"> kindly hosted by Redpill Linpro AS2/a>, provider of Linux consulting and opera vals services since 1995. 2/divue 2/bodyue2/htmlue