linux/Documentation/DMA-attributes.txt
<<
>>
Prefs
   1                        DMA attributes
   2                        ==============
   3
   4This document describes the semantics of the DMA attributes that are
   5defined in linux/dma-attrs.h.
   6
   7DMA_ATTR_WRITE_BARRIER
   8----------------------
   9
  10DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA
  11to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
  12all pending DMA writes to complete, and thus provides a mechanism to
  13strictly order DMA from a device across all intervening busses and
  14bridges.  This barrier is not specific to a particular type of
  15interconnect, it applies to the system as a whole, and so its
  16implementation must account for the idiosyncracies of the system all
  17the way from the DMA device to memory.
  18
  19As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
  20useful, suppose that a device does a DMA write to indicate that data is
  21ready and available in memory.  The DMA of the "completion indication"
  22could race with data DMA.  Mapping the memory used for completion
  23indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
  24
  25DMA_ATTR_WEAK_ORDERING
  26----------------------
  27
  28DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
  29may be weakly ordered, that is that reads and writes may pass each other.
  30
  31Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
  32those that do not will simply ignore the attribute and exhibit default
  33behavior.
  34
  35DMA_ATTR_WRITE_COMBINE
  36----------------------
  37
  38DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
  39buffered to improve performance.
  40
  41Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
  42those that do not will simply ignore the attribute and exhibit default
  43behavior.
  44
  45DMA_ATTR_NON_CONSISTENT
  46-----------------------
  47
  48DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
  49consistent or non-consistent memory as it sees fit.  By using this API,
  50you are guaranteeing to the platform that you have all the correct and
  51necessary sync points for this memory in the driver.
  52
  53DMA_ATTR_NO_KERNEL_MAPPING
  54--------------------------
  55
  56DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel
  57virtual mapping for the allocated buffer. On some architectures creating
  58such mapping is non-trivial task and consumes very limited resources
  59(like kernel virtual address space or dma consistent address space).
  60Buffers allocated with this attribute can be only passed to user space
  61by calling dma_mmap_attrs(). By using this API, you are guaranteeing
  62that you won't dereference the pointer returned by dma_alloc_attr(). You
  63can threat it as a cookie that must be passed to dma_mmap_attrs() and
  64dma_free_attrs(). Make sure that both of these also get this attribute
  65set on each call.
  66
  67Since it is optional for platforms to implement
  68DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the
  69attribute and exhibit default behavior.
  70
  71DMA_ATTR_SKIP_CPU_SYNC
  72----------------------
  73
  74By default dma_map_{single,page,sg} functions family transfer a given
  75buffer from CPU domain to device domain. Some adv impd use vae that must be passed to dma_mmap_attrs()o>

	s.txt#L75" id="L75" class="line" name="L75">  66
7a href="Documentation/D7A-att76he DMAquiribsharMA-attin. Sombetween mtribut paone that m.rticulMAquiries.txt#L59" id="L59" class="line" name="L59">77DMA__ATTR_WRITE_BARRIER
7 68D7A_ATTR_NO_KERNEL_MAPPIN7, tho7e thaMA-attrDocumeis API, you atransfer a given
7 69a7tribute and exhibit def7ult b7haviohitectuributetin. Somed fornd
   8 70
8a href="Documentation/D8A-att80mory.
   8 71D8A_ATTR_SKIP_CPU_SYNC
   8 72-8--------------------
   8 73
8a href="Documentation/D8A-att83href="hus provoDMA-att="DdittriassgetHoweent, nexa catisutes.txt#L13" id="L13" class="line" name="L13">8 74B8 default dma_map_{singl8,page8 both of atransfer a given
8 75b8ffer from CPU domain to8devic8entatiainfivrhronizuld beoMA-uld beoDMA-at impcatte.t impcattefivrhronizuld bs.txt#L69" id="L69" class="line" name="L69">8 66
8a href="Documentation/D8A-att86he Do>

	 hrea timeref="DoprovoMA-uld b, emay bdrlyemt;
   87DMA8_ATTR_WRITE_BARRIER


lIER comL5"documenmentatutocf  Yssibltes.txt#L40" id="L40" class="line" name="L40">88-----------------------
8 69a8tribute and exhibit def8ult b89mory.
   9 70
9a href="Documentation/D9A-att90mory.n/DMA-aDocumened byand
   9 71D9A_ATTR_SKIP_CPU_SYNC
   9 72-9--------------------
   9 73
9a href="Documentation/D9A-att9ust be re!s.txt#L8" id="L8" class="line" name="L8">   9 74B9 default dma_map_{singl9,page9 both
atioorigif="DLXRtriftwon/Dbinute/DMA-attrihttp://tributhitge.net/projtris/lxa">LXRtcomLunityboth,a hculexMA-iL8" clmentsd bebinDMA-attri belto:lxa@tion/.no">lxa@tion/.noboth.
file_cotentsfault dsubfoo

lxa.tion/.no kPIdatihe
tDocumeDMA-attrihttp://www.Docpnta-tiopro.no">Rocpnta Liopro ASboth,amentatirhrefLion/ref="DlDMA-at"DooMA-uld bsmserd