linux/Documentation/pinctrl.txt
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   1PINCTRL (PIN CONTROL) subsystem
   2This document outlines the pin control subsystem in Linux
   3
   4This subsystem deals with:
   5
   6- Enumerating and naming controllable pins
   7
   8- Multiplexing of pins, pads, fingers (etc) see below for details
   9
  10- Configuration of pins, pads, fingers (etc), such as software-controlled
  11  biasing and driving mode specific pins, such as pull-up/down, open drain,
  12  load capacitance etc.
  13
  14Top-level interface
  15===================
  16
  17Definition of PIN CONTROLLER:
  18
  19- A pin controller is a piece of hardware, usually a set of registers, that
  20  can control PINs. It may be able to multiplex, bias, set load capacitance,
  21  set drive strength etc for individual pins or groups of pins.
  22
  23Definition of PIN:
  24
  25- PINS are equal to pads, fingers, balls or whatever packaging input or
  26  output line you want to control and these are denoted by unsigned integers
  27  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  28  there may be several such number spaces in a system. This pin space may
  29  be sparse - i.e. there may be gaps in the space with numbers where no
  30  pin exists.
  31
  32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  33pin control framework, and this descriptor contains an array of pin descriptors
  34describing the pins handled by this specific pin controller.
  35
  36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
  37
  38        A   B   C   D   E   F   G   H
  39
  40   8    o   o   o   o   o   o   o   o
  41
  42   7    o   o   o   o   o   o   o   o
  43
  44   6    o   o   o   o   o   o   o   o
  45
  46   5    o   o   o   o   o   o   o   o
  47
  48   4    o   o   o   o   o   o   o   o
  49
  50   3    o   o   o   o   o   o   o   o
  51
  52   2    o   o   o   o   o   o   o   o
  53
  54   1    o   o   o   o   o   o   o   o
  55
  56To register a pin controller and name all the pins on this package we can do
  57this in our driver:
  58
  59#include <linux/pinctrl/pinctrl.h>
  60
  61const struct pinctrl_pin_desc foo_pins[] = {
  62      PINCTRL_PIN(0, "A8"),
  63      PINCTRL_PIN(1, "B8"),
  64      PINCTRL_PIN(2, "C8"),
  65      ...
  66      PINCTRL_PIN(61, "F1"),
  67      PINCTRL_PIN(62, "G1"),
  68      PINCTRL_PIN(63, "H1"),
  69};
  70
  71static struct pinctrl_desc foo_desc = {
  72        .name = "foo",
  73        .pins = foo_pins,
  74        .npins = ARRAY_SIZE(foo_pins),
  75        .maxpin = 63,
  76        .owner = THIS_MODULE,
  77};
  78
  79int __init foo_probe(void)
  80{
  81        struct pinctrl_dev *pctl;
  82
  83        pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
  84        if (IS_ERR(pctl))
  85                pr_err("could not register foo pin driver\n");
  86}
  87
  88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  89selected drivers, you need to select them from your machine's Kconfig entry,
  90since these are so tightly integrated with the machines they are used on.
  91See for example arch/arm/mach-u300/Kconfig for an example.
  92
  93Pins usually have fancier names than this. You can find these in the dataheet
  94for your chip. Notice that the core pinctrl.h file provides a fancy macro
  95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
  96the pins from 0 in the upper left corner to 63 in the lower right corner.
  97This enumeration was arbitrarily chosen, in practice you need to think
  98through your numbering system so that it matches the layout of registers
  99and such things in your driver, or the code may become complicated. You must
 100also consider matching of offsets to the GPIO ranges that may be handled by
 101the pin controller.
 102
 103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
 104like this, walking around the edge of the chip, which seems to be industry
 105standard too (all these pads had names, too):
 106
 107
 108     0 ..... 104
 109   466        105
 110     .        .
 111     .        .
 112   358        224
 113    357 .... 225
 114
 115
 116Pin groups
 117==========
 118
 119Many controllers need to deal with groups of pins, so the pin controller
 120subsystem has a mechanism for enumerating groups of pins and retrieving the
 121actual enumerated pins that are part of a certain group.
 122
 123For example, say that we have a group of pins dealing with an SPI interface
 124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
 125on { 24, 25 }.
 126
 127These two groups are presented to the pin control subsystem by implementing
 128some generic pinctrl_ops like this:
 129
 130#include <linux/pinctrl/pinctrl.h>
 131
 132struct foo_group {
 133        const char *name;
 134        const unsigned int *pins;
 135        const unsigned num_pins;
 136};
 137
 138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
 139static const unsigned int i2c0_pins[] = { 24, 25 };
 140
 141static const struct foo_group foo_groups[] = {
 142        {
 143                .name = "spi0_grp",
 144                .pins = spi0_pins,
 145                .num_pins = ARRAY_SIZE(spi0_pins),
 146        },
 147        {
 148                .name = "i2c0_grp",
 149                .pins = i2c0_pins,
 150                .num_pins = ARRAY_SIZE(i2c0_pins),
 151        },
 152};
 153
 154
 155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 156{
 157        return ARRAY_SIZE(foo_groups);
 158}
 159
 160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 161                                       unsigned selector)
 162{
 163        return foo_groups[selector].name;
 164}
 165
 166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 167                               unsigned ** const pins,
 168                               unsigned * const num_pins)
 169{
 170        *pins = (unsigned *) foo_groups[selector].pins;
 171        *num_pins = foo_groups[selector].num_pins;
 172        return 0;
 173}
 174
 175static struct pinctrl_ops foo_pctrl_ops = {
 176        .get_groups_count = foo_get_groups_count,
 177        .get_group_name = foo_get_group_name,
 178        .get_group_pins = foo_get_group_pins,
 179};
 180
 181
 182static struct pinctrl_desc foo_desc = {
 183       ...
 184       .pctlops = &foo_pctrl_ops,
 185};
 186
 187The pin control subsystem will call the .get_groups_count() function to
 188determine total number of legal selectors, then it will call the other functions
 189to retrieve the name and pins of the group. Maintaining the data structure of
 190the groups is up to the driver, this is just a simple example - in practice you
 191may need more entries in your group structure, for example specific register
 192ranges associated with each group and so on.
 193
 194
 195Pin configuration
 196=================
 197
 198Pins can sometimes be software-configured in an various ways, mostly related
 199to their electronic properties when used as inputs or outputs. For example you
 200may be able to make an output pin high impedance, or "tristate" meaning it is
 201effectively disconnected. You may be able to connect an input pin to VDD or GND
 202using a certain resistor value - pull up and pull down - so that the pin has a
 203stable value when nothing is driving the rail it is connected to, or when it's
 204unconnected.
 205
 206Pin configuration can be programmed either using the explicit APIs described
 207immediately below, or by adding configuration entries into the mapping table;
 208see section "Board/machine configuration" below.
 209
 210For example, a platform may do the following to pull up a pin to VDD:
 211
 212#include <linux/pinctrl/consumer.h>
 213
 214ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
 215
 216The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
 217above, is entirely defined by the pin controller driver.
 218
 219The pin configuration driver implements callbacks for changing pin
 220configuration in the pin controller ops like this:
 221
 222#include <linux/pinctrl/pinctrl.h>
 223#include <linux/pinctrl/pinconf.h>
 224#include "platform_x_pindefs.h"
 225
 226static int foo_pin_config_get(struct pinctrl_dev *pctldev,
 227                    unsigned offset,
 228                    unsigned long *config)
 229{
 230        struct my_conftype conf;
 231
 232        ... Find setting for pin @ offset ...
 233
 234        *config = (unsigned long) conf;
 235}
 236
 237static int foo_pin_config_set(struct pinctrl_dev *pctldev,
 238                    unsigned offset,
 239                    unsigned long config)
 240{
 241        struct my_conftype *conf = (struct my_conftype *) config;
 242
 243        switch (conf) {
 244                case PLATFORM_X_PULL_UP:
 245                ...
 246                }
 247        }
 248}
 249
 250static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
 251                    unsigned selector,
 252                    unsigned long *config)
 253{
 254        ...
 255}
 256
 257static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
 258                    unsigned selector,
 259                    unsigned long config)
 260{
 261        ...
 262}
 263
 264static struct pinconf_ops foo_pconf_ops = {
 265        .pin_config_get = foo_pin_config_get,
 266        .pin_config_set = foo_pin_config_set,
 267        .pin_config_group_get = foo_pin_config_group_get,
 268        .pin_config_group_set = foo_pin_config_group_set,
 269};
 270
 271/* Pin config operations are handled by some pin controller */
 272static struct pinctrl_desc foo_desc = {
 273        ...
 274        .confops = &foo_pconf_ops,
 275};
 276
 277Since some controllers have special logic for handling entire groups of pins
 278they can exploit the special whole-group pin control function. The
 279pin_config_group_set() callback is allowed to return the error code -EAGAIN,
 280for groups it does not want to handle, or if it just wants to do some
 281group-level handling and then fall through to iterate over all pins, in which
 282case each individual pin will be treated by separate pin_config_set() calls as
 283well.
 284
 285
 286Interaction with the GPIO subsystem
 287===================================
 288
 289The GPIO drivers may want to perform operations of various types on the same
 290physical pins that are also registered as pin controller pins.
 291
 292Since the pin controller subsystem have its pinspace local to the pin
 293controller we need a mapping so that the pin control subsystem can figure out
 294which pin controller handles control of a certain GPIO pin. Since a single
 295pin controller may be muxing several GPIO ranges (typically SoCs that have
 296one set of pins but internally several GPIO silicon blocks, each modeled as
 297a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
 298instance like this:
 299
 300struct gpio_chip chip_a;
 301struct gpio_chip chip_b;
 302
 303static struct pinctrl_gpio_range gpio_range_a = {
 304        .name = "chip a",
 305        .id = 0,
 306        .base = 32,
 307        .pin_base = 32,
 308        .npins = 16,
 309        .gc = &chip_a;
 310};
 311
 312static struct pinctrl_gpio_range gpio_range_b = {
 313        .name = "chip b",
 314        .id = 0,
 315        .base = 48,
 316        .pin_base = 64,
 317        .npins = 8,
 318        .gc = &chip_b;
 319};
 320
 321{
 322        struct pinctrl_dev *pctl;
 323        ...
 324        pinctrl_add_gpio_range(pctl, &gpio_range_a);
 325        pinctrl_add_gpio_range(pctl, &gpio_range_b);
 326}
 327
 328So this complex system has one pin controller handling two different
 329GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
 330"chip b" have different .pin_base, which means a start pin number of the
 331GPIO range.
 332
 333The GPIO range of "chip a" starts from the GPIO base of 32 and actual
 334pin range also starts from 32. However "chip b" has different starting
 335offset for the GPIO range and pin range. The GPIO range of "chip b" starts
 336from GPIO number 48, while the pin range of "chip b" starts from 64.
 337
 338We can convert a gpio number to actual pin number using this "pin_base".
 339They are mapped in the global GPIO pin space at:
 340
 341chip a:
 342 - GPIO range : [32 .. 47]
 343 - pin range  : [32 .. 47]
 344chip b:
 345 - GPIO range : [48 .. 55]
 346 - pin range  : [64 .. 71]
 347
 348When GPIO-specific functions in the pin control subsystem are called, these
 349ranges will be used to look up the appropriate pin controller by inspecting
 350and matching the pin to the pin ranges across all controllers. When a
 351pin controller handling the matching range is found, GPIO-specific functions
 352will be called on that specific pin controller.
 353
 354For all functionalities dealing with pin biasing, pin muxing etc, the pin
 355controller subsystem will subtract the range's .base offset from the passed
 356in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
 357After that, the subsystem passes it on to the pin control driver, so the driver
 358will get an pin number into its handled number range. Further it is also passed
 359the range ID value, so that the pin controller knows which range it should
 360deal with.
 361
 362PINMUX interfaces
 363=================
 364
 365These calls use the pinmux_* naming prefix.  No other calls should use that
 366prefix.
 367
 368
 369What is pinmuxing?
 370==================
 371
 372PINMUX, also known as padmux, ballmux, alternate functions or mission modes
 373is a way for chip vendors producing some kind of electrical packages to use
 374a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
 375functions, depending on the application. By "application" in this context
 376we usually mean a way of soldering or wiring the package into an electronic
 377system, even though the framework makes it possible to also change the function
 378at runtime.
 379
 380Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
 381
 382        A   B   C   D   E   F   G   H
 383      +---+
 384   8  | o | o   o   o   o   o   o   o
 385      |   |
 386   7  | o | o   o   o   o   o   o   o
 387      |   |
 388   6  | o | o   o   o   o   o   o   o
 389      +---+---+
 390   5  | o | o | o   o   o   o   o   o
 391      +---+---+               +---+
 392   4    o   o   o   o   o   o | o | o
 393                              |   |
 394   3    o   o   o   o   o   o | o | o
 395                              |   |
 396   2    o   o   o   o   o   o | o | o
 397      +-------+-------+-------+---+---+
 398   1  | o   o | o   o | o   o | o | o |
 399      +-------+-------+-------+---+---+
 400
 401This is not tetris. The game to think of is chess. Not all PGA/BGA packages
 402are chessboard-like, big ones have "holes" in some arrangement according to
 403different design patterns, but we're using this as a simple example. Of the
 404pins you see some will be taken by things like a few VCC and GND to feed power
 405to the chip, and quite a few will be taken by large ports like an external
 406memory interface. The remaining pins will often be subject to pin multiplexing.
 407
 408The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
 409its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
 410pinctrl_register_pins() and a suitable data set as shown earlier.
 411
 412In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
 413(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
 414some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
 415be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
 416we cannot use the SPI port and I2C port at the same time. However in the inside
 417of the package the silicon performing the SPI logic can alternatively be routed
 418out on pins { G4, G3, G2, G1 }.
 419
 420On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
 421special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
 422consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
 423{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
 424port on pins { G4, G3, G2, G1 } of course.
 425
 426This way the silicon blocks present inside the chip can be multiplexed "muxed"
 427out on different pin ranges. Often contemporary SoC (systems on chip) will
 428contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
 429different pins by pinmux settings.
 430
 431Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
 432common to be able to use almost any pin as a GPIO pin if it is not currently
 433in use by some other I/O port.
 434
 435
 436Pinmux conventions
 437==================
 438
 439The purpose of the pinmux functionality in the pin controller subsystem is to
 440abstract and provide pinmux settings to the devices you choose to instantiate
 441in your machine configuration. It is inspired by the clk, GPIO and regulator
 442subsystems, so devices will request their mux setting, but it's also possible
 443to request a single pin for e.g. GPIO.
 444
 445Definitions:
 446
 447- FUNCTIONS can be switched in and out by a driver residing with the pin
 448  control subsystem in the drivers/pinctrl/* directory of the kernel. The
 449  pin control driver knows the possible functions. In the example above you can
 450  identify three pinmux functions, one for spi, one for i2c and one for mmc.
 451
 452- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
 453  In this case the array could be something like: { spi0, i2c0, mmc0 }
 454  for the three available functions.
 455
 456- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
 457  function is *always* associated with a certain set of pin groups, could
 458  be just a single one, but could also be many. In the example above the
 459  function i2c is associated with the pins { A5, B5 }, enumerated as
 460  { 24, 25 } in the controller pin space.
 461
 462  The Function spi is associated with pin groups { A8, A7, A6, A5 }
 463  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
 464  { 38, 46, 54, 62 } respectively.
 465
 466  Group names must be unique per pin controller, no two groups on the same
 467  controller may have the same name.
 468
 469- The combination of a FUNCTION and a PIN GROUP determine a certain function
 470  for a certain set of pins. The knowledge of the functions and pin groups
 471  and their machine-specific particulars are kept inside the pinmux driver,
 472  from the outside only the enumerators are known, and the driver core can:
 473
 474  - Request the name of a function with a certain selector (>= 0)
 475  - A list of groups associated with a certain function
 476  - Request that a certain group in that list to be activated for a certain
 477    function
 478
 479  As already described above, pin groups are in turn self-descriptive, so
 480  the core will retrieve the actual pin range in a certain group from the
 481  driver.
 482
 483- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
 484  device by the board file, device tree or similar machine setup configuration
 485  mechanism, similar to how regulators are connected to devices, usually by
 486  name. Defining a pin controller, function and group thus uniquely identify
 487  the set of pins to be used by a certain device. (If only one possible group
 488  of pins is available for the function, no group name need to be supplied -
 489  the core will simply select the first and only group available.)
 490
 491  In the example case we can define that this particular machine shall
 492  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
 493  fi2c0 group gi2c0, on the primary pin controller, we get mappings
 494  like these:
 495
 496  {
 497    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
 498    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
 499  }
 500
 501  Every map must be assigned a state name, pin controller, device and
 502  function. The group is not compulsory - if it is omitted the first group
 503  presented by the driver as applicable for the function will be selected,
 504  which is useful for simple cases.
 505
 506  It is possible to map several groups to the same combination of device,
 507  pin controller and function. This is for cases where a certain function on
 508  a certain pin controller may use different sets of pins in different
 509  configurations.
 510
 511- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
 512  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
 513  other device mux setting or GPIO pin request has already taken your physical
 514  pin, you will be denied the use of it. To get (activate) a new setting, the
 515  old one has to be put (deactivated) first.
 516
 517Sometimes the documentation and hardware registers will be oriented around
 518pads (or "fingers") rather than pins - these are the soldering surfaces on the
 519silicon inside the package, and may or may not match the actual number of
 520pins/balls underneath the capsule. Pick some enumeration that makes sense to
 521you. Define enumerators only for the pins you can control if that makes sense.
 522
 523Assumptions:
 524
 525We assume that the number of possible function maps to pin groups is limited by
 526the hardware. I.e. we assume that there is no system where any function can be
 527mapped to any pin, like in a phone exchange. So the available pins groups for
 528a certain function will be limited to a few choices (say up to eight or so),
 529not hundreds or any amount of choices. This is the characteristic we have found
 530by inspecting available pinmux hardware, and a necessary assumption since we
 531expect pinmux drivers to present *all* possible function vs pin group mappings
 532to the subsystem.
 533
 534
 535Pinmux drivers
 536==============
 537
 538The pinmux core takes care of preventing conflicts on pins and calling
 539the pin controller driver to execute different settings.
 540
 541It is the responsibility of the pinmux driver to impose further restrictions
 542(say for example infer electronic limitations due to load etc) to determine
 543whether or not the requested function can actually be allowed, and in case it
 544is possible to perform the requested mux setting, poke the hardware so that
 545this happens.
 546
 547Pinmux drivers are required to supply a few callback functions, some are
 548optional. Usually the enable() and disable() functions are implemented,
 549writing values into some certain registers to activate a certain mux setting
 550for a certain pin.
 551
 552A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
 553into some register named MUX to select a certain function with a certain
 554group of pins would work something like this:
 555
 556#include <linux/pinctrl/pinctrl.h>
 557#include <linux/pinctrl/pinmux.h>
 558
 559struct foo_group {
 560        const char *name;
 561        const unsigned int *pins;
 562        const unsigned num_pins;
 563};
 564
 565static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
 566static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
 567static const unsigned i2c0_pins[] = { 24, 25 };
 568static const unsigned mmc0_1_pins[] = { 56, 57 };
 569static const unsigned mmc0_2_pins[] = { 58, 59 };
 570static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
 571
 572static const struct foo_group foo_groups[] = {
 573        {
 574                .name = "spi0_0_grp",
 575                .pins = spi0_0_pins,
 576                .num_pins = ARRAY_SIZE(spi0_0_pins),
 577        },
 578        {
 579                .name = "spi0_1_grp",
 580                .pins = spi0_1_pins,
 581                .num_pins = ARRAY_SIZE(spi0_1_pins),
 582        },
 583        {
 584                .name = "i2c0_grp",
 585                .pins = i2c0_pins,
 586                .num_pins = ARRAY_SIZE(i2c0_pins),
 587        },
 588        {
 589                .name = "mmc0_1_grp",
 590                .pins = mmc0_1_pins,
 591                .num_pins = ARRAY_SIZE(mmc0_1_pins),
 592        },
 593        {
 594                .name = "mmc0_2_grp",
 595                .pins = mmc0_2_pins,
 596                .num_pins = ARRAY_SIZE(mmc0_2_pins),
 597        },
 598        {
 599                .name = "mmc0_3_grp",
 600                .pins = mmc0_3_pins,
 601                .num_pins = ARRAY_SIZE(mmc0_3_pins),
 602        },
 603};
 604
 605
 606static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 607{
 608        return ARRAY_SIZE(foo_groups);
 609}
 610
 611static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
 612                                       unsigned selector)
 613{
 614        return foo_groups[selector].name;
 615}
 616
 617static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 618                               unsigned ** const pins,
 619                               unsigned * const num_pins)
 620{
 621        *pins = (unsigned *) foo_groups[selector].pins;
 622        *num_pins = foo_groups[selector].num_pins;
 623        return 0;
 624}
 625
 626static struct pinctrl_ops foo_pctrl_ops = {
 627        .get_groups_count = foo_get_groups_count,
 628        .get_group_name = foo_get_group_name,
 629        .get_group_pins = foo_get_group_pins,
 630};
 631
 632struct foo_pmx_func {
 633        const char *name;
 634        const char * const *groups;
 635        const unsigned num_groups;
 636};
 637
 638static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 639static const char * const i2c0_groups[] = { "i2c0_grp" };
 640static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
 641                                        "mmc0_3_grp" };
 642
 643static const struct foo_pmx_func foo_functions[] = {
 644        {
 645                .name = "spi0",
 646                .groups = spi0_groups,
 647                .num_groups = ARRAY_SIZE(spi0_groups),
 648        },
 649        {
 650                .name = "i2c0",
 651                .groups = i2c0_groups,
 652                .num_groups = ARRAY_SIZE(i2c0_groups),
 653        },
 654        {
 655                .name = "mmc0",
 656                .groups = mmc0_groups,
 657                .num_groups = ARRAY_SIZE(mmc0_groups),
 658        },
 659};
 660
 661int foo_get_functions_count(struct pinctrl_dev *pctldev)
 662{
 663        return ARRAY_SIZE(foo_functions);
 664}
 665
 666const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
 667{
 668        return foo_functions[selector].name;
 669}
 670
 671static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 672                          const char * const **groups,
 673                          unsigned * const num_groups)
 674{
 675        *groups = foo_functions[selector].groups;
 676        *num_groups = foo_functions[selector].num_groups;
 677        return 0;
 678}
 679
 680int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
 681                unsigned group)
 682{
 683        u8 regbit = (1 << selector + group);
 684
 685        writeb((readb(MUX)|regbit), MUX)
 686        return 0;
 687}
 688
 689void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 690                unsigned group)
 691{
 692        u8 regbit = (1 << selector + group);
 693
 694        writeb((readb(MUX) & ~(regbit)), MUX)
 695        return 0;
 696}
 697
 698struct pinmux_ops foo_pmxops = {
 699        .get_functions_count = foo_get_functions_count,
 700        .get_function_name = foo_get_fname,
 701        .get_function_groups = foo_get_groups,
 702        .enable = foo_enable,
 703        .disable = foo_disable,
 704};
 705
 706/* Pinmux operations are handled by some pin controller */
 707static struct pinctrl_desc foo_desc = {
 708        ...
 709        .pctlops = &foo_pctrl_ops,
 710        .pmxops = &foo_pmxops,
 711};
 712
 713In the example activating muxing 0 and 1 at the same time setting bits
 7140 and 1, uses one pin in common so they would collide.
 715
 716The beauty of the pinmux subsystem is that since it keeps track of all
 717pins and who is using them, it will already have denied an impossible
 718request like that, so the driver does not need to worry about such
 719things - when it gets a selector passed in, the pinmux subsystem makes
 720sure no other device or GPIO assignment is already using the selected
 721pins. Thus bits 0 and 1 in the control register will never be set at the
 722same time.
 723
 724All the above functions are mandatory to implement for a pinmux driver.
 725
 726
 727Pin control interaction with the GPIO subsystem
 728===============================================
 729
 730The public pinmux API contains two functions named pinctrl_request_gpio()
 731and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
 732gpiolib-based drivers as part of their gpio_request() and
 733gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
 734shall only be called from within respective gpio_direction_[input|output]
 735gpiolib implementation.
 736
 737NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
 738controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
 739that driver request proper muxing and other control for its pins.
 740
 741The function list could become long, especially if you can convert every
 742individual pin into a GPIO pin independent of any other pins, and then try
 743the approach to define every pin as a function.
 744
 745In this case, the function array would become 64 entries for each GPIO
 746setting and then the device functions.
 747
 748For this reason there are two functions a pin control driver can implement
 749to enable only GPIO on an individual pin: .gpio_request_enable() and
 750.gpio_disable_free().
 751
 752This function will pass in the affected GPIO range identified by the pin
 753controller core, so you know which GPIO pins are being affected by the request
 754operation.
 755
 756If your driver needs to have an indication from the framework of whether the
 757GPIO pin shall be used for input or output you can implement the
 758.gpio_set_direction() function. As described this shall be called from the
 759gpiolib driver and the affected GPIO range, pin offset and desired direction
 760will be passed along to this function.
 761
 762Alternatively to using these special functions, it is fully allowed to use
 763named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
 764obtain the function "gpioN" where "N" is the global GPIO pin number if no
 765special GPIO-handler is registered.
 766
 767
 768Board/machine configuration
 769==================================
 770
 771Boards and machines define how a certain complete running system is put
 772together, including how GPIOs and devices are muxed, how regulators are
 773constrained and how the clock tree looks. Of course pinmux settings are also
 774part of this.
 775
 776A pin controller configuration for a machine looks pretty much like a simple
 777regulator configuration, so for the example array above we want to enable i2c
 778and spi on the second function mapping:
 779
 780#include <linux/pinctrl/machine.h>
 781
 782static const struct pinctrl_map mapping[] __initconst = {
 783        {
 784                .dev_name = "foo-spi.0",
 785                .name = PINCTRL_STATE_DEFAULT,
 786                .type = PIN_MAP_TYPE_MUX_GROUP,
 787                .ctrl_dev_name = "pinctrl-foo",
 788                .data.mux.function = "spi0",
 789        },
 790        {
 791                .dev_name = "foo-i2c.0",
 792                .name = PINCTRL_STATE_DEFAULT,
 793                .type = PIN_MAP_TYPE_MUX_GROUP,
 794                .ctrl_dev_name = "pinctrl-foo",
 795                .data.mux.function = "i2c0",
 796        },
 797        {
 798                .dev_name = "foo-mmc.0",
 799                .name = PINCTRL_STATE_DEFAULT,
 800                .type = PIN_MAP_TYPE_MUX_GROUP,
 801                .ctrl_dev_name = "pinctrl-foo",
 802                .data.mux.function = "mmc0",
 803        },
 804};
 805
 806The dev_name here matches to the unique device name that can be used to look
 807up the device struct (just like with clockdev or regulators). The function name
 808must match a function provided by the pinmux driver handling this pin range.
 809
 810As you can see we may have several pin controllers on the system and thus
 811we need to specify which one of them that contain the functions we wish
 812to map.
 813
 814You register this pinmux mapping to the pinmux subsystem by simply:
 815
 816       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
 817
 818Since the above construct is pretty common there is a helper macro to make
 819it even more compact which assumes you want to use pinctrl-foo and position
 8200 for mapping, for example:
 821
 822static struct pinctrl_map __initdata mapping[] = {
 823        PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
 824};
 825
 826The mapping table may also contain pin configuration entries. It's common for
 827each pin/group to have a number of configuration entries that affect it, so
 828the table entries for configuration reference an array of config parameters
 829and values. An example using the convenience macros is shown below:
 830
 831static unsigned long i2c_grp_configs[] = {
 832        FOO_PIN_DRIVEN,
 833        FOO_PIN_PULLUP,
 834};
 835
 836static unsigned long i2c_pin_configs[] = {
 837        FOO_OPEN_COLLECTOR,
 838        FOO_SLEW_RATE_SLOW,
 839};
 840
 841static struct pinctrl_map __initdata mapping[] = {
 842        PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
 843        PIN_MAP_MUX_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
 844        PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
 845        PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
 846};
 847
 848Finally, some devices expect the mapping table to contain certain specific
 849named states. When running on hardware that doesn't need any pin controller
 850configuration, the mapping table must still contain those named states, in
 851order to explicitly indicate that the states were provided and intended to
 852be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
 853a named state without causing any pin controller to be programmed:
 854
 855static struct pinctrl_map __initdata mapping[] = {
 856        PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
 857};
 858
 859
 860Complex mappings
 861================
 862
 863As it is possible to map a function to different groups of pins an optional
 864.group can be specified like this:
 865
 866...
 867{
 868        .dev_name = "foo-spi.0",
 869        .name = "spi0-pos-A",
 870        .type = PIN_MAP_TYPE_MUX_GROUP,
 871        .ctrl_dev_name = "pinctrl-foo",
 872        .function = "spi0",
 873        .group = "spi0_0_grp",
 874},
 875{
 876        .dev_name = "foo-spi.0",
 877        .name = "spi0-pos-B",
 878        .type = PIN_MAP_TYPE_MUX_GROUP,
 879        .ctrl_dev_name = "pinctrl-foo",
 880        .function = "spi0",
 881        .group = "spi0_1_grp",
 882},
 883...
 884
 885This example mapping is used to switch between two positions for spi0 at
 886runtime, as described further below under the heading "Runtime pinmuxing".
 887
 888Further it is possible for one named state to affect the muxing of several
 889groups of pins, say for example in the mmc0 example above, where you can
 890additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
 891three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
 892case), we define a mapping like this:
 893
 894...
 895{
 896        .dev_name = "foo-mmc.0",
 897        .name = "2bit"
 898        .type = PIN_MAP_TYPE_MUX_GROUP,
 899        .ctrl_dev_name = "pinctrl-foo",
 900        .function = "mmc0",
 901        .group = "mmc0_1_grp",
 902},
 903{
 904        .dev_name = "foo-mmc.0",
 905        .name = "4bit"
 906        .type = PIN_MAP_TYPE_MUX_GROUP,
 907        .ctrl_dev_name = "pinctrl-foo",
 908        .function = "mmc0",
 909        .group = "mmc0_1_grp",
 910},
 911{
 912        .dev_name = "foo-mmc.0",
 913        .name = "4bit"
 914        .type = PIN_MAP_TYPE_MUX_GROUP,
 915        .ctrl_dev_name = "pinctrl-foo",
 916        .function = "mmc0",
 917        .group = "mmc0_2_grp",
 918},
 919{
 920        .dev_name = "foo-mmc.0",
 921        .name = "8bit"
 922        .type = PIN_MAP_TYPE_MUX_GROUP,
 923        .ctrl_dev_name = "pinctrl-foo",
 924        .function = "mmc0",
 925        .group = "mmc0_1_grp",
 926},
 927{
 928        .dev_name = "foo-mmc.0",
 929        .name = "8bit"
 930        .type = PIN_MAP_TYPE_MUX_GROUP,
 931        .ctrl_dev_name = "pinctrl-foo",
 932        .function = "mmc0",
 933        .group = "mmc0_2_grp",
 934},
 935{
 936        .dev_name = "foo-mmc.0",
 937        .name = "8bit"
 938        .type = PIN_MAP_TYPE_MUX_GROUP,
 939        .ctrl_dev_name = "pinctrl-foo",
 940        .function = "mmc0",
 941        .group = "mmc0_3_grp",
 942},
 943...
 944
 945The result of grabbing this mapping from the device with something like
 946this (see next paragraph):
 947
 948        p = devm_pinctrl_get(dev);
 949        s = pinctrl_lookup_state(p, "8bit");
 950        ret = pinctrl_select_state(p, s);
 951
 952or more simply:
 953
 954        p = devm_pinctrl_get_select(dev, "8bit");
 955
 956Will be that you activate all the three bottom records in the mapping at
 957once. Since they share the same name, pin controller device, function and
 958device, and since we allow multiple groups to match to a single device, they
 959all get selected, and they all get enabled and disable simultaneously by the
 960pinmux core.
 961
 962
 963Pinmux requests from drivers
 964============================
 965
 966Generally it is discouraged to let individual drivers get and enable pin
 967control. So if possible, handle the pin control in platform code or some other
 968place where you have access to all the affected struct device * pointers. In
 969some cases where a driver needs to e.g. switch between different mux mappings
 970at runtime this is not possible.
 971
 972A driver may request a certain control state to be activated, usually just the
 973default state like this:
 974
 975#include <linux/pinctrl/consumer.h>
 976
 977struct foo_state {
 978       struct pinctrl *p;
 979       struct pinctrl_state *s;
 980       ...
 981};
 982
 983foo_probe()
 984{
 985        /* Allocate a state holder named "foo" etc */
 986        struct foo_state *foo = ...;
 987
 988        foo->p = devm_pinctrl_get(&device);
 989        if (IS_ERR(foo->p)) {
 990                /* FIXME: clean up "foo" here */
 991                return PTR_ERR(foo->p);
 992        }
 993
 994        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
 995        if (IS_ERR(foo->s)) {
 996                /* FIXME: clean up "foo" here */
 997                return PTR_ERR(s);
 998        }
 999
1000        ret = pinctrl_select_state(foo->s);
1001        if (ret < 0) {
1002                /* FIXME: clean up "foo" here */
1003                return ret;
1004        }
1005}
1006
1007This get/lookup/select/put sequence can just as well be handled by bus drivers
1008if you don't want each and every driver to handle it and you know the
1009arrangement on your bus.
1010
1011The semantics of the pinctrl APIs are:
1012
1013- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1014  information for a given client device. It will allocate a struct from the
1015  kernel memory to hold the pinmux state. All mapping table parsing or similar
1016  slow operations take place within this API.
1017
1018- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1019  to be called automatically on the retrieved pointer when the associated
1020  device is removed. It is recommended to use this function over plain
1021  pinctrl_get().
1022
1023- pinctrl_lookup_state() is called in process context to obtain a handle to a
1024  specific state for a the client device. This operation may be slow too.
1025
1026- pinctrl_select_state() programs pin controller hardware according to the
1027  definition of the state as given by the mapping table. In theory this is a
1028  fast-path operation, since it only involved blasting some register settings
1029  into hardware. However, note that some pin controllers may have their
1030  registers on a slow/IRQ-based bus, so client devices should not assume they
1031  can call pinctrl_select_state() from non-blocking contexts.
1032
1033- pinctrl_put() frees all information associated with a pinctrl handle.
1034
1035- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1036  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1037  However, use of this function will be rare, due to the automatic cleanup
1038  that will occur even without calling it.
1039
1040  pinctrl_get() must be paired with a plain pinctrl_put().
1041  pinctrl_get() may not be paired with devm_pinctrl_put().
1042  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1043  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1044
1045Usually the pin control core handled the get/put pair and call out to the
1046device drivers bookkeeping operations, like checking available functions and
1047the associated pins, whereas the enable/disable pass on to the pin controller
1048driver which takes care of activating and/or deactivating the mux setting by
1049quickly poking some registers.
1050
1051The pins are allocated for your device when you issue the devm_pinctrl_get()
1052call, after this you should be able to see this in the debugfs listing of all
1053pins.
1054
1055NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1056requested pinctrl handles, for example if the pinctrl driver has not yet
1057registered. Thus make sure that the error path in your driver gracefully
1058cleans up and is ready to retry the probing later in the startup process.
1059
1060
1061System pin control hogging
1062==========================
1063
1064Pin control map entries can be hogged by the core when the pin controller
1065is registered. This means that the core will attempt to call pinctrl_get(),
1066lookup_state() and select_state() on it immediately after the pin control
1067device has been registered.
1068
1069This occurs for mapping table entries where the client device name is equal
1070to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1071
1072{
1073        .dev_name = "pinctrl-foo",
1074        .name = PINCTRL_STATE_DEFAULT,
1075        .type = PIN_MAP_TYPE_MUX_GROUP,
1076        .ctrl_dev_name = "pinctrl-foo",
1077        .function = "power_func",
1078},
1079
1080Since it may be common to request the core to hog a few always-applicable
1081mux settings on the primary pin controller, there is a convenience macro for
1082this:
1083
1084PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1085
1086This gives the exact same result as the above construction.
1087
1088
1089Runtime pinmuxing
1090=================
1091
1092It is possible to mux a certain function in and out at runtime, say to move
1093an SPI port from one set of pins to another set of pins. Say for example for
1094spi0 in the example above, we expose two different groups of pins for the same
1095function, but with different named in the mapping as described under
1096"Advanced mapping" above. So that for an SPI device, we have two states named
1097"pos-A" and "pos-B".
1098
1099This snippet first muxes the function in the pins defined by group A, enables
1100it, disables and releases it, and muxes it in on the pins defined by group B:
1101
1102#include <linux/pinctrl/consumer.h>
1103
1104struct pinctrl *p;
1105struct pinctrl_state *s1, *s2;
1106
1107foo_probe()
1108{
1109        /* Setup */
1110        p = devm_pinctrl_get(&device);
1111        if (IS_ERR(p))
1112                ...
1113
1114        s1 = pinctrl_lookup_state(foo->p, "pos-A");
1115        if (IS_ERR(s1))
1116                ...
1117
1118        s2 = pinctrl_lookup_state(foo->p, "pos-B");
1119        if (IS_ERR(s2))
1120                ...
1121}
1122
1123foo_switch()
1124{
1125        /* Enable on position A */
1126        ret = pinctrl_select_state(s1);
1127        if (ret < 0)
1128            ...
1129
1130        ...
1131
1132        /* Enable on position B */
1133        ret = pinctrl_select_state(s2);
1134        if (ret < 0)
1135            ...
1136
1137        ...
1138}
1139
1140The above has to be done from process context.
1141
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