1/* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14#ifndef LINUX_MMC_DW_MMC_H 15#define LINUX_MMC_DW_MMC_H 16 17#include <linux/scatterlist.h> 18 19#define MAX_MCI_SLOTS 2 20 21enum dw_mci_state { 22 STATE_IDLE = 0, 23 STATE_SENDING_CMD, 24 STATE_SENDING_DATA, 25 STATE_DATA_BUSY, 26 STATE_SENDING_STOP, 27 STATE_DATA_ERROR, 28}; 29 30enum { 31 EVENT_CMD_COMPLETE = 0, 32 EVENT_XFER_COMPLETE, 33 EVENT_DATA_COMPLETE, 34 EVENT_DATA_ERROR, 35 EVENT_XFER_ERROR 36}; 37 38struct mmc_data; 39 40/** 41 * struct dw_mci - MMC controller state shared between all slots 42 * @lock: Spinlock protecting the queue and associated data. 43 * @regs: Pointer to MMIO registers. 44 * @sg: Scatterlist entry currently being processed by PIO code, if any. 45 * @sg_miter: PIO mapping scatterlist iterator. 46 * @cur_slot: The slot which is currently using the controller. 47 * @mrq: The request currently being processed on @cur_slot, 48 * or NULL if the controller is idle. 49 * @cmd: The command currently being sent to the card, or NULL. 50 * @data: The data currently being transferred, or NULL if no data 51 * transfer is in progress. 52 * @use_dma: Whether DMA channel is initialized or not. 53 * @using_dma: Whether DMA is in use for the current transfer. 54 * @sg_dma: Bus address of DMA buffer. 55 * @sg_cpu: Virtual address of DMA buffer. 56 * @dma_ops: Pointer to platform-specific DMA callbacks. 57 * @cmd_status: Snapshot of SR taken upon completion of the current 58 * command. Only valid when EVENT_CMD_COMPLETE is pending. 59 * @data_status: Snapshot of SR taken upon completion of the current 60 * data transfer. Only valid when EVENT_DATA_COMPLETE or 61 * EVENT_DATA_ERROR is pending. 62 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 63 * to be sent. 64 * @dir_status: Direction of current transfer. 65 * @tasklet: Tasklet running the request state machine. 66 * @card_tasklet: Tasklet handling card detect. 67 * @pending_events: Bitmask of events flagged by the interrupt handler 68 * to be processed by the tasklet. 69 * @completed_events: Bitmask of events which the state machine has 70 * processed. 71 * @state: Tasklet state. 72 * @queue: List of slots waiting for access to the controller. 73 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 74 * rate and timeout calculations. 75 * @current_speed: Configured rate of the controller. 76 * @num_slots: Number of slots available. 77 * @verid: Denote Version ID. 78 * @data_offset: Set the offset of DATA register according to VERID. 79 * @pdev: Platform device associated with the MMC controller. 80 * @pdata: Platform data associated with the MMC controller. 81 * @slot: Slots sharing this MMC controller. 82 * @fifo_depth: depth of FIFO. 83 * @data_shift: log2 of FIFO item size. 84 * @part_buf_start: Start index in part_buf. 85 * @part_buf_count: Bytes of partial data in part_buf. 86 * @part_buf: Simple buffer for partial fifo reads/writes. 87 * @push_data: Pointer to FIFO push function. 88 * @pull_data: Pointer to FIFO pull function. 89 * @quirks: Set of quirks that apply to specific versions of the IP. 90 * 91 * Locking 92 * ======= 93 * 94 * @lock is a softirq-safe spinlock protecting @queue as well as 95 * @cur_slot, @mrq and @state. These must always be updated 96 * at the same time while holding @lock. 97 * 98 * The @mrq field of struct dw_mci_slot is also protected by @lock, 99 * and must always be written at the same time as the slot is added to 100 * @queue. 101 * 102 * @pending_events and @completed_events are accessed using atomic bit 103 * operations, so they don't need any locking. 104 * 105 * None of the fields touched by the interrupt handler need any 106 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 107 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 108 * interrupts must be disabled and @data_status updated with a 109 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 110 * CMDRDY interrupt must be disabled and @cmd_status updated with a 111 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 112 * bytes_xfered field of @data must be written. This is ensured by 113 * using barriers. 114 */ 115struct dw_mci { 116 spinlock_t lock; 117 void __iomem *regs; 118 119 struct scatterlist *sg; 120 struct sg_mapping_iter sg_miter; 121 122 struct dw_mci_slot *cur_slot; 123 struct mmc_request *mrq; 124 struct mmc_command *cmd; 125 struct mmc_data *data; 126 127 /* DMA interface members*/ 128 int use_dma; 129 int using_dma; 130 131 dma_addr_t sg_dma; 132 void *sg_cpu; 133 struct dw_mci_dma_ops *dma_ops; 134#ifdef CONFIG_MMC_DW_IDMAC 135 unsigned int ring_size; 136#else 137 struct dw_mci_dma_data *dma_data; 138#endif 139 u32 cmd_status; 140 u32 data_status; 141 u32 stop_cmdr; 142 u32 dir_status; 143 struct tasklet_struct tasklet; 144 struct work_struct card_work; 145 unsigned long pending_events; 146 unsigned long completed_events; 147 enum dw_mci_state state; 148 struct list_head queue; 149 150 u32 bus_hz; 151 u32 current_speed; 152 u32 num_slots; 153 u32 fifoth_val; 154 u16 verid; 155 u16 data_offset; 156 struct platform_device *pdev; 157 struct dw_mci_board *pdata; 158 struct dw_mci_slot *slot[MAX_MCI_SLOTS]; 159 160 /* FIFO push and pull */ 161 int fifo_depth; 162 int data_shift; 163 u8 part_buf_start; 164 u8 part_buf_count; 165 union { 166 u16 part_buf16; 167 u32 part_buf32; 168 u64 part_buf; 169 }; 170 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 171 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 172 173 /* Workaround flags */ 174 u32 quirks; 175 176 struct regulator *vmmc; /* Power regulator */ 177}; 178 179/* DMA ops for Internal/External DMAC interface */ 180struct dw_mci_dma_ops { 181 /* DMA Ops */ 182 int (*init)(struct dw_mci *host); 183 void (*start)(struct dw_mci *host, unsigned int sg_len); 184 void (*complete)(struct dw_mci *host); 185 void (*stop)(struct dw_mci *host); 186 void (*cleanup)(struct dw_mci *host); 187 void (*exit)(struct dw_mci *host); 188}; 189 190/* IP Quirks/flags. */ 191/* DTO fix for command transmission with IDMAC configured */ 192#define DW_MCI_QUIRK_IDMAC_DTO BIT(0) 193/* delay needed between retries on some 2.11a implementations */ 194#define DW_MCI_QUIRK_RETRY_DELAY BIT(1) 195/* High Speed Capable - Supports HS cards (up to 50MHz) */ 196#define DW_MCI_QUIRK_HIGHSPEED BIT(2) 197/* Unreliable card detection */ 198#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3) 199 200 201struct dma_pdata; 202 203struct block_settings { 204 unsigned short max_segs; /* see blk_queue_max_segments */ 205 unsigned int max_blk_size; /* maximum size of one mmc block */ 206 unsigned int max_blk_count; /* maximum number of blocks in one req*/ 207 unsigned int max_req_size; /* maximum number of bytes in one req*/ 208 unsigned int max_seg_size; /* see blk_queue_max_segment_size */ 209}; 210 211/* Board platform data */ 212struct dw_mci_board { 213 u32 num_slots; 214 215 u32 quirks; /* Workaround / Quirk flags */ 216 unsigned int bus_hz; /* Bus speed */ 217 218 unsigned int caps; /* Capabilities */ 219 unsigned int caps2; /* More capabilities */ 220 /* 221 * Override fifo depth. If 0, autodetect it from the FIFOTH register, 222 * but note that this may not be reliable after a bootloader has used 223 * it. 224 */ 225 unsigned int fifo_depth; 226 227 /* delay in mS before detecting cards after interrupt */ 228 u32 detect_delay_ms; 229 230 int (*init)(u32 slot_id, irq_handler_t , void *); 231 int (*get_ro)(u32 slot_id); 232 int (*get_cd)(u32 slot_id); 233 int (*get_ocr)(u32 slot_id); 234 int (*get_bus_wd)(u32 slot_id); 235 /* 236 * Enable power to selected slot and set voltage to desired level. 237 * Voltage levels are specified using MMC_VDD_xxx defines defined 238 * in linux/mmc/host.h file. 239 */ 240 void (*setpower)(u32 slot_id, u32 volt); 241 void (*exit)(u32 slot_id); 242 void (*select_slot)(u32 slot_id); 243 244 struct dw_mci_dma_ops *dma_ops; 245 struct dma_pdata *data; 246 struct block_settings *blk_settings; 247}; 248 249#endif /* LINUX_MMC_DW_MMC_H */ 250