1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2010 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_AGL_DEFS_H__ 29#define __CVMX_AGL_DEFS_H__ 30 31#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull)) 32#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull)) 33#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull)) 34#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull)) 35#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048) 36#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048) 37#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048) 38#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048) 39#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048) 40#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048) 41#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048) 42#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048) 43#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048) 44#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048) 45#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048) 46#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048) 47#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048) 48#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048) 49#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048) 50#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048) 51#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048) 52#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048) 53#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048) 54#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048) 55#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048) 56#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048) 57#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048) 58#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048) 59#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048) 60#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048) 61#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048) 62#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048) 63#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048) 64#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048) 65#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048) 66#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8) 67#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8) 68#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8) 69#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull)) 70#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull)) 71#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048) 72#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull)) 73#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048) 74#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048) 75#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048) 76#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048) 77#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048) 78#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048) 79#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048) 80#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048) 81#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048) 82#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048) 83#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048) 84#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048) 85#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048) 86#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048) 87#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048) 88#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048) 89#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048) 90#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048) 91#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048) 92#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048) 93#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048) 94#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull)) 95#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull)) 96#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull)) 97#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull)) 98#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull)) 99#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull)) 100#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull)) 101#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull)) 102#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull)) 103#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull)) 104#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8) 105 106union cvmx_agl_gmx_bad_reg { 107 uint64_t u64; 108 struct cvmx_agl_gmx_bad_reg_s { 109 uint64_t reserved_38_63:26; 110 uint64_t txpsh1:1; 111 uint64_t txpop1:1; 112 uint64_t ovrflw1:1; 113 uint64_t txpsh:1; 114 uint64_t txpop:1; 115 uint64_t ovrflw:1; 116 uint64_t reserved_27_31:5; 117 uint64_t statovr:1; 118 uint64_t reserved_24_25:2; 119 uint64_t loststat:2; 120 uint64_t reserved_4_21:18; 121 uint64_t out_ovr:2; 122 uint64_t reserved_0_1:2; 123 } s; 124 struct cvmx_agl_gmx_bad_reg_cn52xx { 125 uint64_t reserved_38_63:26; 126 uint64_t txpsh1:1; 127 uint64_t txpop1:1; 128 uint64_t ovrflw1:1; 129 uint64_t txpsh:1; 130 uint64_t txpop:1; 131 uint64_t ovrflw:1; 132 uint64_t reserved_27_31:5; 133 uint64_t statovr:1; 134 uint64_t reserved_23_25:3; 135 uint64_t loststat:1; 136 uint64_t reserved_4_21:18; 137 uint64_t out_ovr:2; 138 uint64_t reserved_0_1:2; 139 } cn52xx; 140 struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; 141 struct cvmx_agl_gmx_bad_reg_cn56xx { 142 uint64_t reserved_35_63:29; 143 uint64_t txpsh:1; 144 uint64_t txpop:1; 145 uint64_t ovrflw:1; 146 uint64_t reserved_27_31:5; 147 uint64_t statovr:1; 148 uint64_t reserved_23_25:3; 149 uint64_t loststat:1; 150 uint64_t reserved_3_21:19; 151 uint64_t out_ovr:1; 152 uint64_t reserved_0_1:2; 153 } cn56xx; 154 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 155 struct cvmx_agl_gmx_bad_reg_s cn63xx; 156 struct cvmx_agl_gmx_bad_reg_s cn63xxp1; 157}; 158 159union cvmx_agl_gmx_bist { 160 uint64_t u64; 161 struct cvmx_agl_gmx_bist_s { 162 uint64_t reserved_25_63:39; 163 uint64_t status:25; 164 } s; 165 struct cvmx_agl_gmx_bist_cn52xx { 166 uint64_t reserved_10_63:54; 167 uint64_t status:10; 168 } cn52xx; 169 struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; 170 struct cvmx_agl_gmx_bist_cn52xx cn56xx; 171 struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; 172 struct cvmx_agl_gmx_bist_s cn63xx; 173 struct cvmx_agl_gmx_bist_s cn63xxp1; 174}; 175 176union cvmx_agl_gmx_drv_ctl { 177 uint64_t u64; 178 struct cvmx_agl_gmx_drv_ctl_s { 179 uint64_t reserved_49_63:15; 180 uint64_t byp_en1:1; 181 uint64_t reserved_45_47:3; 182 uint64_t pctl1:5; 183 uint64_t reserved_37_39:3; 184 uint64_t nctl1:5; 185 uint64_t reserved_17_31:15; 186 uint64_t byp_en:1; 187 uint64_t reserved_13_15:3; 188 uint64_t pctl:5; 189 uint64_t reserved_5_7:3; 190 uint64_t nctl:5; 191 } s; 192 struct cvmx_agl_gmx_drv_ctl_s cn52xx; 193 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; 194 struct cvmx_agl_gmx_drv_ctl_cn56xx { 195 uint64_t reserved_17_63:47; 196 uint64_t byp_en:1; 197 uint64_t reserved_13_15:3; 198 uint64_t pctl:5; 199 uint64_t reserved_5_7:3; 200 uint64_t nctl:5; 201 } cn56xx; 202 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; 203}; 204 205union cvmx_agl_gmx_inf_mode { 206 uint64_t u64; 207 struct cvmx_agl_gmx_inf_mode_s { 208 uint64_t reserved_2_63:62; 209 uint64_t en:1; 210 uint64_t reserved_0_0:1; 211 } s; 212 struct cvmx_agl_gmx_inf_mode_s cn52xx; 213 struct cvmx_agl_gmx_inf_mode_s cn52xxp1; 214 struct cvmx_agl_gmx_inf_mode_s cn56xx; 215 struct cvmx_agl_gmx_inf_mode_s cn56xxp1; 216}; 217 218union cvmx_agl_gmx_prtx_cfg { 219 uint64_t u64; 220 struct cvmx_agl_gmx_prtx_cfg_s { 221 uint64_t reserved_14_63:50; 222 uint64_t tx_idle:1; 223 uint64_t rx_idle:1; 224 uint64_t reserved_9_11:3; 225 uint64_t speed_msb:1; 226 uint64_t reserved_7_7:1; 227 uint64_t burst:1; 228 uint64_t tx_en:1; 229 uint64_t rx_en:1; 230 uint64_t slottime:1; 231 uint64_t duplex:1; 232 uint64_t speed:1; 233 uint64_t en:1; 234 } s; 235 struct cvmx_agl_gmx_prtx_cfg_cn52xx { 236 uint64_t reserved_6_63:58; 237 uint64_t tx_en:1; 238 uint64_t rx_en:1; 239 uint64_t slottime:1; 240 uint64_t duplex:1; 241 uint64_t speed:1; 242 uint64_t en:1; 243 } cn52xx; 244 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; 245 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; 246 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; 247 struct cvmx_agl_gmx_prtx_cfg_s cn63xx; 248 struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; 249}; 250 251union cvmx_agl_gmx_rxx_adr_cam0 { 252 uint64_t u64; 253 struct cvmx_agl_gmx_rxx_adr_cam0_s { 254 uint64_t adr:64; 255 } s; 256 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; 257 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 258 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 259 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 260 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; 261 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; 262}; 263 264union cvmx_agl_gmx_rxx_adr_cam1 { 265 uint64_t u64; 266 struct cvmx_agl_gmx_rxx_adr_cam1_s { 267 uint64_t adr:64; 268 } s; 269 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; 270 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 271 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 272 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 273 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; 274 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; 275}; 276 277union cvmx_agl_gmx_rxx_adr_cam2 { 278 uint64_t u64; 279 struct cvmx_agl_gmx_rxx_adr_cam2_s { 280 uint64_t adr:64; 281 } s; 282 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; 283 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 284 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 285 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 286 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; 287 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; 288}; 289 290union cvmx_agl_gmx_rxx_adr_cam3 { 291 uint64_t u64; 292 struct cvmx_agl_gmx_rxx_adr_cam3_s { 293 uint64_t adr:64; 294 } s; 295 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; 296 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 297 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 298 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 299 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; 300 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; 301}; 302 303union cvmx_agl_gmx_rxx_adr_cam4 { 304 uint64_t u64; 305 struct cvmx_agl_gmx_rxx_adr_cam4_s { 306 uint64_t adr:64; 307 } s; 308 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; 309 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 310 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 311 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 312 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; 313 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; 314}; 315 316union cvmx_agl_gmx_rxx_adr_cam5 { 317 uint64_t u64; 318 struct cvmx_agl_gmx_rxx_adr_cam5_s { 319 uint64_t adr:64; 320 } s; 321 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; 322 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 323 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 324 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 325 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; 326 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; 327}; 328 329union cvmx_agl_gmx_rxx_adr_cam_en { 330 uint64_t u64; 331 struct cvmx_agl_gmx_rxx_adr_cam_en_s { 332 uint64_t reserved_8_63:56; 333 uint64_t en:8; 334 } s; 335 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; 336 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 337 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 338 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 339 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; 340 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; 341}; 342 343union cvmx_agl_gmx_rxx_adr_ctl { 344 uint64_t u64; 345 struct cvmx_agl_gmx_rxx_adr_ctl_s { 346 uint64_t reserved_4_63:60; 347 uint64_t cam_mode:1; 348 uint64_t mcst:2; 349 uint64_t bcst:1; 350 } s; 351 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; 352 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 353 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 354 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 355 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; 356 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; 357}; 358 359union cvmx_agl_gmx_rxx_decision { 360 uint64_t u64; 361 struct cvmx_agl_gmx_rxx_decision_s { 362 uint64_t reserved_5_63:59; 363 uint64_t cnt:5; 364 } s; 365 struct cvmx_agl_gmx_rxx_decision_s cn52xx; 366 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 367 struct cvmx_agl_gmx_rxx_decision_s cn56xx; 368 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 369 struct cvmx_agl_gmx_rxx_decision_s cn63xx; 370 struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; 371}; 372 373union cvmx_agl_gmx_rxx_frm_chk { 374 uint64_t u64; 375 struct cvmx_agl_gmx_rxx_frm_chk_s { 376 uint64_t reserved_10_63:54; 377 uint64_t niberr:1; 378 uint64_t skperr:1; 379 uint64_t rcverr:1; 380 uint64_t lenerr:1; 381 uint64_t alnerr:1; 382 uint64_t fcserr:1; 383 uint64_t jabber:1; 384 uint64_t maxerr:1; 385 uint64_t carext:1; 386 uint64_t minerr:1; 387 } s; 388 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { 389 uint64_t reserved_9_63:55; 390 uint64_t skperr:1; 391 uint64_t rcverr:1; 392 uint64_t lenerr:1; 393 uint64_t alnerr:1; 394 uint64_t fcserr:1; 395 uint64_t jabber:1; 396 uint64_t maxerr:1; 397 uint64_t reserved_1_1:1; 398 uint64_t minerr:1; 399 } cn52xx; 400 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; 401 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; 402 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; 403 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; 404 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; 405}; 406 407union cvmx_agl_gmx_rxx_frm_ctl { 408 uint64_t u64; 409 struct cvmx_agl_gmx_rxx_frm_ctl_s { 410 uint64_t reserved_13_63:51; 411 uint64_t ptp_mode:1; 412 uint64_t reserved_11_11:1; 413 uint64_t null_dis:1; 414 uint64_t pre_align:1; 415 uint64_t pad_len:1; 416 uint64_t vlan_len:1; 417 uint64_t pre_free:1; 418 uint64_t ctl_smac:1; 419 uint64_t ctl_mcst:1; 420 uint64_t ctl_bck:1; 421 uint64_t ctl_drp:1; 422 uint64_t pre_strp:1; 423 uint64_t pre_chk:1; 424 } s; 425 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { 426 uint64_t reserved_10_63:54; 427 uint64_t pre_align:1; 428 uint64_t pad_len:1; 429 uint64_t vlan_len:1; 430 uint64_t pre_free:1; 431 uint64_t ctl_smac:1; 432 uint64_t ctl_mcst:1; 433 uint64_t ctl_bck:1; 434 uint64_t ctl_drp:1; 435 uint64_t pre_strp:1; 436 uint64_t pre_chk:1; 437 } cn52xx; 438 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; 439 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; 440 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; 441 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; 442 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; 443}; 444 445union cvmx_agl_gmx_rxx_frm_max { 446 uint64_t u64; 447 struct cvmx_agl_gmx_rxx_frm_max_s { 448 uint64_t reserved_16_63:48; 449 uint64_t len:16; 450 } s; 451 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; 452 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 453 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 454 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 455 struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; 456 struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; 457}; 458 459union cvmx_agl_gmx_rxx_frm_min { 460 uint64_t u64; 461 struct cvmx_agl_gmx_rxx_frm_min_s { 462 uint64_t reserved_16_63:48; 463 uint64_t len:16; 464 } s; 465 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; 466 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 467 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 468 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 469 struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; 470 struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; 471}; 472 473union cvmx_agl_gmx_rxx_ifg { 474 uint64_t u64; 475 struct cvmx_agl_gmx_rxx_ifg_s { 476 uint64_t reserved_4_63:60; 477 uint64_t ifg:4; 478 } s; 479 struct cvmx_agl_gmx_rxx_ifg_s cn52xx; 480 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 481 struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 482 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 483 struct cvmx_agl_gmx_rxx_ifg_s cn63xx; 484 struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; 485}; 486 487union cvmx_agl_gmx_rxx_int_en { 488 uint64_t u64; 489 struct cvmx_agl_gmx_rxx_int_en_s { 490 uint64_t reserved_20_63:44; 491 uint64_t pause_drp:1; 492 uint64_t phy_dupx:1; 493 uint64_t phy_spd:1; 494 uint64_t phy_link:1; 495 uint64_t ifgerr:1; 496 uint64_t coldet:1; 497 uint64_t falerr:1; 498 uint64_t rsverr:1; 499 uint64_t pcterr:1; 500 uint64_t ovrerr:1; 501 uint64_t niberr:1; 502 uint64_t skperr:1; 503 uint64_t rcverr:1; 504 uint64_t lenerr:1; 505 uint64_t alnerr:1; 506 uint64_t fcserr:1; 507 uint64_t jabber:1; 508 uint64_t maxerr:1; 509 uint64_t carext:1; 510 uint64_t minerr:1; 511 } s; 512 struct cvmx_agl_gmx_rxx_int_en_cn52xx { 513 uint64_t reserved_20_63:44; 514 uint64_t pause_drp:1; 515 uint64_t reserved_16_18:3; 516 uint64_t ifgerr:1; 517 uint64_t coldet:1; 518 uint64_t falerr:1; 519 uint64_t rsverr:1; 520 uint64_t pcterr:1; 521 uint64_t ovrerr:1; 522 uint64_t reserved_9_9:1; 523 uint64_t skperr:1; 524 uint64_t rcverr:1; 525 uint64_t lenerr:1; 526 uint64_t alnerr:1; 527 uint64_t fcserr:1; 528 uint64_t jabber:1; 529 uint64_t maxerr:1; 530 uint64_t reserved_1_1:1; 531 uint64_t minerr:1; 532 } cn52xx; 533 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; 534 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; 535 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; 536 struct cvmx_agl_gmx_rxx_int_en_s cn63xx; 537 struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; 538}; 539 540union cvmx_agl_gmx_rxx_int_reg { 541 uint64_t u64; 542 struct cvmx_agl_gmx_rxx_int_reg_s { 543 uint64_t reserved_20_63:44; 544 uint64_t pause_drp:1; 545 uint64_t phy_dupx:1; 546 uint64_t phy_spd:1; 547 uint64_t phy_link:1; 548 uint64_t ifgerr:1; 549 uint64_t coldet:1; 550 uint64_t falerr:1; 551 uint64_t rsverr:1; 552 uint64_t pcterr:1; 553 uint64_t ovrerr:1; 554 uint64_t niberr:1; 555 uint64_t skperr:1; 556 uint64_t rcverr:1; 557 uint64_t lenerr:1; 558 uint64_t alnerr:1; 559 uint64_t fcserr:1; 560 uint64_t jabber:1; 561 uint64_t maxerr:1; 562 uint64_t carext:1; 563 uint64_t minerr:1; 564 } s; 565 struct cvmx_agl_gmx_rxx_int_reg_cn52xx { 566 uint64_t reserved_20_63:44; 567 uint64_t pause_drp:1; 568 uint64_t reserved_16_18:3; 569 uint64_t ifgerr:1; 570 uint64_t coldet:1; 571 uint64_t falerr:1; 572 uint64_t rsverr:1; 573 uint64_t pcterr:1; 574 uint64_t ovrerr:1; 575 uint64_t reserved_9_9:1; 576 uint64_t skperr:1; 577 uint64_t rcverr:1; 578 uint64_t lenerr:1; 579 uint64_t alnerr:1; 580 uint64_t fcserr:1; 581 uint64_t jabber:1; 582 uint64_t maxerr:1; 583 uint64_t reserved_1_1:1; 584 uint64_t minerr:1; 585 } cn52xx; 586 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; 587 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; 588 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; 589 struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; 590 struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; 591}; 592 593union cvmx_agl_gmx_rxx_jabber { 594 uint64_t u64; 595 struct cvmx_agl_gmx_rxx_jabber_s { 596 uint64_t reserved_16_63:48; 597 uint64_t cnt:16; 598 } s; 599 struct cvmx_agl_gmx_rxx_jabber_s cn52xx; 600 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 601 struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 602 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 603 struct cvmx_agl_gmx_rxx_jabber_s cn63xx; 604 struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; 605}; 606 607union cvmx_agl_gmx_rxx_pause_drop_time { 608 uint64_t u64; 609 struct cvmx_agl_gmx_rxx_pause_drop_time_s { 610 uint64_t reserved_16_63:48; 611 uint64_t status:16; 612 } s; 613 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; 614 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 615 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 616 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 617 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; 618 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; 619}; 620 621union cvmx_agl_gmx_rxx_rx_inbnd { 622 uint64_t u64; 623 struct cvmx_agl_gmx_rxx_rx_inbnd_s { 624 uint64_t reserved_4_63:60; 625 uint64_t duplex:1; 626 uint64_t speed:2; 627 uint64_t status:1; 628 } s; 629 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; 630 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; 631}; 632 633union cvmx_agl_gmx_rxx_stats_ctl { 634 uint64_t u64; 635 struct cvmx_agl_gmx_rxx_stats_ctl_s { 636 uint64_t reserved_1_63:63; 637 uint64_t rd_clr:1; 638 } s; 639 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; 640 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 641 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 642 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 643 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; 644 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; 645}; 646 647union cvmx_agl_gmx_rxx_stats_octs { 648 uint64_t u64; 649 struct cvmx_agl_gmx_rxx_stats_octs_s { 650 uint64_t reserved_48_63:16; 651 uint64_t cnt:48; 652 } s; 653 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; 654 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 655 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 656 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 657 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; 658 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; 659}; 660 661union cvmx_agl_gmx_rxx_stats_octs_ctl { 662 uint64_t u64; 663 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { 664 uint64_t reserved_48_63:16; 665 uint64_t cnt:48; 666 } s; 667 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; 668 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 669 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 670 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 671 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; 672 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; 673}; 674 675union cvmx_agl_gmx_rxx_stats_octs_dmac { 676 uint64_t u64; 677 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { 678 uint64_t reserved_48_63:16; 679 uint64_t cnt:48; 680 } s; 681 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; 682 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 683 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 684 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 685 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; 686 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; 687}; 688 689union cvmx_agl_gmx_rxx_stats_octs_drp { 690 uint64_t u64; 691 struct cvmx_agl_gmx_rxx_stats_octs_drp_s { 692 uint64_t reserved_48_63:16; 693 uint64_t cnt:48; 694 } s; 695 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; 696 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 697 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 698 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 699 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; 700 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; 701}; 702 703union cvmx_agl_gmx_rxx_stats_pkts { 704 uint64_t u64; 705 struct cvmx_agl_gmx_rxx_stats_pkts_s { 706 uint64_t reserved_32_63:32; 707 uint64_t cnt:32; 708 } s; 709 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; 710 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 711 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 712 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 713 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; 714 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; 715}; 716 717union cvmx_agl_gmx_rxx_stats_pkts_bad { 718 uint64_t u64; 719 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { 720 uint64_t reserved_32_63:32; 721 uint64_t cnt:32; 722 } s; 723 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; 724 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 725 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 726 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 727 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; 728 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; 729}; 730 731union cvmx_agl_gmx_rxx_stats_pkts_ctl { 732 uint64_t u64; 733 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { 734 uint64_t reserved_32_63:32; 735 uint64_t cnt:32; 736 } s; 737 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; 738 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 739 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 740 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 741 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; 742 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; 743}; 744 745union cvmx_agl_gmx_rxx_stats_pkts_dmac { 746 uint64_t u64; 747 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { 748 uint64_t reserved_32_63:32; 749 uint64_t cnt:32; 750 } s; 751 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; 752 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 753 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 754 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 755 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; 756 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; 757}; 758 759union cvmx_agl_gmx_rxx_stats_pkts_drp { 760 uint64_t u64; 761 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { 762 uint64_t reserved_32_63:32; 763 uint64_t cnt:32; 764 } s; 765 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; 766 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 767 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 768 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 769 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; 770 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; 771}; 772 773union cvmx_agl_gmx_rxx_udd_skp { 774 uint64_t u64; 775 struct cvmx_agl_gmx_rxx_udd_skp_s { 776 uint64_t reserved_9_63:55; 777 uint64_t fcssel:1; 778 uint64_t reserved_7_7:1; 779 uint64_t len:7; 780 } s; 781 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; 782 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 783 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 784 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 785 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; 786 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; 787}; 788 789union cvmx_agl_gmx_rx_bp_dropx { 790 uint64_t u64; 791 struct cvmx_agl_gmx_rx_bp_dropx_s { 792 uint64_t reserved_6_63:58; 793 uint64_t mark:6; 794 } s; 795 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; 796 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 797 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 798 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 799 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; 800 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; 801}; 802 803union cvmx_agl_gmx_rx_bp_offx { 804 uint64_t u64; 805 struct cvmx_agl_gmx_rx_bp_offx_s { 806 uint64_t reserved_6_63:58; 807 uint64_t mark:6; 808 } s; 809 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; 810 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 811 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 812 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 813 struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; 814 struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; 815}; 816 817union cvmx_agl_gmx_rx_bp_onx { 818 uint64_t u64; 819 struct cvmx_agl_gmx_rx_bp_onx_s { 820 uint64_t reserved_9_63:55; 821 uint64_t mark:9; 822 } s; 823 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; 824 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 825 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 826 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 827 struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; 828 struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; 829}; 830 831union cvmx_agl_gmx_rx_prt_info { 832 uint64_t u64; 833 struct cvmx_agl_gmx_rx_prt_info_s { 834 uint64_t reserved_18_63:46; 835 uint64_t drop:2; 836 uint64_t reserved_2_15:14; 837 uint64_t commit:2; 838 } s; 839 struct cvmx_agl_gmx_rx_prt_info_s cn52xx; 840 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; 841 struct cvmx_agl_gmx_rx_prt_info_cn56xx { 842 uint64_t reserved_17_63:47; 843 uint64_t drop:1; 844 uint64_t reserved_1_15:15; 845 uint64_t commit:1; 846 } cn56xx; 847 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 848 struct cvmx_agl_gmx_rx_prt_info_s cn63xx; 849 struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; 850}; 851 852union cvmx_agl_gmx_rx_tx_status { 853 uint64_t u64; 854 struct cvmx_agl_gmx_rx_tx_status_s { 855 uint64_t reserved_6_63:58; 856 uint64_t tx:2; 857 uint64_t reserved_2_3:2; 858 uint64_t rx:2; 859 } s; 860 struct cvmx_agl_gmx_rx_tx_status_s cn52xx; 861 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; 862 struct cvmx_agl_gmx_rx_tx_status_cn56xx { 863 uint64_t reserved_5_63:59; 864 uint64_t tx:1; 865 uint64_t reserved_1_3:3; 866 uint64_t rx:1; 867 } cn56xx; 868 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 869 struct cvmx_agl_gmx_rx_tx_status_s cn63xx; 870 struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; 871}; 872 873union cvmx_agl_gmx_smacx { 874 uint64_t u64; 875 struct cvmx_agl_gmx_smacx_s { 876 uint64_t reserved_48_63:16; 877 uint64_t smac:48; 878 } s; 879 struct cvmx_agl_gmx_smacx_s cn52xx; 880 struct cvmx_agl_gmx_smacx_s cn52xxp1; 881 struct cvmx_agl_gmx_smacx_s cn56xx; 882 struct cvmx_agl_gmx_smacx_s cn56xxp1; 883 struct cvmx_agl_gmx_smacx_s cn63xx; 884 struct cvmx_agl_gmx_smacx_s cn63xxp1; 885}; 886 887union cvmx_agl_gmx_stat_bp { 888 uint64_t u64; 889 struct cvmx_agl_gmx_stat_bp_s { 890 uint64_t reserved_17_63:47; 891 uint64_t bp:1; 892 uint64_t cnt:16; 893 } s; 894 struct cvmx_agl_gmx_stat_bp_s cn52xx; 895 struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 896 struct cvmx_agl_gmx_stat_bp_s cn56xx; 897 struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 898 struct cvmx_agl_gmx_stat_bp_s cn63xx; 899 struct cvmx_agl_gmx_stat_bp_s cn63xxp1; 900}; 901 902union cvmx_agl_gmx_txx_append { 903 uint64_t u64; 904 struct cvmx_agl_gmx_txx_append_s { 905 uint64_t reserved_4_63:60; 906 uint64_t force_fcs:1; 907 uint64_t fcs:1; 908 uint64_t pad:1; 909 uint64_t preamble:1; 910 } s; 911 struct cvmx_agl_gmx_txx_append_s cn52xx; 912 struct cvmx_agl_gmx_txx_append_s cn52xxp1; 913 struct cvmx_agl_gmx_txx_append_s cn56xx; 914 struct cvmx_agl_gmx_txx_append_s cn56xxp1; 915 struct cvmx_agl_gmx_txx_append_s cn63xx; 916 struct cvmx_agl_gmx_txx_append_s cn63xxp1; 917}; 918 919union cvmx_agl_gmx_txx_clk { 920 uint64_t u64; 921 struct cvmx_agl_gmx_txx_clk_s { 922 uint64_t reserved_6_63:58; 923 uint64_t clk_cnt:6; 924 } s; 925 struct cvmx_agl_gmx_txx_clk_s cn63xx; 926 struct cvmx_agl_gmx_txx_clk_s cn63xxp1; 927}; 928 929union cvmx_agl_gmx_txx_ctl { 930 uint64_t u64; 931 struct cvmx_agl_gmx_txx_ctl_s { 932 uint64_t reserved_2_63:62; 933 uint64_t xsdef_en:1; 934 uint64_t xscol_en:1; 935 } s; 936 struct cvmx_agl_gmx_txx_ctl_s cn52xx; 937 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 938 struct cvmx_agl_gmx_txx_ctl_s cn56xx; 939 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 940 struct cvmx_agl_gmx_txx_ctl_s cn63xx; 941 struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; 942}; 943 944union cvmx_agl_gmx_txx_min_pkt { 945 uint64_t u64; 946 struct cvmx_agl_gmx_txx_min_pkt_s { 947 uint64_t reserved_8_63:56; 948 uint64_t min_size:8; 949 } s; 950 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; 951 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 952 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 953 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 954 struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; 955 struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; 956}; 957 958union cvmx_agl_gmx_txx_pause_pkt_interval { 959 uint64_t u64; 960 struct cvmx_agl_gmx_txx_pause_pkt_interval_s { 961 uint64_t reserved_16_63:48; 962 uint64_t interval:16; 963 } s; 964 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; 965 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 966 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 967 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 968 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; 969 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; 970}; 971 972union cvmx_agl_gmx_txx_pause_pkt_time { 973 uint64_t u64; 974 struct cvmx_agl_gmx_txx_pause_pkt_time_s { 975 uint64_t reserved_16_63:48; 976 uint64_t time:16; 977 } s; 978 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; 979 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 980 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 981 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 982 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; 983 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; 984}; 985 986union cvmx_agl_gmx_txx_pause_togo { 987 uint64_t u64; 988 struct cvmx_agl_gmx_txx_pause_togo_s { 989 uint64_t reserved_16_63:48; 990 uint64_t time:16; 991 } s; 992 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; 993 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 994 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 995 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 996 struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; 997 struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; 998}; 999 1000union cvmx_agl_gmx_txx_pause_zero {
1001 uint64_t u64; 1002 struct cvmx_agl_gmx_txx_pause_zero_s { 1003 uint64_t reserved_1_63:63; 1004 uint64_t send:1; 1005 } s; 1006 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; 1007 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 1008 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 1009 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 1010 struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; 1011 struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; 1012}; 1013 1014union cvmx_agl_gmx_txx_soft_pause { 1015 uint64_t u64; 1016 struct cvmx_agl_gmx_txx_soft_pause_s { 1017 uint64_t reserved_16_63:48; 1018 uint64_t time:16; 1019 } s; 1020 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; 1021 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 1022 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 1023 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 1024 struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; 1025 struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; 1026}; 1027 1028union cvmx_agl_gmx_txx_stat0 { 1029 uint64_t u64; 1030 struct cvmx_agl_gmx_txx_stat0_s { 1031 uint64_t xsdef:32; 1032 uint64_t xscol:32; 1033 } s; 1034 struct cvmx_agl_gmx_txx_stat0_s cn52xx; 1035 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 1036 struct cvmx_agl_gmx_txx_stat0_s cn56xx; 1037 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 1038 struct cvmx_agl_gmx_txx_stat0_s cn63xx; 1039 struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; 1040}; 1041 1042union cvmx_agl_gmx_txx_stat1 { 1043 uint64_t u64; 1044 struct cvmx_agl_gmx_txx_stat1_s { 1045 uint64_t scol:32; 1046 uint64_t mcol:32; 1047 } s; 1048 struct cvmx_agl_gmx_txx_stat1_s cn52xx; 1049 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 1050 struct cvmx_agl_gmx_txx_stat1_s cn56xx; 1051 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 1052 struct cvmx_agl_gmx_txx_stat1_s cn63xx; 1053 struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; 1054}; 1055 1056union cvmx_agl_gmx_txx_stat2 { 1057 uint64_t u64; 1058 struct cvmx_agl_gmx_txx_stat2_s { 1059 uint64_t reserved_48_63:16; 1060 uint64_t octs:48; 1061 } s; 1062 struct cvmx_agl_gmx_txx_stat2_s cn52xx; 1063 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 1064 struct cvmx_agl_gmx_txx_stat2_s cn56xx; 1065 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 1066 struct cvmx_agl_gmx_txx_stat2_s cn63xx; 1067 struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; 1068}; 1069 1070union cvmx_agl_gmx_txx_stat3 { 1071 uint64_t u64; 1072 struct cvmx_agl_gmx_txx_stat3_s { 1073 uint64_t reserved_32_63:32; 1074 uint64_t pkts:32; 1075 } s; 1076 struct cvmx_agl_gmx_txx_stat3_s cn52xx; 1077 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 1078 struct cvmx_agl_gmx_txx_stat3_s cn56xx; 1079 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 1080 struct cvmx_agl_gmx_txx_stat3_s cn63xx; 1081 struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; 1082}; 1083 1084union cvmx_agl_gmx_txx_stat4 { 1085 uint64_t u64; 1086 struct cvmx_agl_gmx_txx_stat4_s { 1087 uint64_t hist1:32; 1088 uint64_t hist0:32; 1089 } s; 1090 struct cvmx_agl_gmx_txx_stat4_s cn52xx; 1091 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 1092 struct cvmx_agl_gmx_txx_stat4_s cn56xx; 1093 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 1094 struct cvmx_agl_gmx_txx_stat4_s cn63xx; 1095 struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; 1096}; 1097 1098union cvmx_agl_gmx_txx_stat5 { 1099 uint64_t u64; 1100 struct cvmx_agl_gmx_txx_stat5_s { 1101 uint64_t hist3:32; 1102 uint64_t hist2:32; 1103 } s; 1104 struct cvmx_agl_gmx_txx_stat5_s cn52xx; 1105 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 1106 struct cvmx_agl_gmx_txx_stat5_s cn56xx; 1107 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 1108 struct cvmx_agl_gmx_txx_stat5_s cn63xx; 1109 struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; 1110}; 1111 1112union cvmx_agl_gmx_txx_stat6 { 1113 uint64_t u64; 1114 struct cvmx_agl_gmx_txx_stat6_s { 1115 uint64_t hist5:32; 1116 uint64_t hist4:32; 1117 } s; 1118 struct cvmx_agl_gmx_txx_stat6_s cn52xx; 1119 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 1120 struct cvmx_agl_gmx_txx_stat6_s cn56xx; 1121 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 1122 struct cvmx_agl_gmx_txx_stat6_s cn63xx; 1123 struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; 1124}; 1125 1126union cvmx_agl_gmx_txx_stat7 { 1127 uint64_t u64; 1128 struct cvmx_agl_gmx_txx_stat7_s { 1129 uint64_t hist7:32; 1130 uint64_t hist6:32; 1131 } s; 1132 struct cvmx_agl_gmx_txx_stat7_s cn52xx; 1133 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 1134 struct cvmx_agl_gmx_txx_stat7_s cn56xx; 1135 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 1136 struct cvmx_agl_gmx_txx_stat7_s cn63xx; 1137 struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; 1138}; 1139 1140union cvmx_agl_gmx_txx_stat8 { 1141 uint64_t u64; 1142 struct cvmx_agl_gmx_txx_stat8_s { 1143 uint64_t mcst:32; 1144 uint64_t bcst:32; 1145 } s; 1146 struct cvmx_agl_gmx_txx_stat8_s cn52xx; 1147 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 1148 struct cvmx_agl_gmx_txx_stat8_s cn56xx; 1149 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 1150 struct cvmx_agl_gmx_txx_stat8_s cn63xx; 1151 struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; 1152}; 1153 1154union cvmx_agl_gmx_txx_stat9 { 1155 uint64_t u64; 1156 struct cvmx_agl_gmx_txx_stat9_s { 1157 uint64_t undflw:32; 1158 uint64_t ctl:32; 1159 } s; 1160 struct cvmx_agl_gmx_txx_stat9_s cn52xx; 1161 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 1162 struct cvmx_agl_gmx_txx_stat9_s cn56xx; 1163 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 1164 struct cvmx_agl_gmx_txx_stat9_s cn63xx; 1165 struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; 1166}; 1167 1168union cvmx_agl_gmx_txx_stats_ctl { 1169 uint64_t u64; 1170 struct cvmx_agl_gmx_txx_stats_ctl_s { 1171 uint64_t reserved_1_63:63; 1172 uint64_t rd_clr:1; 1173 } s; 1174 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; 1175 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 1176 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 1177 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 1178 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; 1179 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; 1180}; 1181 1182union cvmx_agl_gmx_txx_thresh { 1183 uint64_t u64; 1184 struct cvmx_agl_gmx_txx_thresh_s { 1185 uint64_t reserved_6_63:58; 1186 uint64_t cnt:6; 1187 } s; 1188 struct cvmx_agl_gmx_txx_thresh_s cn52xx; 1189 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 1190 struct cvmx_agl_gmx_txx_thresh_s cn56xx; 1191 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 1192 struct cvmx_agl_gmx_txx_thresh_s cn63xx; 1193 struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; 1194}; 1195 1196union cvmx_agl_gmx_tx_bp { 1197 uint64_t u64; 1198 struct cvmx_agl_gmx_tx_bp_s { 1199 uint64_t reserved_2_63:62; 1200 uint64_t bp:2; 1201 } s; 1202 struct cvmx_agl_gmx_tx_bp_s cn52xx; 1203 struct cvmx_agl_gmx_tx_bp_s cn52xxp1; 1204 struct cvmx_agl_gmx_tx_bp_cn56xx { 1205 uint64_t reserved_1_63:63; 1206 uint64_t bp:1; 1207 } cn56xx; 1208 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 1209 struct cvmx_agl_gmx_tx_bp_s cn63xx; 1210 struct cvmx_agl_gmx_tx_bp_s cn63xxp1; 1211}; 1212 1213union cvmx_agl_gmx_tx_col_attempt { 1214 uint64_t u64; 1215 struct cvmx_agl_gmx_tx_col_attempt_s { 1216 uint64_t reserved_5_63:59; 1217 uint64_t limit:5; 1218 } s; 1219 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; 1220 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 1221 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 1222 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 1223 struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; 1224 struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; 1225}; 1226 1227union cvmx_agl_gmx_tx_ifg { 1228 uint64_t u64; 1229 struct cvmx_agl_gmx_tx_ifg_s { 1230 uint64_t reserved_8_63:56; 1231 uint64_t ifg2:4; 1232 uint64_t ifg1:4; 1233 } s; 1234 struct cvmx_agl_gmx_tx_ifg_s cn52xx; 1235 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 1236 struct cvmx_agl_gmx_tx_ifg_s cn56xx; 1237 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 1238 struct cvmx_agl_gmx_tx_ifg_s cn63xx; 1239 struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; 1240}; 1241 1242union cvmx_agl_gmx_tx_int_en { 1243 uint64_t u64; 1244 struct cvmx_agl_gmx_tx_int_en_s { 1245 uint64_t reserved_22_63:42; 1246 uint64_t ptp_lost:2; 1247 uint64_t reserved_18_19:2; 1248 uint64_t late_col:2; 1249 uint64_t reserved_14_15:2; 1250 uint64_t xsdef:2; 1251 uint64_t reserved_10_11:2; 1252 uint64_t xscol:2; 1253 uint64_t reserved_4_7:4; 1254 uint64_t undflw:2; 1255 uint64_t reserved_1_1:1; 1256 uint64_t pko_nxa:1; 1257 } s; 1258 struct cvmx_agl_gmx_tx_int_en_cn52xx { 1259 uint64_t reserved_18_63:46; 1260 uint64_t late_col:2; 1261 uint64_t reserved_14_15:2; 1262 uint64_t xsdef:2; 1263 uint64_t reserved_10_11:2; 1264 uint64_t xscol:2; 1265 uint64_t reserved_4_7:4; 1266 uint64_t undflw:2; 1267 uint64_t reserved_1_1:1; 1268 uint64_t pko_nxa:1; 1269 } cn52xx; 1270 struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; 1271 struct cvmx_agl_gmx_tx_int_en_cn56xx { 1272 uint64_t reserved_17_63:47; 1273 uint64_t late_col:1; 1274 uint64_t reserved_13_15:3; 1275 uint64_t xsdef:1; 1276 uint64_t reserved_9_11:3; 1277 uint64_t xscol:1; 1278 uint64_t reserved_3_7:5; 1279 uint64_t undflw:1; 1280 uint64_t reserved_1_1:1; 1281 uint64_t pko_nxa:1; 1282 } cn56xx; 1283 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 1284 struct cvmx_agl_gmx_tx_int_en_s cn63xx; 1285 struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; 1286}; 1287 1288union cvmx_agl_gmx_tx_int_reg { 1289 uint64_t u64; 1290 struct cvmx_agl_gmx_tx_int_reg_s { 1291 uint64_t reserved_22_63:42; 1292 uint64_t ptp_lost:2; 1293 uint64_t reserved_18_19:2; 1294 uint64_t late_col:2; 1295 uint64_t reserved_14_15:2; 1296 uint64_t xsdef:2; 1297 uint64_t reserved_10_11:2; 1298 uint64_t xscol:2; 1299 uint64_t reserved_4_7:4; 1300 uint64_t undflw:2; 1301 uint64_t reserved_1_1:1; 1302 uint64_t pko_nxa:1; 1303 } s; 1304 struct cvmx_agl_gmx_tx_int_reg_cn52xx { 1305 uint64_t reserved_18_63:46; 1306 uint64_t late_col:2; 1307 uint64_t reserved_14_15:2; 1308 uint64_t xsdef:2; 1309 uint64_t reserved_10_11:2; 1310 uint64_t xscol:2; 1311 uint64_t reserved_4_7:4; 1312 uint64_t undflw:2; 1313 uint64_t reserved_1_1:1; 1314 uint64_t pko_nxa:1; 1315 } cn52xx; 1316 struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; 1317 struct cvmx_agl_gmx_tx_int_reg_cn56xx { 1318 uint64_t reserved_17_63:47; 1319 uint64_t late_col:1; 1320 uint64_t reserved_13_15:3; 1321 uint64_t xsdef:1; 1322 uint64_t reserved_9_11:3; 1323 uint64_t xscol:1; 1324 uint64_t reserved_3_7:5; 1325 uint64_t undflw:1; 1326 uint64_t reserved_1_1:1; 1327 uint64_t pko_nxa:1; 1328 } cn56xx; 1329 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 1330 struct cvmx_agl_gmx_tx_int_reg_s cn63xx; 1331 struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; 1332}; 1333 1334union cvmx_agl_gmx_tx_jam { 1335 uint64_t u64; 1336 struct cvmx_agl_gmx_tx_jam_s { 1337 uint64_t reserved_8_63:56; 1338 uint64_t jam:8; 1339 } s; 1340 struct cvmx_agl_gmx_tx_jam_s cn52xx; 1341 struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 1342 struct cvmx_agl_gmx_tx_jam_s cn56xx; 1343 struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 1344 struct cvmx_agl_gmx_tx_jam_s cn63xx; 1345 struct cvmx_agl_gmx_tx_jam_s cn63xxp1; 1346}; 1347 1348union cvmx_agl_gmx_tx_lfsr { 1349 uint64_t u64; 1350 struct cvmx_agl_gmx_tx_lfsr_s { 1351 uint64_t reserved_16_63:48; 1352 uint64_t lfsr:16; 1353 } s; 1354 struct cvmx_agl_gmx_tx_lfsr_s cn52xx; 1355 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 1356 struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 1357 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 1358 struct cvmx_agl_gmx_tx_lfsr_s cn63xx; 1359 struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; 1360}; 1361 1362union cvmx_agl_gmx_tx_ovr_bp { 1363 uint64_t u64; 1364 struct cvmx_agl_gmx_tx_ovr_bp_s { 1365 uint64_t reserved_10_63:54; 1366 uint64_t en:2; 1367 uint64_t reserved_6_7:2; 1368 uint64_t bp:2; 1369 uint64_t reserved_2_3:2; 1370 uint64_t ign_full:2; 1371 } s; 1372 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; 1373 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; 1374 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { 1375 uint64_t reserved_9_63:55; 1376 uint64_t en:1; 1377 uint64_t reserved_5_7:3; 1378 uint64_t bp:1; 1379 uint64_t reserved_1_3:3; 1380 uint64_t ign_full:1; 1381 } cn56xx; 1382 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 1383 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; 1384 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; 1385}; 1386 1387union cvmx_agl_gmx_tx_pause_pkt_dmac { 1388 uint64_t u64; 1389 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { 1390 uint64_t reserved_48_63:16; 1391 uint64_t dmac:48; 1392 } s; 1393 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; 1394 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 1395 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 1396 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 1397 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; 1398 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; 1399}; 1400 1401union cvmx_agl_gmx_tx_pause_pkt_type { 1402 uint64_t u64; 1403 struct cvmx_agl_gmx_tx_pause_pkt_type_s { 1404 uint64_t reserved_16_63:48; 1405 uint64_t type:16; 1406 } s; 1407 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; 1408 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 1409 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 1410 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 1411 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; 1412 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; 1413}; 1414 1415union cvmx_agl_prtx_ctl { 1416 uint64_t u64; 1417 struct cvmx_agl_prtx_ctl_s { 1418 uint64_t drv_byp:1; 1419 uint64_t reserved_62_62:1; 1420 uint64_t cmp_pctl:6; 1421 uint64_t reserved_54_55:2; 1422 uint64_t cmp_nctl:6; 1423 uint64_t reserved_46_47:2; 1424 uint64_t drv_pctl:6; 1425 uint64_t reserved_38_39:2; 1426 uint64_t drv_nctl:6; 1427 uint64_t reserved_29_31:3; 1428 uint64_t clk_set:5; 1429 uint64_t clkrx_byp:1; 1430 uint64_t reserved_21_22:2; 1431 uint64_t clkrx_set:5; 1432 uint64_t clktx_byp:1; 1433 uint64_t reserved_13_14:2; 1434 uint64_t clktx_set:5; 1435 uint64_t reserved_5_7:3; 1436 uint64_t dllrst:1; 1437 uint64_t comp:1; 1438 uint64_t enable:1; 1439 uint64_t clkrst:1; 1440 uint64_t mode:1; 1441 } s; 1442 struct cvmx_agl_prtx_ctl_s cn63xx; 1443 struct cvmx_agl_prtx_ctl_s cn63xxp1; 1444}; 1445 1446#endif 1447