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18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h>
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
42#include <linux/if.h>
43#include <linux/if_vlan.h>
44#include <net/ip.h>
45#include <net/ipv6.h>
46#include <net/tcp.h>
47#include <net/checksum.h>
48#include <net/ip6_checksum.h>
49#include <linux/workqueue.h>
50#include <linux/crc32.h>
51#include <linux/crc32c.h>
52#include <linux/prefetch.h>
53#include <linux/zlib.h>
54#include <linux/io.h>
55#include <linux/stringify.h>
56#include <linux/vmalloc.h>
57
58#include "bnx2x.h"
59#include "bnx2x_init.h"
60#include "bnx2x_init_ops.h"
61#include "bnx2x_cmn.h"
62#include "bnx2x_dcb.h"
63#include "bnx2x_sp.h"
64
65#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h"
67
68#define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77
78#define TX_TIMEOUT (5*HZ)
79
80static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
84MODULE_AUTHOR("Eliezer Tamir");
85MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_MODULE_VERSION);
91MODULE_FIRMWARE(FW_FILE_NAME_E1);
92MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93MODULE_FIRMWARE(FW_FILE_NAME_E2);
94
95static int multi_mode = 1;
96module_param(multi_mode, int, 0);
97MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
100int num_queues;
101module_param(num_queues, int, 0);
102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
104
105static int disable_tpa;
106module_param(disable_tpa, int, 0);
107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108
109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
111static int int_mode;
112module_param(int_mode, int, 0);
113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 "(1 INT#x; 2 MSI)");
115
116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
120static int mrrs = -1;
121module_param(mrrs, int, 0);
122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
124static int debug;
125module_param(debug, int, 0);
126MODULE_PARM_DESC(debug, " Default debug msglevel");
127
128
129
130struct workqueue_struct *bnx2x_wq;
131
132enum bnx2x_board_type {
133 BCM57710 = 0,
134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
138 BCM57800,
139 BCM57800_MF,
140 BCM57810,
141 BCM57810_MF,
142 BCM57840,
143 BCM57840_MF
144};
145
146
147static struct {
148 char *name;
149} board_info[] __devinitdata = {
150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
162};
163
164#ifndef PCI_DEVICE_ID_NX2_57710
165#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
166#endif
167#ifndef PCI_DEVICE_ID_NX2_57711
168#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
169#endif
170#ifndef PCI_DEVICE_ID_NX2_57711E
171#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
172#endif
173#ifndef PCI_DEVICE_ID_NX2_57712
174#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
175#endif
176#ifndef PCI_DEVICE_ID_NX2_57712_MF
177#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
178#endif
179#ifndef PCI_DEVICE_ID_NX2_57800
180#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
181#endif
182#ifndef PCI_DEVICE_ID_NX2_57800_MF
183#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
184#endif
185#ifndef PCI_DEVICE_ID_NX2_57810
186#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
187#endif
188#ifndef PCI_DEVICE_ID_NX2_57810_MF
189#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
190#endif
191#ifndef PCI_DEVICE_ID_NX2_57840
192#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
193#endif
194#ifndef PCI_DEVICE_ID_NX2_57840_MF
195#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
196#endif
197static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
209 { 0 }
210};
211
212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
213
214
215
216
217
218static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
219 u32 addr, dma_addr_t mapping)
220{
221 REG_WR(bp, addr, U64_LO(mapping));
222 REG_WR(bp, addr + 4, U64_HI(mapping));
223}
224
225static inline void storm_memset_spq_addr(struct bnx2x *bp,
226 dma_addr_t mapping, u16 abs_fid)
227{
228 u32 addr = XSEM_REG_FAST_MEMORY +
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
230
231 __storm_memset_dma_mapping(bp, addr, mapping);
232}
233
234static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
235 u16 pf_id)
236{
237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
238 pf_id);
239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
240 pf_id);
241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245}
246
247static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
248 u8 enable)
249{
250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
251 enable);
252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
253 enable);
254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258}
259
260static inline void storm_memset_eq_data(struct bnx2x *bp,
261 struct event_ring_data *eq_data,
262 u16 pfid)
263{
264 size_t size = sizeof(struct event_ring_data);
265
266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
269}
270
271static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
272 u16 pfid)
273{
274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
275 REG_WR16(bp, addr, eq_prod);
276}
277
278
279
280
281static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
282{
283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
286 PCICFG_VENDOR_ID_OFFSET);
287}
288
289static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
290{
291 u32 val;
292
293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
296 PCICFG_VENDOR_ID_OFFSET);
297
298 return val;
299}
300
301#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305#define DMAE_DP_DST_NONE "dst_addr [none]"
306
307static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
308 int msglvl)
309{
310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
311
312 switch (dmae->opcode & DMAE_COMMAND_DST) {
313 case DMAE_CMD_DST_PCI:
314 if (src_type == DMAE_CMD_SRC_PCI)
315 DP(msglvl, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
320 dmae->comp_addr_hi, dmae->comp_addr_lo,
321 dmae->comp_val);
322 else
323 DP(msglvl, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae->opcode, dmae->src_addr_lo >> 2,
327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
328 dmae->comp_addr_hi, dmae->comp_addr_lo,
329 dmae->comp_val);
330 break;
331 case DMAE_CMD_DST_GRC:
332 if (src_type == DMAE_CMD_SRC_PCI)
333 DP(msglvl, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
337 dmae->len, dmae->dst_addr_lo >> 2,
338 dmae->comp_addr_hi, dmae->comp_addr_lo,
339 dmae->comp_val);
340 else
341 DP(msglvl, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae->opcode, dmae->src_addr_lo >> 2,
345 dmae->len, dmae->dst_addr_lo >> 2,
346 dmae->comp_addr_hi, dmae->comp_addr_lo,
347 dmae->comp_val);
348 break;
349 default:
350 if (src_type == DMAE_CMD_SRC_PCI)
351 DP(msglvl, "DMAE: opcode 0x%08x\n"
352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
353 "comp_addr [%x:%08x] comp_val 0x%08x\n",
354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
356 dmae->comp_val);
357 else
358 DP(msglvl, "DMAE: opcode 0x%08x\n"
359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
360 "comp_addr [%x:%08x] comp_val 0x%08x\n",
361 dmae->opcode, dmae->src_addr_lo >> 2,
362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
363 dmae->comp_val);
364 break;
365 }
366
367}
368
369
370void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
371{
372 u32 cmd_offset;
373 int i;
374
375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
378
379 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
380 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
381 }
382 REG_WR(bp, dmae_reg_go_c[idx], 1);
383}
384
385u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
386{
387 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
388 DMAE_CMD_C_ENABLE);
389}
390
391u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
392{
393 return opcode & ~DMAE_CMD_SRC_RESET;
394}
395
396u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
397 bool with_comp, u8 comp_type)
398{
399 u32 opcode = 0;
400
401 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
402 (dst_type << DMAE_COMMAND_DST_SHIFT));
403
404 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
405
406 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
407 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
408 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
409 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
410
411#ifdef __BIG_ENDIAN
412 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
413#else
414 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
415#endif
416 if (with_comp)
417 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
418 return opcode;
419}
420
421static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
422 struct dmae_command *dmae,
423 u8 src_type, u8 dst_type)
424{
425 memset(dmae, 0, sizeof(struct dmae_command));
426
427
428 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
429 true, DMAE_COMP_PCI);
430
431
432 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
433 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
434 dmae->comp_val = DMAE_COMP_VAL;
435}
436
437
438static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
439 struct dmae_command *dmae)
440{
441 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
442 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
443 int rc = 0;
444
445 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
446 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
447 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
448
449
450
451
452
453
454 spin_lock_bh(&bp->dmae_lock);
455
456
457 *wb_comp = 0;
458
459
460 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
461
462
463 udelay(5);
464 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
465 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
466
467 if (!cnt) {
468 BNX2X_ERR("DMAE timeout!\n");
469 rc = DMAE_TIMEOUT;
470 goto unlock;
471 }
472 cnt--;
473 udelay(50);
474 }
475 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
476 BNX2X_ERR("DMAE PCI error!\n");
477 rc = DMAE_PCI_ERROR;
478 }
479
480 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
481 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
482 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
483
484unlock:
485 spin_unlock_bh(&bp->dmae_lock);
486 return rc;
487}
488
489void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
490 u32 len32)
491{
492 struct dmae_command dmae;
493
494 if (!bp->dmae_ready) {
495 u32 *data = bnx2x_sp(bp, wb_data[0]);
496
497 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
498 " using indirect\n", dst_addr, len32);
499 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
500 return;
501 }
502
503
504 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
505
506
507 dmae.src_addr_lo = U64_LO(dma_addr);
508 dmae.src_addr_hi = U64_HI(dma_addr);
509 dmae.dst_addr_lo = dst_addr >> 2;
510 dmae.dst_addr_hi = 0;
511 dmae.len = len32;
512
513 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
514
515
516 bnx2x_issue_dmae_with_comp(bp, &dmae);
517}
518
519void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
520{
521 struct dmae_command dmae;
522
523 if (!bp->dmae_ready) {
524 u32 *data = bnx2x_sp(bp, wb_data[0]);
525 int i;
526
527 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
528 " using indirect\n", src_addr, len32);
529 for (i = 0; i < len32; i++)
530 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
531 return;
532 }
533
534
535 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
536
537
538 dmae.src_addr_lo = src_addr >> 2;
539 dmae.src_addr_hi = 0;
540 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
541 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
542 dmae.len = len32;
543
544 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
545
546
547 bnx2x_issue_dmae_with_comp(bp, &dmae);
548}
549
550static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
551 u32 addr, u32 len)
552{
553 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
554 int offset = 0;
555
556 while (len > dmae_wr_max) {
557 bnx2x_write_dmae(bp, phys_addr + offset,
558 addr + offset, dmae_wr_max);
559 offset += dmae_wr_max * 4;
560 len -= dmae_wr_max;
561 }
562
563 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
564}
565
566
567static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
568{
569 u32 wb_write[2];
570
571 wb_write[0] = val_hi;
572 wb_write[1] = val_lo;
573 REG_WR_DMAE(bp, reg, wb_write, 2);
574}
575
576#ifdef USE_WB_RD
577static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
578{
579 u32 wb_data[2];
580
581 REG_RD_DMAE(bp, reg, wb_data, 2);
582
583 return HILO_U64(wb_data[0], wb_data[1]);
584}
585#endif
586
587static int bnx2x_mc_assert(struct bnx2x *bp)
588{
589 char last_idx;
590 int i, rc = 0;
591 u32 row0, row1, row2, row3;
592
593
594 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
595 XSTORM_ASSERT_LIST_INDEX_OFFSET);
596 if (last_idx)
597 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
598
599
600 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
601
602 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
603 XSTORM_ASSERT_LIST_OFFSET(i));
604 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
605 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
606 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
608 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
610
611 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
612 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
613 " 0x%08x 0x%08x 0x%08x\n",
614 i, row3, row2, row1, row0);
615 rc++;
616 } else {
617 break;
618 }
619 }
620
621
622 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
623 TSTORM_ASSERT_LIST_INDEX_OFFSET);
624 if (last_idx)
625 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
626
627
628 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
629
630 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
631 TSTORM_ASSERT_LIST_OFFSET(i));
632 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
633 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
634 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
636 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
638
639 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
640 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
641 " 0x%08x 0x%08x 0x%08x\n",
642 i, row3, row2, row1, row0);
643 rc++;
644 } else {
645 break;
646 }
647 }
648
649
650 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
651 CSTORM_ASSERT_LIST_INDEX_OFFSET);
652 if (last_idx)
653 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
654
655
656 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
657
658 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
659 CSTORM_ASSERT_LIST_OFFSET(i));
660 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
661 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
662 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
664 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
666
667 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
668 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
669 " 0x%08x 0x%08x 0x%08x\n",
670 i, row3, row2, row1, row0);
671 rc++;
672 } else {
673 break;
674 }
675 }
676
677
678 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
679 USTORM_ASSERT_LIST_INDEX_OFFSET);
680 if (last_idx)
681 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
682
683
684 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
685
686 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
687 USTORM_ASSERT_LIST_OFFSET(i));
688 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
689 USTORM_ASSERT_LIST_OFFSET(i) + 4);
690 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i) + 8);
692 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 12);
694
695 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
696 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
697 " 0x%08x 0x%08x 0x%08x\n",
698 i, row3, row2, row1, row0);
699 rc++;
700 } else {
701 break;
702 }
703 }
704
705 return rc;
706}
707
708void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
709{
710 u32 addr, val;
711 u32 mark, offset;
712 __be32 data[9];
713 int word;
714 u32 trace_shmem_base;
715 if (BP_NOMCP(bp)) {
716 BNX2X_ERR("NO MCP - can not dump\n");
717 return;
718 }
719 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
720 (bp->common.bc_ver & 0xff0000) >> 16,
721 (bp->common.bc_ver & 0xff00) >> 8,
722 (bp->common.bc_ver & 0xff));
723
724 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
725 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
726 printk("%s" "MCP PC at 0x%x\n", lvl, val);
727
728 if (BP_PATH(bp) == 0)
729 trace_shmem_base = bp->common.shmem_base;
730 else
731 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
732 addr = trace_shmem_base - 0x0800 + 4;
733 mark = REG_RD(bp, addr);
734 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
735 + ((mark + 0x3) & ~0x3) - 0x08000000;
736 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
737
738 printk("%s", lvl);
739 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
740 for (word = 0; word < 8; word++)
741 data[word] = htonl(REG_RD(bp, offset + 4*word));
742 data[8] = 0x0;
743 pr_cont("%s", (char *)data);
744 }
745 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
746 for (word = 0; word < 8; word++)
747 data[word] = htonl(REG_RD(bp, offset + 4*word));
748 data[8] = 0x0;
749 pr_cont("%s", (char *)data);
750 }
751 printk("%s" "end of fw dump\n", lvl);
752}
753
754static inline void bnx2x_fw_dump(struct bnx2x *bp)
755{
756 bnx2x_fw_dump_lvl(bp, KERN_ERR);
757}
758
759void bnx2x_panic_dump(struct bnx2x *bp)
760{
761 int i;
762 u16 j;
763 struct hc_sp_status_block_data sp_sb_data;
764 int func = BP_FUNC(bp);
765#ifdef BNX2X_STOP_ON_ERROR
766 u16 start = 0, end = 0;
767 u8 cos;
768#endif
769
770 bp->stats_state = STATS_STATE_DISABLED;
771 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
772
773 BNX2X_ERR("begin crash dump -----------------\n");
774
775
776
777 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
778 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
779 bp->def_idx, bp->def_att_idx, bp->attn_state,
780 bp->spq_prod_idx, bp->stats_counter);
781 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
782 bp->def_status_blk->atten_status_block.attn_bits,
783 bp->def_status_blk->atten_status_block.attn_bits_ack,
784 bp->def_status_blk->atten_status_block.status_block_id,
785 bp->def_status_blk->atten_status_block.attn_bits_index);
786 BNX2X_ERR(" def (");
787 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
788 pr_cont("0x%x%s",
789 bp->def_status_blk->sp_sb.index_values[i],
790 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
791
792 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
793 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
795 i*sizeof(u32));
796
797 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
798 sp_sb_data.igu_sb_id,
799 sp_sb_data.igu_seg_id,
800 sp_sb_data.p_func.pf_id,
801 sp_sb_data.p_func.vnic_id,
802 sp_sb_data.p_func.vf_id,
803 sp_sb_data.p_func.vf_valid,
804 sp_sb_data.state);
805
806
807 for_each_eth_queue(bp, i) {
808 struct bnx2x_fastpath *fp = &bp->fp[i];
809 int loop;
810 struct hc_status_block_data_e2 sb_data_e2;
811 struct hc_status_block_data_e1x sb_data_e1x;
812 struct hc_status_block_sm *hc_sm_p =
813 CHIP_IS_E1x(bp) ?
814 sb_data_e1x.common.state_machine :
815 sb_data_e2.common.state_machine;
816 struct hc_index_data *hc_index_p =
817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.index_data :
819 sb_data_e2.index_data;
820 u8 data_size, cos;
821 u32 *sb_data_p;
822 struct bnx2x_fp_txdata txdata;
823
824
825 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
826 " rx_comp_prod(0x%x)"
827 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
828 i, fp->rx_bd_prod, fp->rx_bd_cons,
829 fp->rx_comp_prod,
830 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
831 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
832 " fp_hc_idx(0x%x)\n",
833 fp->rx_sge_prod, fp->last_max_sge,
834 le16_to_cpu(fp->fp_hc_idx));
835
836
837 for_each_cos_in_tx_queue(fp, cos)
838 {
839 txdata = fp->txdata[cos];
840 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
841 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
842 " *tx_cons_sb(0x%x)\n",
843 i, txdata.tx_pkt_prod,
844 txdata.tx_pkt_cons, txdata.tx_bd_prod,
845 txdata.tx_bd_cons,
846 le16_to_cpu(*txdata.tx_cons_sb));
847 }
848
849 loop = CHIP_IS_E1x(bp) ?
850 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
851
852
853
854#ifdef BCM_CNIC
855 if (IS_FCOE_FP(fp))
856 continue;
857#endif
858 BNX2X_ERR(" run indexes (");
859 for (j = 0; j < HC_SB_MAX_SM; j++)
860 pr_cont("0x%x%s",
861 fp->sb_running_index[j],
862 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
863
864 BNX2X_ERR(" indexes (");
865 for (j = 0; j < loop; j++)
866 pr_cont("0x%x%s",
867 fp->sb_index_values[j],
868 (j == loop - 1) ? ")" : " ");
869
870 data_size = CHIP_IS_E1x(bp) ?
871 sizeof(struct hc_status_block_data_e1x) :
872 sizeof(struct hc_status_block_data_e2);
873 data_size /= sizeof(u32);
874 sb_data_p = CHIP_IS_E1x(bp) ?
875 (u32 *)&sb_data_e1x :
876 (u32 *)&sb_data_e2;
877
878 for (j = 0; j < data_size; j++)
879 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
880 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
881 j * sizeof(u32));
882
883 if (!CHIP_IS_E1x(bp)) {
884 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
885 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
886 "state(0x%x)\n",
887 sb_data_e2.common.p_func.pf_id,
888 sb_data_e2.common.p_func.vf_id,
889 sb_data_e2.common.p_func.vf_valid,
890 sb_data_e2.common.p_func.vnic_id,
891 sb_data_e2.common.same_igu_sb_1b,
892 sb_data_e2.common.state);
893 } else {
894 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
895 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
896 "state(0x%x)\n",
897 sb_data_e1x.common.p_func.pf_id,
898 sb_data_e1x.common.p_func.vf_id,
899 sb_data_e1x.common.p_func.vf_valid,
900 sb_data_e1x.common.p_func.vnic_id,
901 sb_data_e1x.common.same_igu_sb_1b,
902 sb_data_e1x.common.state);
903 }
904
905
906 for (j = 0; j < HC_SB_MAX_SM; j++) {
907 pr_cont("SM[%d] __flags (0x%x) "
908 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
909 "time_to_expire (0x%x) "
910 "timer_value(0x%x)\n", j,
911 hc_sm_p[j].__flags,
912 hc_sm_p[j].igu_sb_id,
913 hc_sm_p[j].igu_seg_id,
914 hc_sm_p[j].time_to_expire,
915 hc_sm_p[j].timer_value);
916 }
917
918
919 for (j = 0; j < loop; j++) {
920 pr_cont("INDEX[%d] flags (0x%x) "
921 "timeout (0x%x)\n", j,
922 hc_index_p[j].flags,
923 hc_index_p[j].timeout);
924 }
925 }
926
927#ifdef BNX2X_STOP_ON_ERROR
928
929
930 for_each_rx_queue(bp, i) {
931 struct bnx2x_fastpath *fp = &bp->fp[i];
932
933 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
934 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
935 for (j = start; j != end; j = RX_BD(j + 1)) {
936 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
937 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
938
939 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
940 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
941 }
942
943 start = RX_SGE(fp->rx_sge_prod);
944 end = RX_SGE(fp->last_max_sge);
945 for (j = start; j != end; j = RX_SGE(j + 1)) {
946 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
947 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
948
949 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
950 i, j, rx_sge[1], rx_sge[0], sw_page->page);
951 }
952
953 start = RCQ_BD(fp->rx_comp_cons - 10);
954 end = RCQ_BD(fp->rx_comp_cons + 503);
955 for (j = start; j != end; j = RCQ_BD(j + 1)) {
956 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
957
958 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
959 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
960 }
961 }
962
963
964 for_each_tx_queue(bp, i) {
965 struct bnx2x_fastpath *fp = &bp->fp[i];
966 for_each_cos_in_tx_queue(fp, cos) {
967 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
968
969 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
970 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
971 for (j = start; j != end; j = TX_BD(j + 1)) {
972 struct sw_tx_bd *sw_bd =
973 &txdata->tx_buf_ring[j];
974
975 BNX2X_ERR("fp%d: txdata %d, "
976 "packet[%x]=[%p,%x]\n",
977 i, cos, j, sw_bd->skb,
978 sw_bd->first_bd);
979 }
980
981 start = TX_BD(txdata->tx_bd_cons - 10);
982 end = TX_BD(txdata->tx_bd_cons + 254);
983 for (j = start; j != end; j = TX_BD(j + 1)) {
984 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
985
986 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
987 "[%x:%x:%x:%x]\n",
988 i, cos, j, tx_bd[0], tx_bd[1],
989 tx_bd[2], tx_bd[3]);
990 }
991 }
992 }
993#endif
994 bnx2x_fw_dump(bp);
995 bnx2x_mc_assert(bp);
996 BNX2X_ERR("end crash dump -----------------\n");
997}
998
999
1000
1001
1002
1003
1004
1005#define FLR_WAIT_USEC 10000
1006#define FLR_WAIT_INTERAVAL 50
1007#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL)
1008
1009struct pbf_pN_buf_regs {
1010 int pN;
1011 u32 init_crd;
1012 u32 crd;
1013 u32 crd_freed;
1014};
1015
1016struct pbf_pN_cmd_regs {
1017 int pN;
1018 u32 lines_occup;
1019 u32 lines_freed;
1020};
1021
1022static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1023 struct pbf_pN_buf_regs *regs,
1024 u32 poll_count)
1025{
1026 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1027 u32 cur_cnt = poll_count;
1028
1029 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1030 crd = crd_start = REG_RD(bp, regs->crd);
1031 init_crd = REG_RD(bp, regs->init_crd);
1032
1033 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1034 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1035 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1036
1037 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1038 (init_crd - crd_start))) {
1039 if (cur_cnt--) {
1040 udelay(FLR_WAIT_INTERAVAL);
1041 crd = REG_RD(bp, regs->crd);
1042 crd_freed = REG_RD(bp, regs->crd_freed);
1043 } else {
1044 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1045 regs->pN);
1046 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1047 regs->pN, crd);
1048 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1049 regs->pN, crd_freed);
1050 break;
1051 }
1052 }
1053 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1054 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1055}
1056
1057static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1058 struct pbf_pN_cmd_regs *regs,
1059 u32 poll_count)
1060{
1061 u32 occup, to_free, freed, freed_start;
1062 u32 cur_cnt = poll_count;
1063
1064 occup = to_free = REG_RD(bp, regs->lines_occup);
1065 freed = freed_start = REG_RD(bp, regs->lines_freed);
1066
1067 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1068 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1069
1070 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1071 if (cur_cnt--) {
1072 udelay(FLR_WAIT_INTERAVAL);
1073 occup = REG_RD(bp, regs->lines_occup);
1074 freed = REG_RD(bp, regs->lines_freed);
1075 } else {
1076 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1077 regs->pN);
1078 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1079 regs->pN, occup);
1080 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1081 regs->pN, freed);
1082 break;
1083 }
1084 }
1085 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1086 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1087}
1088
1089static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1090 u32 expected, u32 poll_count)
1091{
1092 u32 cur_cnt = poll_count;
1093 u32 val;
1094
1095 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1096 udelay(FLR_WAIT_INTERAVAL);
1097
1098 return val;
1099}
1100
1101static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1102 char *msg, u32 poll_cnt)
1103{
1104 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1105 if (val != 0) {
1106 BNX2X_ERR("%s usage count=%d\n", msg, val);
1107 return 1;
1108 }
1109 return 0;
1110}
1111
1112static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1113{
1114
1115 if (CHIP_REV_IS_EMUL(bp))
1116 return FLR_POLL_CNT * 2000;
1117
1118 if (CHIP_REV_IS_FPGA(bp))
1119 return FLR_POLL_CNT * 120;
1120
1121 return FLR_POLL_CNT;
1122}
1123
1124static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1125{
1126 struct pbf_pN_cmd_regs cmd_regs[] = {
1127 {0, (CHIP_IS_E3B0(bp)) ?
1128 PBF_REG_TQ_OCCUPANCY_Q0 :
1129 PBF_REG_P0_TQ_OCCUPANCY,
1130 (CHIP_IS_E3B0(bp)) ?
1131 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1132 PBF_REG_P0_TQ_LINES_FREED_CNT},
1133 {1, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q1 :
1135 PBF_REG_P1_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1138 PBF_REG_P1_TQ_LINES_FREED_CNT},
1139 {4, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_LB_Q :
1141 PBF_REG_P4_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1144 PBF_REG_P4_TQ_LINES_FREED_CNT}
1145 };
1146
1147 struct pbf_pN_buf_regs buf_regs[] = {
1148 {0, (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_INIT_CRD_Q0 :
1150 PBF_REG_P0_INIT_CRD ,
1151 (CHIP_IS_E3B0(bp)) ?
1152 PBF_REG_CREDIT_Q0 :
1153 PBF_REG_P0_CREDIT,
1154 (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1156 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1157 {1, (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_INIT_CRD_Q1 :
1159 PBF_REG_P1_INIT_CRD,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_CREDIT_Q1 :
1162 PBF_REG_P1_CREDIT,
1163 (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1165 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1166 {4, (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_INIT_CRD_LB_Q :
1168 PBF_REG_P4_INIT_CRD,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_CREDIT_LB_Q :
1171 PBF_REG_P4_CREDIT,
1172 (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1174 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1175 };
1176
1177 int i;
1178
1179
1180 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1181 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1182
1183
1184
1185 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1186 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1187}
1188
1189#define OP_GEN_PARAM(param) \
1190 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1191
1192#define OP_GEN_TYPE(type) \
1193 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1194
1195#define OP_GEN_AGG_VECT(index) \
1196 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1197
1198
1199static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1200 u32 poll_cnt)
1201{
1202 struct sdm_op_gen op_gen = {0};
1203
1204 u32 comp_addr = BAR_CSTRORM_INTMEM +
1205 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1206 int ret = 0;
1207
1208 if (REG_RD(bp, comp_addr)) {
1209 BNX2X_ERR("Cleanup complete is not 0\n");
1210 return 1;
1211 }
1212
1213 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1214 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1215 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1216 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1217
1218 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1219 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1220
1221 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1222 BNX2X_ERR("FW final cleanup did not succeed\n");
1223 ret = 1;
1224 }
1225
1226 REG_WR(bp, comp_addr, 0);
1227
1228 return ret;
1229}
1230
1231static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1232{
1233 int pos;
1234 u16 status;
1235
1236 pos = pci_pcie_cap(dev);
1237 if (!pos)
1238 return false;
1239
1240 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1241 return status & PCI_EXP_DEVSTA_TRPND;
1242}
1243
1244
1245
1246static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1247{
1248
1249
1250 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1251 CFC_REG_NUM_LCIDS_INSIDE_PF,
1252 "CFC PF usage counter timed out",
1253 poll_cnt))
1254 return 1;
1255
1256
1257
1258 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1259 DORQ_REG_PF_USAGE_CNT,
1260 "DQ PF usage counter timed out",
1261 poll_cnt))
1262 return 1;
1263
1264
1265 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1266 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1267 "QM PF usage counter timed out",
1268 poll_cnt))
1269 return 1;
1270
1271
1272 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1273 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1274 "Timers VNIC usage counter timed out",
1275 poll_cnt))
1276 return 1;
1277 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1278 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1279 "Timers NUM_SCANS usage counter timed out",
1280 poll_cnt))
1281 return 1;
1282
1283
1284 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1285 dmae_reg_go_c[INIT_DMAE_C(bp)],
1286 "DMAE dommand register timed out",
1287 poll_cnt))
1288 return 1;
1289
1290 return 0;
1291}
1292
1293static void bnx2x_hw_enable_status(struct bnx2x *bp)
1294{
1295 u32 val;
1296
1297 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1298 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1299
1300 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1301 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1302
1303 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1304 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1305
1306 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1307 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1311
1312 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1313 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1314
1315 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1316 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1320 val);
1321}
1322
1323static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1324{
1325 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1326
1327 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1328
1329
1330 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1331
1332
1333 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1334 return -EBUSY;
1335
1336
1337
1338
1339 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1340 return -EBUSY;
1341
1342
1343
1344
1345 bnx2x_tx_hw_flushed(bp, poll_cnt);
1346
1347
1348 msleep(100);
1349
1350
1351 if (bnx2x_is_pcie_pending(bp->pdev))
1352 BNX2X_ERR("PCIE Transactions still pending\n");
1353
1354
1355 bnx2x_hw_enable_status(bp);
1356
1357
1358
1359
1360
1361 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1362
1363 return 0;
1364}
1365
1366static void bnx2x_hc_int_enable(struct bnx2x *bp)
1367{
1368 int port = BP_PORT(bp);
1369 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1370 u32 val = REG_RD(bp, addr);
1371 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1372 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1373
1374 if (msix) {
1375 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1376 HC_CONFIG_0_REG_INT_LINE_EN_0);
1377 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1378 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1379 } else if (msi) {
1380 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1381 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1383 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1384 } else {
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1388 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1389
1390 if (!CHIP_IS_E1(bp)) {
1391 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1392 val, port, addr);
1393
1394 REG_WR(bp, addr, val);
1395
1396 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1397 }
1398 }
1399
1400 if (CHIP_IS_E1(bp))
1401 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1402
1403 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1404 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1405
1406 REG_WR(bp, addr, val);
1407
1408
1409
1410 mmiowb();
1411 barrier();
1412
1413 if (!CHIP_IS_E1(bp)) {
1414
1415 if (IS_MF(bp)) {
1416 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1417 if (bp->port.pmf)
1418
1419 val |= 0x1100;
1420 } else
1421 val = 0xffff;
1422
1423 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1424 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1425 }
1426
1427
1428 mmiowb();
1429}
1430
1431static void bnx2x_igu_int_enable(struct bnx2x *bp)
1432{
1433 u32 val;
1434 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1435 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1436
1437 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1438
1439 if (msix) {
1440 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1441 IGU_PF_CONF_SINGLE_ISR_EN);
1442 val |= (IGU_PF_CONF_FUNC_EN |
1443 IGU_PF_CONF_MSI_MSIX_EN |
1444 IGU_PF_CONF_ATTN_BIT_EN);
1445 } else if (msi) {
1446 val &= ~IGU_PF_CONF_INT_LINE_EN;
1447 val |= (IGU_PF_CONF_FUNC_EN |
1448 IGU_PF_CONF_MSI_MSIX_EN |
1449 IGU_PF_CONF_ATTN_BIT_EN |
1450 IGU_PF_CONF_SINGLE_ISR_EN);
1451 } else {
1452 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_INT_LINE_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 }
1458
1459 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1460 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1461
1462 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1463
1464 barrier();
1465
1466
1467 if (IS_MF(bp)) {
1468 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1469 if (bp->port.pmf)
1470
1471 val |= 0x1100;
1472 } else
1473 val = 0xffff;
1474
1475 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1476 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1477
1478
1479 mmiowb();
1480}
1481
1482void bnx2x_int_enable(struct bnx2x *bp)
1483{
1484 if (bp->common.int_block == INT_BLOCK_HC)
1485 bnx2x_hc_int_enable(bp);
1486 else
1487 bnx2x_igu_int_enable(bp);
1488}
1489
1490static void bnx2x_hc_int_disable(struct bnx2x *bp)
1491{
1492 int port = BP_PORT(bp);
1493 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1494 u32 val = REG_RD(bp, addr);
1495
1496
1497
1498
1499
1500
1501 if (CHIP_IS_E1(bp)) {
1502
1503
1504
1505
1506 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1507
1508 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1509 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1510 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1511 } else
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1514 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1515 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1516
1517 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1518 val, port, addr);
1519
1520
1521 mmiowb();
1522
1523 REG_WR(bp, addr, val);
1524 if (REG_RD(bp, addr) != val)
1525 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1526}
1527
1528static void bnx2x_igu_int_disable(struct bnx2x *bp)
1529{
1530 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1531
1532 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1533 IGU_PF_CONF_INT_LINE_EN |
1534 IGU_PF_CONF_ATTN_BIT_EN);
1535
1536 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1537
1538
1539 mmiowb();
1540
1541 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1542 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1543 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1544}
1545
1546void bnx2x_int_disable(struct bnx2x *bp)
1547{
1548 if (bp->common.int_block == INT_BLOCK_HC)
1549 bnx2x_hc_int_disable(bp);
1550 else
1551 bnx2x_igu_int_disable(bp);
1552}
1553
1554void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1555{
1556 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1557 int i, offset;
1558
1559 if (disable_hw)
1560
1561 bnx2x_int_disable(bp);
1562
1563
1564 if (msix) {
1565 synchronize_irq(bp->msix_table[0].vector);
1566 offset = 1;
1567#ifdef BCM_CNIC
1568 offset++;
1569#endif
1570 for_each_eth_queue(bp, i)
1571 synchronize_irq(bp->msix_table[offset++].vector);
1572 } else
1573 synchronize_irq(bp->pdev->irq);
1574
1575
1576 cancel_delayed_work(&bp->sp_task);
1577 cancel_delayed_work(&bp->period_task);
1578 flush_workqueue(bnx2x_wq);
1579}
1580
1581
1582
1583
1584
1585
1586
1587
1588static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1589{
1590 u32 lock_status;
1591 u32 resource_bit = (1 << resource);
1592 int func = BP_FUNC(bp);
1593 u32 hw_lock_control_reg;
1594
1595 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1596
1597
1598 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1599 DP(NETIF_MSG_HW,
1600 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1601 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1602 return false;
1603 }
1604
1605 if (func <= 5)
1606 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1607 else
1608 hw_lock_control_reg =
1609 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1610
1611
1612 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1613 lock_status = REG_RD(bp, hw_lock_control_reg);
1614 if (lock_status & resource_bit)
1615 return true;
1616
1617 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1618 return false;
1619}
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1630{
1631 if (BP_PATH(bp))
1632 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1633 else
1634 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1635}
1636
1637
1638
1639
1640
1641
1642
1643
1644static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1645{
1646 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1647}
1648
1649#ifdef BCM_CNIC
1650static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1651#endif
1652
1653void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1654{
1655 struct bnx2x *bp = fp->bp;
1656 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1657 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1658 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1659 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1660
1661 DP(BNX2X_MSG_SP,
1662 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1663 fp->index, cid, command, bp->state,
1664 rr_cqe->ramrod_cqe.ramrod_type);
1665
1666 switch (command) {
1667 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1668 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1669 drv_cmd = BNX2X_Q_CMD_UPDATE;
1670 break;
1671
1672 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1673 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1674 drv_cmd = BNX2X_Q_CMD_SETUP;
1675 break;
1676
1677 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1679 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1680 break;
1681
1682 case (RAMROD_CMD_ID_ETH_HALT):
1683 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1684 drv_cmd = BNX2X_Q_CMD_HALT;
1685 break;
1686
1687 case (RAMROD_CMD_ID_ETH_TERMINATE):
1688 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1689 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1690 break;
1691
1692 case (RAMROD_CMD_ID_ETH_EMPTY):
1693 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1694 drv_cmd = BNX2X_Q_CMD_EMPTY;
1695 break;
1696
1697 default:
1698 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1699 command, fp->index);
1700 return;
1701 }
1702
1703 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1704 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1705
1706
1707
1708
1709
1710
1711
1712#ifdef BNX2X_STOP_ON_ERROR
1713 bnx2x_panic();
1714#else
1715 return;
1716#endif
1717
1718 smp_mb__before_atomic_inc();
1719 atomic_inc(&bp->cq_spq_left);
1720
1721 smp_mb__after_atomic_inc();
1722
1723 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1724
1725 return;
1726}
1727
1728void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1729 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1730{
1731 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1732
1733 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1734 start);
1735}
1736
1737irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1738{
1739 struct bnx2x *bp = netdev_priv(dev_instance);
1740 u16 status = bnx2x_ack_int(bp);
1741 u16 mask;
1742 int i;
1743 u8 cos;
1744
1745
1746 if (unlikely(status == 0)) {
1747 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1748 return IRQ_NONE;
1749 }
1750 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1751
1752#ifdef BNX2X_STOP_ON_ERROR
1753 if (unlikely(bp->panic))
1754 return IRQ_HANDLED;
1755#endif
1756
1757 for_each_eth_queue(bp, i) {
1758 struct bnx2x_fastpath *fp = &bp->fp[i];
1759
1760 mask = 0x2 << (fp->index + CNIC_PRESENT);
1761 if (status & mask) {
1762
1763 prefetch(fp->rx_cons_sb);
1764 for_each_cos_in_tx_queue(fp, cos)
1765 prefetch(fp->txdata[cos].tx_cons_sb);
1766 prefetch(&fp->sb_running_index[SM_RX_ID]);
1767 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1768 status &= ~mask;
1769 }
1770 }
1771
1772#ifdef BCM_CNIC
1773 mask = 0x2;
1774 if (status & (mask | 0x1)) {
1775 struct cnic_ops *c_ops = NULL;
1776
1777 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1778 rcu_read_lock();
1779 c_ops = rcu_dereference(bp->cnic_ops);
1780 if (c_ops)
1781 c_ops->cnic_handler(bp->cnic_data, NULL);
1782 rcu_read_unlock();
1783 }
1784
1785 status &= ~mask;
1786 }
1787#endif
1788
1789 if (unlikely(status & 0x1)) {
1790 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1791
1792 status &= ~0x1;
1793 if (!status)
1794 return IRQ_HANDLED;
1795 }
1796
1797 if (unlikely(status))
1798 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1799 status);
1800
1801 return IRQ_HANDLED;
1802}
1803
1804
1805
1806
1807
1808
1809
1810int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1811{
1812 u32 lock_status;
1813 u32 resource_bit = (1 << resource);
1814 int func = BP_FUNC(bp);
1815 u32 hw_lock_control_reg;
1816 int cnt;
1817
1818
1819 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1820 DP(NETIF_MSG_HW,
1821 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1822 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1823 return -EINVAL;
1824 }
1825
1826 if (func <= 5) {
1827 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1828 } else {
1829 hw_lock_control_reg =
1830 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1831 }
1832
1833
1834 lock_status = REG_RD(bp, hw_lock_control_reg);
1835 if (lock_status & resource_bit) {
1836 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1837 lock_status, resource_bit);
1838 return -EEXIST;
1839 }
1840
1841
1842 for (cnt = 0; cnt < 1000; cnt++) {
1843
1844 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1845 lock_status = REG_RD(bp, hw_lock_control_reg);
1846 if (lock_status & resource_bit)
1847 return 0;
1848
1849 msleep(5);
1850 }
1851 DP(NETIF_MSG_HW, "Timeout\n");
1852 return -EAGAIN;
1853}
1854
1855int bnx2x_release_leader_lock(struct bnx2x *bp)
1856{
1857 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1858}
1859
1860int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1861{
1862 u32 lock_status;
1863 u32 resource_bit = (1 << resource);
1864 int func = BP_FUNC(bp);
1865 u32 hw_lock_control_reg;
1866
1867 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1868
1869
1870 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1871 DP(NETIF_MSG_HW,
1872 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1873 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1874 return -EINVAL;
1875 }
1876
1877 if (func <= 5) {
1878 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1879 } else {
1880 hw_lock_control_reg =
1881 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1882 }
1883
1884
1885 lock_status = REG_RD(bp, hw_lock_control_reg);
1886 if (!(lock_status & resource_bit)) {
1887 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1888 lock_status, resource_bit);
1889 return -EFAULT;
1890 }
1891
1892 REG_WR(bp, hw_lock_control_reg, resource_bit);
1893 return 0;
1894}
1895
1896
1897int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1898{
1899
1900 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1901 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1902 int gpio_shift = gpio_num +
1903 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1904 u32 gpio_mask = (1 << gpio_shift);
1905 u32 gpio_reg;
1906 int value;
1907
1908 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1909 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1910 return -EINVAL;
1911 }
1912
1913
1914 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1915
1916
1917 if ((gpio_reg & gpio_mask) == gpio_mask)
1918 value = 1;
1919 else
1920 value = 0;
1921
1922 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1923
1924 return value;
1925}
1926
1927int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1928{
1929
1930 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1931 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1932 int gpio_shift = gpio_num +
1933 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1934 u32 gpio_mask = (1 << gpio_shift);
1935 u32 gpio_reg;
1936
1937 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1938 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1939 return -EINVAL;
1940 }
1941
1942 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1943
1944 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1945
1946 switch (mode) {
1947 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1948 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1949 gpio_num, gpio_shift);
1950
1951 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1952 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1953 break;
1954
1955 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1956 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1957 gpio_num, gpio_shift);
1958
1959 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1960 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1961 break;
1962
1963 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1964 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1965 gpio_num, gpio_shift);
1966
1967 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1968 break;
1969
1970 default:
1971 break;
1972 }
1973
1974 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1975 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1976
1977 return 0;
1978}
1979
1980int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1981{
1982 u32 gpio_reg = 0;
1983 int rc = 0;
1984
1985
1986
1987 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1988
1989 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1990 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1991 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1992 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1993
1994 switch (mode) {
1995 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1996 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1997
1998 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1999 break;
2000
2001 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2003
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2005 break;
2006
2007 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2009
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2011 break;
2012
2013 default:
2014 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2015 rc = -EINVAL;
2016 break;
2017 }
2018
2019 if (rc == 0)
2020 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2021
2022 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2023
2024 return rc;
2025}
2026
2027int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2028{
2029
2030 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2031 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2032 int gpio_shift = gpio_num +
2033 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2034 u32 gpio_mask = (1 << gpio_shift);
2035 u32 gpio_reg;
2036
2037 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2038 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2039 return -EINVAL;
2040 }
2041
2042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2043
2044 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2045
2046 switch (mode) {
2047 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2048 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2049 "output low\n", gpio_num, gpio_shift);
2050
2051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2053 break;
2054
2055 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2056 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2057 "output high\n", gpio_num, gpio_shift);
2058
2059 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2060 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2061 break;
2062
2063 default:
2064 break;
2065 }
2066
2067 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2068 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2069
2070 return 0;
2071}
2072
2073static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2074{
2075 u32 spio_mask = (1 << spio_num);
2076 u32 spio_reg;
2077
2078 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2079 (spio_num > MISC_REGISTERS_SPIO_7)) {
2080 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2081 return -EINVAL;
2082 }
2083
2084 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2085
2086 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2087
2088 switch (mode) {
2089 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2090 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2091
2092 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2093 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2094 break;
2095
2096 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2097 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2098
2099 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2100 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2101 break;
2102
2103 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2105
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2107 break;
2108
2109 default:
2110 break;
2111 }
2112
2113 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2114 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2115
2116 return 0;
2117}
2118
2119void bnx2x_calc_fc_adv(struct bnx2x *bp)
2120{
2121 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2122 switch (bp->link_vars.ieee_fc &
2123 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2124 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2125 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2126 ADVERTISED_Pause);
2127 break;
2128
2129 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2130 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2131 ADVERTISED_Pause);
2132 break;
2133
2134 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2135 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2136 break;
2137
2138 default:
2139 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2140 ADVERTISED_Pause);
2141 break;
2142 }
2143}
2144
2145u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2146{
2147 if (!BP_NOMCP(bp)) {
2148 u8 rc;
2149 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2150 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2151
2152
2153
2154
2155
2156 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2157 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2158 else
2159 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2160
2161 bnx2x_acquire_phy_lock(bp);
2162
2163 if (load_mode == LOAD_DIAG) {
2164 struct link_params *lp = &bp->link_params;
2165 lp->loopback_mode = LOOPBACK_XGXS;
2166
2167 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2168 if (lp->speed_cap_mask[cfx_idx] &
2169 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2170 lp->req_line_speed[cfx_idx] =
2171 SPEED_10000;
2172 else
2173 lp->req_line_speed[cfx_idx] =
2174 SPEED_1000;
2175 }
2176 }
2177
2178 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2179
2180 bnx2x_release_phy_lock(bp);
2181
2182 bnx2x_calc_fc_adv(bp);
2183
2184 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2185 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2186 bnx2x_link_report(bp);
2187 } else
2188 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2189 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2190 return rc;
2191 }
2192 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2193 return -EINVAL;
2194}
2195
2196void bnx2x_link_set(struct bnx2x *bp)
2197{
2198 if (!BP_NOMCP(bp)) {
2199 bnx2x_acquire_phy_lock(bp);
2200 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2201 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2202 bnx2x_release_phy_lock(bp);
2203
2204 bnx2x_calc_fc_adv(bp);
2205 } else
2206 BNX2X_ERR("Bootcode is missing - can not set link\n");
2207}
2208
2209static void bnx2x__link_reset(struct bnx2x *bp)
2210{
2211 if (!BP_NOMCP(bp)) {
2212 bnx2x_acquire_phy_lock(bp);
2213 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2214 bnx2x_release_phy_lock(bp);
2215 } else
2216 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2217}
2218
2219u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2220{
2221 u8 rc = 0;
2222
2223 if (!BP_NOMCP(bp)) {
2224 bnx2x_acquire_phy_lock(bp);
2225 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2226 is_serdes);
2227 bnx2x_release_phy_lock(bp);
2228 } else
2229 BNX2X_ERR("Bootcode is missing - can not test link\n");
2230
2231 return rc;
2232}
2233
2234static void bnx2x_init_port_minmax(struct bnx2x *bp)
2235{
2236 u32 r_param = bp->link_vars.line_speed / 8;
2237 u32 fair_periodic_timeout_usec;
2238 u32 t_fair;
2239
2240 memset(&(bp->cmng.rs_vars), 0,
2241 sizeof(struct rate_shaping_vars_per_port));
2242 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2243
2244
2245 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2246
2247
2248
2249
2250 bp->cmng.rs_vars.rs_threshold =
2251 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2252
2253
2254 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2255
2256 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2257
2258
2259 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2260
2261
2262
2263
2264 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2265
2266 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2267}
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2279{
2280 int all_zero = 1;
2281 int vn;
2282
2283 bp->vn_weight_sum = 0;
2284 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2285 u32 vn_cfg = bp->mf_config[vn];
2286 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2287 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2288
2289
2290 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2291 continue;
2292
2293
2294 if (!vn_min_rate)
2295 vn_min_rate = DEF_MIN_RATE;
2296 else
2297 all_zero = 0;
2298
2299 bp->vn_weight_sum += vn_min_rate;
2300 }
2301
2302
2303 if (BNX2X_IS_ETS_ENABLED(bp)) {
2304 bp->cmng.flags.cmng_enables &=
2305 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2306 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2307 } else if (all_zero) {
2308 bp->cmng.flags.cmng_enables &=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2311 " fairness will be disabled\n");
2312 } else
2313 bp->cmng.flags.cmng_enables |=
2314 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2315}
2316
2317static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2318{
2319 struct rate_shaping_vars_per_vn m_rs_vn;
2320 struct fairness_vars_per_vn m_fair_vn;
2321 u32 vn_cfg = bp->mf_config[vn];
2322 int func = func_by_vn(bp, vn);
2323 u16 vn_min_rate, vn_max_rate;
2324 int i;
2325
2326
2327 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2328 vn_min_rate = 0;
2329 vn_max_rate = 0;
2330
2331 } else {
2332 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2333
2334 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2335 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2336
2337
2338
2339 if (bp->vn_weight_sum && (vn_min_rate == 0))
2340 vn_min_rate = DEF_MIN_RATE;
2341
2342 if (IS_MF_SI(bp))
2343
2344 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2345 else
2346
2347 vn_max_rate = maxCfg * 100;
2348 }
2349
2350 DP(NETIF_MSG_IFUP,
2351 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2352 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2353
2354 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2355 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2356
2357
2358 m_rs_vn.vn_counter.rate = vn_max_rate;
2359
2360
2361 m_rs_vn.vn_counter.quota =
2362 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2363
2364 if (bp->vn_weight_sum) {
2365
2366
2367
2368
2369
2370 m_fair_vn.vn_credit_delta =
2371 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2372 (8 * bp->vn_weight_sum))),
2373 (bp->cmng.fair_vars.fair_threshold +
2374 MIN_ABOVE_THRESH));
2375 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2376 m_fair_vn.vn_credit_delta);
2377 }
2378
2379
2380 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2381 REG_WR(bp, BAR_XSTRORM_INTMEM +
2382 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2383 ((u32 *)(&m_rs_vn))[i]);
2384
2385 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2386 REG_WR(bp, BAR_XSTRORM_INTMEM +
2387 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2388 ((u32 *)(&m_fair_vn))[i]);
2389}
2390
2391static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2392{
2393 if (CHIP_REV_IS_SLOW(bp))
2394 return CMNG_FNS_NONE;
2395 if (IS_MF(bp))
2396 return CMNG_FNS_MINMAX;
2397
2398 return CMNG_FNS_NONE;
2399}
2400
2401void bnx2x_read_mf_cfg(struct bnx2x *bp)
2402{
2403 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2404
2405 if (BP_NOMCP(bp))
2406 return;
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2420 int func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2421
2422 if (func >= E1H_FUNC_MAX)
2423 break;
2424
2425 bp->mf_config[vn] =
2426 MF_CFG_RD(bp, func_mf_config[func].config);
2427 }
2428}
2429
2430static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2431{
2432
2433 if (cmng_type == CMNG_FNS_MINMAX) {
2434 int vn;
2435
2436
2437 bp->cmng.flags.cmng_enables = 0;
2438
2439
2440 if (read_cfg)
2441 bnx2x_read_mf_cfg(bp);
2442
2443
2444 bnx2x_init_port_minmax(bp);
2445
2446
2447 bnx2x_calc_vn_weight_sum(bp);
2448
2449
2450 if (bp->port.pmf)
2451 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2452 bnx2x_init_vn_minmax(bp, vn);
2453
2454
2455 bp->cmng.flags.cmng_enables |=
2456 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2457 if (!bp->vn_weight_sum)
2458 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2459 " fairness will be disabled\n");
2460 return;
2461 }
2462
2463
2464 DP(NETIF_MSG_IFUP,
2465 "rate shaping and fairness are disabled\n");
2466}
2467
2468
2469static void bnx2x_link_attn(struct bnx2x *bp)
2470{
2471
2472 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2473
2474 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2475
2476 if (bp->link_vars.link_up) {
2477
2478
2479 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2480 int port = BP_PORT(bp);
2481 u32 pause_enabled = 0;
2482
2483 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2484 pause_enabled = 1;
2485
2486 REG_WR(bp, BAR_USTRORM_INTMEM +
2487 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2488 pause_enabled);
2489 }
2490
2491 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2492 struct host_port_stats *pstats;
2493
2494 pstats = bnx2x_sp(bp, port_stats);
2495
2496 memset(&(pstats->mac_stx[0]), 0,
2497 sizeof(struct mac_stx));
2498 }
2499 if (bp->state == BNX2X_STATE_OPEN)
2500 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2501 }
2502
2503 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2504 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2505
2506 if (cmng_fns != CMNG_FNS_NONE) {
2507 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2508 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2509 } else
2510
2511 DP(NETIF_MSG_IFUP,
2512 "single function mode without fairness\n");
2513 }
2514
2515 __bnx2x_link_report(bp);
2516
2517 if (IS_MF(bp))
2518 bnx2x_link_sync_notify(bp);
2519}
2520
2521void bnx2x__link_status_update(struct bnx2x *bp)
2522{
2523 if (bp->state != BNX2X_STATE_OPEN)
2524 return;
2525
2526
2527 bnx2x_dcbx_pmf_update(bp);
2528
2529 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2530
2531 if (bp->link_vars.link_up)
2532 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2533 else
2534 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2535
2536
2537 bnx2x_link_report(bp);
2538}
2539
2540static void bnx2x_pmf_update(struct bnx2x *bp)
2541{
2542 int port = BP_PORT(bp);
2543 u32 val;
2544
2545 bp->port.pmf = 1;
2546 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2547
2548
2549
2550
2551
2552 smp_mb();
2553
2554
2555 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2556
2557 bnx2x_dcbx_pmf_update(bp);
2558
2559
2560 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2561 if (bp->common.int_block == INT_BLOCK_HC) {
2562 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2563 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2564 } else if (!CHIP_IS_E1x(bp)) {
2565 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2566 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2567 }
2568
2569 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2570}
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2582{
2583 int mb_idx = BP_FW_MB_IDX(bp);
2584 u32 seq;
2585 u32 rc = 0;
2586 u32 cnt = 1;
2587 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2588
2589 mutex_lock(&bp->fw_mb_mutex);
2590 seq = ++bp->fw_seq;
2591 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2592 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2593
2594 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2595 (command | seq), param);
2596
2597 do {
2598
2599 msleep(delay);
2600
2601 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2602
2603
2604 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2605
2606 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2607 cnt*delay, rc, seq);
2608
2609
2610 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2611 rc &= FW_MSG_CODE_MASK;
2612 else {
2613
2614 BNX2X_ERR("FW failed to respond!\n");
2615 bnx2x_fw_dump(bp);
2616 rc = 0;
2617 }
2618 mutex_unlock(&bp->fw_mb_mutex);
2619
2620 return rc;
2621}
2622
2623
2624void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2625{
2626 if (CHIP_IS_E1x(bp)) {
2627 struct tstorm_eth_function_common_config tcfg = {0};
2628
2629 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2630 }
2631
2632
2633 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2634 storm_memset_func_en(bp, p->func_id, 1);
2635
2636
2637 if (p->func_flgs & FUNC_FLG_SPQ) {
2638 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2639 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2640 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2641 }
2642}
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2654 struct bnx2x_fastpath *fp,
2655 bool zero_stats)
2656{
2657 unsigned long flags = 0;
2658
2659
2660 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2661
2662
2663
2664
2665
2666
2667 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2668 if (zero_stats)
2669 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2670
2671
2672 return flags;
2673}
2674
2675static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2676 struct bnx2x_fastpath *fp,
2677 bool leading)
2678{
2679 unsigned long flags = 0;
2680
2681
2682 if (IS_MF_SD(bp))
2683 __set_bit(BNX2X_Q_FLG_OV, &flags);
2684
2685 if (IS_FCOE_FP(fp))
2686 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2687
2688 if (!fp->disable_tpa) {
2689 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2690 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2691 }
2692
2693 if (leading) {
2694 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2695 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2696 }
2697
2698
2699 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2700
2701
2702 return flags | bnx2x_get_common_flags(bp, fp, true);
2703}
2704
2705static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2706 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2707 u8 cos)
2708{
2709 gen_init->stat_id = bnx2x_stats_id(fp);
2710 gen_init->spcl_id = fp->cl_id;
2711
2712
2713 if (IS_FCOE_FP(fp))
2714 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2715 else
2716 gen_init->mtu = bp->dev->mtu;
2717
2718 gen_init->cos = cos;
2719}
2720
2721static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2722 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2723 struct bnx2x_rxq_setup_params *rxq_init)
2724{
2725 u8 max_sge = 0;
2726 u16 sge_sz = 0;
2727 u16 tpa_agg_size = 0;
2728
2729 if (!fp->disable_tpa) {
2730 pause->sge_th_lo = SGE_TH_LO(bp);
2731 pause->sge_th_hi = SGE_TH_HI(bp);
2732
2733
2734 WARN_ON(bp->dropless_fc &&
2735 pause->sge_th_hi + FW_PREFETCH_CNT >
2736 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2737
2738 tpa_agg_size = min_t(u32,
2739 (min_t(u32, 8, MAX_SKB_FRAGS) *
2740 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2741 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2742 SGE_PAGE_SHIFT;
2743 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2744 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2745 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2746 0xffff);
2747 }
2748
2749
2750 if (!CHIP_IS_E1(bp)) {
2751 pause->bd_th_lo = BD_TH_LO(bp);
2752 pause->bd_th_hi = BD_TH_HI(bp);
2753
2754 pause->rcq_th_lo = RCQ_TH_LO(bp);
2755 pause->rcq_th_hi = RCQ_TH_HI(bp);
2756
2757
2758
2759
2760 WARN_ON(bp->dropless_fc &&
2761 pause->bd_th_hi + FW_PREFETCH_CNT >
2762 bp->rx_ring_size);
2763 WARN_ON(bp->dropless_fc &&
2764 pause->rcq_th_hi + FW_PREFETCH_CNT >
2765 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2766
2767 pause->pri_map = 1;
2768 }
2769
2770
2771 rxq_init->dscr_map = fp->rx_desc_mapping;
2772 rxq_init->sge_map = fp->rx_sge_mapping;
2773 rxq_init->rcq_map = fp->rx_comp_mapping;
2774 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2775
2776
2777
2778
2779 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2780 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2781
2782 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2783 rxq_init->tpa_agg_sz = tpa_agg_size;
2784 rxq_init->sge_buf_sz = sge_sz;
2785 rxq_init->max_sges_pkt = max_sge;
2786 rxq_init->rss_engine_id = BP_FUNC(bp);
2787
2788
2789
2790
2791
2792
2793 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2794
2795 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2796 rxq_init->fw_sb_id = fp->fw_sb_id;
2797
2798 if (IS_FCOE_FP(fp))
2799 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2800 else
2801 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2802}
2803
2804static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2805 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2806 u8 cos)
2807{
2808 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2809 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2810 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2811 txq_init->fw_sb_id = fp->fw_sb_id;
2812
2813
2814
2815
2816
2817 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2818
2819 if (IS_FCOE_FP(fp)) {
2820 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2821 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2822 }
2823}
2824
2825static void bnx2x_pf_init(struct bnx2x *bp)
2826{
2827 struct bnx2x_func_init_params func_init = {0};
2828 struct event_ring_data eq_data = { {0} };
2829 u16 flags;
2830
2831 if (!CHIP_IS_E1x(bp)) {
2832
2833
2834 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2835 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2836 (CHIP_MODE_IS_4_PORT(bp) ?
2837 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2838
2839 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2840 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2841 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2842 (CHIP_MODE_IS_4_PORT(bp) ?
2843 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2844 }
2845
2846
2847 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2848
2849
2850
2851
2852 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2853
2854 func_init.func_flgs = flags;
2855 func_init.pf_id = BP_FUNC(bp);
2856 func_init.func_id = BP_FUNC(bp);
2857 func_init.spq_map = bp->spq_mapping;
2858 func_init.spq_prod = bp->spq_prod_idx;
2859
2860 bnx2x_func_init(bp, &func_init);
2861
2862 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2863
2864
2865
2866
2867
2868
2869
2870 bp->link_vars.line_speed = SPEED_10000;
2871 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2872
2873
2874 if (bp->port.pmf)
2875 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2876
2877
2878 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2879 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2880 eq_data.producer = bp->eq_prod;
2881 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2882 eq_data.sb_id = DEF_SB_ID;
2883 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2884}
2885
2886
2887static void bnx2x_e1h_disable(struct bnx2x *bp)
2888{
2889 int port = BP_PORT(bp);
2890
2891 bnx2x_tx_disable(bp);
2892
2893 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2894}
2895
2896static void bnx2x_e1h_enable(struct bnx2x *bp)
2897{
2898 int port = BP_PORT(bp);
2899
2900 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2901
2902
2903 netif_tx_wake_all_queues(bp->dev);
2904
2905
2906
2907
2908
2909}
2910
2911#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2912
2913static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2914{
2915 struct eth_stats_info *ether_stat =
2916 &bp->slowpath->drv_info_to_mcp.ether_stat;
2917
2918
2919 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2920 ETH_STAT_INFO_VERSION_LEN - 1);
2921
2922 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2923 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2924 ether_stat->mac_local);
2925
2926 ether_stat->mtu_size = bp->dev->mtu;
2927
2928 if (bp->dev->features & NETIF_F_RXCSUM)
2929 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2930 if (bp->dev->features & NETIF_F_TSO)
2931 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2932 ether_stat->feature_flags |= bp->common.boot_mode;
2933
2934 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2935
2936 ether_stat->txq_size = bp->tx_ring_size;
2937 ether_stat->rxq_size = bp->rx_ring_size;
2938}
2939
2940static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2941{
2942#ifdef BCM_CNIC
2943 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2944 struct fcoe_stats_info *fcoe_stat =
2945 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2946
2947 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2948
2949 fcoe_stat->qos_priority =
2950 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2951
2952
2953 if (!NO_FCOE(bp)) {
2954 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2955 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2956 tstorm_queue_statistics;
2957
2958 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2959 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2960 xstorm_queue_statistics;
2961
2962 struct fcoe_statistics_params *fw_fcoe_stat =
2963 &bp->fw_stats_data->fcoe;
2964
2965 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2966 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2967
2968 ADD_64(fcoe_stat->rx_bytes_hi,
2969 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2970 fcoe_stat->rx_bytes_lo,
2971 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2972
2973 ADD_64(fcoe_stat->rx_bytes_hi,
2974 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2975 fcoe_stat->rx_bytes_lo,
2976 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2977
2978 ADD_64(fcoe_stat->rx_bytes_hi,
2979 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2980 fcoe_stat->rx_bytes_lo,
2981 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2982
2983 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2984 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
2985
2986 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2987 fcoe_q_tstorm_stats->rcv_ucast_pkts);
2988
2989 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2990 fcoe_q_tstorm_stats->rcv_bcast_pkts);
2991
2992 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2993 fcoe_q_tstorm_stats->rcv_mcast_pkts);
2994
2995 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
2996 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
2997
2998 ADD_64(fcoe_stat->tx_bytes_hi,
2999 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3000 fcoe_stat->tx_bytes_lo,
3001 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3002
3003 ADD_64(fcoe_stat->tx_bytes_hi,
3004 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3005 fcoe_stat->tx_bytes_lo,
3006 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3007
3008 ADD_64(fcoe_stat->tx_bytes_hi,
3009 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3010 fcoe_stat->tx_bytes_lo,
3011 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3012
3013 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3014 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3015
3016 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3017 fcoe_q_xstorm_stats->ucast_pkts_sent);
3018
3019 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3020 fcoe_q_xstorm_stats->bcast_pkts_sent);
3021
3022 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3023 fcoe_q_xstorm_stats->mcast_pkts_sent);
3024 }
3025
3026
3027 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3028#endif
3029}
3030
3031static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3032{
3033#ifdef BCM_CNIC
3034 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3035 struct iscsi_stats_info *iscsi_stat =
3036 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3037
3038 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3039
3040 iscsi_stat->qos_priority =
3041 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3042
3043
3044 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3045#endif
3046}
3047
3048
3049
3050
3051
3052
3053static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
3054{
3055 if (bp->link_vars.link_up) {
3056 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3057 bnx2x_link_sync_notify(bp);
3058 }
3059 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3060}
3061
3062static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
3063{
3064 bnx2x_config_mf_bw(bp);
3065 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3066}
3067
3068static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3069{
3070 enum drv_info_opcode op_code;
3071 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3072
3073
3074 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3075 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3076 return;
3077 }
3078
3079 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3080 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3081
3082 memset(&bp->slowpath->drv_info_to_mcp, 0,
3083 sizeof(union drv_info_to_mcp));
3084
3085 switch (op_code) {
3086 case ETH_STATS_OPCODE:
3087 bnx2x_drv_info_ether_stat(bp);
3088 break;
3089 case FCOE_STATS_OPCODE:
3090 bnx2x_drv_info_fcoe_stat(bp);
3091 break;
3092 case ISCSI_STATS_OPCODE:
3093 bnx2x_drv_info_iscsi_stat(bp);
3094 break;
3095 default:
3096
3097 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3098 return;
3099 }
3100
3101
3102
3103
3104 SHMEM2_WR(bp, drv_info_host_addr_lo,
3105 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3106 SHMEM2_WR(bp, drv_info_host_addr_hi,
3107 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3108
3109 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3110}
3111
3112static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3113{
3114 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3115
3116 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3117
3118
3119
3120
3121
3122
3123 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3124 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
3125 bp->flags |= MF_FUNC_DIS;
3126
3127 bnx2x_e1h_disable(bp);
3128 } else {
3129 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
3130 bp->flags &= ~MF_FUNC_DIS;
3131
3132 bnx2x_e1h_enable(bp);
3133 }
3134 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3135 }
3136 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3137 bnx2x_config_mf_bw(bp);
3138 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3139 }
3140
3141
3142 if (dcc_event)
3143 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3144 else
3145 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3146}
3147
3148
3149static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3150{
3151 struct eth_spe *next_spe = bp->spq_prod_bd;
3152
3153 if (bp->spq_prod_bd == bp->spq_last_bd) {
3154 bp->spq_prod_bd = bp->spq;
3155 bp->spq_prod_idx = 0;
3156 DP(NETIF_MSG_TIMER, "end of spq\n");
3157 } else {
3158 bp->spq_prod_bd++;
3159 bp->spq_prod_idx++;
3160 }
3161 return next_spe;
3162}
3163
3164
3165static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3166{
3167 int func = BP_FUNC(bp);
3168
3169
3170
3171
3172
3173
3174 mb();
3175
3176 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3177 bp->spq_prod_idx);
3178 mmiowb();
3179}
3180
3181
3182
3183
3184
3185
3186
3187static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3188{
3189 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3190 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3191 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3192 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3193 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3194 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3195 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3196 return true;
3197 else
3198 return false;
3199
3200}
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3218 u32 data_hi, u32 data_lo, int cmd_type)
3219{
3220 struct eth_spe *spe;
3221 u16 type;
3222 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3223
3224#ifdef BNX2X_STOP_ON_ERROR
3225 if (unlikely(bp->panic))
3226 return -EIO;
3227#endif
3228
3229 spin_lock_bh(&bp->spq_lock);
3230
3231 if (common) {
3232 if (!atomic_read(&bp->eq_spq_left)) {
3233 BNX2X_ERR("BUG! EQ ring full!\n");
3234 spin_unlock_bh(&bp->spq_lock);
3235 bnx2x_panic();
3236 return -EBUSY;
3237 }
3238 } else if (!atomic_read(&bp->cq_spq_left)) {
3239 BNX2X_ERR("BUG! SPQ ring full!\n");
3240 spin_unlock_bh(&bp->spq_lock);
3241 bnx2x_panic();
3242 return -EBUSY;
3243 }
3244
3245 spe = bnx2x_sp_get_next(bp);
3246
3247
3248 spe->hdr.conn_and_cmd_data =
3249 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3250 HW_CID(bp, cid));
3251
3252 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3253
3254 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3255 SPE_HDR_FUNCTION_ID);
3256
3257 spe->hdr.type = cpu_to_le16(type);
3258
3259 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3260 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3261
3262
3263
3264
3265
3266
3267 if (common)
3268 atomic_dec(&bp->eq_spq_left);
3269 else
3270 atomic_dec(&bp->cq_spq_left);
3271
3272
3273 DP(BNX2X_MSG_SP,
3274 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3275 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3276 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3277 (u32)(U64_LO(bp->spq_mapping) +
3278 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3279 HW_CID(bp, cid), data_hi, data_lo, type,
3280 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3281
3282 bnx2x_sp_prod_update(bp);
3283 spin_unlock_bh(&bp->spq_lock);
3284 return 0;
3285}
3286
3287
3288static int bnx2x_acquire_alr(struct bnx2x *bp)
3289{
3290 u32 j, val;
3291 int rc = 0;
3292
3293 might_sleep();
3294 for (j = 0; j < 1000; j++) {
3295 val = (1UL << 31);
3296 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3297 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3298 if (val & (1L << 31))
3299 break;
3300
3301 msleep(5);
3302 }
3303 if (!(val & (1L << 31))) {
3304 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3305 rc = -EBUSY;
3306 }
3307
3308 return rc;
3309}
3310
3311
3312static void bnx2x_release_alr(struct bnx2x *bp)
3313{
3314 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3315}
3316
3317#define BNX2X_DEF_SB_ATT_IDX 0x0001
3318#define BNX2X_DEF_SB_IDX 0x0002
3319
3320static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3321{
3322 struct host_sp_status_block *def_sb = bp->def_status_blk;
3323 u16 rc = 0;
3324
3325 barrier();
3326 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3327 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3328 rc |= BNX2X_DEF_SB_ATT_IDX;
3329 }
3330
3331 if (bp->def_idx != def_sb->sp_sb.running_index) {
3332 bp->def_idx = def_sb->sp_sb.running_index;
3333 rc |= BNX2X_DEF_SB_IDX;
3334 }
3335
3336
3337 barrier();
3338 return rc;
3339}
3340
3341
3342
3343
3344
3345static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3346{
3347 int port = BP_PORT(bp);
3348 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3349 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3350 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3351 NIG_REG_MASK_INTERRUPT_PORT0;
3352 u32 aeu_mask;
3353 u32 nig_mask = 0;
3354 u32 reg_addr;
3355
3356 if (bp->attn_state & asserted)
3357 BNX2X_ERR("IGU ERROR\n");
3358
3359 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3360 aeu_mask = REG_RD(bp, aeu_addr);
3361
3362 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3363 aeu_mask, asserted);
3364 aeu_mask &= ~(asserted & 0x3ff);
3365 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3366
3367 REG_WR(bp, aeu_addr, aeu_mask);
3368 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3369
3370 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3371 bp->attn_state |= asserted;
3372 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3373
3374 if (asserted & ATTN_HARD_WIRED_MASK) {
3375 if (asserted & ATTN_NIG_FOR_FUNC) {
3376
3377 bnx2x_acquire_phy_lock(bp);
3378
3379
3380 nig_mask = REG_RD(bp, nig_int_mask_addr);
3381
3382
3383
3384
3385 if (nig_mask) {
3386 REG_WR(bp, nig_int_mask_addr, 0);
3387
3388 bnx2x_link_attn(bp);
3389 }
3390
3391
3392 }
3393 if (asserted & ATTN_SW_TIMER_4_FUNC)
3394 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3395
3396 if (asserted & GPIO_2_FUNC)
3397 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3398
3399 if (asserted & GPIO_3_FUNC)
3400 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3401
3402 if (asserted & GPIO_4_FUNC)
3403 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3404
3405 if (port == 0) {
3406 if (asserted & ATTN_GENERAL_ATTN_1) {
3407 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3408 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3409 }
3410 if (asserted & ATTN_GENERAL_ATTN_2) {
3411 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3412 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3413 }
3414 if (asserted & ATTN_GENERAL_ATTN_3) {
3415 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3416 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3417 }
3418 } else {
3419 if (asserted & ATTN_GENERAL_ATTN_4) {
3420 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3421 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3422 }
3423 if (asserted & ATTN_GENERAL_ATTN_5) {
3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3426 }
3427 if (asserted & ATTN_GENERAL_ATTN_6) {
3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3430 }
3431 }
3432
3433 }
3434
3435 if (bp->common.int_block == INT_BLOCK_HC)
3436 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3437 COMMAND_REG_ATTN_BITS_SET);
3438 else
3439 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3440
3441 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3442 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3443 REG_WR(bp, reg_addr, asserted);
3444
3445
3446 if (asserted & ATTN_NIG_FOR_FUNC) {
3447 REG_WR(bp, nig_int_mask_addr, nig_mask);
3448 bnx2x_release_phy_lock(bp);
3449 }
3450}
3451
3452static inline void bnx2x_fan_failure(struct bnx2x *bp)
3453{
3454 int port = BP_PORT(bp);
3455 u32 ext_phy_config;
3456
3457 ext_phy_config =
3458 SHMEM_RD(bp,
3459 dev_info.port_hw_config[port].external_phy_config);
3460
3461 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3462 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3463 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3464 ext_phy_config);
3465
3466
3467 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3468 " the driver to shutdown the card to prevent permanent"
3469 " damage. Please contact OEM Support for assistance\n");
3470
3471
3472
3473
3474
3475
3476 smp_mb__before_clear_bit();
3477 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3478 smp_mb__after_clear_bit();
3479 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3480
3481}
3482
3483static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3484{
3485 int port = BP_PORT(bp);
3486 int reg_offset;
3487 u32 val;
3488
3489 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3490 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3491
3492 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3493
3494 val = REG_RD(bp, reg_offset);
3495 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3496 REG_WR(bp, reg_offset, val);
3497
3498 BNX2X_ERR("SPIO5 hw attention\n");
3499
3500
3501 bnx2x_hw_reset_phy(&bp->link_params);
3502 bnx2x_fan_failure(bp);
3503 }
3504
3505 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3506 bnx2x_acquire_phy_lock(bp);
3507 bnx2x_handle_module_detect_int(&bp->link_params);
3508 bnx2x_release_phy_lock(bp);
3509 }
3510
3511 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3512
3513 val = REG_RD(bp, reg_offset);
3514 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3515 REG_WR(bp, reg_offset, val);
3516
3517 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3518 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3519 bnx2x_panic();
3520 }
3521}
3522
3523static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3524{
3525 u32 val;
3526
3527 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3528
3529 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3530 BNX2X_ERR("DB hw attention 0x%x\n", val);
3531
3532 if (val & 0x2)
3533 BNX2X_ERR("FATAL error from DORQ\n");
3534 }
3535
3536 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3537
3538 int port = BP_PORT(bp);
3539 int reg_offset;
3540
3541 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3542 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3543
3544 val = REG_RD(bp, reg_offset);
3545 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3546 REG_WR(bp, reg_offset, val);
3547
3548 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3549 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3550 bnx2x_panic();
3551 }
3552}
3553
3554static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3555{
3556 u32 val;
3557
3558 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3559
3560 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3561 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3562
3563 if (val & 0x2)
3564 BNX2X_ERR("FATAL error from CFC\n");
3565 }
3566
3567 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3568 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3569 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3570
3571 if (val & 0x18000)
3572 BNX2X_ERR("FATAL error from PXP\n");
3573
3574 if (!CHIP_IS_E1x(bp)) {
3575 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3576 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3577 }
3578 }
3579
3580 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3581
3582 int port = BP_PORT(bp);
3583 int reg_offset;
3584
3585 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3586 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3587
3588 val = REG_RD(bp, reg_offset);
3589 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3590 REG_WR(bp, reg_offset, val);
3591
3592 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3593 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3594 bnx2x_panic();
3595 }
3596}
3597
3598static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3599{
3600 u32 val;
3601
3602 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3603
3604 if (attn & BNX2X_PMF_LINK_ASSERT) {
3605 int func = BP_FUNC(bp);
3606
3607 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3608 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3609 func_mf_config[BP_ABS_FUNC(bp)].config);
3610 val = SHMEM_RD(bp,
3611 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3612 if (val & DRV_STATUS_DCC_EVENT_MASK)
3613 bnx2x_dcc_event(bp,
3614 (val & DRV_STATUS_DCC_EVENT_MASK));
3615
3616 if (val & DRV_STATUS_SET_MF_BW)
3617 bnx2x_set_mf_bw(bp);
3618
3619 if (val & DRV_STATUS_DRV_INFO_REQ)
3620 bnx2x_handle_drv_info_req(bp);
3621 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3622 bnx2x_pmf_update(bp);
3623
3624 if (bp->port.pmf &&
3625 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3626 bp->dcbx_enabled > 0)
3627
3628 bnx2x_dcbx_set_params(bp,
3629 BNX2X_DCBX_STATE_NEG_RECEIVED);
3630 if (bp->link_vars.periodic_flags &
3631 PERIODIC_FLAGS_LINK_EVENT) {
3632
3633 bnx2x_acquire_phy_lock(bp);
3634 bp->link_vars.periodic_flags &=
3635 ~PERIODIC_FLAGS_LINK_EVENT;
3636 bnx2x_release_phy_lock(bp);
3637 if (IS_MF(bp))
3638 bnx2x_link_sync_notify(bp);
3639 bnx2x_link_report(bp);
3640 }
3641
3642
3643
3644 bnx2x__link_status_update(bp);
3645 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3646
3647 BNX2X_ERR("MC assert!\n");
3648 bnx2x_mc_assert(bp);
3649 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3650 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3651 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3652 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3653 bnx2x_panic();
3654
3655 } else if (attn & BNX2X_MCP_ASSERT) {
3656
3657 BNX2X_ERR("MCP assert!\n");
3658 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3659 bnx2x_fw_dump(bp);
3660
3661 } else
3662 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3663 }
3664
3665 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3666 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3667 if (attn & BNX2X_GRC_TIMEOUT) {
3668 val = CHIP_IS_E1(bp) ? 0 :
3669 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3670 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3671 }
3672 if (attn & BNX2X_GRC_RSV) {
3673 val = CHIP_IS_E1(bp) ? 0 :
3674 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3675 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3676 }
3677 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3678 }
3679}
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3696
3697#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3698#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3699#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3700#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3701#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3702#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3703#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3704
3705
3706
3707
3708
3709
3710void bnx2x_set_reset_global(struct bnx2x *bp)
3711{
3712 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3713
3714 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3715 barrier();
3716 mmiowb();
3717}
3718
3719
3720
3721
3722
3723
3724static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3725{
3726 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3727
3728 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3729 barrier();
3730 mmiowb();
3731}
3732
3733
3734
3735
3736
3737
3738static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3739{
3740 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3741
3742 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3743 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3744}
3745
3746
3747
3748
3749
3750
3751static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3752{
3753 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3754 u32 bit = BP_PATH(bp) ?
3755 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3756
3757
3758 val &= ~bit;
3759 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3760 barrier();
3761 mmiowb();
3762}
3763
3764
3765
3766
3767
3768
3769void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3770{
3771 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3772 u32 bit = BP_PATH(bp) ?
3773 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3774
3775
3776 val |= bit;
3777 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3778 barrier();
3779 mmiowb();
3780}
3781
3782
3783
3784
3785
3786bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3787{
3788 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3789 u32 bit = engine ?
3790 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3791
3792
3793 return (val & bit) ? false : true;
3794}
3795
3796
3797
3798
3799
3800
3801void bnx2x_inc_load_cnt(struct bnx2x *bp)
3802{
3803 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3804 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3805 BNX2X_PATH0_LOAD_CNT_MASK;
3806 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3807 BNX2X_PATH0_LOAD_CNT_SHIFT;
3808
3809 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3810
3811
3812 val1 = (val & mask) >> shift;
3813
3814
3815 val1++;
3816
3817
3818 val &= ~mask;
3819
3820
3821 val |= ((val1 << shift) & mask);
3822
3823 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3824 barrier();
3825 mmiowb();
3826}
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3838{
3839 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3840 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3841 BNX2X_PATH0_LOAD_CNT_MASK;
3842 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3843 BNX2X_PATH0_LOAD_CNT_SHIFT;
3844
3845 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3846
3847
3848 val1 = (val & mask) >> shift;
3849
3850
3851 val1--;
3852
3853
3854 val &= ~mask;
3855
3856
3857 val |= ((val1 << shift) & mask);
3858
3859 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3860 barrier();
3861 mmiowb();
3862
3863 return val1;
3864}
3865
3866
3867
3868
3869
3870
3871static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3872{
3873 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3874 BNX2X_PATH0_LOAD_CNT_MASK);
3875 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3876 BNX2X_PATH0_LOAD_CNT_SHIFT);
3877 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3878
3879 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3880
3881 val = (val & mask) >> shift;
3882
3883 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3884
3885 return val;
3886}
3887
3888
3889
3890
3891
3892
3893static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3894{
3895 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3896 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3897 BNX2X_PATH0_LOAD_CNT_MASK);
3898
3899 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3900}
3901
3902static inline void _print_next_block(int idx, const char *blk)
3903{
3904 pr_cont("%s%s", idx ? ", " : "", blk);
3905}
3906
3907static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3908 bool print)
3909{
3910 int i = 0;
3911 u32 cur_bit = 0;
3912 for (i = 0; sig; i++) {
3913 cur_bit = ((u32)0x1 << i);
3914 if (sig & cur_bit) {
3915 switch (cur_bit) {
3916 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3917 if (print)
3918 _print_next_block(par_num++, "BRB");
3919 break;
3920 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3921 if (print)
3922 _print_next_block(par_num++, "PARSER");
3923 break;
3924 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3925 if (print)
3926 _print_next_block(par_num++, "TSDM");
3927 break;
3928 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3929 if (print)
3930 _print_next_block(par_num++,
3931 "SEARCHER");
3932 break;
3933 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3934 if (print)
3935 _print_next_block(par_num++, "TCM");
3936 break;
3937 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3938 if (print)
3939 _print_next_block(par_num++, "TSEMI");
3940 break;
3941 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3942 if (print)
3943 _print_next_block(par_num++, "XPB");
3944 break;
3945 }
3946
3947
3948 sig &= ~cur_bit;
3949 }
3950 }
3951
3952 return par_num;
3953}
3954
3955static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3956 bool *global, bool print)
3957{
3958 int i = 0;
3959 u32 cur_bit = 0;
3960 for (i = 0; sig; i++) {
3961 cur_bit = ((u32)0x1 << i);
3962 if (sig & cur_bit) {
3963 switch (cur_bit) {
3964 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3965 if (print)
3966 _print_next_block(par_num++, "PBF");
3967 break;
3968 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3969 if (print)
3970 _print_next_block(par_num++, "QM");
3971 break;
3972 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3973 if (print)
3974 _print_next_block(par_num++, "TM");
3975 break;
3976 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3977 if (print)
3978 _print_next_block(par_num++, "XSDM");
3979 break;
3980 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3981 if (print)
3982 _print_next_block(par_num++, "XCM");
3983 break;
3984 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3985 if (print)
3986 _print_next_block(par_num++, "XSEMI");
3987 break;
3988 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3989 if (print)
3990 _print_next_block(par_num++,
3991 "DOORBELLQ");
3992 break;
3993 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3994 if (print)
3995 _print_next_block(par_num++, "NIG");
3996 break;
3997 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3998 if (print)
3999 _print_next_block(par_num++,
4000 "VAUX PCI CORE");
4001 *global = true;
4002 break;
4003 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4004 if (print)
4005 _print_next_block(par_num++, "DEBUG");
4006 break;
4007 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4008 if (print)
4009 _print_next_block(par_num++, "USDM");
4010 break;
4011 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4012 if (print)
4013 _print_next_block(par_num++, "UCM");
4014 break;
4015 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4016 if (print)
4017 _print_next_block(par_num++, "USEMI");
4018 break;
4019 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4020 if (print)
4021 _print_next_block(par_num++, "UPB");
4022 break;
4023 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4024 if (print)
4025 _print_next_block(par_num++, "CSDM");
4026 break;
4027 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4028 if (print)
4029 _print_next_block(par_num++, "CCM");
4030 break;
4031 }
4032
4033
4034 sig &= ~cur_bit;
4035 }
4036 }
4037
4038 return par_num;
4039}
4040
4041static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4042 bool print)
4043{
4044 int i = 0;
4045 u32 cur_bit = 0;
4046 for (i = 0; sig; i++) {
4047 cur_bit = ((u32)0x1 << i);
4048 if (sig & cur_bit) {
4049 switch (cur_bit) {
4050 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4051 if (print)
4052 _print_next_block(par_num++, "CSEMI");
4053 break;
4054 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4055 if (print)
4056 _print_next_block(par_num++, "PXP");
4057 break;
4058 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4059 if (print)
4060 _print_next_block(par_num++,
4061 "PXPPCICLOCKCLIENT");
4062 break;
4063 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4064 if (print)
4065 _print_next_block(par_num++, "CFC");
4066 break;
4067 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4068 if (print)
4069 _print_next_block(par_num++, "CDU");
4070 break;
4071 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4072 if (print)
4073 _print_next_block(par_num++, "DMAE");
4074 break;
4075 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4076 if (print)
4077 _print_next_block(par_num++, "IGU");
4078 break;
4079 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4080 if (print)
4081 _print_next_block(par_num++, "MISC");
4082 break;
4083 }
4084
4085
4086 sig &= ~cur_bit;
4087 }
4088 }
4089
4090 return par_num;
4091}
4092
4093static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4094 bool *global, bool print)
4095{
4096 int i = 0;
4097 u32 cur_bit = 0;
4098 for (i = 0; sig; i++) {
4099 cur_bit = ((u32)0x1 << i);
4100 if (sig & cur_bit) {
4101 switch (cur_bit) {
4102 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4103 if (print)
4104 _print_next_block(par_num++, "MCP ROM");
4105 *global = true;
4106 break;
4107 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4108 if (print)
4109 _print_next_block(par_num++,
4110 "MCP UMP RX");
4111 *global = true;
4112 break;
4113 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4114 if (print)
4115 _print_next_block(par_num++,
4116 "MCP UMP TX");
4117 *global = true;
4118 break;
4119 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4120 if (print)
4121 _print_next_block(par_num++,
4122 "MCP SCPAD");
4123 *global = true;
4124 break;
4125 }
4126
4127
4128 sig &= ~cur_bit;
4129 }
4130 }
4131
4132 return par_num;
4133}
4134
4135static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4136 bool print)
4137{
4138 int i = 0;
4139 u32 cur_bit = 0;
4140 for (i = 0; sig; i++) {
4141 cur_bit = ((u32)0x1 << i);
4142 if (sig & cur_bit) {
4143 switch (cur_bit) {
4144 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4145 if (print)
4146 _print_next_block(par_num++, "PGLUE_B");
4147 break;
4148 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4149 if (print)
4150 _print_next_block(par_num++, "ATC");
4151 break;
4152 }
4153
4154
4155 sig &= ~cur_bit;
4156 }
4157 }
4158
4159 return par_num;
4160}
4161
4162static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4163 u32 *sig)
4164{
4165 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4166 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4167 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4168 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4169 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4170 int par_num = 0;
4171 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4172 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4173 "[4]:0x%08x\n",
4174 sig[0] & HW_PRTY_ASSERT_SET_0,
4175 sig[1] & HW_PRTY_ASSERT_SET_1,
4176 sig[2] & HW_PRTY_ASSERT_SET_2,
4177 sig[3] & HW_PRTY_ASSERT_SET_3,
4178 sig[4] & HW_PRTY_ASSERT_SET_4);
4179 if (print)
4180 netdev_err(bp->dev,
4181 "Parity errors detected in blocks: ");
4182 par_num = bnx2x_check_blocks_with_parity0(
4183 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4184 par_num = bnx2x_check_blocks_with_parity1(
4185 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4186 par_num = bnx2x_check_blocks_with_parity2(
4187 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4188 par_num = bnx2x_check_blocks_with_parity3(
4189 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4190 par_num = bnx2x_check_blocks_with_parity4(
4191 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4192
4193 if (print)
4194 pr_cont("\n");
4195
4196 return true;
4197 } else
4198 return false;
4199}
4200
4201
4202
4203
4204
4205
4206
4207
4208bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4209{
4210 struct attn_route attn = { {0} };
4211 int port = BP_PORT(bp);
4212
4213 attn.sig[0] = REG_RD(bp,
4214 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4215 port*4);
4216 attn.sig[1] = REG_RD(bp,
4217 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4218 port*4);
4219 attn.sig[2] = REG_RD(bp,
4220 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4221 port*4);
4222 attn.sig[3] = REG_RD(bp,
4223 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4224 port*4);
4225
4226 if (!CHIP_IS_E1x(bp))
4227 attn.sig[4] = REG_RD(bp,
4228 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4229 port*4);
4230
4231 return bnx2x_parity_attn(bp, global, print, attn.sig);
4232}
4233
4234
4235static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4236{
4237 u32 val;
4238 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4239
4240 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4241 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4242 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4243 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4244 "ADDRESS_ERROR\n");
4245 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4247 "INCORRECT_RCV_BEHAVIOR\n");
4248 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4249 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4250 "WAS_ERROR_ATTN\n");
4251 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4252 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4253 "VF_LENGTH_VIOLATION_ATTN\n");
4254 if (val &
4255 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4257 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4258 if (val &
4259 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4261 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4262 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4263 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4264 "TCPL_ERROR_ATTN\n");
4265 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4267 "TCPL_IN_TWO_RCBS_ATTN\n");
4268 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4269 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4270 "CSSNOOP_FIFO_OVERFLOW\n");
4271 }
4272 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4273 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4274 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4275 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4276 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4277 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4278 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4279 "_ATC_TCPL_TO_NOT_PEND\n");
4280 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4281 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4282 "ATC_GPA_MULTIPLE_HITS\n");
4283 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4284 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4285 "ATC_RCPL_TO_EMPTY_CNT\n");
4286 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4287 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4288 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4289 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4290 "ATC_IREQ_LESS_THAN_STU\n");
4291 }
4292
4293 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4294 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4295 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4296 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4297 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4298 }
4299
4300}
4301
4302static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4303{
4304 struct attn_route attn, *group_mask;
4305 int port = BP_PORT(bp);
4306 int index;
4307 u32 reg_addr;
4308 u32 val;
4309 u32 aeu_mask;
4310 bool global = false;
4311
4312
4313
4314 bnx2x_acquire_alr(bp);
4315
4316 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4317#ifndef BNX2X_STOP_ON_ERROR
4318 bp->recovery_state = BNX2X_RECOVERY_INIT;
4319 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4320
4321 bnx2x_int_disable(bp);
4322
4323
4324
4325#else
4326 bnx2x_panic();
4327#endif
4328 bnx2x_release_alr(bp);
4329 return;
4330 }
4331
4332 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4333 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4334 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4335 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4336 if (!CHIP_IS_E1x(bp))
4337 attn.sig[4] =
4338 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4339 else
4340 attn.sig[4] = 0;
4341
4342 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4343 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4344
4345 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4346 if (deasserted & (1 << index)) {
4347 group_mask = &bp->attn_group[index];
4348
4349 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4350 "%08x %08x %08x\n",
4351 index,
4352 group_mask->sig[0], group_mask->sig[1],
4353 group_mask->sig[2], group_mask->sig[3],
4354 group_mask->sig[4]);
4355
4356 bnx2x_attn_int_deasserted4(bp,
4357 attn.sig[4] & group_mask->sig[4]);
4358 bnx2x_attn_int_deasserted3(bp,
4359 attn.sig[3] & group_mask->sig[3]);
4360 bnx2x_attn_int_deasserted1(bp,
4361 attn.sig[1] & group_mask->sig[1]);
4362 bnx2x_attn_int_deasserted2(bp,
4363 attn.sig[2] & group_mask->sig[2]);
4364 bnx2x_attn_int_deasserted0(bp,
4365 attn.sig[0] & group_mask->sig[0]);
4366 }
4367 }
4368
4369 bnx2x_release_alr(bp);
4370
4371 if (bp->common.int_block == INT_BLOCK_HC)
4372 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4373 COMMAND_REG_ATTN_BITS_CLR);
4374 else
4375 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4376
4377 val = ~deasserted;
4378 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4379 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4380 REG_WR(bp, reg_addr, val);
4381
4382 if (~bp->attn_state & deasserted)
4383 BNX2X_ERR("IGU ERROR\n");
4384
4385 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4386 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4387
4388 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4389 aeu_mask = REG_RD(bp, reg_addr);
4390
4391 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4392 aeu_mask, deasserted);
4393 aeu_mask |= (deasserted & 0x3ff);
4394 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4395
4396 REG_WR(bp, reg_addr, aeu_mask);
4397 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4398
4399 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4400 bp->attn_state &= ~deasserted;
4401 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4402}
4403
4404static void bnx2x_attn_int(struct bnx2x *bp)
4405{
4406
4407 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4408 attn_bits);
4409 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4410 attn_bits_ack);
4411 u32 attn_state = bp->attn_state;
4412
4413
4414 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4415 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4416
4417 DP(NETIF_MSG_HW,
4418 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4419 attn_bits, attn_ack, asserted, deasserted);
4420
4421 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4422 BNX2X_ERR("BAD attention state\n");
4423
4424
4425 if (asserted)
4426 bnx2x_attn_int_asserted(bp, asserted);
4427
4428 if (deasserted)
4429 bnx2x_attn_int_deasserted(bp, deasserted);
4430}
4431
4432void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4433 u16 index, u8 op, u8 update)
4434{
4435 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4436
4437 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4438 igu_addr);
4439}
4440
4441static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4442{
4443
4444 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4445 mmiowb();
4446}
4447
4448#ifdef BCM_CNIC
4449static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4450 union event_ring_elem *elem)
4451{
4452 u8 err = elem->message.error;
4453
4454 if (!bp->cnic_eth_dev.starting_cid ||
4455 (cid < bp->cnic_eth_dev.starting_cid &&
4456 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4457 return 1;
4458
4459 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4460
4461 if (unlikely(err)) {
4462
4463 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4464 cid);
4465 bnx2x_panic_dump(bp);
4466 }
4467 bnx2x_cnic_cfc_comp(bp, cid, err);
4468 return 0;
4469}
4470#endif
4471
4472static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4473{
4474 struct bnx2x_mcast_ramrod_params rparam;
4475 int rc;
4476
4477 memset(&rparam, 0, sizeof(rparam));
4478
4479 rparam.mcast_obj = &bp->mcast_obj;
4480
4481 netif_addr_lock_bh(bp->dev);
4482
4483
4484 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4485
4486
4487 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4488 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4489 if (rc < 0)
4490 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4491 rc);
4492 }
4493
4494 netif_addr_unlock_bh(bp->dev);
4495}
4496
4497static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4498 union event_ring_elem *elem)
4499{
4500 unsigned long ramrod_flags = 0;
4501 int rc = 0;
4502 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4503 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4504
4505
4506 __set_bit(RAMROD_CONT, &ramrod_flags);
4507
4508 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4509 case BNX2X_FILTER_MAC_PENDING:
4510#ifdef BCM_CNIC
4511 if (cid == BNX2X_ISCSI_ETH_CID)
4512 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4513 else
4514#endif
4515 vlan_mac_obj = &bp->fp[cid].mac_obj;
4516
4517 break;
4518 case BNX2X_FILTER_MCAST_PENDING:
4519
4520
4521
4522 bnx2x_handle_mcast_eqe(bp);
4523 return;
4524 default:
4525 BNX2X_ERR("Unsupported classification command: %d\n",
4526 elem->message.data.eth_event.echo);
4527 return;
4528 }
4529
4530 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4531
4532 if (rc < 0)
4533 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4534 else if (rc > 0)
4535 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4536
4537}
4538
4539#ifdef BCM_CNIC
4540static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4541#endif
4542
4543static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4544{
4545 netif_addr_lock_bh(bp->dev);
4546
4547 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4548
4549
4550 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4551 bnx2x_set_storm_rx_mode(bp);
4552#ifdef BCM_CNIC
4553 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
