linux/drivers/scsi/mpt2sas/mpi/mpi2.h
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   1/*
   2 *  Copyright (c) 2000-2011 LSI Corporation.
   3 *
   4 *
   5 *           Name:  mpi2.h
   6 *          Title:  MPI Message independent structures and definitions
   7 *                  including System Interface Register Set and
   8 *                  scatter/gather formats.
   9 *  Creation Date:  June 21, 2006
  10 *
  11 *  mpi2.h Version:  02.00.22
  12 *
  13 *  Version History
  14 *  ---------------
  15 *
  16 *  Date      Version   Description
  17 *  --------  --------  ------------------------------------------------------
  18 *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  19 *  06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
  20 *  06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
  21 *  08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
  22 *                      Moved ReplyPostHostIndex register to offset 0x6C of the
  23 *                      MPI2_SYSTEM_INTERFACE_REGS and modified the define for
  24 *                      MPI2_REPLY_POST_HOST_INDEX_OFFSET.
  25 *                      Added union of request descriptors.
  26 *                      Added union of reply descriptors.
  27 *  10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
  28 *                      Added define for MPI2_VERSION_02_00.
  29 *                      Fixed the size of the FunctionDependent5 field in the
  30 *                      MPI2_DEFAULT_REPLY structure.
  31 *  12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
  32 *                      Removed the MPI-defined Fault Codes and extended the
  33 *                      product specific codes up to 0xEFFF.
  34 *                      Added a sixth key value for the WriteSequence register
  35 *                      and changed the flush value to 0x0.
  36 *                      Added message function codes for Diagnostic Buffer Post
  37 *                      and Diagnsotic Release.
  38 *                      New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
  39 *                      Moved MPI2_VERSION_UNION from mpi2_ioc.h.
  40 *  02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
  41 *  03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
  42 *  05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
  43 *                      Added #defines for marking a reply descriptor as unused.
  44 *  06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
  45 *  10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
  46 *                      Moved LUN field defines from mpi2_init.h.
  47 *  01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
  48 *  05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
  49 *                      In all request and reply descriptors, replaced VF_ID
  50 *                      field with MSIxIndex field.
  51 *                      Removed DevHandle field from
  52 *                      MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
  53 *                      bytes reserved.
  54 *                      Added RAID Accelerator functionality.
  55 *  07-30-09  02.00.13  Bumped MPI2_HEADER_VERSION_UNIT.
  56 *  10-28-09  02.00.14  Bumped MPI2_HEADER_VERSION_UNIT.
  57 *                      Added MSI-x index mask and shift for Reply Post Host
  58 *                      Index register.
  59 *                      Added function code for Host Based Discovery Action.
  60 *  02-10-10  02.00.15  Bumped MPI2_HEADER_VERSION_UNIT.
  61 *                      Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
  62 *                      Added defines for product-specific range of message
  63 *                      function codes, 0xF0 to 0xFF.
  64 *  05-12-10  02.00.16  Bumped MPI2_HEADER_VERSION_UNIT.
  65 *                      Added alternative defines for the SGE Direction bit.
  66 *  08-11-10  02.00.17  Bumped MPI2_HEADER_VERSION_UNIT.
  67 *  11-10-10  02.00.18  Bumped MPI2_HEADER_VERSION_UNIT.
  68 *                      Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
  69 *  02-23-11  02.00.19  Bumped MPI2_HEADER_VERSION_UNIT.
  70 *                      Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
  71 *  03-09-11  02.00.20  Bumped MPI2_HEADER_VERSION_UNIT.
  72 *  05-25-11  02.00.21  Bumped MPI2_HEADER_VERSION_UNIT.
  73 *  08-24-11  02.00.22  Bumped MPI2_HEADER_VERSION_UNIT.
  74 *  --------------------------------------------------------------------------
  75 */
  76
  77#ifndef MPI2_H
  78#define MPI2_H
  79
  80
  81/*****************************************************************************
  82*
  83*        MPI Version Definitions
  84*
  85*****************************************************************************/
  86
  87#define MPI2_VERSION_MAJOR                  (0x02)
  88#define MPI2_VERSION_MINOR                  (0x00)
  89#define MPI2_VERSION_MAJOR_MASK             (0xFF00)
  90#define MPI2_VERSION_MAJOR_SHIFT            (8)
  91#define MPI2_VERSION_MINOR_MASK             (0x00FF)
  92#define MPI2_VERSION_MINOR_SHIFT            (0)
  93#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
  94                                      MPI2_VERSION_MINOR)
  95
  96#define MPI2_VERSION_02_00                  (0x0200)
  97
  98/* versioning for this MPI header set */
  99#define MPI2_HEADER_VERSION_UNIT            (0x16)
 100#define MPI2_HEADER_VERSION_DEV             (0x00)
 101#define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 102#define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 103#define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 104#define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 105#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
 106
 107
 108/*****************************************************************************
 109*
 110*        IOC State Definitions
 111*
 112*****************************************************************************/
 113
 114#define MPI2_IOC_STATE_RESET               (0x00000000)
 115#define MPI2_IOC_STATE_READY               (0x10000000)
 116#define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
 117#define MPI2_IOC_STATE_FAULT               (0x40000000)
 118
 119#define MPI2_IOC_STATE_MASK                (0xF0000000)
 120#define MPI2_IOC_STATE_SHIFT               (28)
 121
 122/* Fault state range for prodcut specific codes */
 123#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
 124#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
 125
 126
 127/*****************************************************************************
 128*
 129*        System Interface Register Definitions
 130*
 131*****************************************************************************/
 132
 133typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
 134{
 135    U32         Doorbell;                   /* 0x00 */
 136    U32         WriteSequence;              /* 0x04 */
 137    U32         HostDiagnostic;             /* 0x08 */
 138    U32         Reserved1;                  /* 0x0C */
 139    U32         DiagRWData;                 /* 0x10 */
 140    U32         DiagRWAddressLow;           /* 0x14 */
 141    U32         DiagRWAddressHigh;          /* 0x18 */
 142    U32         Reserved2[5];               /* 0x1C */
 143    U32         HostInterruptStatus;        /* 0x30 */
 144    U32         HostInterruptMask;          /* 0x34 */
 145    U32         DCRData;                    /* 0x38 */
 146    U32         DCRAddress;                 /* 0x3C */
 147    U32         Reserved3[2];               /* 0x40 */
 148    U32         ReplyFreeHostIndex;         /* 0x48 */
 149    U32         Reserved4[8];               /* 0x4C */
 150    U32         ReplyPostHostIndex;         /* 0x6C */
 151    U32         Reserved5;                  /* 0x70 */
 152    U32         HCBSize;                    /* 0x74 */
 153    U32         HCBAddressLow;              /* 0x78 */
 154    U32         HCBAddressHigh;             /* 0x7C */
 155    U32         Reserved6[16];              /* 0x80 */
 156    U32         RequestDescriptorPostLow;   /* 0xC0 */
 157    U32         RequestDescriptorPostHigh;  /* 0xC4 */
 158    U32         Reserved7[14];              /* 0xC8 */
 159} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
 160  Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
 161
 162/*
 163 * Defines for working with the Doorbell register.
 164 */
 165#define MPI2_DOORBELL_OFFSET                    (0x00000000)
 166
 167/* IOC --> System values */
 168#define MPI2_DOORBELL_USED                      (0x08000000)
 169#define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
 170#define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
 171#define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
 172#define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
 173
 174/* System --> IOC values */
 175#define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
 176#define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
 177#define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
 178#define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
 179
 180
 181/*
 182 * Defines for the WriteSequence register
 183 */
 184#define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 185#define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
 186#define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 187#define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 188#define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 189#define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 190#define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 191#define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 192#define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 193
 194/*
 195 * Defines for the HostDiagnostic register
 196 */
 197#define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
 198
 199#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
 200#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
 201#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
 202
 203#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
 204#define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
 205#define MPI2_DIAG_HCB_MODE                      (0x00000100)
 206#define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
 207#define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
 208#define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
 209#define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
 210#define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
 211#define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
 212
 213/*
 214 * Offsets for DiagRWData and address
 215 */
 216#define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
 217#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
 218#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
 219
 220/*
 221 * Defines for the HostInterruptStatus register
 222 */
 223#define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
 224#define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
 225#define MPI2_HIS_IOP_DOORBELL_STATUS            MPI2_HIS_SYS2IOC_DB_STATUS
 226#define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
 227#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
 228#define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
 229#define MPI2_HIS_DOORBELL_INTERRUPT             MPI2_HIS_IOC2SYS_DB_STATUS
 230
 231/*
 232 * Defines for the HostInterruptMask register
 233 */
 234#define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
 235#define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
 236#define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
 237#define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
 238#define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
 239#define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
 240
 241/*
 242 * Offsets for DCRData and address
 243 */
 244#define MPI2_DCR_DATA_OFFSET                    (0x00000038)
 245#define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
 246
 247/*
 248 * Offset for the Reply Free Queue
 249 */
 250#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
 251
 252/*
 253 * Defines for the Reply Descriptor Post Queue
 254 */
 255#define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
 256#define MPI2_REPLY_POST_HOST_INDEX_MASK         (0x00FFFFFF)
 257#define MPI2_RPHI_MSIX_INDEX_MASK               (0xFF000000)
 258#define MPI2_RPHI_MSIX_INDEX_SHIFT              (24)
 259
 260/*
 261 * Defines for the HCBSize and address
 262 */
 263#define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
 264#define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
 265#define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
 266
 267#define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
 268#define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
 269
 270/*
 271 * Offsets for the Request Queue
 272 */
 273#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
 274#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
 275
 276
 277/*****************************************************************************
 278*
 279*        Message Descriptors
 280*
 281*****************************************************************************/
 282
 283/* Request Descriptors */
 284
 285/* Default Request Descriptor */
 286typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
 287{
 288    U8              RequestFlags;               /* 0x00 */
 289    U8              MSIxIndex;                  /* 0x01 */
 290    U16             SMID;                       /* 0x02 */
 291    U16             LMID;                       /* 0x04 */
 292    U16             DescriptorTypeDependent;    /* 0x06 */
 293} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 294  MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 295  Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 296
 297/* defines for the RequestFlags field */
 298#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 299#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 300#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 301#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 302#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 303#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 304
 305#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 306
 307
 308/* High Priority Request Descriptor */
 309typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
 310{
 311    U8              RequestFlags;               /* 0x00 */
 312    U8              MSIxIndex;                  /* 0x01 */
 313    U16             SMID;                       /* 0x02 */
 314    U16             LMID;                       /* 0x04 */
 315    U16             Reserved1;                  /* 0x06 */
 316} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 317  MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 318  Mpi2HighPriorityRequestDescriptor_t,
 319  MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 320
 321
 322/* SCSI IO Request Descriptor */
 323typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 324{
 325    U8              RequestFlags;               /* 0x00 */
 326    U8              MSIxIndex;                  /* 0x01 */
 327    U16             SMID;                       /* 0x02 */
 328    U16             LMID;                       /* 0x04 */
 329    U16             DevHandle;                  /* 0x06 */
 330} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 331  MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 332  Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 333
 334
 335/* SCSI Target Request Descriptor */
 336typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
 337{
 338    U8              RequestFlags;               /* 0x00 */
 339    U8              MSIxIndex;                  /* 0x01 */
 340    U16             SMID;                       /* 0x02 */
 341    U16             LMID;                       /* 0x04 */
 342    U16             IoIndex;                    /* 0x06 */
 343} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 344  MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 345  Mpi2SCSITargetRequestDescriptor_t,
 346  MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 347
 348
 349/* RAID Accelerator Request Descriptor */
 350typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 351    U8              RequestFlags;               /* 0x00 */
 352    U8              MSIxIndex;                  /* 0x01 */
 353    U16             SMID;                       /* 0x02 */
 354    U16             LMID;                       /* 0x04 */
 355    U16             Reserved;                   /* 0x06 */
 356} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 357  MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 358  Mpi2RAIDAcceleratorRequestDescriptor_t,
 359  MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 360
 361
 362/* union of Request Descriptors */
 363typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
 364{
 365    MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 366    MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 367    MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 368    MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 369    MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 370    U64                                         Words;
 371} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
 372  Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
 373
 374
 375/* Reply Descriptors */
 376
 377/* Default Reply Descriptor */
 378typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
 379{
 380    U8              ReplyFlags;                 /* 0x00 */
 381    U8              MSIxIndex;                  /* 0x01 */
 382    U16             DescriptorTypeDependent1;   /* 0x02 */
 383    U32             DescriptorTypeDependent2;   /* 0x04 */
 384} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 385  Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 386
 387/* defines for the ReplyFlags field */
 388#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 389#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 390#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 391#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 392#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 393#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 394#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 395
 396/* values for marking a reply descriptor as unused */
 397#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 398#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 399
 400/* Address Reply Descriptor */
 401typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
 402{
 403    U8              ReplyFlags;                 /* 0x00 */
 404    U8              MSIxIndex;                  /* 0x01 */
 405    U16             SMID;                       /* 0x02 */
 406    U32             ReplyFrameAddress;          /* 0x04 */
 407} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 408  Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 409
 410#define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
 411
 412
 413/* SCSI IO Success Reply Descriptor */
 414typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
 415{
 416    U8              ReplyFlags;                 /* 0x00 */
 417    U8              MSIxIndex;                  /* 0x01 */
 418    U16             SMID;                       /* 0x02 */
 419    U16             TaskTag;                    /* 0x04 */
 420    U16             Reserved1;                  /* 0x06 */
 421} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 422  MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 423  Mpi2SCSIIOSuccessReplyDescriptor_t,
 424  MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 425
 426
 427/* TargetAssist Success Reply Descriptor */
 428typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
 429{
 430    U8              ReplyFlags;                 /* 0x00 */
 431    U8              MSIxIndex;                  /* 0x01 */
 432    U16             SMID;                       /* 0x02 */
 433    U8              SequenceNumber;             /* 0x04 */
 434    U8              Reserved1;                  /* 0x05 */
 435    U16             IoIndex;                    /* 0x06 */
 436} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 437  MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 438  Mpi2TargetAssistSuccessReplyDescriptor_t,
 439  MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 440
 441
 442/* Target Command Buffer Reply Descriptor */
 443typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
 444{
 445    U8              ReplyFlags;                 /* 0x00 */
 446    U8              MSIxIndex;                  /* 0x01 */
 447    U8              VP_ID;                      /* 0x02 */
 448    U8              Flags;                      /* 0x03 */
 449    U16             InitiatorDevHandle;         /* 0x04 */
 450    U16             IoIndex;                    /* 0x06 */
 451} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 452  MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 453  Mpi2TargetCommandBufferReplyDescriptor_t,
 454  MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 455
 456/* defines for Flags field */
 457#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
 458
 459
 460/* RAID Accelerator Success Reply Descriptor */
 461typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 462    U8              ReplyFlags;                 /* 0x00 */
 463    U8              MSIxIndex;                  /* 0x01 */
 464    U16             SMID;                       /* 0x02 */
 465    U32             Reserved;                   /* 0x04 */
 466} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 467  MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 468  Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
 469  MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 470
 471
 472/* union of Reply Descriptors */
 473typedef union _MPI2_REPLY_DESCRIPTORS_UNION
 474{
 475    MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 476    MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 477    MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 478    MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR      TargetAssistSuccess;
 479    MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR     TargetCommandBuffer;
 480    MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR  RAIDAcceleratorSuccess;
 481    U64                                             Words;
 482} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 483  Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 484
 485
 486
 487/*****************************************************************************
 488*
 489*        Message Functions
 490*
 491*****************************************************************************/
 492
 493#define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 494#define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 495#define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 496#define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 497#define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 498#define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 499#define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 500#define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 501#define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 502#define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 503#define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 504#define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 505#define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 506#define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 507#define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 508#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 509#define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 510#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 511#define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 512#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 513#define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 514#define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 515#define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 516#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 517#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 518#define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator*/
 519/* Host Based Discovery Action */
 520#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F)
 521/* Power Management Control */
 522#define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30)
 523/* Send Host Message */
 524#define MPI2_FUNCTION_SEND_HOST_MESSAGE             (0x31)
 525/* beginning of product-specific range */
 526#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0)
 527/* end of product-specific range */
 528#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF)
 529
 530
 531
 532
 533/* Doorbell functions */
 534#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 535#define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 536
 537
 538/*****************************************************************************
 539*
 540*        IOC Status Values
 541*
 542*****************************************************************************/
 543
 544/* mask for IOCStatus status value */
 545#define MPI2_IOCSTATUS_MASK                     (0x7FFF)
 546
 547/****************************************************************************
 548*  Common IOCStatus values for all replies
 549****************************************************************************/
 550
 551#define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
 552#define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 553#define MPI2_IOCSTATUS_BUSY                         (0x0002)
 554#define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
 555#define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 556#define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
 557#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 558#define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
 559#define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
 560#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
 561
 562/****************************************************************************
 563*  Config IOCStatus values
 564****************************************************************************/
 565
 566#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 567#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 568#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 569#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 570#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 571#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 572
 573/****************************************************************************
 574*  SCSI IO Reply
 575****************************************************************************/
 576
 577#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 578#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 579#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 580#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 581#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 582#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 583#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 584#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 585#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 586#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
 587#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
 588#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
 589
 590/****************************************************************************
 591*  For use by SCSI Initiator and SCSI Target end-to-end data protection
 592****************************************************************************/
 593
 594#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
 595#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
 596#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
 597
 598/****************************************************************************
 599*  SCSI Target values
 600****************************************************************************/
 601
 602#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 603#define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
 604#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 605#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 606#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
 607#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
 608#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
 609#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
 610#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 611#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 612
 613/****************************************************************************
 614*  Serial Attached SCSI values
 615****************************************************************************/
 616
 617#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 618#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 619
 620/****************************************************************************
 621*  Diagnostic Buffer Post / Diagnostic Release values
 622****************************************************************************/
 623
 624#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
 625
 626/****************************************************************************
 627*  RAID Accelerator values
 628****************************************************************************/
 629
 630#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
 631
 632/****************************************************************************
 633*  IOCStatus flag to indicate that log info is available
 634****************************************************************************/
 635
 636#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
 637
 638/****************************************************************************
 639*  IOCLogInfo Types
 640****************************************************************************/
 641
 642#define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
 643#define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
 644#define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
 645#define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
 646#define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
 647#define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
 648#define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
 649#define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
 650
 651
 652/*****************************************************************************
 653*
 654*        Standard Message Structures
 655*
 656*****************************************************************************/
 657
 658/****************************************************************************
 659* Request Message Header for all request messages
 660****************************************************************************/
 661
 662typedef struct _MPI2_REQUEST_HEADER
 663{
 664    U16             FunctionDependent1;         /* 0x00 */
 665    U8              ChainOffset;                /* 0x02 */
 666    U8              Function;                   /* 0x03 */
 667    U16             FunctionDependent2;         /* 0x04 */
 668    U8              FunctionDependent3;         /* 0x06 */
 669    U8              MsgFlags;                   /* 0x07 */
 670    U8              VP_ID;                      /* 0x08 */
 671    U8              VF_ID;                      /* 0x09 */
 672    U16             Reserved1;                  /* 0x0A */
 673} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
 674  MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
 675
 676
 677/****************************************************************************
 678*  Default Reply
 679****************************************************************************/
 680
 681typedef struct _MPI2_DEFAULT_REPLY
 682{
 683    U16             FunctionDependent1;         /* 0x00 */
 684    U8              MsgLength;                  /* 0x02 */
 685    U8              Function;                   /* 0x03 */
 686    U16             FunctionDependent2;         /* 0x04 */
 687    U8              FunctionDependent3;         /* 0x06 */
 688    U8              MsgFlags;                   /* 0x07 */
 689    U8              VP_ID;                      /* 0x08 */
 690    U8              VF_ID;                      /* 0x09 */
 691    U16             Reserved1;                  /* 0x0A */
 692    U16             FunctionDependent5;         /* 0x0C */
 693    U16             IOCStatus;                  /* 0x0E */
 694    U32             IOCLogInfo;                 /* 0x10 */
 695} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
 696  MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
 697
 698
 699/* common version structure/union used in messages and configuration pages */
 700
 701typedef struct _MPI2_VERSION_STRUCT
 702{
 703    U8                      Dev;                        /* 0x00 */
 704    U8                      Unit;                       /* 0x01 */
 705    U8                      Minor;                      /* 0x02 */
 706    U8                      Major;                      /* 0x03 */
 707} MPI2_VERSION_STRUCT;
 708
 709typedef union _MPI2_VERSION_UNION
 710{
 711    MPI2_VERSION_STRUCT     Struct;
 712    U32                     Word;
 713} MPI2_VERSION_UNION;
 714
 715
 716/* LUN field defines, common to many structures */
 717#define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
 718#define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
 719#define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
 720#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
 721#define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
 722#define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
 723
 724
 725/*****************************************************************************
 726*
 727*        Fusion-MPT MPI Scatter Gather Elements
 728*
 729*****************************************************************************/
 730
 731/****************************************************************************
 732*  MPI Simple Element structures
 733****************************************************************************/
 734
 735typedef struct _MPI2_SGE_SIMPLE32
 736{
 737    U32                     FlagsLength;
 738    U32                     Address;
 739} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
 740  Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
 741
 742typedef struct _MPI2_SGE_SIMPLE64
 743{
 744    U32                     FlagsLength;
 745    U64                     Address;
 746} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
 747  Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
 748
 749typedef struct _MPI2_SGE_SIMPLE_UNION
 750{
 751    U32                     FlagsLength;
 752    union
 753    {
 754        U32                 Address32;
 755        U64                 Address64;
 756    } u;
 757} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 758  Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 759
 760
 761/****************************************************************************
 762*  MPI Chain Element structures
 763****************************************************************************/
 764
 765typedef struct _MPI2_SGE_CHAIN32
 766{
 767    U16                     Length;
 768    U8                      NextChainOffset;
 769    U8                      Flags;
 770    U32                     Address;
 771} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
 772  Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
 773
 774typedef struct _MPI2_SGE_CHAIN64
 775{
 776    U16                     Length;
 777    U8                      NextChainOffset;
 778    U8                      Flags;
 779    U64                     Address;
 780} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
 781  Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
 782
 783typedef struct _MPI2_SGE_CHAIN_UNION
 784{
 785    U16                     Length;
 786    U8                      NextChainOffset;
 787    U8                      Flags;
 788    union
 789    {
 790        U32                 Address32;
 791        U64                 Address64;
 792    } u;
 793} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 794  Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 795
 796
 797/****************************************************************************
 798*  MPI Transaction Context Element structures
 799****************************************************************************/
 800
 801typedef struct _MPI2_SGE_TRANSACTION32
 802{
 803    U8                      Reserved;
 804    U8                      ContextSize;
 805    U8                      DetailsLength;
 806    U8                      Flags;
 807    U32                     TransactionContext[1];
 808    U32                     TransactionDetails[1];
 809} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
 810  Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
 811
 812typedef struct _MPI2_SGE_TRANSACTION64
 813{
 814    U8                      Reserved;
 815    U8                      ContextSize;
 816    U8                      DetailsLength;
 817    U8                      Flags;
 818    U32                     TransactionContext[2];
 819    U32                     TransactionDetails[1];
 820} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
 821  Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
 822
 823typedef struct _MPI2_SGE_TRANSACTION96
 824{
 825    U8                      Reserved;
 826    U8                      ContextSize;
 827    U8                      DetailsLength;
 828    U8                      Flags;
 829    U32                     TransactionContext[3];
 830    U32                     TransactionDetails[1];
 831} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
 832  Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
 833
 834typedef struct _MPI2_SGE_TRANSACTION128
 835{
 836    U8                      Reserved;
 837    U8                      ContextSize;
 838    U8                      DetailsLength;
 839    U8                      Flags;
 840    U32                     TransactionContext[4];
 841    U32                     TransactionDetails[1];
 842} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
 843  Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
 844
 845typedef struct _MPI2_SGE_TRANSACTION_UNION
 846{
 847    U8                      Reserved;
 848    U8                      ContextSize;
 849    U8                      DetailsLength;
 850    U8                      Flags;
 851    union
 852    {
 853        U32                 TransactionContext32[1];
 854        U32                 TransactionContext64[2];
 855        U32                 TransactionContext96[3];
 856        U32                 TransactionContext128[4];
 857    } u;
 858    U32                     TransactionDetails[1];
 859} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
 860  Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
 861
 862
 863/****************************************************************************
 864*  MPI SGE union for IO SGL's
 865****************************************************************************/
 866
 867typedef struct _MPI2_MPI_SGE_IO_UNION
 868{
 869    union
 870    {
 871        MPI2_SGE_SIMPLE_UNION   Simple;
 872        MPI2_SGE_CHAIN_UNION    Chain;
 873    } u;
 874} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
 875  Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
 876
 877
 878/****************************************************************************
 879*  MPI SGE union for SGL's with Simple and Transaction elements
 880****************************************************************************/
 881
 882typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
 883{
 884    union
 885    {
 886        MPI2_SGE_SIMPLE_UNION       Simple;
 887        MPI2_SGE_TRANSACTION_UNION  Transaction;
 888    } u;
 889} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
 890  Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
 891
 892
 893/****************************************************************************
 894*  All MPI SGE types union
 895****************************************************************************/
 896
 897typedef struct _MPI2_MPI_SGE_UNION
 898{
 899    union
 900    {
 901        MPI2_SGE_SIMPLE_UNION       Simple;
 902        MPI2_SGE_CHAIN_UNION        Chain;
 903        MPI2_SGE_TRANSACTION_UNION  Transaction;
 904    } u;
 905} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
 906  Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
 907
 908
 909/****************************************************************************
 910*  MPI SGE field definition and masks
 911****************************************************************************/
 912
 913/* Flags field bit definitions */
 914
 915#define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
 916#define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
 917#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
 918#define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
 919#define MPI2_SGE_FLAGS_DIRECTION                (0x04)
 920#define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
 921#define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
 922
 923#define MPI2_SGE_FLAGS_SHIFT                    (24)
 924
 925#define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
 926#define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
 927
 928/* Element Type */
 929
 930#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
 931#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
 932#define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
 933#define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
 934
 935/* Address location */
 936
 937#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
 938
 939/* Direction */
 940
 941#define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
 942#define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
 943
 944#define MPI2_SGE_FLAGS_DEST                     (MPI2_SGE_FLAGS_IOC_TO_HOST)
 945#define MPI2_SGE_FLAGS_SOURCE                   (MPI2_SGE_FLAGS_HOST_TO_IOC)
 946
 947/* Address Size */
 948
 949#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 950#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 951
 952/* Context Size */
 953
 954#define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
 955#define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
 956#define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
 957#define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
 958
 959#define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
 960#define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
 961
 962/****************************************************************************
 963*  MPI SGE operation Macros
 964****************************************************************************/
 965
 966/* SIMPLE FlagsLength manipulations... */
 967#define MPI2_SGE_SET_FLAGS(f)          ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
 968#define MPI2_SGE_GET_FLAGS(f)          (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
 969#define MPI2_SGE_LENGTH(f)             ((f) & MPI2_SGE_LENGTH_MASK)
 970#define MPI2_SGE_CHAIN_LENGTH(f)       ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
 971
 972#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
 973
 974#define MPI2_pSGE_GET_FLAGS(psg)            MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
 975#define MPI2_pSGE_GET_LENGTH(psg)           MPI2_SGE_LENGTH((psg)->FlagsLength)
 976#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
 977
 978/* CAUTION - The following are READ-MODIFY-WRITE! */
 979#define MPI2_pSGE_SET_FLAGS(psg,f)      (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
 980#define MPI2_pSGE_SET_LENGTH(psg,l)     (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
 981
 982#define MPI2_GET_CHAIN_OFFSET(x)    ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
 983
 984
 985/*****************************************************************************
 986*
 987*        Fusion-MPT IEEE Scatter Gather Elements
 988*
 989*****************************************************************************/
 990
 991/****************************************************************************
 992*  IEEE Simple Element structures
 993****************************************************************************/
 994
 995typedef struct _MPI2_IEEE_SGE_SIMPLE32
 996{
 997    U32                     Address;
 998    U32                     FlagsLength;
 999} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1000  Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1001
1002typedef struct _MPI2_IEEE_SGE_SIMPLE64
1003{
1004    U64                     Address;
1005    U32                     Length;
1006    U16                     Reserved1;
1007    U8                      Reserved2;
1008    U8                      Flags;
1009} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1010  Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1011
1012typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1013{
1014    MPI2_IEEE_SGE_SIMPLE32  Simple32;
1015    MPI2_IEEE_SGE_SIMPLE64  Simple64;
1016} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1017  Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1018
1019
1020/****************************************************************************
1021*  IEEE Chain Element structures
1022****************************************************************************/
1023
1024typedef MPI2_IEEE_SGE_SIMPLE32  MPI2_IEEE_SGE_CHAIN32;
1025
1026typedef MPI2_IEEE_SGE_SIMPLE64  MPI2_IEEE_SGE_CHAIN64;
1027
1028typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1029{
1030    MPI2_IEEE_SGE_CHAIN32   Chain32;
1031    MPI2_IEEE_SGE_CHAIN64   Chain64;
1032} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1033  Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1034
1035
1036/****************************************************************************
1037*  All IEEE SGE types union
1038****************************************************************************/
1039
1040typedef struct _MPI2_IEEE_SGE_UNION
1041{
1042    union
1043    {
1044        MPI2_IEEE_SGE_SIMPLE_UNION  Simple;
1045        MPI2_IEEE_SGE_CHAIN_UNION   Chain;
1046    } u;
1047} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1048  Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1049
1050
1051/****************************************************************************
1052*  IEEE SGE field definitions and masks
1053****************************************************************************/
1054
1055/* Flags field bit definitions */
1056
1057#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1058
1059#define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1060
1061#define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1062
1063/* Element Type */
1064
1065#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1066#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1067
1068/* Data Location Address Space */
1069
1070#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1071#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1072                                                /* IEEE Simple Element only */
1073#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1074                                                /* IEEE Simple Element only */
1075#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1076#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1077                                                /* IEEE Simple Element only */
1078#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR   (0x03)
1079                                                /* IEEE Chain Element only */
1080#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR   \
1081        (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1082
1083/****************************************************************************
1084*  IEEE SGE operation Macros
1085****************************************************************************/
1086
1087/* SIMPLE FlagsLength manipulations... */
1088#define MPI2_IEEE32_SGE_SET_FLAGS(f)     ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1089#define MPI2_IEEE32_SGE_GET_FLAGS(f)     (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1090#define MPI2_IEEE32_SGE_LENGTH(f)        ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1091
1092#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)      (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1093
1094#define MPI2_IEEE32_pSGE_GET_FLAGS(psg)             MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1095#define MPI2_IEEE32_pSGE_GET_LENGTH(psg)            MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1096#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l)  (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1097
1098/* CAUTION - The following are READ-MODIFY-WRITE! */
1099#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f)    (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1100#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l)   (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1101
1102
1103
1104
1105/*****************************************************************************
1106*
1107*        Fusion-MPT MPI/IEEE Scatter Gather Unions
1108*
1109*****************************************************************************/
1110
1111typedef union _MPI2_SIMPLE_SGE_UNION
1112{
1113    MPI2_SGE_SIMPLE_UNION       MpiSimple;
1114    MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1115} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1116  Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1117
1118
1119typedef union _MPI2_SGE_IO_UNION
1120{
1121    MPI2_SGE_SIMPLE_UNION       MpiSimple;
1122    MPI2_SGE_CHAIN_UNION        MpiChain;
1123    MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1124    MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
1125} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1126  Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1127
1128
1129/****************************************************************************
1130*
1131*  Values for SGLFlags field, used in many request messages with an SGL
1132*
1133****************************************************************************/
1134
1135/* values for MPI SGL Data Location Address Space subfield */
1136#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1137#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1138#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1139#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1140#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1141/* values for SGL Type subfield */
1142#define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1143#define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1144#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1145#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1146
1147
1148#endif
1149
1150
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