/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/vmalloc.h>
#include <linux/string.h>
#include <linux/in.h>
#include <linux/interrupt.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/sctp.h>
#include <linux/pkt_sched.h>
#include <linux/ipv6.h>
#include <linux/slab.h>
#include <net/checksum.h>
#include <net/ip6_checksum.h>
#include <linux/ethtool.h>
#include <linux/if.h>
#include <linux/if_vlan.h>
#include <linux/prefetch.h>
#include <scsi/fc/fc_fcoe.h>

#include "ixgbe.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb_82599.h"
#include "ixgbe_sriov.h"

char ixgbe_driver_name[] = "ixgbe";
static const char ixgbe_driver_string[] =
                              "Intel(R) 10 Gigabit PCI Express Network Driver";
char ixgbe_default_device_descr[] =
                              "Intel(R) 10 Gigabit Network Connection";
#define MAJ 3
#define MIN 6
#define BUILD 7
#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
        __stringify(BUILD) "-k"
const char ixgbe_driver_version[] = DRV_VERSION;
static const char ixgbe_copyright[] =
                                "Copyright (c) 1999-2012 Intel Corporation.";

static const struct ixgbe_info *ixgbe_info_tbl[] = {
        [board_82598] = &ixgbe_82598_info,
        [board_82599] = &ixgbe_82599_info,
        [board_X540] = &ixgbe_X540_info,
};

/* ixgbe_pci_tbl - PCI Device ID Table
 *
 * Wildcard entries (PCI_ANY_ID) should come last
 * Last entry must be all 0s
 *
 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
 *   Class, Class Mask, private data (not used) }
 */
static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
        /* required last entry */
        {0, }
};
MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);

#ifdef CONFIG_IXGBE_DCA
static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
                            void *p);
static struct notifier_block dca_notifier = {
        .notifier_call = ixgbe_notify_dca,
        .next          = NULL,
        .priority      = 0
};
#endif

#ifdef CONFIG_PCI_IOV
static unsigned int max_vfs;
module_param(max_vfs, uint, 0);
MODULE_PARM_DESC(max_vfs,
                 "Maximum number of virtual functions to allocate per physical function");
#endif /* CONFIG_PCI_IOV */

MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

#define DEFAULT_DEBUG_LEVEL_SHIFT 3

static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
{
        if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
            !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
                schedule_work(&adapter->service_task);
}

static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
{
        BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));

        /* flush memory to make sure state is correct before next watchdog */
        smp_mb__before_clear_bit();
        clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
}

struct ixgbe_reg_info {
        u32 ofs;
        char *name;
};

static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {

        /* General Registers */
        {IXGBE_CTRL, "CTRL"},
        {IXGBE_STATUS, "STATUS"},
        {IXGBE_CTRL_EXT, "CTRL_EXT"},

        /* Interrupt Registers */
        {IXGBE_EICR, "EICR"},

        /* RX Registers */
        {IXGBE_SRRCTL(0), "SRRCTL"},
        {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
        {IXGBE_RDLEN(0), "RDLEN"},
        {IXGBE_RDH(0), "RDH"},
        {IXGBE_RDT(0), "RDT"},
        {IXGBE_RXDCTL(0), "RXDCTL"},
        {IXGBE_RDBAL(0), "RDBAL"},
        {IXGBE_RDBAH(0), "RDBAH"},

        /* TX Registers */
        {IXGBE_TDBAL(0), "TDBAL"},
        {IXGBE_TDBAH(0), "TDBAH"},
        {IXGBE_TDLEN(0), "TDLEN"},
        {IXGBE_TDH(0), "TDH"},
        {IXGBE_TDT(0), "TDT"},
        {IXGBE_TXDCTL(0), "TXDCTL"},

        /* List Terminator */
        {}
};


/*
 * ixgbe_regdump - register printout routine
 */
static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
{
        int i = 0, j = 0;
        char rname[16];
        u32 regs[64];

        switch (reginfo->ofs) {
        case IXGBE_SRRCTL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
                break;
        case IXGBE_DCA_RXCTRL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
                break;
        case IXGBE_RDLEN(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
                break;
        case IXGBE_RDH(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
                break;
        case IXGBE_RDT(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
                break;
        case IXGBE_RXDCTL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
                break;
        case IXGBE_RDBAL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
                break;
        case IXGBE_RDBAH(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
                break;
        case IXGBE_TDBAL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
                break;
        case IXGBE_TDBAH(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
                break;
        case IXGBE_TDLEN(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
                break;
        case IXGBE_TDH(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
                break;
        case IXGBE_TDT(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
                break;
        case IXGBE_TXDCTL(0):
                for (i = 0; i < 64; i++)
                        regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
                break;
        default:
                pr_info("%-15s %08x\n", reginfo->name,
                        IXGBE_READ_REG(hw, reginfo->ofs));
                return;
        }

        for (i = 0; i < 8; i++) {
                snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
                pr_err("%-15s", rname);
                for (j = 0; j < 8; j++)
                        pr_cont(" %08x", regs[i*8+j]);
                pr_cont("\n");
        }

}

/*
 * ixgbe_dump - Print registers, tx-rings and rx-rings
 */
static void ixgbe_dump(struct ixgbe_adapter *adapter)
{
        struct net_device *netdev = adapter->netdev;
        struct ixgbe_hw *hw = &adapter->hw;
        struct ixgbe_reg_info *reginfo;
        int n = 0;
        struct ixgbe_ring *tx_ring;
        struct ixgbe_tx_buffer *tx_buffer_info;
        union ixgbe_adv_tx_desc *tx_desc;
        struct my_u0 { u64 a; u64 b; } *u0;
        struct ixgbe_ring *rx_ring;
        union ixgbe_adv_rx_desc *rx_desc;
        struct ixgbe_rx_buffer *rx_buffer_info;
        u32 staterr;
        int i = 0;

        if (!netif_msg_hw(adapter))
                return;

        /* Print netdevice Info */
        if (netdev) {
                dev_info(&adapter->pdev->dev, "Net device Info\n");
                pr_info("Device Name     state            "
                        "trans_start      last_rx\n");
                pr_info("%-15s %016lX %016lX %016lX\n",
                        netdev->name,
                        netdev->state,
                        netdev->trans_start,
                        netdev->last_rx);
        }

        /* Print Registers */
        dev_info(&adapter->pdev->dev, "Register Dump\n");
        pr_info(" Register Name   Value\n");
        for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
             reginfo->name; reginfo++) {
                ixgbe_regdump(hw, reginfo);
        }

        /* Print TX Ring Summary */
        if (!netdev || !netif_running(netdev))
                goto exit;

        dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
        pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
        for (n = 0; n < adapter->num_tx_queues; n++) {
                tx_ring = adapter->tx_ring[n];
                tx_buffer_info =
                        &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
                pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
                           n, tx_ring->next_to_use, tx_ring->next_to_clean,
                           (u64)tx_buffer_info->dma,
                           tx_buffer_info->length,
                           tx_buffer_info->next_to_watch,
                           (u64)tx_buffer_info->time_stamp);
        }

        /* Print TX Rings */
        if (!netif_msg_tx_done(adapter))
                goto rx_ring_summary;

        dev_info(&adapter->pdev->dev, "TX Rings Dump\n");

        /* Transmit Descriptor Formats
         *
         * Advanced Transmit Descriptor
         *   +--------------------------------------------------------------+
         * 0 |         Buffer Address [63:0]                                |
         *   +--------------------------------------------------------------+
         * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
         *   +--------------------------------------------------------------+
         *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
         */

        for (n = 0; n < adapter->num_tx_queues; n++) {
                tx_ring = adapter->tx_ring[n];
                pr_info("------------------------------------\n");
                pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
                pr_info("------------------------------------\n");
                pr_info("T [desc]     [address 63:0  ] "
                        "[PlPOIdStDDt Ln] [bi->dma       ] "
                        "leng  ntw timestamp        bi->skb\n");

                for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
                        tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
                        tx_buffer_info = &tx_ring->tx_buffer_info[i];
                        u0 = (struct my_u0 *)tx_desc;
                        pr_info("T [0x%03X]    %016llX %016llX %016llX"
                                " %04X  %p %016llX %p", i,
                                le64_to_cpu(u0->a),
                                le64_to_cpu(u0->b),
                                (u64)tx_buffer_info->dma,
                                tx_buffer_info->length,
                                tx_buffer_info->next_to_watch,
                                (u64)tx_buffer_info->time_stamp,
                                tx_buffer_info->skb);
                        if (i == tx_ring->next_to_use &&
                                i == tx_ring->next_to_clean)
                                pr_cont(" NTC/U\n");
                        else if (i == tx_ring->next_to_use)
                                pr_cont(" NTU\n");
                        else if (i == tx_ring->next_to_clean)
                                pr_cont(" NTC\n");
                        else
                                pr_cont("\n");

                        if (netif_msg_pktdata(adapter) &&
                                tx_buffer_info->dma != 0)
                                print_hex_dump(KERN_INFO, "",
                                        DUMP_PREFIX_ADDRESS, 16, 1,
                                        phys_to_virt(tx_buffer_info->dma),
                                        tx_buffer_info->length, true);
                }
        }

        /* Print RX Rings Summary */
rx_ring_summary:
        dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
        pr_info("Queue [NTU] [NTC]\n");
        for (n = 0; n < adapter->num_rx_queues; n++) {
                rx_ring = adapter->rx_ring[n];
                pr_info("%5d %5X %5X\n",
                        n, rx_ring->next_to_use, rx_ring->next_to_clean);
        }

        /* Print RX Rings */
        if (!netif_msg_rx_status(adapter))
                goto exit;

        dev_info(&adapter->pdev->dev, "RX Rings Dump\n");

        /* Advanced Receive Descriptor (Read) Format
         *    63                                           1        0
         *    +-----------------------------------------------------+
         *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
         *    +----------------------------------------------+------+
         *  8 |       Header Buffer Address [63:1]           |  DD  |
         *    +-----------------------------------------------------+
         *
         *
         * Advanced Receive Descriptor (Write-Back) Format
         *
         *   63       48 47    32 31  30      21 20 16 15   4 3     0
         *   +------------------------------------------------------+
         * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
         *   | Checksum   Ident  |   |           |    | Type | Type |
         *   +------------------------------------------------------+
         * 8 | VLAN Tag | Length | Extended Error | Extended Status |
         *   +------------------------------------------------------+
         *   63       48 47    32 31            20 19               0
         */
        for (n = 0; n < adapter->num_rx_queues; n++) {
                rx_ring = adapter->rx_ring[n];
                pr_info("------------------------------------\n");
                pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
                pr_info("------------------------------------\n");
                pr_info("R  [desc]      [ PktBuf     A0] "
                        "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
                        "<-- Adv Rx Read format\n");
                pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
                        "[vl er S cks ln] ---------------- [bi->skb] "
                        "<-- Adv Rx Write-Back format\n");

                for (i = 0; i < rx_ring->count; i++) {
                        rx_buffer_info = &rx_ring->rx_buffer_info[i];
                        rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
                        u0 = (struct my_u0 *)rx_desc;
                        staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
                        if (staterr & IXGBE_RXD_STAT_DD) {
                                /* Descriptor Done */
                                pr_info("RWB[0x%03X]     %016llX "
                                        "%016llX ---------------- %p", i,
                                        le64_to_cpu(u0->a),
                                        le64_to_cpu(u0->b),
                                        rx_buffer_info->skb);
                        } else {
                                pr_info("R  [0x%03X]     %016llX "
                                        "%016llX %016llX %p", i,
                                        le64_to_cpu(u0->a),
                                        le64_to_cpu(u0->b),
                                        (u64)rx_buffer_info->dma,
                                        rx_buffer_info->skb);

                                if (netif_msg_pktdata(adapter)) {
                                        print_hex_dump(KERN_INFO, "",
                                           DUMP_PREFIX_ADDRESS, 16, 1,
                                           phys_to_virt(rx_buffer_info->dma),
                                           rx_ring->rx_buf_len, true);

                                        if (rx_ring->rx_buf_len
                                                < IXGBE_RXBUFFER_2K)
                                                print_hex_dump(KERN_INFO, "",
                                                  DUMP_PREFIX_ADDRESS, 16, 1,
                                                  phys_to_virt(
                                                    rx_buffer_info->page_dma +
                                                    rx_buffer_info->page_offset
                                                  ),
                                                  PAGE_SIZE/2, true);
                                }
                        }

                        if (i == rx_ring->next_to_use)
                                pr_cont(" NTU\n");
                        else if (i == rx_ring->next_to_clean)
                                pr_cont(" NTC\n");
                        else
                                pr_cont("\n");

                }
        }

exit:
        return;
}

static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
{
        u32 ctrl_ext;

        /* Let firmware take over control of h/w */
        ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
                        ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
}

static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
{
        u32 ctrl_ext;

        /* Let firmware know the driver has taken over */
        ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
                        ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
}

/*
 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 * @adapter: pointer to adapter struct
 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 * @queue: queue to map the corresponding interrupt to
 * @msix_vector: the vector to map to the corresponding queue
 *
 */
static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
                           u8 queue, u8 msix_vector)
{
        u32 ivar, index;
        struct ixgbe_hw *hw = &adapter->hw;
        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                msix_vector |= IXGBE_IVAR_ALLOC_VAL;
                if (direction == -1)
                        direction = 0;
                index = (((direction * 64) + queue) >> 2) & 0x1F;
                ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
                ivar &= ~(0xFF << (8 * (queue & 0x3)));
                ivar |= (msix_vector << (8 * (queue & 0x3)));
                IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                if (direction == -1) {
                        /* other causes */
                        msix_vector |= IXGBE_IVAR_ALLOC_VAL;
                        index = ((queue & 1) * 8);
                        ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
                        ivar &= ~(0xFF << index);
                        ivar |= (msix_vector << index);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
                        break;
                } else {
                        /* tx or rx causes */
                        msix_vector |= IXGBE_IVAR_ALLOC_VAL;
                        index = ((16 * (queue & 1)) + (8 * direction));
                        ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
                        ivar &= ~(0xFF << index);
                        ivar |= (msix_vector << index);
                        IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
                        break;
                }
        default:
                break;
        }
}

static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
                                          u64 qmask)
{
        u32 mask;

        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82598EB:
                mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
                mask = (qmask >> 32);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
                break;
        default:
                break;
        }
}

static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
                                           struct ixgbe_tx_buffer *tx_buffer)
{
        if (tx_buffer->dma) {
                if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
                        dma_unmap_page(ring->dev,
                                       tx_buffer->dma,
                                       tx_buffer->length,
                                       DMA_TO_DEVICE);
                else
                        dma_unmap_single(ring->dev,
                                         tx_buffer->dma,
                                         tx_buffer->length,
                                         DMA_TO_DEVICE);
        }
        tx_buffer->dma = 0;
}

void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
                                      struct ixgbe_tx_buffer *tx_buffer_info)
{
        ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
        if (tx_buffer_info->skb)
                dev_kfree_skb_any(tx_buffer_info->skb);
        tx_buffer_info->skb = NULL;
        /* tx_buffer_info must be completely set up in the transmit path */
}

static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        struct ixgbe_hw_stats *hwstats = &adapter->stats;
        u32 data = 0;
        u32 xoff[8] = {0};
        int i;

        if ((hw->fc.current_mode == ixgbe_fc_full) ||
            (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
                switch (hw->mac.type) {
                case ixgbe_mac_82598EB:
                        data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
                        break;
                default:
                        data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
                }
                hwstats->lxoffrxc += data;

                /* refill credits (no tx hang) if we received xoff */
                if (!data)
                        return;

                for (i = 0; i < adapter->num_tx_queues; i++)
                        clear_bit(__IXGBE_HANG_CHECK_ARMED,
                                  &adapter->tx_ring[i]->state);
                return;
        } else if (!(adapter->dcb_cfg.pfc_mode_enable))
                return;

        /* update stats for each tc, only valid with PFC enabled */
        for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
                switch (hw->mac.type) {
                case ixgbe_mac_82598EB:
                        xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
                        break;
                default:
                        xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
                }
                hwstats->pxoffrxc[i] += xoff[i];
        }

        /* disarm tx queues that have received xoff frames */
        for (i = 0; i < adapter->num_tx_queues; i++) {
                struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
                u8 tc = tx_ring->dcb_tc;

                if (xoff[tc])
                        clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
        }
}

static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
{
        return ring->tx_stats.completed;
}

static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
{
        struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
        struct ixgbe_hw *hw = &adapter->hw;

        u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
        u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));

        if (head != tail)
                return (head < tail) ?
                        tail - head : (tail + ring->count - head);

        return 0;
}

static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
{
        u32 tx_done = ixgbe_get_tx_completed(tx_ring);
        u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
        u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
        bool ret = false;

        clear_check_for_tx_hang(tx_ring);

        /*
         * Check for a hung queue, but be thorough. This verifies
         * that a transmit has been completed since the previous
         * check AND there is at least one packet pending. The
         * ARMED bit is set to indicate a potential hang. The
         * bit is cleared if a pause frame is received to remove
         * false hang detection due to PFC or 802.3x frames. By
         * requiring this to fail twice we avoid races with
         * pfc clearing the ARMED bit and conditions where we
         * run the check_tx_hang logic with a transmit completion
         * pending but without time to complete it yet.
         */
        if ((tx_done_old == tx_done) && tx_pending) {
                /* make sure it is true for two checks in a row */
                ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
                                       &tx_ring->state);
        } else {
                /* update completed stats and continue */
                tx_ring->tx_stats.tx_done_old = tx_done;
                /* reset the countdown */
                clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
        }

        return ret;
}

/**
 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 * @adapter: driver private struct
 **/
static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
{

        /* Do the reset outside of interrupt context */
        if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
                adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
                ixgbe_service_event_schedule(adapter);
        }
}

/**
 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 * @q_vector: structure containing interrupt and ring information
 * @tx_ring: tx ring to clean
 **/
static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
                               struct ixgbe_ring *tx_ring)
{
        struct ixgbe_adapter *adapter = q_vector->adapter;
        struct ixgbe_tx_buffer *tx_buffer;
        union ixgbe_adv_tx_desc *tx_desc;
        unsigned int total_bytes = 0, total_packets = 0;
        unsigned int budget = q_vector->tx.work_limit;
        u16 i = tx_ring->next_to_clean;

        tx_buffer = &tx_ring->tx_buffer_info[i];
        tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);

        for (; budget; budget--) {
                union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;

                /* if next_to_watch is not set then there is no work pending */
                if (!eop_desc)
                        break;

                /* if DD is not set pending work has not been completed */
                if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
                        break;

                /* count the packet as being completed */
                tx_ring->tx_stats.completed++;

                /* clear next_to_watch to prevent false hangs */
                tx_buffer->next_to_watch = NULL;

                /* prevent any other reads prior to eop_desc being verified */
                rmb();

                do {
                        ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
                        tx_desc->wb.status = 0;
                        if (likely(tx_desc == eop_desc)) {
                                eop_desc = NULL;
                                dev_kfree_skb_any(tx_buffer->skb);
                                tx_buffer->skb = NULL;

                                total_bytes += tx_buffer->bytecount;
                                total_packets += tx_buffer->gso_segs;
                        }

                        tx_buffer++;
                        tx_desc++;
                        i++;
                        if (unlikely(i == tx_ring->count)) {
                                i = 0;

                                tx_buffer = tx_ring->tx_buffer_info;
                                tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
                        }

                } while (eop_desc);
        }

        tx_ring->next_to_clean = i;
        u64_stats_update_begin(&tx_ring->syncp);
        tx_ring->stats.bytes += total_bytes;
        tx_ring->stats.packets += total_packets;
        u64_stats_update_end(&tx_ring->syncp);
        q_vector->tx.total_bytes += total_bytes;
        q_vector->tx.total_packets += total_packets;

        if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
                /* schedule immediate reset if we believe we hung */
                struct ixgbe_hw *hw = &adapter->hw;
                tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
                e_err(drv, "Detected Tx Unit Hang\n"
                        "  Tx Queue             <%d>\n"
                        "  TDH, TDT             <%x>, <%x>\n"
                        "  next_to_use          <%x>\n"
                        "  next_to_clean        <%x>\n"
                        "tx_buffer_info[next_to_clean]\n"
                        "  time_stamp           <%lx>\n"
                        "  jiffies              <%lx>\n",
                        tx_ring->queue_index,
                        IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
                        IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
                        tx_ring->next_to_use, i,
                        tx_ring->tx_buffer_info[i].time_stamp, jiffies);

                netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);

                e_info(probe,
                       "tx hang %d detected on queue %d, resetting adapter\n",
                        adapter->tx_timeout_count + 1, tx_ring->queue_index);

                /* schedule immediate reset if we believe we hung */
                ixgbe_tx_timeout_reset(adapter);

                /* the adapter is about to reset, no point in enabling stuff */
                return true;
        }

#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
        if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
                     (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
                /* Make sure that anybody stopping the queue after this
                 * sees the new next_to_clean.
                 */
                smp_mb();
                if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
                    !test_bit(__IXGBE_DOWN, &adapter->state)) {
                        netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
                        ++tx_ring->tx_stats.restart_queue;
                }
        }

        return !!budget;
}

#ifdef CONFIG_IXGBE_DCA
static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
                                struct ixgbe_ring *rx_ring,
                                int cpu)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 rxctrl;
        u8 reg_idx = rx_ring->reg_idx;

        rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
                rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
                rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
                           IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
                break;
        default:
                break;
        }
        rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
        rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
        rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
        IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
}

static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
                                struct ixgbe_ring *tx_ring,
                                int cpu)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 txctrl;
        u8 reg_idx = tx_ring->reg_idx;

        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
                txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
                txctrl |= dca3_get_tag(tx_ring->dev, cpu);
                txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
                txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
                txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
                           IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
                txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
                break;
        default:
                break;
        }
}

static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
{
        struct ixgbe_adapter *adapter = q_vector->adapter;
        struct ixgbe_ring *ring;
        int cpu = get_cpu();

        if (q_vector->cpu == cpu)
                goto out_no_update;

        for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
                ixgbe_update_tx_dca(adapter, ring, cpu);

        for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
                ixgbe_update_rx_dca(adapter, ring, cpu);

        q_vector->cpu = cpu;
out_no_update:
        put_cpu();
}

static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
{
        int num_q_vectors;
        int i;

        if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
                return;

        /* always use CB2 mode, difference is masked in the CB driver */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);

        if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
                num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
        else
                num_q_vectors = 1;

        for (i = 0; i < num_q_vectors; i++) {
                adapter->q_vector[i]->cpu = -1;
                ixgbe_update_dca(adapter->q_vector[i]);
        }
}

static int __ixgbe_notify_dca(struct device *dev, void *data)
{
        struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
        unsigned long event = *(unsigned long *)data;

        if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
                return 0;

        switch (event) {
        case DCA_PROVIDER_ADD:
                /* if we're already enabled, don't do it again */
                if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
                        break;
                if (dca_add_requester(dev) == 0) {
                        adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
                        ixgbe_setup_dca(adapter);
                        break;
                }
                /* Fall Through since DCA is disabled. */
        case DCA_PROVIDER_REMOVE:
                if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
                        dca_remove_requester(dev);
                        adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
                }
                break;
        }

        return 0;
}
#endif /* CONFIG_IXGBE_DCA */

static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
                                 struct sk_buff *skb)
{
        skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
}

/**
 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
 * @adapter: address of board private structure
 * @rx_desc: advanced rx descriptor
 *
 * Returns : true if it is FCoE pkt

 */
static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
                                    union ixgbe_adv_rx_desc *rx_desc)
{
        __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;

        return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
               ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
                (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
                             IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
}

/**
 * ixgbe_receive_skb - Send a completed packet up the stack
 * @adapter: board private structure
 * @skb: packet to send up
 * @status: hardware indication of status of receive
 * @rx_ring: rx descriptor ring (for a specific queue) to setup
 * @rx_desc: rx descriptor
 **/
static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
                              struct sk_buff *skb, u8 status,
                              struct ixgbe_ring *ring,
                              union ixgbe_adv_rx_desc *rx_desc)
{
        struct ixgbe_adapter *adapter = q_vector->adapter;
        struct napi_struct *napi = &q_vector->napi;
        bool is_vlan = (status & IXGBE_RXD_STAT_VP);
        u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);

        if (is_vlan && (tag & VLAN_VID_MASK))
                __vlan_hwaccel_put_tag(skb, tag);

        if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
                napi_gro_receive(napi, skb);
        else
                netif_rx(skb);
}

/**
 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 * @adapter: address of board private structure
 * @status_err: hardware indication of status of receive
 * @skb: skb currently being received and modified
 * @status_err: status error value of last descriptor in packet
 **/
static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
                                     union ixgbe_adv_rx_desc *rx_desc,
                                     struct sk_buff *skb,
                                     u32 status_err)
{
        skb->ip_summed = CHECKSUM_NONE;

        /* Rx csum disabled */
        if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
                return;

        /* if IP and error */
        if ((status_err & IXGBE_RXD_STAT_IPCS) &&
            (status_err & IXGBE_RXDADV_ERR_IPE)) {
                adapter->hw_csum_rx_error++;
                return;
        }

        if (!(status_err & IXGBE_RXD_STAT_L4CS))
                return;

        if (status_err & IXGBE_RXDADV_ERR_TCPE) {
                u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;

                /*
                 * 82599 errata, UDP frames with a 0 checksum can be marked as
                 * checksum errors.
                 */
                if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
                    (adapter->hw.mac.type == ixgbe_mac_82599EB))
                        return;

                adapter->hw_csum_rx_error++;
                return;
        }

        /* It must be a TCP or UDP packet with a valid checksum */
        skb->ip_summed = CHECKSUM_UNNECESSARY;
}

static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
{
        /*
         * Force memory writes to complete before letting h/w
         * know there are new descriptors to fetch.  (Only
         * applicable for weak-ordered memory model archs,
         * such as IA-64).
         */
        wmb();
        writel(val, rx_ring->tail);
}

/**
 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 * @rx_ring: ring to place buffers on
 * @cleaned_count: number of buffers to replace
 **/
void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
{
        union ixgbe_adv_rx_desc *rx_desc;
        struct ixgbe_rx_buffer *bi;
        struct sk_buff *skb;
        u16 i = rx_ring->next_to_use;

        /* do nothing if no valid netdev defined */
        if (!rx_ring->netdev)
                return;

        while (cleaned_count--) {
                rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
                bi = &rx_ring->rx_buffer_info[i];
                skb = bi->skb;

                if (!skb) {
                        skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
                                                        rx_ring->rx_buf_len);
                        if (!skb) {
                                rx_ring->rx_stats.alloc_rx_buff_failed++;
                                goto no_buffers;
                        }
                        /* initialize queue mapping */
                        skb_record_rx_queue(skb, rx_ring->queue_index);
                        bi->skb = skb;
                }

                if (!bi->dma) {
                        bi->dma = dma_map_single(rx_ring->dev,
                                                 skb->data,
                                                 rx_ring->rx_buf_len,
                                                 DMA_FROM_DEVICE);
                        if (dma_mapping_error(rx_ring->dev, bi->dma)) {
                                rx_ring->rx_stats.alloc_rx_buff_failed++;
                                bi->dma = 0;
                                goto no_buffers;
                        }
                }

                if (ring_is_ps_enabled(rx_ring)) {
                        if (!bi->page) {
                                bi->page = alloc_page(GFP_ATOMIC | __GFP_COLD);
                                if (!bi->page) {
                                        rx_ring->rx_stats.alloc_rx_page_failed++;
                                        goto no_buffers;
                                }
                        }

                        if (!bi->page_dma) {
                                /* use a half page if we're re-using */
                                bi->page_offset ^= PAGE_SIZE / 2;
                                bi->page_dma = dma_map_page(rx_ring->dev,
                                                            bi->page,
                                                            bi->page_offset,
                                                            PAGE_SIZE / 2,
                                                            DMA_FROM_DEVICE);
                                if (dma_mapping_error(rx_ring->dev,
                                                      bi->page_dma)) {
                                        rx_ring->rx_stats.alloc_rx_page_failed++;
                                        bi->page_dma = 0;
                                        goto no_buffers;
                                }
                        }

                        /* Refresh the desc even if buffer_addrs didn't change
                         * because each write-back erases this info. */
                        rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
                        rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
                } else {
                        rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
                        rx_desc->read.hdr_addr = 0;
                }

                i++;
                if (i == rx_ring->count)
                        i = 0;
        }

no_buffers:
        if (rx_ring->next_to_use != i) {
                rx_ring->next_to_use = i;
                ixgbe_release_rx_desc(rx_ring, i);
        }
}

static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
{
        /* HW will not DMA in data larger than the given buffer, even if it
         * parses the (NFS, of course) header to be larger.  In that case, it
         * fills the header buffer and spills the rest into the page.
         */
        u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
        u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
                    IXGBE_RXDADV_HDRBUFLEN_SHIFT;
        if (hlen > IXGBE_RX_HDR_SIZE)
                hlen = IXGBE_RX_HDR_SIZE;
        return hlen;
}

/**
 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 * @skb: pointer to the last skb in the rsc queue
 *
 * This function changes a queue full of hw rsc buffers into a completed
 * packet.  It uses the ->prev pointers to find the first packet and then
 * turns it into the frag list owner.
 **/
static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
{
        unsigned int frag_list_size = 0;
        unsigned int skb_cnt = 1;

        while (skb->prev) {
                struct sk_buff *prev = skb->prev;
                frag_list_size += skb->len;
                skb->prev = NULL;
                skb = prev;
                skb_cnt++;
        }

        skb_shinfo(skb)->frag_list = skb->next;
        skb->next = NULL;
        skb->len += frag_list_size;
        skb->data_len += frag_list_size;
        skb->truesize += frag_list_size;
        IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;

        return skb;
}

static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
{
        return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
                IXGBE_RXDADV_RSCCNT_MASK);
}

static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                               struct ixgbe_ring *rx_ring,
                               int budget)
{
        struct ixgbe_adapter *adapter = q_vector->adapter;
        union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
        struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
        struct sk_buff *skb;
        unsigned int total_rx_bytes = 0, total_rx_packets = 0;
        const int current_node = numa_node_id();
#ifdef IXGBE_FCOE
        int ddp_bytes = 0;
#endif /* IXGBE_FCOE */
        u32 staterr;
        u16 i;
        u16 cleaned_count = 0;
        bool pkt_is_rsc = false;

        i = rx_ring->next_to_clean;
        rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
        staterr = le32_to_cpu(rx_desc->wb.upper.status_error);

        while (staterr & IXGBE_RXD_STAT_DD) {
                u32 upper_len = 0;

                rmb(); /* read descriptor and rx_buffer_info after status DD */

                rx_buffer_info = &rx_ring->rx_buffer_info[i];

                skb = rx_buffer_info->skb;
                rx_buffer_info->skb = NULL;
                prefetch(skb->data);

                if (ring_is_rsc_enabled(rx_ring))
                        pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);

                /* linear means we are building an skb from multiple pages */
                if (!skb_is_nonlinear(skb)) {
                        u16 hlen;
                        if (pkt_is_rsc &&
                            !(staterr & IXGBE_RXD_STAT_EOP) &&
                            !skb->prev) {
                                /*
                                 * When HWRSC is enabled, delay unmapping
                                 * of the first packet. It carries the
                                 * header information, HW may still
                                 * access the header after the writeback.
                                 * Only unmap it when EOP is reached
                                 */
                                IXGBE_RSC_CB(skb)->delay_unmap = true;
                                IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
                        } else {
                                dma_unmap_single(rx_ring->dev,
                                                 rx_buffer_info->dma,
                                                 rx_ring->rx_buf_len,
                                                 DMA_FROM_DEVICE);
                        }
                        rx_buffer_info->dma = 0;

                        if (ring_is_ps_enabled(rx_ring)) {
                                hlen = ixgbe_get_hlen(rx_desc);
                                upper_len = le16_to_cpu(rx_desc->wb.upper.length);
                        } else {
                                hlen = le16_to_cpu(rx_desc->wb.upper.length);
                        }

                        skb_put(skb, hlen);
                } else {
                        /* assume packet split since header is unmapped */
                        upper_len = le16_to_cpu(rx_desc->wb.upper.length);
                }

                if (upper_len) {
                        dma_unmap_page(rx_ring->dev,
                                       rx_buffer_info->page_dma,
                                       PAGE_SIZE / 2,
                                       DMA_FROM_DEVICE);
                        rx_buffer_info->page_dma = 0;
                        skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
                                           rx_buffer_info->page,
                                           rx_buffer_info->page_offset,
                                           upper_len);

                        if ((page_count(rx_buffer_info->page) == 1) &&
                            (page_to_nid(rx_buffer_info->page) == current_node))
                                get_page(rx_buffer_info->page);
                        else
                                rx_buffer_info->page = NULL;

                        skb->len += upper_len;
                        skb->data_len += upper_len;
                        skb->truesize += PAGE_SIZE / 2;
                }

                i++;
                if (i == rx_ring->count)
                        i = 0;

                next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
                prefetch(next_rxd);
                cleaned_count++;

                if (pkt_is_rsc) {
                        u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
                                     IXGBE_RXDADV_NEXTP_SHIFT;
                        next_buffer = &rx_ring->rx_buffer_info[nextp];
                } else {
                        next_buffer = &rx_ring->rx_buffer_info[i];
                }

                if (!(staterr & IXGBE_RXD_STAT_EOP)) {
                        if (ring_is_ps_enabled(rx_ring)) {
                                rx_buffer_info->skb = next_buffer->skb;
                                rx_buffer_info->dma = next_buffer->dma;
                                next_buffer->skb = skb;
                                next_buffer->dma = 0;
                        } else {
                                skb->next = next_buffer->skb;
                                skb->next->prev = skb;
                        }
                        rx_ring->rx_stats.non_eop_descs++;
                        goto next_desc;
                }

                if (skb->prev) {
                        skb = ixgbe_transform_rsc_queue(skb);
                        /* if we got here without RSC the packet is invalid */
                        if (!pkt_is_rsc) {
                                __pskb_trim(skb, 0);
                                rx_buffer_info->skb = skb;
                                goto next_desc;
                        }
                }

                if (ring_is_rsc_enabled(rx_ring)) {
                        if (IXGBE_RSC_CB(skb)->delay_unmap) {
                                dma_unmap_single(rx_ring->dev,
                                                 IXGBE_RSC_CB(skb)->dma,
                                                 rx_ring->rx_buf_len,
                                                 DMA_FROM_DEVICE);
                                IXGBE_RSC_CB(skb)->dma = 0;
                                IXGBE_RSC_CB(skb)->delay_unmap = false;
                        }
                }
                if (pkt_is_rsc) {
                        if (ring_is_ps_enabled(rx_ring))
                                rx_ring->rx_stats.rsc_count +=
                                        skb_shinfo(skb)->nr_frags;
                        else
                                rx_ring->rx_stats.rsc_count +=
                                        IXGBE_RSC_CB(skb)->skb_cnt;
                        rx_ring->rx_stats.rsc_flush++;
                }

                /* ERR_MASK will only have valid bits if EOP set */
                if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
                        dev_kfree_skb_any(skb);
                        goto next_desc;
                }

                ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
                if (adapter->netdev->features & NETIF_F_RXHASH)
                        ixgbe_rx_hash(rx_desc, skb);

                /* probably a little skewed due to removing CRC */
                total_rx_bytes += skb->len;
                total_rx_packets++;

                skb->protocol = eth_type_trans(skb, rx_ring->netdev);
#ifdef IXGBE_FCOE
                /* if ddp, not passing to ULD unless for FCP_RSP or error */
                if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
                        ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
                                                   staterr);
                        if (!ddp_bytes) {
                                dev_kfree_skb_any(skb);
                                goto next_desc;
                        }
                }
#endif /* IXGBE_FCOE */
                ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);

                budget--;
next_desc:
                rx_desc->wb.upper.status_error = 0;

                if (!budget)
                        break;

                /* return some buffers to hardware, one at a time is too slow */
                if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
                        ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
                        cleaned_count = 0;
                }

                /* use prefetched values */
                rx_desc = next_rxd;
                staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
        }

        rx_ring->next_to_clean = i;
        cleaned_count = ixgbe_desc_unused(rx_ring);

        if (cleaned_count)
                ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);

#ifdef IXGBE_FCOE
        /* include DDPed FCoE data */
        if (ddp_bytes > 0) {
                unsigned int mss;

                mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
                        sizeof(struct fc_frame_header) -
                        sizeof(struct fcoe_crc_eof);
                if (mss > 512)
                        mss &= ~511;
                total_rx_bytes += ddp_bytes;
                total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
        }
#endif /* IXGBE_FCOE */

        u64_stats_update_begin(&rx_ring->syncp);
        rx_ring->stats.packets += total_rx_packets;
        rx_ring->stats.bytes += total_rx_bytes;
        u64_stats_update_end(&rx_ring->syncp);
        q_vector->rx.total_packets += total_rx_packets;
        q_vector->rx.total_bytes += total_rx_bytes;

        return !!budget;
}

/**
 * ixgbe_configure_msix - Configure MSI-X hardware
 * @adapter: board private structure
 *
 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 * interrupts.
 **/
static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
{
        struct ixgbe_q_vector *q_vector;
        int q_vectors, v_idx;
        u32 mask;

        q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;

        /* Populate MSIX to EITR Select */
        if (adapter->num_vfs > 32) {
                u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
        }

        /*
         * Populate the IVAR table and set the ITR values to the
         * corresponding register.
         */
        for (v_idx = 0; v_idx < q_vectors; v_idx++) {
                struct ixgbe_ring *ring;
                q_vector = adapter->q_vector[v_idx];

                for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
                        ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);

                for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
                        ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);

                if (q_vector->tx.ring && !q_vector->rx.ring) {
                        /* tx only vector */
                        if (adapter->tx_itr_setting == 1)
                                q_vector->itr = IXGBE_10K_ITR;
                        else
                                q_vector->itr = adapter->tx_itr_setting;
                } else {
                        /* rx or rx/tx vector */
                        if (adapter->rx_itr_setting == 1)
                                q_vector->itr = IXGBE_20K_ITR;
                        else
                                q_vector->itr = adapter->rx_itr_setting;
                }

                ixgbe_write_eitr(q_vector);
        }

        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82598EB:
                ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
                               v_idx);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                ixgbe_set_ivar(adapter, -1, 1, v_idx);
                break;
        default:
                break;
        }
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);

        /* set up to autoclear timer, and the vectors */
        mask = IXGBE_EIMS_ENABLE_MASK;
        mask &= ~(IXGBE_EIMS_OTHER |
                  IXGBE_EIMS_MAILBOX |
                  IXGBE_EIMS_LSC);

        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
}

enum latency_range {
        lowest_latency = 0,
        low_latency = 1,
        bulk_latency = 2,
        latency_invalid = 255
};

/**
 * ixgbe_update_itr - update the dynamic ITR value based on statistics
 * @q_vector: structure containing interrupt and ring information
 * @ring_container: structure containing ring performance data
 *
 *      Stores a new ITR value based on packets and byte
 *      counts during the last interrupt.  The advantage of per interrupt
 *      computation is faster updates and more accurate ITR for the current
 *      traffic pattern.  Constants in this function were computed
 *      based on theoretical maximum wire speed and thresholds were set based
 *      on testing data as well as attempting to minimize response time
 *      while increasing bulk throughput.
 *      this functionality is controlled by the InterruptThrottleRate module
 *      parameter (see ixgbe_param.c)
 **/
static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
                             struct ixgbe_ring_container *ring_container)
{
        u64 bytes_perint;
        struct ixgbe_adapter *adapter = q_vector->adapter;
        int bytes = ring_container->total_bytes;
        int packets = ring_container->total_packets;
        u32 timepassed_us;
        u8 itr_setting = ring_container->itr;

        if (packets == 0)
                return;

        /* simple throttlerate management
         *    0-20MB/s lowest (100000 ints/s)
         *   20-100MB/s low   (20000 ints/s)
         *  100-1249MB/s bulk (8000 ints/s)
         */
        /* what was last interrupt timeslice? */
        timepassed_us = q_vector->itr >> 2;
        bytes_perint = bytes / timepassed_us; /* bytes/usec */

        switch (itr_setting) {
        case lowest_latency:
                if (bytes_perint > adapter->eitr_low)
                        itr_setting = low_latency;
                break;
        case low_latency:
                if (bytes_perint > adapter->eitr_high)
                        itr_setting = bulk_latency;
                else if (bytes_perint <= adapter->eitr_low)
                        itr_setting = lowest_latency;
                break;
        case bulk_latency:
                if (bytes_perint <= adapter->eitr_high)
                        itr_setting = low_latency;
                break;
        }

        /* clear work counters since we have the values we need */
        ring_container->total_bytes = 0;
        ring_container->total_packets = 0;

        /* write updated itr to ring container */
        ring_container->itr = itr_setting;
}

/**
 * ixgbe_write_eitr - write EITR register in hardware specific way
 * @q_vector: structure containing interrupt and ring information
 *
 * This function is made to be called by ethtool and by the driver
 * when it needs to update EITR registers at runtime.  Hardware
 * specific quirks/differences are taken care of here.
 */
void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
{
        struct ixgbe_adapter *adapter = q_vector->adapter;
        struct ixgbe_hw *hw = &adapter->hw;
        int v_idx = q_vector->v_idx;
        u32 itr_reg = q_vector->itr;

        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82598EB:
                /* must write high and low 16 bits to reset counter */
                itr_reg |= (itr_reg << 16);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                /*
                 * set the WDIS bit to not clear the timer bits and cause an
                 * immediate assertion of the interrupt
                 */
                itr_reg |= IXGBE_EITR_CNT_WDIS;
                break;
        default:
                break;
        }
        IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
}

static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
{
        u32 new_itr = q_vector->itr;
        u8 current_itr;

        ixgbe_update_itr(q_vector, &q_vector->tx);
        ixgbe_update_itr(q_vector, &q_vector->rx);

        current_itr = max(q_vector->rx.itr, q_vector->tx.itr);

        switch (current_itr) {
        /* counts and packets in update_itr are dependent on these numbers */
        case lowest_latency:
                new_itr = IXGBE_100K_ITR;
                break;
        case low_latency:
                new_itr = IXGBE_20K_ITR;
                break;
        case bulk_latency:
                new_itr = IXGBE_8K_ITR;
                break;
        default:
                break;
        }

        if (new_itr != q_vector->itr) {
                /* do an exponential smoothing */
                new_itr = (10 * new_itr * q_vector->itr) /
                          ((9 * new_itr) + q_vector->itr);

                /* save the algorithm value here */
                q_vector->itr = new_itr & IXGBE_MAX_EITR;

                ixgbe_write_eitr(q_vector);
        }
}

/**
 * ixgbe_check_overtemp_subtask - check for over tempurature
 * @adapter: pointer to adapter
 **/
static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 eicr = adapter->interrupt_event;

        if (test_bit(__IXGBE_DOWN, &adapter->state))
                return;

        if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
            !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
                return;

        adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;

        switch (hw->device_id) {
        case IXGBE_DEV_ID_82599_T3_LOM:
                /*
                 * Since the warning interrupt is for both ports
                 * we don't have to check if:
                 *  - This interrupt wasn't for our port.
                 *  - We may have missed the interrupt so always have to
                 *    check if we  got a LSC
                 */
                if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
                    !(eicr & IXGBE_EICR_LSC))
                        return;

                if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
                        u32 autoneg;
                        bool link_up = false;

                        hw->mac.ops.check_link(hw, &autoneg, &link_up, false);

                        if (link_up)
                                return;
                }

                /* Check if this is not due to overtemp */
                if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
                        return;

                break;
        default:
                if (!(eicr & IXGBE_EICR_GPI_SDP0))
                        return;
                break;
        }
        e_crit(drv,
               "Network adapter has been stopped because it has over heated. "
               "Restart the computer. If the problem persists, "
               "power off the system and replace the adapter\n");

        adapter->interrupt_event = 0;
}

static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
{
        struct ixgbe_hw *hw = &adapter->hw;

        if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
            (eicr & IXGBE_EICR_GPI_SDP1)) {
                e_crit(probe, "Fan has stopped, replace the adapter\n");
                /* write to clear the interrupt */
                IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
        }
}

static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
{
        if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
                return;

        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
                /*
                 * Need to check link state so complete overtemp check
                 * on service task
                 */
                if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
                    (!test_bit(__IXGBE_DOWN, &adapter->state))) {
                        adapter->interrupt_event = eicr;
                        adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
                        ixgbe_service_event_schedule(adapter);
                        return;
                }
                return;
        case ixgbe_mac_X540:
                if (!(eicr & IXGBE_EICR_TS))
                        return;
                break;
        default:
                return;
        }

        e_crit(drv,
               "Network adapter has been stopped because it has over heated. "
               "Restart the computer. If the problem persists, "
               "power off the system and replace the adapter\n");
}

static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
{
        struct ixgbe_hw *hw = &adapter->hw;

        if (eicr & IXGBE_EICR_GPI_SDP2) {
                /* Clear the interrupt */
                IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
                if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
                        adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
                        ixgbe_service_event_schedule(adapter);
                }
        }

        if (eicr & IXGBE_EICR_GPI_SDP1) {
                /* Clear the interrupt */
                IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
                if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
                        adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
                        ixgbe_service_event_schedule(adapter);
                }
        }
}

static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;

        adapter->lsc_int++;
        adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
        adapter->link_check_timeout = jiffies;
        if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
                IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
                IXGBE_WRITE_FLUSH(hw);
                ixgbe_service_event_schedule(adapter);
        }
}

static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
                                           u64 qmask)
{
        u32 mask;
        struct ixgbe_hw *hw = &adapter->hw;

        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
                IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
                mask = (qmask >> 32);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
                break;
        default:
                break;
        }
        /* skip the flush */
}

static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
                                            u64 qmask)
{
        u32 mask;
        struct ixgbe_hw *hw = &adapter->hw;

        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
                IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
                mask = (qmask >> 32);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
                break;
        default:
                break;
        }
        /* skip the flush */
}

/**
 * ixgbe_irq_enable - Enable default interrupt generation settings
 * @adapter: board private structure
 **/
static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
                                    bool flush)
{
        u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);

        /* don't reenable LSC while waiting for link */
        if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
                mask &= ~IXGBE_EIMS_LSC;

        if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
                switch (adapter->hw.mac.type) {
                case ixgbe_mac_82599EB:
                        mask |= IXGBE_EIMS_GPI_SDP0;
                        break;
                case ixgbe_mac_X540:
                        mask |= IXGBE_EIMS_TS;
                        break;
                default:
                        break;
                }
        if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
                mask |= IXGBE_EIMS_GPI_SDP1;
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
                mask |= IXGBE_EIMS_GPI_SDP1;
                mask |= IXGBE_EIMS_GPI_SDP2;
        case ixgbe_mac_X540:
                mask |= IXGBE_EIMS_ECC;
                mask |= IXGBE_EIMS_MAILBOX;
                break;
        default:
                break;
        }
        if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
            !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
                mask |= IXGBE_EIMS_FLOW_DIR;

        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
        if (queues)
                ixgbe_irq_enable_queues(adapter, ~0);
        if (flush)
                IXGBE_WRITE_FLUSH(&adapter->hw);
}

static irqreturn_t ixgbe_msix_other(int irq, void *data)
{
        struct ixgbe_adapter *adapter = data;
        struct ixgbe_hw *hw = &adapter->hw;
        u32 eicr;

        /*
         * Workaround for Silicon errata.  Use clear-by-write instead
         * of clear-by-read.  Reading with EICS will return the
         * interrupt causes without clearing, which later be done
         * with the write to EICR.
         */
        eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
        IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);

        if (eicr & IXGBE_EICR_LSC)
                ixgbe_check_lsc(adapter);

        if (eicr & IXGBE_EICR_MAILBOX)
                ixgbe_msg_task(adapter);

        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                if (eicr & IXGBE_EICR_ECC)
                        e_info(link, "Received unrecoverable ECC Err, please "
                               "reboot\n");
                /* Handle Flow Director Full threshold interrupt */
                if (eicr & IXGBE_EICR_FLOW_DIR) {
                        int reinit_count = 0;
                        int i;
                        for (i = 0; i < adapter->num_tx_queues; i++) {
                                struct ixgbe_ring *ring = adapter->tx_ring[i];
                                if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
                                                       &ring->state))
                                        reinit_count++;
                        }
                        if (reinit_count) {
                                /* no more flow director interrupts until after init */
                                IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
                                adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
                                ixgbe_service_event_schedule(adapter);
                        }
                }
                ixgbe_check_sfp_event(adapter, eicr);
                ixgbe_check_overtemp_event(adapter, eicr);
                break;
        default:
                break;
        }

        ixgbe_check_fan_failure(adapter, eicr);

        /* re-enable the original interrupt state, no lsc, no queues */
        if (!test_bit(__IXGBE_DOWN, &adapter->state))
                ixgbe_irq_enable(adapter, false, false);

        return IRQ_HANDLED;
}

static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
{
        struct ixgbe_q_vector *q_vector = data;

        /* EIAM disabled interrupts (on this vector) for us */

        if (q_vector->rx.ring || q_vector->tx.ring)
                napi_schedule(&q_vector->napi);

        return IRQ_HANDLED;
}

static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,

                                     int r_idx)
{
        struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
        struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];

        rx_ring->q_vector = q_vector;
        rx_ring->next = q_vector->rx.ring;
        q_vector->rx.ring = rx_ring;
        q_vector->rx.count++;
}

static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
                                     int t_idx)
{
        struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
        struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];

        tx_ring->q_vector = q_vector;
        tx_ring->next = q_vector->tx.ring;
        q_vector->tx.ring = tx_ring;
        q_vector->tx.count++;
        q_vector->tx.work_limit = a->tx_work_limit;
}

/**
 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
 * @adapter: board private structure to initialize
 *
 * This function maps descriptor rings to the queue-specific vectors
 * we were allotted through the MSI-X enabling code.  Ideally, we'd have
 * one vector per ring/queue, but on a constrained vector budget, we
 * group the rings as "efficiently" as possible.  You would add new
 * mapping configurations in here.
 **/
static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
{
        int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
        int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
        int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
        int v_start = 0;

        /* only one q_vector if MSI-X is disabled. */
        if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
                q_vectors = 1;

        /*
         * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
         * group them so there are multiple queues per vector.
         *
         * Re-adjusting *qpv takes care of the remainder.
         */
        for (; v_start < q_vectors && rxr_remaining; v_start++) {
                int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
                for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
                        map_vector_to_rxq(adapter, v_start, rxr_idx);
        }

        /*
         * If there are not enough q_vectors for each ring to have it's own
         * vector then we must pair up Rx/Tx on a each vector
         */
        if ((v_start + txr_remaining) > q_vectors)
                v_start = 0;

        for (; v_start < q_vectors && txr_remaining; v_start++) {
                int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
                for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
                        map_vector_to_txq(adapter, v_start, txr_idx);
        }
}

/**
 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
 * @adapter: board private structure
 *
 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
 * interrupts from the kernel.
 **/
static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
{
        struct net_device *netdev = adapter->netdev;
        int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
        int vector, err;
        int ri = 0, ti = 0;

        for (vector = 0; vector < q_vectors; vector++) {
                struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
                struct msix_entry *entry = &adapter->msix_entries[vector];

                if (q_vector->tx.ring && q_vector->rx.ring) {
                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
                                 "%s-%s-%d", netdev->name, "TxRx", ri++);
                        ti++;
                } else if (q_vector->rx.ring) {
                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
                                 "%s-%s-%d", netdev->name, "rx", ri++);
                } else if (q_vector->tx.ring) {
                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
                                 "%s-%s-%d", netdev->name, "tx", ti++);
                } else {
                        /* skip this unused q_vector */
                        continue;
                }
                err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
                                  q_vector->name, q_vector);
                if (err) {
                        e_err(probe, "request_irq failed for MSIX interrupt "
                              "Error: %d\n", err);
                        goto free_queue_irqs;
                }
                /* If Flow Director is enabled, set interrupt affinity */
                if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
                        /* assign the mask for this irq */
                        irq_set_affinity_hint(entry->vector,
                                              q_vector->affinity_mask);
                }
        }

        err = request_irq(adapter->msix_entries[vector].vector,
                          ixgbe_msix_other, 0, netdev->name, adapter);
        if (err) {
                e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
                goto free_queue_irqs;
        }

        return 0;

free_queue_irqs:
        while (vector) {
                vector--;
                irq_set_affinity_hint(adapter->msix_entries[vector].vector,
                                      NULL);
                free_irq(adapter->msix_entries[vector].vector,
                         adapter->q_vector[vector]);
        }
        adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
        pci_disable_msix(adapter->pdev);
        kfree(adapter->msix_entries);
        adapter->msix_entries = NULL;
        return err;
}

/**
 * ixgbe_intr - legacy mode Interrupt Handler
 * @irq: interrupt number
 * @data: pointer to a network interface device structure
 **/
static irqreturn_t ixgbe_intr(int irq, void *data)
{
        struct ixgbe_adapter *adapter = data;
        struct ixgbe_hw *hw = &adapter->hw;
        struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
        u32 eicr;

        /*
         * Workaround for silicon errata on 82598.  Mask the interrupts
         * before the read of EICR.
         */
        IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);

        /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
         * therefore no explicit interrupt disable is necessary */
        eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
        if (!eicr) {
                /*
                 * shared interrupt alert!
                 * make sure interrupts are enabled because the read will
                 * have disabled interrupts due to EIAM
                 * finish the workaround of silicon errata on 82598.  Unmask
                 * the interrupt that we masked before the EICR read.
                 */
                if (!test_bit(__IXGBE_DOWN, &adapter->state))
                        ixgbe_irq_enable(adapter, true, true);
                return IRQ_NONE;        /* Not our interrupt */
        }

        if (eicr & IXGBE_EICR_LSC)
                ixgbe_check_lsc(adapter);

        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
                ixgbe_check_sfp_event(adapter, eicr);
                /* Fall through */
        case ixgbe_mac_X540:
                if (eicr & IXGBE_EICR_ECC)
                        e_info(link, "Received unrecoverable ECC err, please "
                                     "reboot\n");
                ixgbe_check_overtemp_event(adapter, eicr);
                break;
        default:
                break;
        }

        ixgbe_check_fan_failure(adapter, eicr);

        if (napi_schedule_prep(&(q_vector->napi))) {
                /* would disable interrupts here but EIAM disabled it */
                __napi_schedule(&(q_vector->napi));
        }

        /*
         * re-enable link(maybe) and non-queue interrupts, no flush.
         * ixgbe_poll will re-enable the queue interrupts
         */

        if (!test_bit(__IXGBE_DOWN, &adapter->state))
                ixgbe_irq_enable(adapter, false, false);

        return IRQ_HANDLED;
}

static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
{
        int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
        int i;

        /* legacy and MSI only use one vector */
        if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
                q_vectors = 1;

        for (i = 0; i < adapter->num_rx_queues; i++) {
                adapter->rx_ring[i]->q_vector = NULL;
                adapter->rx_ring[i]->next = NULL;
        }
        for (i = 0; i < adapter->num_tx_queues; i++) {
                adapter->tx_ring[i]->q_vector = NULL;
                adapter->tx_ring[i]->next = NULL;
        }

        for (i = 0; i < q_vectors; i++) {
                struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
                memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
                memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
        }
}

/**
 * ixgbe_request_irq - initialize interrupts
 * @adapter: board private structure
 *
 * Attempts to configure interrupts using the best available
 * capabilities of the hardware and kernel.
 **/
static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
{
        struct net_device *netdev = adapter->netdev;
        int err;

        /* map all of the rings to the q_vectors */
        ixgbe_map_rings_to_vectors(adapter);

        if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
                err = ixgbe_request_msix_irqs(adapter);
        else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
                err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
                                  netdev->name, adapter);
        else
                err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
                                  netdev->name, adapter);

        if (err) {
                e_err(probe, "request_irq failed, Error %d\n", err);

                /* place q_vectors and rings back into a known good state */
                ixgbe_reset_q_vectors(adapter);
        }

        return err;
}

static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
{
        if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
                int i, q_vectors;

                q_vectors = adapter->num_msix_vectors;
                i = q_vectors - 1;
                free_irq(adapter->msix_entries[i].vector, adapter);
                i--;

                for (; i >= 0; i--) {
                        /* free only the irqs that were actually requested */
                        if (!adapter->q_vector[i]->rx.ring &&
                            !adapter->q_vector[i]->tx.ring)
                                continue;

                        /* clear the affinity_mask in the IRQ descriptor */
                        irq_set_affinity_hint(adapter->msix_entries[i].vector,
                                              NULL);

                        free_irq(adapter->msix_entries[i].vector,
                                 adapter->q_vector[i]);
                }
        } else {
                free_irq(adapter->pdev->irq, adapter);
        }

        /* clear q_vector state information */
        ixgbe_reset_q_vectors(adapter);
}

/**
 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
 * @adapter: board private structure
 **/
static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
{
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82598EB:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
                break;
        default:
                break;
        }
        IXGBE_WRITE_FLUSH(&adapter->hw);
        if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
                int i;
                for (i = 0; i < adapter->num_msix_vectors; i++)
                        synchronize_irq(adapter->msix_entries[i].vector);
        } else {
                synchronize_irq(adapter->pdev->irq);
        }
}

/**
 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
 *
 **/
static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
{
        struct ixgbe_q_vector *q_vector = adapter->q_vector[0];

        /* rx/tx vector */
        if (adapter->rx_itr_setting == 1)
                q_vector->itr = IXGBE_20K_ITR;
        else
                q_vector->itr = adapter->rx_itr_setting;

        ixgbe_write_eitr(q_vector);

        ixgbe_set_ivar(adapter, 0, 0, 0);
        ixgbe_set_ivar(adapter, 1, 0, 0);

        e_info(hw, "Legacy interrupt IVAR setup done\n");
}

/**
 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
 * @adapter: board private structure
 * @ring: structure containing ring specific data
 *
 * Configure the Tx descriptor ring after a reset.
 **/
void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
                             struct ixgbe_ring *ring)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u64 tdba = ring->dma;
        int wait_loop = 10;
        u32 txdctl = IXGBE_TXDCTL_ENABLE;
        u8 reg_idx = ring->reg_idx;

        /* disable queue to avoid issues while updating state */
        IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
        IXGBE_WRITE_FLUSH(hw);

        IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
                        (tdba & DMA_BIT_MASK(32)));
        IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
        IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
                        ring->count * sizeof(union ixgbe_adv_tx_desc));
        IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
        IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
        ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);

        /*
         * set WTHRESH to encourage burst writeback, it should not be set
         * higher than 1 when ITR is 0 as it could cause false TX hangs
         *
         * In order to avoid issues WTHRESH + PTHRESH should always be equal
         * to or less than the number of on chip descriptors, which is
         * currently 40.
         */
        if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
                txdctl |= (1 << 16);    /* WTHRESH = 1 */
        else
                txdctl |= (8 << 16);    /* WTHRESH = 8 */

        /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
        txdctl |= (1 << 8) |    /* HTHRESH = 1 */
                   32;          /* PTHRESH = 32 */

        /* reinitialize flowdirector state */
        if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
            adapter->atr_sample_rate) {
                ring->atr_sample_rate = adapter->atr_sample_rate;
                ring->atr_count = 0;
                set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
        } else {
                ring->atr_sample_rate = 0;
        }

        clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);

        /* enable queue */
        IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);

        /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
        if (hw->mac.type == ixgbe_mac_82598EB &&
            !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
                return;

        /* poll to verify queue is enabled */
        do {
                usleep_range(1000, 2000);
                txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
        } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
        if (!wait_loop)
                e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
}

static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 rttdcs;
        u32 reg;
        u8 tcs = netdev_get_num_tc(adapter->netdev);

        if (hw->mac.type == ixgbe_mac_82598EB)
                return;

        /* disable the arbiter while setting MTQC */
        rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
        rttdcs |= IXGBE_RTTDCS_ARBDIS;
        IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);

        /* set transmit pool layout */
        switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
        case (IXGBE_FLAG_SRIOV_ENABLED):
                IXGBE_WRITE_REG(hw, IXGBE_MTQC,
                                (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
                break;
        default:
                if (!tcs)
                        reg = IXGBE_MTQC_64Q_1PB;
                else if (tcs <= 4)
                        reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
                else
                        reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;

                IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);

                /* Enable Security TX Buffer IFG for multiple pb */
                if (tcs) {
                        reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
                        reg |= IXGBE_SECTX_DCB;
                        IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
                }
                break;
        }

        /* re-enable the arbiter */
        rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
        IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
}

/**
 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 **/
static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 dmatxctl;
        u32 i;

        ixgbe_setup_mtqc(adapter);

        if (hw->mac.type != ixgbe_mac_82598EB) {
                /* DMATXCTL.EN must be before Tx queues are enabled */
                dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
                dmatxctl |= IXGBE_DMATXCTL_TE;
                IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
        }

        /* Setup the HW Tx Head and Tail descriptor pointers */
        for (i = 0; i < adapter->num_tx_queues; i++)
                ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
}

#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2

static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
                                   struct ixgbe_ring *rx_ring)
{
        u32 srrctl;
        u8 reg_idx = rx_ring->reg_idx;

        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82598EB: {
                struct ixgbe_ring_feature *feature = adapter->ring_feature;
                const int mask = feature[RING_F_RSS].mask;
                reg_idx = reg_idx & mask;
        }
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
        default:
                break;
        }

        srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));

        srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
        srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
        if (adapter->num_vfs)
                srrctl |= IXGBE_SRRCTL_DROP_EN;

        srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
                  IXGBE_SRRCTL_BSIZEHDR_MASK;

        if (ring_is_ps_enabled(rx_ring)) {
#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
                srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
#else
                srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
#endif
                srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
        } else {
                srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
                          IXGBE_SRRCTL_BSIZEPKT_SHIFT;
                srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
        }

        IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
}

static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
                          0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
                          0x6A3E67EA, 0x14364D17, 0x3BED200D};
        u32 mrqc = 0, reta = 0;
        u32 rxcsum;
        int i, j;
        u8 tcs = netdev_get_num_tc(adapter->netdev);
        int maxq = adapter->ring_feature[RING_F_RSS].indices;

        if (tcs)
                maxq = min(maxq, adapter->num_tx_queues / tcs);

        /* Fill out hash function seeds */
        for (i = 0; i < 10; i++)
                IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);

        /* Fill out redirection table */
        for (i = 0, j = 0; i < 128; i++, j++) {
                if (j == maxq)
                        j = 0;
                /* reta = 4-byte sliding window of
                 * 0x00..(indices-1)(indices-1)00..etc. */
                reta = (reta << 8) | (j * 0x11);
                if ((i & 3) == 3)
                        IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
        }

        /* Disable indicating checksum in descriptor, enables RSS hash */
        rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
        rxcsum |= IXGBE_RXCSUM_PCSD;
        IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);

        if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
            (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
                mrqc = IXGBE_MRQC_RSSEN;
        } else {
                int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
                                             | IXGBE_FLAG_SRIOV_ENABLED);

                switch (mask) {
                case (IXGBE_FLAG_RSS_ENABLED):
                        if (!tcs)
                                mrqc = IXGBE_MRQC_RSSEN;
                        else if (tcs <= 4)
                                mrqc = IXGBE_MRQC_RTRSS4TCEN;
                        else
                                mrqc = IXGBE_MRQC_RTRSS8TCEN;
                        break;
                case (IXGBE_FLAG_SRIOV_ENABLED):
                        mrqc = IXGBE_MRQC_VMDQEN;
                        break;
                default:
                        break;
                }
        }

        /* Perform hash on these packet types */
        mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
              | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
              | IXGBE_MRQC_RSS_FIELD_IPV6
              | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;

        IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
}

/**
 * ixgbe_configure_rscctl - enable RSC for the indicated ring
 * @adapter:    address of board private structure
 * @index:      index of ring to set
 **/
static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
                                   struct ixgbe_ring *ring)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 rscctrl;
        int rx_buf_len;
        u8 reg_idx = ring->reg_idx;

        if (!ring_is_rsc_enabled(ring))
                return;

        rx_buf_len = ring->rx_buf_len;
        rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
        rscctrl |= IXGBE_RSCCTL_RSCEN;
        /*
         * we must limit the number of descriptors so that the
         * total size of max desc * buf_len is not greater
         * than 65536
         */
        if (ring_is_ps_enabled(ring)) {
#if (PAGE_SIZE < 8192)
                rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
#elif (PAGE_SIZE < 16384)
                rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
#elif (PAGE_SIZE < 32768)
                rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
#else
                rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
#endif
        } else {
                if (rx_buf_len <= IXGBE_RXBUFFER_4K)
                        rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
                else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
                        rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
                else
                        rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
        }
        IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
}

/**
 *  ixgbe_set_uta - Set unicast filter table address
 *  @adapter: board private structure
 *
 *  The unicast table address is a register array of 32-bit registers.
 *  The table is meant to be used in a way similar to how the MTA is used
 *  however due to certain limitations in the hardware it is necessary to
 *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
 *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
 **/
static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        int i;

        /* The UTA table only exists on 82599 hardware and newer */
        if (hw->mac.type < ixgbe_mac_82599EB)
                return;

        /* we only need to do this if VMDq is enabled */
        if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
                return;

        for (i = 0; i < 128; i++)
                IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
}

#define IXGBE_MAX_RX_DESC_POLL 10
static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
                                       struct ixgbe_ring *ring)
{
        struct ixgbe_hw *hw = &adapter->hw;
        int wait_loop = IXGBE_MAX_RX_DESC_POLL;
        u32 rxdctl;
        u8 reg_idx = ring->reg_idx;

        /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
        if (hw->mac.type == ixgbe_mac_82598EB &&
            !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
                return;

        do {
                usleep_range(1000, 2000);
                rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
        } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));

        if (!wait_loop) {
                e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
                      "the polling period\n", reg_idx);
        }
}

void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
                            struct ixgbe_ring *ring)
{
        struct ixgbe_hw *hw = &adapter->hw;
        int wait_loop = IXGBE_MAX_RX_DESC_POLL;
        u32 rxdctl;
        u8 reg_idx = ring->reg_idx;

        rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
        rxdctl &= ~IXGBE_RXDCTL_ENABLE;

        /* write value back with RXDCTL.ENABLE bit cleared */
        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);

        if (hw->mac.type == ixgbe_mac_82598EB &&
            !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
                return;

        /* the hardware may take up to 100us to really disable the rx queue */
        do {
                udelay(10);
                rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
        } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));

        if (!wait_loop) {
                e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
                      "the polling period\n", reg_idx);
        }
}

void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
                             struct ixgbe_ring *ring)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u64 rdba = ring->dma;
        u32 rxdctl;
        u8 reg_idx = ring->reg_idx;

        /* disable queue to avoid issues while updating state */
        rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
        ixgbe_disable_rx_queue(adapter, ring);

        IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
        IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
        IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
                        ring->count * sizeof(union ixgbe_adv_rx_desc));
        IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
        IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
        ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);

        ixgbe_configure_srrctl(adapter, ring);
        ixgbe_configure_rscctl(adapter, ring);

        /* If operating in IOV mode set RLPML for X540 */
        if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
            hw->mac.type == ixgbe_mac_X540) {
                rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
                rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
                            ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
        }

        if (hw->mac.type == ixgbe_mac_82598EB) {
                /*
                 * enable cache line friendly hardware writes:
                 * PTHRESH=32 descriptors (half the internal cache),
                 * this also removes ugly rx_no_buffer_count increment
                 * HTHRESH=4 descriptors (to minimize latency on fetch)
                 * WTHRESH=8 burst writeback up to two cache lines
                 */
                rxdctl &= ~0x3FFFFF;
                rxdctl |=  0x080420;
        }

        /* enable receive descriptor ring */
        rxdctl |= IXGBE_RXDCTL_ENABLE;
        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);

        ixgbe_rx_desc_queue_enable(adapter, ring);
        ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
}

static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        int p;

        /* PSRTYPE must be initialized in non 82598 adapters */
        u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
                      IXGBE_PSRTYPE_UDPHDR |
                      IXGBE_PSRTYPE_IPV4HDR |
                      IXGBE_PSRTYPE_L2HDR |
                      IXGBE_PSRTYPE_IPV6HDR;

        if (hw->mac.type == ixgbe_mac_82598EB)
                return;

        if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
                psrtype |= (adapter->num_rx_queues_per_pool << 29);

        for (p = 0; p < adapter->num_rx_pools; p++)
                IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
                                psrtype);
}

static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 gcr_ext;
        u32 vt_reg_bits;
        u32 reg_offset, vf_shift;
        u32 vmdctl;
        int i;

        if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
                return;

        vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
        vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
        vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
        IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);

        vf_shift = adapter->num_vfs % 32;
        reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;

        /* Enable only the PF's pool for Tx/Rx */
        IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
        IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
        IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
        IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
        IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);

        /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
        hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);

        /*
         * Set up VF register offsets for selected VT Mode,
         * i.e. 32 or 64 VFs for SR-IOV
         */
        gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
        gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
        gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
        IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);

        /* enable Tx loopback for VF/PF communication */
        IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
        /* Enable MAC Anti-Spoofing */
        hw->mac.ops.set_mac_anti_spoofing(hw,
                                           (adapter->num_vfs != 0),
                                          adapter->num_vfs);
        /* For VFs that have spoof checking turned off */
        for (i = 0; i < adapter->num_vfs; i++) {
                if (!adapter->vfinfo[i].spoofchk_enabled)
                        ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
        }
}

static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        struct net_device *netdev = adapter->netdev;
        int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
        int rx_buf_len;
        struct ixgbe_ring *rx_ring;
        int i;
        u32 mhadd, hlreg0;

        /* Decide whether to use packet split mode or not */
        /* On by default */
        adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;

        /* Do not use packet split if we're in SR-IOV Mode */
        if (adapter->num_vfs)
                adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;

        /* Disable packet split due to 82599 erratum #45 */
        if (hw->mac.type == ixgbe_mac_82599EB)
                adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;

#ifdef IXGBE_FCOE
        /* adjust max frame to be able to do baby jumbo for FCoE */
        if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
            (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
                max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;

#endif /* IXGBE_FCOE */
        mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
        if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
                mhadd &= ~IXGBE_MHADD_MFS_MASK;
                mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;

                IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
        }

        /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
        max_frame += VLAN_HLEN;

        /* Set the RX buffer length according to the mode */
        if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
                rx_buf_len = IXGBE_RX_HDR_SIZE;
        } else {
                if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
                    (netdev->mtu <= ETH_DATA_LEN))
                        rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
                /*
                 * Make best use of allocation by using all but 1K of a
                 * power of 2 allocation that will be used for skb->head.
                 */
                else if (max_frame <= IXGBE_RXBUFFER_3K)
                        rx_buf_len = IXGBE_RXBUFFER_3K;
                else if (max_frame <= IXGBE_RXBUFFER_7K)
                        rx_buf_len = IXGBE_RXBUFFER_7K;
                else if (max_frame <= IXGBE_RXBUFFER_15K)
                        rx_buf_len = IXGBE_RXBUFFER_15K;
                else
                        rx_buf_len = IXGBE_MAX_RXBUFFER;
        }

        hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
        /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
        hlreg0 |= IXGBE_HLREG0_JUMBOEN;
        IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);

        /*
         * Setup the HW Rx Head and Tail Descriptor Pointers and
         * the Base and Length of the Rx Descriptor Ring
         */
        for (i = 0; i < adapter->num_rx_queues; i++) {
                rx_ring = adapter->rx_ring[i];
                rx_ring->rx_buf_len = rx_buf_len;

                if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
                        set_ring_ps_enabled(rx_ring);
                else
                        clear_ring_ps_enabled(rx_ring);

                if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
                        set_ring_rsc_enabled(rx_ring);
                else
                        clear_ring_rsc_enabled(rx_ring);

#ifdef IXGBE_FCOE
                if (netdev->features & NETIF_F_FCOE_MTU) {
                        struct ixgbe_ring_feature *f;
                        f = &adapter->ring_feature[RING_F_FCOE];
                        if ((i >= f->mask) && (i < f->mask + f->indices)) {
                                clear_ring_ps_enabled(rx_ring);
                                if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
                                        rx_ring->rx_buf_len =
                                                IXGBE_FCOE_JUMBO_FRAME_SIZE;
                        } else if (!ring_is_rsc_enabled(rx_ring) &&
                                   !ring_is_ps_enabled(rx_ring)) {
                                rx_ring->rx_buf_len =
                                                IXGBE_FCOE_JUMBO_FRAME_SIZE;
                        }
                }
#endif /* IXGBE_FCOE */
        }
}

static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
{
        struct ixgbe_hw *hw = &adapter->hw;
        u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

        switch (hw->mac.type) {
        case ixgbe_mac_82598EB:
                /*
                 * For VMDq support of different descriptor types or
                 * buffer sizes through the use of multiple SRRCTL
                 * registers, RDRXCTL.MVMEN must be set to 1
                 *
                 * also, the manual doesn't mention it clearly but DCA hints
                 * will only use queue 0's tags unless this bit is set.  Side
                 * effects of setting this bit are only that SRRCTL must be
                 * fully programmed [0..15]
                 */
                rdrxctl |= IXGBE_RDRXCTL_MVMEN;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
                /* Disable RSC for ACK packets */
                IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
                   (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
                rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
                /* hardware requires some bits to be set by default */
                rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
                rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
                break;
        default:
                /* We should do nothing since we don't know this hardware */