LXR linux/include/linux/mlx4/qp.h

   1/*
   2 * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef MLX4_QP_H
  34#define MLX4_QP_H
  35
  36#include <linux/types.h>
  37
  38#include <linux/mlx4/device.h>
  39
  40#define MLX4_INVALID_LKEY       0x100
  41
  42enum mlx4_qp_optpar {
  43        MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  44        MLX4_QP_OPTPAR_RRE                      = 1 << 1,
  45        MLX4_QP_OPTPAR_RAE                      = 1 << 2,
  46        MLX4_QP_OPTPAR_RWE                      = 1 << 3,
  47        MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  48        MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
  49        MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  50        MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  51        MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  52        MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  53        MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
  54        MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  55        MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  56        MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  57        MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
  58        MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20
  59};
  60
  61enum mlx4_qp_state {
  62        MLX4_QP_STATE_RST                       = 0,
  63        MLX4_QP_STATE_INIT                      = 1,
  64        MLX4_QP_STATE_RTR                       = 2,
  65        MLX4_QP_STATE_RTS                       = 3,
  66        MLX4_QP_STATE_SQER                      = 4,
  67        MLX4_QP_STATE_SQD                       = 5,
  68        MLX4_QP_STATE_ERR                       = 6,
  69        MLX4_QP_STATE_SQ_DRAINING               = 7,
  70        MLX4_QP_NUM_STATE
  71};
  72
  73enum {
  74        MLX4_QP_ST_RC                           = 0x0,
  75        MLX4_QP_ST_UC                           = 0x1,
  76        MLX4_QP_ST_RD                           = 0x2,
  77        MLX4_QP_ST_UD                           = 0x3,
  78        MLX4_QP_ST_XRC                          = 0x6,
  79        MLX4_QP_ST_MLX                          = 0x7
  80};
  81
  82enum {
  83        MLX4_QP_PM_MIGRATED                     = 0x3,
  84        MLX4_QP_PM_ARMED                        = 0x0,
  85        MLX4_QP_PM_REARM                        = 0x1
  86};
  87
  88enum {
  89        /* params1 */
  90        MLX4_QP_BIT_SRE                         = 1 << 15,
  91        MLX4_QP_BIT_SWE                         = 1 << 14,
  92        MLX4_QP_BIT_SAE                         = 1 << 13,
  93        /* params2 */
  94        MLX4_QP_BIT_RRE                         = 1 << 15,
  95        MLX4_QP_BIT_RWE                         = 1 << 14,
  96        MLX4_QP_BIT_RAE                         = 1 << 13,
  97        MLX4_QP_BIT_RIC                         = 1 <<  4,
  98};
  99
 100enum {
 101        MLX4_RSS_HASH_XOR                       = 0,
 102        MLX4_RSS_HASH_TOP                       = 1,
 103
 104        MLX4_RSS_UDP_IPV6                       = 1 << 0,
 105        MLX4_RSS_UDP_IPV4                       = 1 << 1,
 106        MLX4_RSS_TCP_IPV6                       = 1 << 2,
 107        MLX4_RSS_IPV6                           = 1 << 3,
 108        MLX4_RSS_TCP_IPV4                       = 1 << 4,
 109        MLX4_RSS_IPV4                           = 1 << 5,
 110
 111        /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
 112        MLX4_RSS_OFFSET_IN_QPC_PRI_PATH         = 0x24,
 113        /* offset of being RSS indirection QP within mlx4_qp_context.flags */
 114        MLX4_RSS_QPC_FLAG_OFFSET                = 13,
 115};
 116
 117struct mlx4_rss_context {
 118        __be32                  base_qpn;
 119        __be32                  default_qpn;
 120        u16                     reserved;
 121        u8                      hash_fn;
 122        u8                      flags;
 123        __be32                  rss_key[10];
 124        __be32                  base_qpn_udp;
 125};
 126
 127struct mlx4_qp_path {
 128        u8                      fl;
 129        u8                      reserved1[2];
 130        u8                      pkey_index;
 131        u8                      counter_index;
 132        u8                      grh_mylmc;
 133        __be16                  rlid;
 134        u8                      ackto;
 135        u8                      mgid_index;
 136        u8                      static_rate;
 137        u8                      hop_limit;
 138        __be32                  tclass_flowlabel;
 139        u8                      rgid[16];
 140        u8                      sched_queue;
 141        u8                      vlan_index;
 142        u8                      reserved3[2];
 143        u8                      reserved4[2];
 144        u8                      dmac[6];
 145};
 146
 147struct mlx4_qp_context {
 148        __be32                  flags;
 149        __be32                  pd;
 150        u8                      mtu_msgmax;
 151        u8                      rq_size_stride;
 152        u8                      sq_size_stride;
 153        u8                      rlkey;
 154        __be32                  usr_page;
 155        __be32                  local_qpn;
 156        __be32                  remote_qpn;
 157        struct                  mlx4_qp_path pri_path;
 158        struct                  mlx4_qp_path alt_path;
 159        __be32                  params1;
 160        u32                     reserved1;
 161        __be32                  next_send_psn;
 162        __be32                  cqn_send;
 163        u32                     reserved2[2];
 164        __be32                  last_acked_psn;
 165        __be32                  ssn;
 166        __be32                  params2;
 167        __be32                  rnr_nextrecvpsn;
 168        __be32                  xrcd;
 169        __be32                  cqn_recv;
 170        __be64                  db_rec_addr;
 171        __be32                  qkey;
 172        __be32                  srqn;
 173        __be32                  msn;
 174        __be16                  rq_wqe_counter;
 175        __be16                  sq_wqe_counter;
 176        u32                     reserved3[2];
 177        __be32                  param3;
 178        __be32                  nummmcpeers_basemkey;
 179        u8                      log_page_size;
 180        u8                      reserved4[2];
 181        u8                      mtt_base_addr_h;
 182        __be32                  mtt_base_addr_l;
 183        u32                     reserved5[10];
 184};
 185
 186/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
 187#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
 188
 189enum {
 190        MLX4_WQE_CTRL_NEC               = 1 << 29,
 191        MLX4_WQE_CTRL_FENCE             = 1 << 6,
 192        MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
 193        MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
 194        MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
 195        MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
 196        MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
 197        MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
 198        MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 199};
 200
 201struct mlx4_wqe_ctrl_seg {
 202        __be32                  owner_opcode;
 203        __be16                  vlan_tag;
 204        u8                      ins_vlan;
 205        u8                      fence_size;
 206        /*
 207         * High 24 bits are SRC remote buffer; low 8 bits are flags:
 208         * [7]   SO (strong ordering)
 209         * [5]   TCP/UDP checksum
 210         * [4]   IP checksum
 211         * [3:2] C (generate completion queue entry)
 212         * [1]   SE (solicited event)
 213         * [0]   FL (force loopback)
 214         */
 215        __be32                  srcrb_flags;
 216        /*
 217         * imm is immediate data for send/RDMA write w/ immediate;
 218         * also invalidation key for send with invalidate; input
 219         * modifier for WQEs on CCQs.
 220         */
 221        __be32                  imm;
 222};
 223
 224enum {
 225        MLX4_WQE_MLX_VL15       = 1 << 17,
 226        MLX4_WQE_MLX_SLR        = 1 << 16
 227};
 228
 229struct mlx4_wqe_mlx_seg {
 230        u8                      owner;
 231        u8                      reserved1[2];
 232        u8                      opcode;
 233        u8                      reserved2[3];
 234        u8                      size;
 235        /*
 236         * [17]    VL15
 237         * [16]    SLR
 238         * [15:12] static rate
 239         * [11:8]  SL
 240         * [4]     ICRC
 241         * [3:2]   C
 242         * [0]     FL (force loopback)
 243         */
 244        __be32                  flags;
 245        __be16                  rlid;
 246        u16                     reserved3;
 247};
 248
 249struct mlx4_wqe_datagram_seg {
 250        __be32                  av[8];
 251        __be32                  dqpn;
 252        __be32                  qkey;
 253        __be16                  vlan;
 254        u8                      mac[6];
 255};
 256
 257struct mlx4_wqe_lso_seg {
 258        __be32                  mss_hdr_size;
 259        __be32                  header[0];
 260};
 261
 262struct mlx4_wqe_bind_seg {
 263        __be32                  flags1;
 264        __be32                  flags2;
 265        __be32                  new_rkey;
 266        __be32                  lkey;
 267        __be64                  addr;
 268        __be64                  length;
 269};
 270
 271enum {
 272        MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 273        MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 274        MLX4_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 275        MLX4_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 276        MLX4_WQE_FMR_PERM_ATOMIC        = 1 << 31
 277};
 278
 279struct mlx4_wqe_fmr_seg {
 280        __be32                  flags;
 281        __be32                  mem_key;
 282        __be64                  buf_list;
 283        __be64                  start_addr;
 284        __be64                  reg_len;
 285        __be32                  offset;
 286        __be32                  page_size;
 287        u32                     reserved[2];
 288};
 289
 290struct mlx4_wqe_fmr_ext_seg {
 291        u8                      flags;
 292        u8                      reserved;
 293        __be16                  app_mask;
 294        __be16                  wire_app_tag;
 295        __be16                  mem_app_tag;
 296        __be32                  wire_ref_tag_base;
 297        __be32                  mem_ref_tag_base;
 298};
 299
 300struct mlx4_wqe_local_inval_seg {
 301        __be32                  flags;
 302        u32                     reserved1;
 303        __be32                  mem_key;
 304        u32                     reserved2[2];
 305        __be32                  guest_id;
 306        __be64                  pa;
 307};
 308
 309struct mlx4_wqe_raddr_seg {
 310        __be64                  raddr;
 311        __be32                  rkey;
 312        u32                     reserved;
 313};
 314
 315struct mlx4_wqe_atomic_seg {
 316        __be64                  swap_add;
 317        __be64                  compare;
 318};
 319
 320struct mlx4_wqe_masked_atomic_seg {
 321        __be64                  swap_add;
 322        __be64                  compare;
 323        __be64                  swap_add_mask;
 324        __be64                  compare_mask;
 325};
 326
 327struct mlx4_wqe_data_seg {
 328        __be32                  byte_count;
 329        __be32                  lkey;
 330        __be64                  addr;
 331};
 332
 333enum {
 334        MLX4_INLINE_ALIGN       = 64,
 335        MLX4_INLINE_SEG         = 1 << 31,
 336};
 337
 338struct mlx4_wqe_inline_seg {
 339        __be32                  byte_count;
 340};
 341
 342int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 343                   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 344                   struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
 345                   int sqd_event, struct mlx4_qp *qp);
 346
 347int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 348                  struct mlx4_qp_context *context);
 349
 350int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 351                     struct mlx4_qp_context *context,
 352                     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
 353
 354static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 355{
 356        return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
 357}
 358
 359void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 360
 361#endif /* MLX4_QP_H */
 362