LXR linux/drivers/media/dvb/frontends/drxk

   1#include "drxk_map.h"
   2
   3#define DRXK_VERSION_MAJOR 0
   4#define DRXK_VERSION_MINOR 9
   5#define DRXK_VERSION_PATCH 4300
   6
   7#define HI_I2C_DELAY        42
   8#define HI_I2C_BRIDGE_DELAY 350
   9#define DRXK_MAX_RETRIES    100
  10
  11#define DRIVER_4400 1
  12
  13#define DRXX_JTAGID   0x039210D9
  14#define DRXX_J_JTAGID 0x239310D9
  15#define DRXX_K_JTAGID 0x039210D9
  16
  17#define DRX_UNKNOWN     254
  18#define DRX_AUTO        255
  19
  20#define DRX_SCU_READY   0
  21#define DRXK_MAX_WAITTIME (200)
  22#define SCU_RESULT_OK      0
  23#define SCU_RESULT_SIZE   -4
  24#define SCU_RESULT_INVPAR -3
  25#define SCU_RESULT_UNKSTD -2
  26#define SCU_RESULT_UNKCMD -1
  27
  28#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
  29#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
  30#endif
  31
  32#define DRXK_8VSB_MPEG_BIT_RATE     19392658UL  /*bps*/
  33#define DRXK_DVBT_MPEG_BIT_RATE     32000000UL  /*bps*/
  34#define DRXK_QAM16_MPEG_BIT_RATE    27000000UL  /*bps*/
  35#define DRXK_QAM32_MPEG_BIT_RATE    33000000UL  /*bps*/
  36#define DRXK_QAM64_MPEG_BIT_RATE    40000000UL  /*bps*/
  37#define DRXK_QAM128_MPEG_BIT_RATE   46000000UL  /*bps*/
  38#define DRXK_QAM256_MPEG_BIT_RATE   52000000UL  /*bps*/
  39#define DRXK_MAX_MPEG_BIT_RATE      52000000UL  /*bps*/
  40
  41#define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
  42#define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
  43#define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
  44#define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
  45#define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
  46#define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
  47#define     IQM_RC_ADJ_SEL_B_VSB                                            0x2
  48
  49enum OperationMode {
  50        OM_NONE,
  51        OM_QAM_ITU_A,
  52        OM_QAM_ITU_B,
  53        OM_QAM_ITU_C,
  54        OM_DVBT
  55};
  56
  57enum DRXPowerMode {
  58        DRX_POWER_UP = 0,
  59        DRX_POWER_MODE_1,
  60        DRX_POWER_MODE_2,
  61        DRX_POWER_MODE_3,
  62        DRX_POWER_MODE_4,
  63        DRX_POWER_MODE_5,
  64        DRX_POWER_MODE_6,
  65        DRX_POWER_MODE_7,
  66        DRX_POWER_MODE_8,
  67
  68        DRX_POWER_MODE_9,
  69        DRX_POWER_MODE_10,
  70        DRX_POWER_MODE_11,
  71        DRX_POWER_MODE_12,
  72        DRX_POWER_MODE_13,
  73        DRX_POWER_MODE_14,
  74        DRX_POWER_MODE_15,
  75        DRX_POWER_MODE_16,
  76        DRX_POWER_DOWN = 255
  77};
  78
  79
  80/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
  81#ifndef DRXK_POWER_DOWN_OFDM
  82#define DRXK_POWER_DOWN_OFDM        DRX_POWER_MODE_1
  83#endif
  84
  85/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
  86#ifndef DRXK_POWER_DOWN_CORE
  87#define DRXK_POWER_DOWN_CORE        DRX_POWER_MODE_9
  88#endif
  89
  90/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
  91#ifndef DRXK_POWER_DOWN_PLL
  92#define DRXK_POWER_DOWN_PLL         DRX_POWER_MODE_10
  93#endif
  94
  95
  96enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
  97enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN };
  98enum EDrxkCoefArrayIndex {
  99        DRXK_COEF_IDX_MN = 0,
 100        DRXK_COEF_IDX_FM    ,
 101        DRXK_COEF_IDX_L     ,
 102        DRXK_COEF_IDX_LP    ,
 103        DRXK_COEF_IDX_BG    ,
 104        DRXK_COEF_IDX_DK    ,
 105        DRXK_COEF_IDX_I     ,
 106        DRXK_COEF_IDX_MAX
 107};
 108enum EDrxkSifAttenuation {
 109        DRXK_SIF_ATTENUATION_0DB,
 110        DRXK_SIF_ATTENUATION_3DB,
 111        DRXK_SIF_ATTENUATION_6DB,
 112        DRXK_SIF_ATTENUATION_9DB
 113};
 114enum EDrxkConstellation {
 115        DRX_CONSTELLATION_BPSK = 0,
 116        DRX_CONSTELLATION_QPSK,
 117        DRX_CONSTELLATION_PSK8,
 118        DRX_CONSTELLATION_QAM16,
 119        DRX_CONSTELLATION_QAM32,
 120        DRX_CONSTELLATION_QAM64,
 121        DRX_CONSTELLATION_QAM128,
 122        DRX_CONSTELLATION_QAM256,
 123        DRX_CONSTELLATION_QAM512,
 124        DRX_CONSTELLATION_QAM1024,
 125        DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
 126        DRX_CONSTELLATION_AUTO    = DRX_AUTO
 127};
 128enum EDrxkInterleaveMode {
 129        DRXK_QAM_I12_J17    = 16,
 130        DRXK_QAM_I_UNKNOWN  = DRX_UNKNOWN
 131};
 132enum {
 133        DRXK_SPIN_A1 = 0,
 134        DRXK_SPIN_A2,
 135        DRXK_SPIN_A3,
 136        DRXK_SPIN_UNKNOWN
 137};
 138
 139enum DRXKCfgDvbtSqiSpeed {
 140        DRXK_DVBT_SQI_SPEED_FAST = 0,
 141        DRXK_DVBT_SQI_SPEED_MEDIUM,
 142        DRXK_DVBT_SQI_SPEED_SLOW,
 143        DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
 144} ;
 145
 146enum DRXFftmode_t {
 147        DRX_FFTMODE_2K = 0,
 148        DRX_FFTMODE_4K,
 149        DRX_FFTMODE_8K,
 150        DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
 151        DRX_FFTMODE_AUTO    = DRX_AUTO
 152};
 153
 154enum DRXMPEGStrWidth_t {
 155        DRX_MPEG_STR_WIDTH_1,
 156        DRX_MPEG_STR_WIDTH_8
 157};
 158
 159enum DRXQamLockRange_t {
 160        DRX_QAM_LOCKRANGE_NORMAL,
 161        DRX_QAM_LOCKRANGE_EXTENDED
 162};
 163
 164struct DRXKCfgDvbtEchoThres_t {
 165        u16             threshold;
 166        enum DRXFftmode_t      fftMode;
 167} ;
 168
 169struct SCfgAgc {
 170        enum AGC_CTRL_MODE     ctrlMode;        /* off, user, auto */
 171        u16            outputLevel;     /* range dependent on AGC */
 172        u16            minOutputLevel;  /* range dependent on AGC */
 173        u16            maxOutputLevel;  /* range dependent on AGC */
 174        u16            speed;           /* range dependent on AGC */
 175        u16            top;             /* rf-agc take over point */
 176        u16            cutOffCurrent;   /* rf-agc is accelerated if output current
 177                                           is below cut-off current */
 178        u16            IngainTgtMax;
 179        u16            FastClipCtrlDelay;
 180};
 181
 182struct SCfgPreSaw {
 183        u16        reference; /* pre SAW reference value, range 0 .. 31 */
 184        bool          usePreSaw; /* TRUE algorithms must use pre SAW sense */
 185};
 186
 187struct DRXKOfdmScCmd_t {
 188        u16 cmd;        /**< Command number */
 189        u16 subcmd;     /**< Sub-command parameter*/
 190        u16 param0;     /**< General purpous param */
 191        u16 param1;     /**< General purpous param */
 192        u16 param2;     /**< General purpous param */
 193        u16 param3;     /**< General purpous param */
 194        u16 param4;     /**< General purpous param */
 195};
 196
 197struct drxk_state {
 198        struct dvb_frontend frontend;
 199        struct dtv_frontend_properties props;
 200        struct device *dev;
 201
 202        struct i2c_adapter *i2c;
 203        u8     demod_address;
 204        void  *priv;
 205
 206        struct mutex mutex;
 207
 208        u32    m_Instance;           /**< Channel 1,2,3 or 4 */
 209
 210        int    m_ChunkSize;
 211        u8 Chunk[256];
 212
 213        bool   m_hasLNA;
 214        bool   m_hasDVBT;
 215        bool   m_hasDVBC;
 216        bool   m_hasAudio;
 217        bool   m_hasATV;
 218        bool   m_hasOOB;
 219        bool   m_hasSAWSW;         /**< TRUE if mat_tx is available */
 220        bool   m_hasGPIO1;         /**< TRUE if mat_rx is available */
 221        bool   m_hasGPIO2;         /**< TRUE if GPIO is available */
 222        bool   m_hasIRQN;          /**< TRUE if IRQN is available */
 223        u16    m_oscClockFreq;
 224        u16    m_HICfgTimingDiv;
 225        u16    m_HICfgBridgeDelay;
 226        u16    m_HICfgWakeUpKey;
 227        u16    m_HICfgTimeout;
 228        u16    m_HICfgCtrl;
 229        s32    m_sysClockFreq;      /**< system clock frequency in kHz */
 230
 231        enum EDrxkState    m_DrxkState;      /**< State of Drxk (init,stopped,started) */
 232        enum OperationMode m_OperationMode;  /**< digital standards */
 233        struct SCfgAgc     m_vsbRfAgcCfg;    /**< settings for VSB RF-AGC */
 234        struct SCfgAgc     m_vsbIfAgcCfg;    /**< settings for VSB IF-AGC */
 235        u16                m_vsbPgaCfg;      /**< settings for VSB PGA */
 236        struct SCfgPreSaw  m_vsbPreSawCfg;   /**< settings for pre SAW sense */
 237        s32    m_Quality83percent;  /**< MER level (*0.1 dB) for 83% quality indication */
 238        s32    m_Quality93percent;  /**< MER level (*0.1 dB) for 93% quality indication */
 239        bool   m_smartAntInverted;
 240        bool   m_bDebugEnableBridge;
 241        bool   m_bPDownOpenBridge;  /**< only open DRXK bridge before power-down once it has been accessed */
 242        bool   m_bPowerDown;        /**< Power down when not used */
 243
 244        u32    m_IqmFsRateOfs;      /**< frequency shift as written to DRXK register (28bit fixpoint) */
 245
 246        bool   m_enableMPEGOutput;  /**< If TRUE, enable MPEG output */
 247        bool   m_insertRSByte;      /**< If TRUE, insert RS byte */
 248        bool   m_enableParallel;    /**< If TRUE, parallel out otherwise serial */
 249        bool   m_invertDATA;        /**< If TRUE, invert DATA signals */
 250        bool   m_invertERR;         /**< If TRUE, invert ERR signal */
 251        bool   m_invertSTR;         /**< If TRUE, invert STR signals */
 252        bool   m_invertVAL;         /**< If TRUE, invert VAL signals */
 253        bool   m_invertCLK;         /**< If TRUE, invert CLK signals */
 254        bool   m_DVBCStaticCLK;
 255        bool   m_DVBTStaticCLK;     /**< If TRUE, static MPEG clockrate will
 256                                         be used, otherwise clockrate will
 257                                         adapt to the bitrate of the TS */
 258        u32    m_DVBTBitrate;
 259        u32    m_DVBCBitrate;
 260
 261        u8     m_TSDataStrength;
 262        u8     m_TSClockkStrength;
 263
 264        bool   m_itut_annex_c;      /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
 265
 266        enum DRXMPEGStrWidth_t  m_widthSTR;    /**< MPEG start width */
 267        u32    m_mpegTsStaticBitrate;          /**< Maximum bitrate in b/s in case
 268                                                    static clockrate is selected */
 269
 270        /* LARGE_INTEGER   m_StartTime; */     /**< Contains the time of the last demod start */
 271        s32    m_MpegLockTimeOut;      /**< WaitForLockStatus Timeout (counts from start time) */
 272        s32    m_DemodLockTimeOut;     /**< WaitForLockStatus Timeout (counts from start time) */
 273
 274        bool   m_disableTEIhandling;
 275
 276        bool   m_RfAgcPol;
 277        bool   m_IfAgcPol;
 278
 279        struct SCfgAgc    m_atvRfAgcCfg;  /**< settings for ATV RF-AGC */
 280        struct SCfgAgc    m_atvIfAgcCfg;  /**< settings for ATV IF-AGC */
 281        struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
 282        bool              m_phaseCorrectionBypass;
 283        s16               m_atvTopVidPeak;
 284        u16               m_atvTopNoiseTh;
 285        enum EDrxkSifAttenuation m_sifAttenuation;
 286        bool              m_enableCVBSOutput;
 287        bool              m_enableSIFOutput;
 288        bool              m_bMirrorFreqSpect;
 289        enum EDrxkConstellation  m_Constellation; /**< Constellation type of the channel */
 290        u32               m_CurrSymbolRate;       /**< Current QAM symbol rate */
 291        struct SCfgAgc    m_qamRfAgcCfg;          /**< settings for QAM RF-AGC */
 292        struct SCfgAgc    m_qamIfAgcCfg;          /**< settings for QAM IF-AGC */
 293        u16               m_qamPgaCfg;            /**< settings for QAM PGA */
 294        struct SCfgPreSaw m_qamPreSawCfg;         /**< settings for QAM pre SAW sense */
 295        enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
 296        u16               m_fecRsPlen;
 297        u16               m_fecRsPrescale;
 298
 299        enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
 300
 301        u16               m_GPIO;
 302        u16               m_GPIOCfg;
 303
 304        struct SCfgAgc    m_dvbtRfAgcCfg;     /**< settings for QAM RF-AGC */
 305        struct SCfgAgc    m_dvbtIfAgcCfg;     /**< settings for QAM IF-AGC */
 306        struct SCfgPreSaw m_dvbtPreSawCfg;    /**< settings for QAM pre SAW sense */
 307
 308        u16               m_agcFastClipCtrlDelay;
 309        bool              m_adcCompPassed;
 310        u16               m_adcCompCoef[64];
 311        u16               m_adcState;
 312
 313        u8               *m_microcode;
 314        int               m_microcode_length;
 315        bool              m_DRXK_A1_PATCH_CODE;
 316        bool              m_DRXK_A1_ROM_CODE;
 317        bool              m_DRXK_A2_ROM_CODE;
 318        bool              m_DRXK_A3_ROM_CODE;
 319        bool              m_DRXK_A2_PATCH_CODE;
 320        bool              m_DRXK_A3_PATCH_CODE;
 321
 322        bool              m_rfmirror;
 323        u8                m_deviceSpin;
 324        u32               m_iqmRcRate;
 325
 326        enum DRXPowerMode m_currentPowerMode;
 327
 328        /*
 329         * Configurable parameters at the driver. They stores the values found
 330         * at struct drxk_config.
 331         */
 332
 333        u16     UIO_mask;       /* Bits used by UIO */
 334
 335        bool    single_master;
 336        bool    no_i2c_bridge;
 337        bool    antenna_dvbt;
 338        u16     antenna_gpio;
 339
 340        const char *microcode_name;
 341};
 342
 343#define NEVER_LOCK 0
 344#define NOT_LOCKED 1
 345#define DEMOD_LOCK 2
 346#define FEC_LOCK   3
 347#define MPEG_LOCK  4
 348
 349