linux/arch/blackfin/Kconfig
<<
>>
Prefs
   1config SYMBOL_PREFIX
   2        string
   3        default "_"
   4
   5config MMU
   6        def_bool n
   7
   8config FPU
   9        def_bool n
  10
  11config RWSEM_GENERIC_SPINLOCK
  12        def_bool y
  13
  14config RWSEM_XCHGADD_ALGORITHM
  15        def_bool n
  16
  17config BLACKFIN
  18        def_bool y
  19        select HAVE_ARCH_KGDB
  20        select HAVE_ARCH_TRACEHOOK
  21        select HAVE_DYNAMIC_FTRACE
  22        select HAVE_FTRACE_MCOUNT_RECORD
  23        select HAVE_FUNCTION_GRAPH_TRACER
  24        select HAVE_FUNCTION_TRACER
  25        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26        select HAVE_IDE
  27        select HAVE_IRQ_WORK
  28        select HAVE_KERNEL_GZIP if RAMKERNEL
  29        select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30        select HAVE_KERNEL_LZMA if RAMKERNEL
  31        select HAVE_KERNEL_LZO if RAMKERNEL
  32        select HAVE_OPROFILE
  33        select HAVE_PERF_EVENTS
  34        select ARCH_WANT_OPTIONAL_GPIOLIB
  35        select HAVE_GENERIC_HARDIRQS
  36        select GENERIC_ATOMIC64
  37        select GENERIC_IRQ_PROBE
  38        select IRQ_PER_CPU if SMP
  39
  40config GENERIC_CSUM
  41        def_bool y
  42
  43config GENERIC_BUG
  44        def_bool y
  45        depends on BUG
  46
  47config ZONE_DMA
  48        def_bool y
  49
  50config GENERIC_GPIO
  51        def_bool y
  52
  53config FORCE_MAX_ZONEORDER
  54        int
  55        default "14"
  56
  57config GENERIC_CALIBRATE_DELAY
  58        def_bool y
  59
  60config LOCKDEP_SUPPORT
  61        def_bool y
  62
  63config STACKTRACE_SUPPORT
  64        def_bool y
  65
  66config TRACE_IRQFLAGS_SUPPORT
  67        def_bool y
  68
  69source "init/Kconfig"
  70
  71source "kernel/Kconfig.preempt"
  72
  73source "kernel/Kconfig.freezer"
  74
  75menu "Blackfin Processor Options"
  76
  77comment "Processor and Board Settings"
  78
  79choice
  80        prompt "CPU"
  81        default BF533
  82
  83config BF512
  84        bool "BF512"
  85        help
  86          BF512 Processor Support.
  87
  88config BF514
  89        bool "BF514"
  90        help
  91          BF514 Processor Support.
  92
  93config BF516
  94        bool "BF516"
  95        help
  96          BF516 Processor Support.
  97
  98config BF518
  99        bool "BF518"
 100        help
 101          BF518 Processor Support.
 102
 103config BF522
 104        bool "BF522"
 105        help
 106          BF522 Processor Support.
 107
 108config BF523
 109        bool "BF523"
 110        help
 111          BF523 Processor Support.
 112
 113config BF524
 114        bool "BF524"
 115        help
 116          BF524 Processor Support.
 117
 118config BF525
 119        bool "BF525"
 120        help
 121          BF525 Processor Support.
 122
 123config BF526
 124        bool "BF526"
 125        help
 126          BF526 Processor Support.
 127
 128config BF527
 129        bool "BF527"
 130        help
 131          BF527 Processor Support.
 132
 133config BF531
 134        bool "BF531"
 135        help
 136          BF531 Processor Support.
 137
 138config BF532
 139        bool "BF532"
 140        help
 141          BF532 Processor Support.
 142
 143config BF533
 144        bool "BF533"
 145        help
 146          BF533 Processor Support.
 147
 148config BF534
 149        bool "BF534"
 150        help
 151          BF534 Processor Support.
 152
 153config BF536
 154        bool "BF536"
 155        help
 156          BF536 Processor Support.
 157
 158config BF537
 159        bool "BF537"
 160        help
 161          BF537 Processor Support.
 162
 163config BF538
 164        bool "BF538"
 165        help
 166          BF538 Processor Support.
 167
 168config BF539
 169        bool "BF539"
 170        help
 171          BF539 Processor Support.
 172
 173config BF542_std
 174        bool "BF542"
 175        help
 176          BF542 Processor Support.
 177
 178config BF542M
 179        bool "BF542m"
 180        help
 181          BF542 Processor Support.
 182
 183config BF544_std
 184        bool "BF544"
 185        help
 186          BF544 Processor Support.
 187
 188config BF544M
 189        bool "BF544m"
 190        help
 191          BF544 Processor Support.
 192
 193config BF547_std
 194        bool "BF547"
 195        help
 196          BF547 Processor Support.
 197
 198config BF547M
 199        bool "BF547m"
 200        help
 201          BF547 Processor Support.
 202
 203config BF548_std
 204        bool "BF548"
 205        help
 206          BF548 Processor Support.
 207
 208config BF548M
 209        bool "BF548m"
 210        help
 211          BF548 Processor Support.
 212
 213config BF549_std
 214        bool "BF549"
 215        help
 216          BF549 Processor Support.
 217
 218config BF549M
 219        bool "BF549m"
 220        help
 221          BF549 Processor Support.
 222
 223config BF561
 224        bool "BF561"
 225        help
 226          BF561 Processor Support.
 227
 228endchoice
 229
 230config SMP
 231        depends on BF561
 232        select TICKSOURCE_CORETMR
 233        bool "Symmetric multi-processing support"
 234        ---help---
 235          This enables support for systems with more than one CPU,
 236          like the dual core BF561. If you have a system with only one
 237          CPU, say N. If you have a system with more than one CPU, say Y.
 238
 239          If you don't know what to do here, say N.
 240
 241config NR_CPUS
 242        int
 243        depends on SMP
 244        default 2 if BF561
 245
 246config HOTPLUG_CPU
 247        bool "Support for hot-pluggable CPUs"
 248        depends on SMP && HOTPLUG
 249        default y
 250
 251config BF_REV_MIN
 252        int
 253        default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 254        default 2 if (BF537 || BF536 || BF534)
 255        default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 256        default 4 if (BF538 || BF539)
 257
 258config BF_REV_MAX
 259        int
 260        default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 261        default 3 if (BF537 || BF536 || BF534 || BF54xM)
 262        default 5 if (BF561 || BF538 || BF539)
 263        default 6 if (BF533 || BF532 || BF531)
 264
 265choice
 266        prompt "Silicon Rev"
 267        default BF_REV_0_0 if (BF51x || BF52x)
 268        default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 269        default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 270
 271config BF_REV_0_0
 272        bool "0.0"
 273        depends on (BF51x || BF52x || (BF54x && !BF54xM))
 274
 275config BF_REV_0_1
 276        bool "0.1"
 277        depends on (BF51x || BF52x || (BF54x && !BF54xM))
 278
 279config BF_REV_0_2
 280        bool "0.2"
 281        depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 282
 283config BF_REV_0_3
 284        bool "0.3"
 285        depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 286
 287config BF_REV_0_4
 288        bool "0.4"
 289        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 290
 291config BF_REV_0_5
 292        bool "0.5"
 293        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 294
 295config BF_REV_0_6
 296        bool "0.6"
 297        depends on (BF533 || BF532 || BF531)
 298
 299config BF_REV_ANY
 300        bool "any"
 301
 302config BF_REV_NONE
 303        bool "none"
 304
 305endchoice
 306
 307config BF53x
 308        bool
 309        depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 310        default y
 311
 312config MEM_MT48LC64M4A2FB_7E
 313        bool
 314        depends on (BFIN533_STAMP)
 315        default y
 316
 317config MEM_MT48LC16M16A2TG_75
 318        bool
 319        depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 320                || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 321                || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 322                || BFIN527_BLUETECHNIX_CM)
 323        default y
 324
 325config MEM_MT48LC32M8A2_75
 326        bool
 327        depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 328        default y
 329
 330config MEM_MT48LC8M32B2B5_7
 331        bool
 332        depends on (BFIN561_BLUETECHNIX_CM)
 333        default y
 334
 335config MEM_MT48LC32M16A2TG_75
 336        bool
 337        depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 338        default y
 339
 340config MEM_MT48H32M16LFCJ_75
 341        bool
 342        depends on (BFIN526_EZBRD)
 343        default y
 344
 345source "arch/blackfin/mach-bf518/Kconfig"
 346source "arch/blackfin/mach-bf527/Kconfig"
 347source "arch/blackfin/mach-bf533/Kconfig"
 348source "arch/blackfin/mach-bf561/Kconfig"
 349source "arch/blackfin/mach-bf537/Kconfig"
 350source "arch/blackfin/mach-bf538/Kconfig"
 351source "arch/blackfin/mach-bf548/Kconfig"
 352
 353menu "Board customizations"
 354
 355config CMDLINE_BOOL
 356        bool "Default bootloader kernel arguments"
 357
 358config CMDLINE
 359        string "Initial kernel command string"
 360        depends on CMDLINE_BOOL
 361        default "console=ttyBF0,57600"
 362        help
 363          If you don't have a boot loader capable of passing a command line string
 364          to the kernel, you may specify one here. As a minimum, you should specify
 365          the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 366
 367config BOOT_LOAD
 368        hex "Kernel load address for booting"
 369        default "0x1000"
 370        range 0x1000 0x20000000
 371        help
 372          This option allows you to set the load address of the kernel.
 373          This can be useful if you are on a board which has a small amount
 374          of memory or you wish to reserve some memory at the beginning of
 375          the address space.
 376
 377          Note that you need to keep this value above 4k (0x1000) as this
 378          memory region is used to capture NULL pointer references as well
 379          as some core kernel functions.
 380
 381config ROM_BASE
 382        hex "Kernel ROM Base"
 383        depends on ROMKERNEL
 384        default "0x20040040"
 385        range 0x20000000 0x20400000 if !(BF54x || BF561)
 386        range 0x20000000 0x30000000 if (BF54x || BF561)
 387        help
 388          Make sure your ROM base does not include any file-header
 389          information that is prepended to the kernel.
 390
 391          For example, the bootable U-Boot format (created with
 392          mkimage) has a 64 byte header (0x40).  So while the image
 393          you write to flash might start at say 0x20080000, you have
 394          to add 0x40 to get the kernel's ROM base as it will come
 395          after the header.
 396
 397comment "Clock/PLL Setup"
 398
 399config CLKIN_HZ
 400        int "Frequency of the crystal on the board in Hz"
 401        default "10000000" if BFIN532_IP0X
 402        default "11059200" if BFIN533_STAMP
 403        default "24576000" if PNAV10
 404        default "25000000" # most people use this
 405        default "27000000" if BFIN533_EZKIT
 406        default "30000000" if BFIN561_EZKIT
 407        default "24000000" if BFIN527_AD7160EVAL
 408        help
 409          The frequency of CLKIN crystal oscillator on the board in Hz.
 410          Warning: This value should match the crystal on the board. Otherwise,
 411          peripherals won't work properly.
 412
 413config BFIN_KERNEL_CLOCK
 414        bool "Re-program Clocks while Kernel boots?"
 415        default n
 416        help
 417          This option decides if kernel clocks are re-programed from the
 418          bootloader settings. If the clocks are not set, the SDRAM settings
 419          are also not changed, and the Bootloader does 100% of the hardware
 420          configuration.
 421
 422config PLL_BYPASS
 423        bool "Bypass PLL"
 424        depends on BFIN_KERNEL_CLOCK
 425        default n
 426
 427config CLKIN_HALF
 428        bool "Half Clock In"
 429        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 430        default n
 431        help
 432          If this is set the clock will be divided by 2, before it goes to the PLL.
 433
 434config VCO_MULT
 435        int "VCO Multiplier"
 436        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 437        range 1 64
 438        default "22" if BFIN533_EZKIT
 439        default "45" if BFIN533_STAMP
 440        default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 441        default "22" if BFIN533_BLUETECHNIX_CM
 442        default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 443        default "20" if BFIN561_EZKIT
 444        default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 445        default "25" if BFIN527_AD7160EVAL
 446        help
 447          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 448          PLL Frequency = (Crystal Frequency) * (this setting)
 449
 450choice
 451        prompt "Core Clock Divider"
 452        depends on BFIN_KERNEL_CLOCK
 453        default CCLK_DIV_1
 454        help
 455          This sets the frequency of the core. It can be 1, 2, 4 or 8
 456          Core Frequency = (PLL frequency) / (this setting)
 457
 458config CCLK_DIV_1
 459        bool "1"
 460
 461config CCLK_DIV_2
 462        bool "2"
 463
 464config CCLK_DIV_4
 465        bool "4"
 466
 467config CCLK_DIV_8
 468        bool "8"
 469endchoice
 470
 471config SCLK_DIV
 472        int "System Clock Divider"
 473        depends on BFIN_KERNEL_CLOCK
 474        range 1 15
 475        default 5
 476        help
 477          This sets the frequency of the system clock (including SDRAM or DDR).
 478          This can be between 1 and 15
 479          System Clock = (PLL frequency) / (this setting)
 480
 481choice
 482        prompt "DDR SDRAM Chip Type"
 483        depends on BFIN_KERNEL_CLOCK
 484        depends on BF54x
 485        default MEM_MT46V32M16_5B
 486
 487config MEM_MT46V32M16_6T
 488        bool "MT46V32M16_6T"
 489
 490config MEM_MT46V32M16_5B
 491        bool "MT46V32M16_5B"
 492endchoice
 493
 494choice
 495        prompt "DDR/SDRAM Timing"
 496        depends on BFIN_KERNEL_CLOCK
 497        default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 498        help
 499          This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 500          The calculated SDRAM timing parameters may not be 100%
 501          accurate - This option is therefore marked experimental.
 502
 503config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 504        bool "Calculate Timings (EXPERIMENTAL)"
 505        depends on EXPERIMENTAL
 506
 507config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 508        bool "Provide accurate Timings based on target SCLK"
 509        help
 510          Please consult the Blackfin Hardware Reference Manuals as well
 511          as the memory device datasheet.
 512          http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 513endchoice
 514
 515menu "Memory Init Control"
 516        depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 517
 518config MEM_DDRCTL0
 519        depends on BF54x
 520        hex "DDRCTL0"
 521        default 0x0
 522
 523config MEM_DDRCTL1
 524        depends on BF54x
 525        hex "DDRCTL1"
 526        default 0x0
 527
 528config MEM_DDRCTL2
 529        depends on BF54x
 530        hex "DDRCTL2"
 531        default 0x0
 532
 533config MEM_EBIU_DDRQUE
 534        depends on BF54x
 535        hex "DDRQUE"
 536        default 0x0
 537
 538config MEM_SDRRC
 539        depends on !BF54x
 540        hex "SDRRC"
 541        default 0x0
 542
 543config MEM_SDGCTL
 544        depends on !BF54x
 545        hex "SDGCTL"
 546        default 0x0
 547endmenu
 548
 549#
 550# Max & Min Speeds for various Chips
 551#
 552config MAX_VCO_HZ
 553        int
 554        default 400000000 if BF512
 555        default 400000000 if BF514
 556        default 400000000 if BF516
 557        default 400000000 if BF518
 558        default 400000000 if BF522
 559        default 600000000 if BF523
 560        default 400000000 if BF524
 561        default 600000000 if BF525
 562        default 400000000 if BF526
 563        default 600000000 if BF527
 564        default 400000000 if BF531
 565        default 400000000 if BF532
 566        default 750000000 if BF533
 567        default 500000000 if BF534
 568        default 400000000 if BF536
 569        default 600000000 if BF537
 570        default 533333333 if BF538
 571        default 533333333 if BF539
 572        default 600000000 if BF542
 573        default 533333333 if BF544
 574        default 600000000 if BF547
 575        default 600000000 if BF548
 576        default 533333333 if BF549
 577        default 600000000 if BF561
 578
 579config MIN_VCO_HZ
 580        int
 581        default 50000000
 582
 583config MAX_SCLK_HZ
 584        int
 585        default 133333333
 586
 587config MIN_SCLK_HZ
 588        int
 589        default 27000000
 590
 591comment "Kernel Timer/Scheduler"
 592
 593source kernel/Kconfig.hz
 594
 595config GENERIC_CLOCKEVENTS
 596        bool "Generic clock events"
 597        default y
 598
 599menu "Clock event device"
 600        depends on GENERIC_CLOCKEVENTS
 601config TICKSOURCE_GPTMR0
 602        bool "GPTimer0"
 603        depends on !SMP
 604        select BFIN_GPTIMERS
 605
 606config TICKSOURCE_CORETMR
 607        bool "Core timer"
 608        default y
 609endmenu
 610
 611menu "Clock souce"
 612        depends on GENERIC_CLOCKEVENTS
 613config CYCLES_CLOCKSOURCE
 614        bool "CYCLES"
 615        default y
 616        depends on !BFIN_SCRATCH_REG_CYCLES
 617        depends on !SMP
 618        help
 619          If you say Y here, you will enable support for using the 'cycles'
 620          registers as a clock source.  Doing so means you will be unable to
 621          safely write to the 'cycles' register during runtime.  You will
 622          still be able to read it (such as for performance monitoring), but
 623          writing the registers will most likely crash the kernel.
 624
 625config GPTMR0_CLOCKSOURCE
 626        bool "GPTimer0"
 627        select BFIN_GPTIMERS
 628        depends on !TICKSOURCE_GPTMR0
 629endmenu
 630
 631config ARCH_USES_GETTIMEOFFSET
 632        depends on !GENERIC_CLOCKEVENTS
 633        def_bool y
 634
 635source kernel/time/Kconfig
 636
 637comment "Misc"
 638
 639choice
 640        prompt "Blackfin Exception Scratch Register"
 641        default BFIN_SCRATCH_REG_RETN
 642        help
 643          Select the resource to reserve for the Exception handler:
 644            - RETN: Non-Maskable Interrupt (NMI)
 645            - RETE: Exception Return (JTAG/ICE)
 646            - CYCLES: Performance counter
 647
 648          If you are unsure, please select "RETN".
 649
 650config BFIN_SCRATCH_REG_RETN
 651        bool "RETN"
 652        help
 653          Use the RETN register in the Blackfin exception handler
 654          as a stack scratch register.  This means you cannot
 655          safely use NMI on the Blackfin while running Linux, but
 656          you can debug the system with a JTAG ICE and use the
 657          CYCLES performance registers.
 658
 659          If you are unsure, please select "RETN".
 660
 661config BFIN_SCRATCH_REG_RETE
 662        bool "RETE"
 663        help
 664          Use the RETE register in the Blackfin exception handler
 665          as a stack scratch register.  This means you cannot
 666          safely use a JTAG ICE while debugging a Blackfin board,
 667          but you can safely use the CYCLES performance registers
 668          and the NMI.
 669
 670          If you are unsure, please select "RETN".
 671
 672config BFIN_SCRATCH_REG_CYCLES
 673        bool "CYCLES"
 674        help
 675          Use the CYCLES register in the Blackfin exception handler
 676          as a stack scratch register.  This means you cannot
 677          safely use the CYCLES performance registers on a Blackfin
 678          board at anytime, but you can debug the system with a JTAG
 679          ICE and use the NMI.
 680
 681          If you are unsure, please select "RETN".
 682
 683endchoice
 684
 685endmenu
 686
 687
 688menu "Blackfin Kernel Optimizations"
 689
 690comment "Memory Optimizations"
 691
 692config I_ENTRY_L1
 693        bool "Locate interrupt entry code in L1 Memory"
 694        default y
 695        depends on !SMP
 696        help
 697          If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 698          into L1 instruction memory. (less latency)
 699
 700config EXCPT_IRQ_SYSC_L1
 701        bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 702        default y
 703        depends on !SMP
 704        help
 705          If enabled, the entire ASM lowlevel exception and interrupt entry code
 706          (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 707          (less latency)
 708
 709config DO_IRQ_L1
 710        bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 711        default y
 712        depends on !SMP
 713        help
 714          If enabled, the frequently called do_irq dispatcher function is linked
 715          into L1 instruction memory. (less latency)
 716
 717config CORE_TIMER_IRQ_L1
 718        bool "Locate frequently called timer_interrupt() function in L1 Memory"
 719        default y
 720        depends on !SMP
 721        help
 722          If enabled, the frequently called timer_interrupt() function is linked
 723          into L1 instruction memory. (less latency)
 724
 725config IDLE_L1
 726        bool "Locate frequently idle function in L1 Memory"
 727        default y
 728        depends on !SMP
 729        help
 730          If enabled, the frequently called idle function is linked
 731          into L1 instruction memory. (less latency)
 732
 733config SCHEDULE_L1
 734        bool "Locate kernel schedule function in L1 Memory"
 735        default y
 736        depends on !SMP
 737        help
 738          If enabled, the frequently called kernel schedule is linked
 739          into L1 instruction memory. (less latency)
 740
 741config ARITHMETIC_OPS_L1
 742        bool "Locate kernel owned arithmetic functions in L1 Memory"
 743        default y
 744        depends on !SMP
 745        help
 746          If enabled, arithmetic functions are linked
 747          into L1 instruction memory. (less latency)
 748
 749config ACCESS_OK_L1
 750        bool "Locate access_ok function in L1 Memory"
 751        default y
 752        depends on !SMP
 753        help
 754          If enabled, the access_ok function is linked
 755          into L1 instruction memory. (less latency)
 756
 757config MEMSET_L1
 758        bool "Locate memset function in L1 Memory"
 759        default y
 760        depends on !SMP
 761        help
 762          If enabled, the memset function is linked
 763          into L1 instruction memory. (less latency)
 764
 765config MEMCPY_L1
 766        bool "Locate memcpy function in L1 Memory"
 767        default y
 768        depends on !SMP
 769        help
 770          If enabled, the memcpy function is linked
 771          into L1 instruction memory. (less latency)
 772
 773config STRCMP_L1
 774        bool "locate strcmp function in L1 Memory"
 775        default y
 776        depends on !SMP
 777        help
 778          If enabled, the strcmp function is linked
 779          into L1 instruction memory (less latency).
 780
 781config STRNCMP_L1
 782        bool "locate strncmp function in L1 Memory"
 783        default y
 784        depends on !SMP
 785        help
 786          If enabled, the strncmp function is linked
 787          into L1 instruction memory (less latency).
 788
 789config STRCPY_L1
 790        bool "locate strcpy function in L1 Memory"
 791        default y
 792        depends on !SMP
 793        help
 794          If enabled, the strcpy function is linked
 795          into L1 instruction memory (less latency).
 796
 797config STRNCPY_L1
 798        bool "locate strncpy function in L1 Memory"
 799        default y
 800        depends on !SMP
 801        help
 802          If enabled, the strncpy function is linked
 803          into L1 instruction memory (less latency).
 804
 805config SYS_BFIN_SPINLOCK_L1
 806        bool "Locate sys_bfin_spinlock function in L1 Memory"
 807        default y
 808        depends on !SMP
 809        help
 810          If enabled, sys_bfin_spinlock function is linked
 811          into L1 instruction memory. (less latency)
 812
 813config IP_CHECKSUM_L1
 814        bool "Locate IP Checksum function in L1 Memory"
 815        default n
 816        depends on !SMP
 817        help
 818          If enabled, the IP Checksum function is linked
 819          into L1 instruction memory. (less latency)
 820
 821config CACHELINE_ALIGNED_L1
 822        bool "Locate cacheline_aligned data to L1 Data Memory"
 823        default y if !BF54x
 824        default n if BF54x
 825        depends on !SMP && !BF531
 826        help
 827          If enabled, cacheline_aligned data is linked
 828          into L1 data memory. (less latency)
 829
 830config SYSCALL_TAB_L1
 831        bool "Locate Syscall Table L1 Data Memory"
 832        default n
 833        depends on !SMP && !BF531
 834        help
 835          If enabled, the Syscall LUT is linked
 836          into L1 data memory. (less latency)
 837
 838config CPLB_SWITCH_TAB_L1
 839        bool "Locate CPLB Switch Tables L1 Data Memory"
 840        default n
 841        depends on !SMP && !BF531
 842        help
 843          If enabled, the CPLB Switch Tables are linked
 844          into L1 data memory. (less latency)
 845
 846config ICACHE_FLUSH_L1
 847        bool "Locate icache flush funcs in L1 Inst Memory"
 848        default y
 849        help
 850          If enabled, the Blackfin icache flushing functions are linked
 851          into L1 instruction memory.
 852
 853          Note that this might be required to address anomalies, but
 854          these functions are pretty small, so it shouldn't be too bad.
 855          If you are using a processor affected by an anomaly, the build
 856          system will double check for you and prevent it.
 857
 858config DCACHE_FLUSH_L1
 859        bool "Locate dcache flush funcs in L1 Inst Memory"
 860        default y
 861        depends on !SMP
 862        help
 863          If enabled, the Blackfin dcache flushing functions are linked
 864          into L1 instruction memory.
 865
 866config APP_STACK_L1
 867        bool "Support locating application stack in L1 Scratch Memory"
 868        default y
 869        depends on !SMP
 870        help
 871          If enabled the application stack can be located in L1
 872          scratch memory (less latency).
 873
 874          Currently only works with FLAT binaries.
 875
 876config EXCEPTION_L1_SCRATCH
 877        bool "Locate exception stack in L1 Scratch Memory"
 878        default n
 879        depends on !SMP && !APP_STACK_L1
 880        help
 881          Whenever an exception occurs, use the L1 Scratch memory for
 882          stack storage.  You cannot place the stacks of FLAT binaries
 883          in L1 when using this option.
 884
 885          If you don't use L1 Scratch, then you should say Y here.
 886
 887comment "Speed Optimizations"
 888config BFIN_INS_LOWOVERHEAD
 889        bool "ins[bwl] low overhead, higher interrupt latency"
 890        default y
 891        depends on !SMP
 892        help
 893          Reads on the Blackfin are speculative. In Blackfin terms, this means
 894          they can be interrupted at any time (even after they have been issued
 895          on to the external bus), and re-issued after the interrupt occurs.
 896          For memory - this is not a big deal, since memory does not change if
 897          it sees a read.
 898
 899          If a FIFO is sitting on the end of the read, it will see two reads,
 900          when the core only sees one since the FIFO receives both the read
 901          which is cancelled (and not delivered to the core) and the one which
 902          is re-issued (which is delivered to the core).
 903
 904          To solve this, interrupts are turned off before reads occur to
 905          I/O space. This option controls which the overhead/latency of
 906          controlling interrupts during this time
 907           "n" turns interrupts off every read
 908                (higher overhead, but lower interrupt latency)
 909           "y" turns interrupts off every loop
 910                (low overhead, but longer interrupt latency)
 911
 912          default behavior is to leave this set to on (type "Y"). If you are experiencing
 913          interrupt latency issues, it is safe and OK to turn this off.
 914
 915endmenu
 916
 917choice
 918        prompt "Kernel executes from"
 919        help
 920          Choose the memory type that the kernel will be running in.
 921
 922config RAMKERNEL
 923        bool "RAM"
 924        help
 925          The kernel will be resident in RAM when running.
 926
 927config ROMKERNEL
 928        bool "ROM"
 929        help
 930          The kernel will be resident in FLASH/ROM when running.
 931
 932endchoice
 933
 934# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 935config XIP_KERNEL
 936        bool
 937        default y
 938        depends on ROMKERNEL
 939
 940source "mm/Kconfig"
 941
 942config BFIN_GPTIMERS
 943        tristate "Enable Blackfin General Purpose Timers API"
 944        default n
 945        help
 946          Enable support for the General Purpose Timers API.  If you
 947          are unsure, say N.
 948
 949          To compile this driver as a module, choose M here: the module
 950          will be called gptimers.
 951
 952config HAVE_PWM
 953        tristate "Enable PWM API support"
 954        depends on BFIN_GPTIMERS
 955        help
 956          Enable support for the Pulse Width Modulation framework (as
 957          found in linux/pwm.h).
 958
 959          To compile this driver as a module, choose M here: the module
 960          will be called pwm.
 961
 962choice
 963        prompt "Uncached DMA region"
 964        default DMA_UNCACHED_1M
 965config DMA_UNCACHED_4M
 966        bool "Enable 4M DMA region"
 967config DMA_UNCACHED_2M
 968        bool "Enable 2M DMA region"
 969config DMA_UNCACHED_1M
 970        bool "Enable 1M DMA region"
 971config DMA_UNCACHED_512K
 972        bool "Enable 512K DMA region"
 973config DMA_UNCACHED_256K
 974        bool "Enable 256K DMA region"
 975config DMA_UNCACHED_128K
 976        bool "Enable 128K DMA region"
 977config DMA_UNCACHED_NONE
 978        bool "Disable DMA region"
 979endchoice
 980
 981
 982comment "Cache Support"
 983
 984config BFIN_ICACHE
 985        bool "Enable ICACHE"
 986        default y
 987config BFIN_EXTMEM_ICACHEABLE
 988        bool "Enable ICACHE for external memory"
 989        depends on BFIN_ICACHE
 990        default y
 991config BFIN_L2_ICACHEABLE
 992        bool "Enable ICACHE for L2 SRAM"
 993        depends on BFIN_ICACHE
 994        depends on BF54x || BF561
 995        default n
 996
 997config BFIN_DCACHE
 998        bool "Enable DCACHE"
 999        default y
1000config BFIN_DCACHE_BANKA
1001        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1002        depends on BFIN_DCACHE && !BF531
1003        default n
1004config BFIN_EXTMEM_DCACHEABLE
1005        bool "Enable DCACHE for external memory"
1006        depends on BFIN_DCACHE
1007        default y
1008choice
1009        prompt "External memory DCACHE policy"
1010        depends on BFIN_EXTMEM_DCACHEABLE
1011        default BFIN_EXTMEM_WRITEBACK if !SMP
1012        default BFIN_EXTMEM_WRITETHROUGH if SMP
1013config BFIN_EXTMEM_WRITEBACK
1014        bool "Write back"
1015        depends on !SMP
1016        help
1017          Write Back Policy:
1018            Cached data will be written back to SDRAM only when needed.
1019            This can give a nice increase in performance, but beware of
1020            broken drivers that do not properly invalidate/flush their
1021            cache.
1022
1023          Write Through Policy:
1024            Cached data will always be written back to SDRAM when the
1025            cache is updated.  This is a completely safe setting, but
1026            performance is worse than Write Back.
1027
1028          If you are unsure of the options and you want to be safe,
1029          then go with Write Through.
1030
1031config BFIN_EXTMEM_WRITETHROUGH
1032        bool "Write through"
1033        help
1034          Write Back Policy:
1035            Cached data will be written back to SDRAM only when needed.
1036            This can give a nice increase in performance, but beware of
1037            broken drivers that do not properly invalidate/flush their
1038            cache.
1039
1040          Write Through Policy:
1041            Cached data will always be written back to SDRAM when the
1042            cache is updated.  This is a completely safe setting, but
1043            performance is worse than Write Back.
1044
1045          If you are unsure of the options and you want to be safe,
1046          then go with Write Through.
1047
1048endchoice
1049
1050config BFIN_L2_DCACHEABLE
1051        bool "Enable DCACHE for L2 SRAM"
1052        depends on BFIN_DCACHE
1053        depends on (BF54x || BF561) && !SMP
1054        default n
1055choice
1056        prompt "L2 SRAM DCACHE policy"
1057        depends on BFIN_L2_DCACHEABLE
1058        default BFIN_L2_WRITEBACK
1059config BFIN_L2_WRITEBACK
1060        bool "Write back"
1061
1062config BFIN_L2_WRITETHROUGH
1063        bool "Write through"
1064endchoice
1065
1066
1067comment "Memory Protection Unit"
1068config MPU
1069        bool "Enable the memory protection unit (EXPERIMENTAL)"
1070        default n
1071        help
1072          Use the processor's MPU to protect applications from accessing
1073          memory they do not own.  This comes at a performance penalty
1074          and is recommended only for debugging.
1075
1076comment "Asynchronous Memory Configuration"
1077
1078menu "EBIU_AMGCTL Global Control"
1079config C_AMCKEN
1080        bool "Enable CLKOUT"
1081        default y
1082
1083config C_CDPRIO
1084        bool "DMA has priority over core for ext. accesses"
1085        default n
1086
1087config C_B0PEN
1088        depends on BF561
1089        bool "Bank 0 16 bit packing enable"
1090        default y
1091
1092config C_B1PEN
1093        depends on BF561
1094        bool "Bank 1 16 bit packing enable"
1095        default y
1096
1097config C_B2PEN
1098        depends on BF561
1099        bool "Bank 2 16 bit packing enable"
1100        default y
1101
1102config C_B3PEN
1103        depends on BF561
1104        bool "Bank 3 16 bit packing enable"
1105        default n
1106
1107choice
1108        prompt "Enable Asynchronous Memory Banks"
1109        default C_AMBEN_ALL
1110
1111config C_AMBEN
1112        bool "Disable All Banks"
1113
1114config C_AMBEN_B0
1115        bool "Enable Bank 0"
1116
1117config C_AMBEN_B0_B1
1118        bool "Enable Bank 0 & 1"
1119
1120config C_AMBEN_B0_B1_B2
1121        bool "Enable Bank 0 & 1 & 2"
1122
1123config C_AMBEN_ALL
1124        bool "Enable All Banks"
1125endchoice
1126endmenu
1127
1128menu "EBIU_AMBCTL Control"
1129config BANK_0
1130        hex "Bank 0 (AMBCTL0.L)"
1131        default 0x7BB0
1132        help
1133          These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1134          used to control the Asynchronous Memory Bank 0 settings.
1135
1136config BANK_1
1137        hex "Bank 1 (AMBCTL0.H)"
1138        default 0x7BB0
1139        default 0x5558 if BF54x
1140        help
1141          These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1142          used to control the Asynchronous Memory Bank 1 settings.
1143
1144config BANK_2
1145        hex "Bank 2 (AMBCTL1.L)"
1146        default 0x7BB0
1147        help
1148          These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1149          used to control the Asynchronous Memory Bank 2 settings.
1150
1151config BANK_3
1152        hex "Bank 3 (AMBCTL1.H)"
1153        default 0x99B3
1154        help
1155          These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1156          used to control the Asynchronous Memory Bank 3 settings.
1157
1158endmenu
1159
1160config EBIU_MBSCTLVAL
1161        hex "EBIU Bank Select Control Register"
1162        depends on BF54x
1163        default 0
1164
1165config EBIU_MODEVAL
1166        hex "Flash Memory Mode Control Register"
1167        depends on BF54x
1168        default 1
1169
1170config EBIU_FCTLVAL
1171        hex "Flash Memory Bank Control Register"
1172        depends on BF54x
1173        default 6
1174endmenu
1175
1176#############################################################################
1177menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1178
1179config PCI
1180        bool "PCI support"
1181        depends on BROKEN
1182        help
1183          Support for PCI bus.
1184
1185source "drivers/pci/Kconfig"
1186
1187source "drivers/pcmcia/Kconfig"
1188
1189source "drivers/pci/hotplug/Kconfig"
1190
1191endmenu
1192
1193menu "Executable file formats"
1194
1195source "fs/Kconfig.binfmt"
1196
1197endmenu
1198
1199menu "Power management options"
1200
1201source "kernel/power/Kconfig"
1202
1203config ARCH_SUSPEND_POSSIBLE
1204        def_bool y
1205
1206choice
1207        prompt "Standby Power Saving Mode"
1208        depends on PM
1209        default PM_BFIN_SLEEP_DEEPER
1210config  PM_BFIN_SLEEP_DEEPER
1211        bool "Sleep Deeper"
1212        help
1213          Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1214          power dissipation by disabling the clock to the processor core (CCLK).
1215          Furthermore, Standby sets the internal power supply voltage (VDDINT)
1216          to 0.85 V to provide the greatest power savings, while preserving the
1217          processor state.
1218          The PLL and system clock (SCLK) continue to operate at a very low
1219          frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1220          the SDRAM is put into Self Refresh Mode. Typically an external event
1221          such as GPIO interrupt or RTC activity wakes up the processor.
1222          Various Peripherals such as UART, SPORT, PPI may not function as
1223          normal during Sleep Deeper, due to the reduced SCLK frequency.
1224          When in the sleep mode, system DMA access to L1 memory is not supported.
1225
1226          If unsure, select "Sleep Deeper".
1227
1228config  PM_BFIN_SLEEP
1229        bool "Sleep"
1230        help
1231          Sleep Mode (High Power Savings) - The sleep mode reduces power
1232          dissipation by disabling the clock to the processor core (CCLK).
1233          The PLL and system clock (SCLK), however, continue to operate in
1234          this mode. Typically an external event or RTC activity will wake
1235          up the processor. When in the sleep mode, system DMA access to L1
1236          memory is not supported.
1237
1238          If unsure, select "Sleep Deeper".
1239endchoice
1240
1241comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1242        depends on PM
1243
1244config PM_BFIN_WAKE_PH6
1245        bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1246        depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1247        default n
1248        help
1249          Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1250
1251config PM_BFIN_WAKE_GP
1252        bool "Allow Wake-Up from GPIOs"
1253        depends on PM && BF54x
1254        default n
1255        help
1256          Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1257          (all processors, except ADSP-BF549). This option sets
1258          the general-purpose wake-up enable (GPWE) control bit to enable
1259          wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1260          On ADSP-BF549 this option enables the the same functionality on the
1261          /MRXON pin also PH7.
1262
1263endmenu
1264
1265menu "CPU Frequency scaling"
1266
1267source "drivers/cpufreq/Kconfig"
1268
1269config BFIN_CPU_FREQ
1270        bool
1271        depends on CPU_FREQ
1272        select CPU_FREQ_TABLE
1273        default y
1274
1275config CPU_VOLTAGE
1276        bool "CPU Voltage scaling"
1277        depends on EXPERIMENTAL
1278        depends on CPU_FREQ
1279        default n
1280        help
1281          Say Y here if you want CPU voltage scaling according to the CPU frequency.
1282          This option violates the PLL BYPASS recommendation in the Blackfin Processor
1283          manuals. There is a theoretical risk that during VDDINT transitions
1284          the PLL may unlock.
1285
1286endmenu
1287
1288source "net/Kconfig"
1289
1290source "drivers/Kconfig"
1291
1292source "drivers/firmware/Kconfig"
1293
1294source "fs/Kconfig"
1295
1296source "arch/blackfin/Kconfig.debug"
1297
1298source "security/Kconfig"
1299
1300source "crypto/Kconfig"
1301
1302source "lib/Kconfig"
1303
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.