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17#include <asm/unaligned.h>
18#include "hw.h"
19#include "ar9002_phy.h"
20
21#define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
22
23static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
24{
25 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
26}
27
28static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
29{
30 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
31}
32
33static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
34{
35 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
36 struct ath_common *common = ath9k_hw_common(ah);
37 u16 *eep_data;
38 int addr, eep_start_loc = AR9287_EEP_START_LOC;
39 eep_data = (u16 *)eep;
40
41 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
42 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
43 eep_data)) {
44 ath_dbg(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region\n");
46 return false;
47 }
48 eep_data++;
49 }
50
51 return true;
52}
53
54static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
55{
56 u16 *eep_data = (u16 *)&ah->eeprom.map9287;
57
58 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
59 AR9287_HTC_EEP_START_LOC,
60 SIZE_EEPROM_AR9287);
61 return true;
62}
63
64static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
65{
66 struct ath_common *common = ath9k_hw_common(ah);
67
68 if (!ath9k_hw_use_flash(ah)) {
69 ath_dbg(common, ATH_DBG_EEPROM,
70 "Reading from EEPROM, not flash\n");
71 }
72
73 if (common->bus_ops->ath_bus_type == ATH_USB)
74 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
75 else
76 return __ath9k_hw_ar9287_fill_eeprom(ah);
77}
78
79#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
80static u32 ar9287_dump_modal_eeprom(char *buf, u32 len, u32 size,
81 struct modal_eep_ar9287_header *modal_hdr)
82{
83 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
84 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
85 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
86 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
87 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
88 PR_EEP("Switch Settle", modal_hdr->switchSettling);
89 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
90 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]);
91 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
92 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]);
93 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
94 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
95 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
96 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
97 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
98 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
99 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
100 PR_EEP("xpdGain", modal_hdr->xpdGain);
101 PR_EEP("External PD", modal_hdr->xpd);
102 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
103 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]);
104 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
105 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]);
106 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
107 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
108 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
109 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
110 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
111 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
112 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]);
113 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
114 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]);
115 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
116 PR_EEP("AR92x7 Version", modal_hdr->version);
117 PR_EEP("DriverBias1", modal_hdr->db1);
118 PR_EEP("DriverBias2", modal_hdr->db1);
119 PR_EEP("CCK OutputBias", modal_hdr->ob_cck);
120 PR_EEP("PSK OutputBias", modal_hdr->ob_psk);
121 PR_EEP("QAM OutputBias", modal_hdr->ob_qam);
122 PR_EEP("PAL_OFF OutputBias", modal_hdr->ob_pal_off);
123
124 return len;
125}
126
127static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
128 u8 *buf, u32 len, u32 size)
129{
130 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
131 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
132
133 if (!dump_base_hdr) {
134 len += snprintf(buf + len, size - len,
135 "%20s :\n", "2GHz modal Header");
136 len += ar9287_dump_modal_eeprom(buf, len, size,
137 &eep->modalHeader);
138 goto out;
139 }
140
141 PR_EEP("Major Version", pBase->version >> 12);
142 PR_EEP("Minor Version", pBase->version & 0xFFF);
143 PR_EEP("Checksum", pBase->checksum);
144 PR_EEP("Length", pBase->length);
145 PR_EEP("RegDomain1", pBase->regDmn[0]);
146 PR_EEP("RegDomain2", pBase->regDmn[1]);
147 PR_EEP("TX Mask", pBase->txMask);
148 PR_EEP("RX Mask", pBase->rxMask);
149 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
150 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
151 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
152 AR5416_OPFLAGS_N_2G_HT20));
153 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
154 AR5416_OPFLAGS_N_2G_HT40));
155 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
156 AR5416_OPFLAGS_N_5G_HT20));
157 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
158 AR5416_OPFLAGS_N_5G_HT40));
159 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
160 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
161 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
162 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
163 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
164 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
165
166 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
167 pBase->macAddr);
168
169out:
170 if (len > size)
171 len = size;
172
173 return len;
174}
175#else
176static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
177 u8 *buf, u32 len, u32 size)
178{
179 return 0;
180}
181#endif
182
183
184static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
185{
186 u32 sum = 0, el, integer;
187 u16 temp, word, magic, magic2, *eepdata;
188 int i, addr;
189 bool need_swap = false;
190 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
191 struct ath_common *common = ath9k_hw_common(ah);
192
193 if (!ath9k_hw_use_flash(ah)) {
194 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
195 &magic)) {
196 ath_err(common, "Reading Magic # failed\n");
197 return false;
198 }
199
200 ath_dbg(common, ATH_DBG_EEPROM,
201 "Read Magic = 0x%04X\n", magic);
202
203 if (magic != AR5416_EEPROM_MAGIC) {
204 magic2 = swab16(magic);
205
206 if (magic2 == AR5416_EEPROM_MAGIC) {
207 need_swap = true;
208 eepdata = (u16 *)(&ah->eeprom);
209
210 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
211 temp = swab16(*eepdata);
212 *eepdata = temp;
213 eepdata++;
214 }
215 } else {
216 ath_err(common,
217 "Invalid EEPROM Magic. Endianness mismatch.\n");
218 return -EINVAL;
219 }
220 }
221 }
222
223 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
224 need_swap ? "True" : "False");
225
226 if (need_swap)
227 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
228 else
229 el = ah->eeprom.map9287.baseEepHeader.length;
230
231 if (el > sizeof(struct ar9287_eeprom))
232 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
233 else
234 el = el / sizeof(u16);
235
236 eepdata = (u16 *)(&ah->eeprom);
237
238 for (i = 0; i < el; i++)
239 sum ^= *eepdata++;
240
241 if (need_swap) {
242 word = swab16(eep->baseEepHeader.length);
243 eep->baseEepHeader.length = word;
244
245 word = swab16(eep->baseEepHeader.checksum);
246 eep->baseEepHeader.checksum = word;
247
248 word = swab16(eep->baseEepHeader.version);
249 eep->baseEepHeader.version = word;
250
251 word = swab16(eep->baseEepHeader.regDmn[0]);
252 eep->baseEepHeader.regDmn[0] = word;
253
254 word = swab16(eep->baseEepHeader.regDmn[1]);
255 eep->baseEepHeader.regDmn[1] = word;
256
257 word = swab16(eep->baseEepHeader.rfSilent);
258 eep->baseEepHeader.rfSilent = word;
259
260 word = swab16(eep->baseEepHeader.blueToothOptions);
261 eep->baseEepHeader.blueToothOptions = word;
262
263 word = swab16(eep->baseEepHeader.deviceCap);
264 eep->baseEepHeader.deviceCap = word;
265
266 integer = swab32(eep->modalHeader.antCtrlCommon);
267 eep->modalHeader.antCtrlCommon = integer;
268
269 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
270 integer = swab32(eep->modalHeader.antCtrlChain[i]);
271 eep->modalHeader.antCtrlChain[i] = integer;
272 }
273
274 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
275 word = swab16(eep->modalHeader.spurChans[i].spurChan);
276 eep->modalHeader.spurChans[i].spurChan = word;
277 }
278 }
279
280 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
281 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
282 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
283 sum, ah->eep_ops->get_eeprom_ver(ah));
284 return -EINVAL;
285 }
286
287 return 0;
288}
289
290static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
291 enum eeprom_param param)
292{
293 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
294 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
295 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
296 u16 ver_minor;
297
298 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
299
300 switch (param) {
301 case EEP_NFTHRESH_2:
302 return pModal->noiseFloorThreshCh[0];
303 case EEP_MAC_LSW:
304 return get_unaligned_be16(pBase->macAddr);
305 case EEP_MAC_MID:
306 return get_unaligned_be16(pBase->macAddr + 2);
307 case EEP_MAC_MSW:
308 return get_unaligned_be16(pBase->macAddr + 4);
309 case EEP_REG_0:
310 return pBase->regDmn[0];
311 case EEP_OP_CAP:
312 return pBase->deviceCap;
313 case EEP_OP_MODE:
314 return pBase->opCapFlags;
315 case EEP_RF_SILENT:
316 return pBase->rfSilent;
317 case EEP_MINOR_REV:
318 return ver_minor;
319 case EEP_TX_MASK:
320 return pBase->txMask;
321 case EEP_RX_MASK:
322 return pBase->rxMask;
323 case EEP_DEV_TYPE:
324 return pBase->deviceType;
325 case EEP_OL_PWRCTRL:
326 return pBase->openLoopPwrCntl;
327 case EEP_TEMPSENSE_SLOPE:
328 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
329 return pBase->tempSensSlope;
330 else
331 return 0;
332 case EEP_TEMPSENSE_SLOPE_PAL_ON:
333 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
334 return pBase->tempSensSlopePalOn;
335 else
336 return 0;
337 case EEP_ANTENNA_GAIN_2G:
338 return max_t(u8, pModal->antennaGainCh[0],
339 pModal->antennaGainCh[1]);
340 default:
341 return 0;
342 }
343}
344
345static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
346 struct ath9k_channel *chan,
347 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
348 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
349{
350 u16 idxL = 0, idxR = 0, numPiers;
351 bool match;
352 struct chan_centers centers;
353
354 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
355
356 for (numPiers = 0; numPiers < availPiers; numPiers++) {
357 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
358 break;
359 }
360
361 match = ath9k_hw_get_lower_upper_index(
362 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
363 pCalChans, numPiers, &idxL, &idxR);
364
365 if (match) {
366 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
367 } else {
368 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
369 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
370 }
371
372}
373
374static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
375 int32_t txPower, u16 chain)
376{
377 u32 tmpVal;
378 u32 a;
379
380
381
382 tmpVal = REG_READ(ah, 0xa270);
383 tmpVal = tmpVal & 0xFCFFFFFF;
384 tmpVal = tmpVal | (0x3 << 24);
385 REG_WRITE(ah, 0xa270, tmpVal);
386
387
388
389 tmpVal = REG_READ(ah, 0xb270);
390 tmpVal = tmpVal & 0xFCFFFFFF;
391 tmpVal = tmpVal | (0x3 << 24);
392 REG_WRITE(ah, 0xb270, tmpVal);
393
394
395
396 if (chain == 0) {
397 tmpVal = REG_READ(ah, 0xa398);
398 tmpVal = tmpVal & 0xff00ffff;
399 a = (txPower)&0xff;
400 tmpVal = tmpVal | (a << 16);
401 REG_WRITE(ah, 0xa398, tmpVal);
402 }
403
404
405
406 if (chain == 1) {
407 tmpVal = REG_READ(ah, 0xb398);
408 tmpVal = tmpVal & 0xff00ffff;
409 a = (txPower)&0xff;
410 tmpVal = tmpVal | (a << 16);
411 REG_WRITE(ah, 0xb398, tmpVal);
412 }
413}
414
415static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
416 struct ath9k_channel *chan)
417{
418 struct cal_data_per_freq_ar9287 *pRawDataset;
419 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
420 u8 *pCalBChans = NULL;
421 u16 pdGainOverlap_t2;
422 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
423 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
424 u16 numPiers = 0, i, j;
425 u16 numXpdGain, xpdMask;
426 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
427 u32 reg32, regOffset, regChainOffset, regval;
428 int16_t diff = 0;
429 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
430
431 xpdMask = pEepData->modalHeader.xpdGain;
432
433 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
434 AR9287_EEP_MINOR_VER_2)
435 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
436 else
437 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
438 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
439
440 if (IS_CHAN_2GHZ(chan)) {
441 pCalBChans = pEepData->calFreqPier2G;
442 numPiers = AR9287_NUM_2G_CAL_PIERS;
443 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
444 pRawDatasetOpenLoop =
445 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
446 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
447 }
448 }
449
450 numXpdGain = 0;
451
452
453 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
454 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
455 if (numXpdGain >= AR5416_NUM_PD_GAINS)
456 break;
457 xpdGainValues[numXpdGain] =
458 (u16)(AR5416_PD_GAINS_IN_MASK-i);
459 numXpdGain++;
460 }
461 }
462
463 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
464 (numXpdGain - 1) & 0x3);
465 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
466 xpdGainValues[0]);
467 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
468 xpdGainValues[1]);
469 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
470 xpdGainValues[2]);
471
472 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
473 regChainOffset = i * 0x1000;
474
475 if (pEepData->baseEepHeader.txMask & (1 << i)) {
476 pRawDatasetOpenLoop =
477 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
478
479 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
480 int8_t txPower;
481 ar9287_eeprom_get_tx_gain_index(ah, chan,
482 pRawDatasetOpenLoop,
483 pCalBChans, numPiers,
484 &txPower);
485 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
486 } else {
487 pRawDataset =
488 (struct cal_data_per_freq_ar9287 *)
489 pEepData->calPierData2G[i];
490
491 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
492 pRawDataset,
493 pCalBChans, numPiers,
494 pdGainOverlap_t2,
495 gainBoundaries,
496 pdadcValues,
497 numXpdGain);
498 }
499
500 ENABLE_REGWRITE_BUFFER(ah);
501
502 if (i == 0) {
503 if (!ath9k_hw_ar9287_get_eeprom(ah,
504 EEP_OL_PWRCTRL)) {
505
506 regval = SM(pdGainOverlap_t2,
507 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
508 | SM(gainBoundaries[0],
509 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
510 | SM(gainBoundaries[1],
511 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
512 | SM(gainBoundaries[2],
513 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
514 | SM(gainBoundaries[3],
515 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
516
517 REG_WRITE(ah,
518 AR_PHY_TPCRG5 + regChainOffset,
519 regval);
520 }
521 }
522
523 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
524 pEepData->baseEepHeader.pwrTableOffset) {
525 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
526 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
527 diff *= 2;
528
529 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
530 pdadcValues[j] = pdadcValues[j+diff];
531
532 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
533 j < AR5416_NUM_PDADC_VALUES; j++)
534 pdadcValues[j] =
535 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
536 }
537
538 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
539 regOffset = AR_PHY_BASE +
540 (672 << 2) + regChainOffset;
541
542 for (j = 0; j < 32; j++) {
543 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
544
545 REG_WRITE(ah, regOffset, reg32);
546 regOffset += 4;
547 }
548 }
549 REGWRITE_BUFFER_FLUSH(ah);
550 }
551 }
552}
553
554static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
555 struct ath9k_channel *chan,
556 int16_t *ratesArray,
557 u16 cfgCtl,
558 u16 antenna_reduction,
559 u16 powerLimit)
560{
561#define CMP_CTL \
562 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
563 pEepData->ctlIndex[i])
564
565#define CMP_NO_CTL \
566 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
567 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
568
569#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
570#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
571
572 u16 twiceMaxEdgePower = MAX_RATE_POWER;
573 int i;
574 struct cal_ctl_data_ar9287 *rep;
575 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
576 targetPowerCck = {0, {0, 0, 0, 0} };
577 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
578 targetPowerCckExt = {0, {0, 0, 0, 0} };
579 struct cal_target_power_ht targetPowerHt20,
580 targetPowerHt40 = {0, {0, 0, 0, 0} };
581 u16 scaledPower = 0, minCtlPower;
582 static const u16 ctlModesFor11g[] = {
583 CTL_11B, CTL_11G, CTL_2GHT20,
584 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
585 };
586 u16 numCtlModes = 0;
587 const u16 *pCtlMode = NULL;
588 u16 ctlMode, freq;
589 struct chan_centers centers;
590 int tx_chainmask;
591 u16 twiceMinEdgePower;
592 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
593 tx_chainmask = ah->txchainmask;
594
595 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
596 scaledPower = powerLimit - antenna_reduction;
597
598
599
600
601
602 switch (ar5416_get_ntxchains(tx_chainmask)) {
603 case 1:
604 break;
605 case 2:
606 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
607 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
608 else
609 scaledPower = 0;
610 break;
611 case 3:
612 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
613 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
614 else
615 scaledPower = 0;
616 break;
617 }
618 scaledPower = max((u16)0, scaledPower);
619
620
621
622
623 if (IS_CHAN_2GHZ(chan)) {
624
625 numCtlModes =
626 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
627
628 pCtlMode = ctlModesFor11g;
629
630 ath9k_hw_get_legacy_target_powers(ah, chan,
631 pEepData->calTargetPowerCck,
632 AR9287_NUM_2G_CCK_TARGET_POWERS,
633 &targetPowerCck, 4, false);
634 ath9k_hw_get_legacy_target_powers(ah, chan,
635 pEepData->calTargetPower2G,
636 AR9287_NUM_2G_20_TARGET_POWERS,
637 &targetPowerOfdm, 4, false);
638 ath9k_hw_get_target_powers(ah, chan,
639 pEepData->calTargetPower2GHT20,
640 AR9287_NUM_2G_20_TARGET_POWERS,
641 &targetPowerHt20, 8, false);
642
643 if (IS_CHAN_HT40(chan)) {
644
645 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
646 ath9k_hw_get_target_powers(ah, chan,
647 pEepData->calTargetPower2GHT40,
648 AR9287_NUM_2G_40_TARGET_POWERS,
649 &targetPowerHt40, 8, true);
650 ath9k_hw_get_legacy_target_powers(ah, chan,
651 pEepData->calTargetPowerCck,
652 AR9287_NUM_2G_CCK_TARGET_POWERS,
653 &targetPowerCckExt, 4, true);
654 ath9k_hw_get_legacy_target_powers(ah, chan,
655 pEepData->calTargetPower2G,
656 AR9287_NUM_2G_20_TARGET_POWERS,
657 &targetPowerOfdmExt, 4, true);
658 }
659 }
660
661 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
662 bool isHt40CtlMode =
663 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
664
665 if (isHt40CtlMode)
666 freq = centers.synth_center;
667 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
668 freq = centers.ext_center;
669 else
670 freq = centers.ctl_center;
671
672
673 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
674 struct cal_ctl_edges *pRdEdgesPower;
675
676
677
678
679
680 if (CMP_CTL || CMP_NO_CTL) {
681 rep = &(pEepData->ctlData[i]);
682 pRdEdgesPower =
683 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
684
685 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
686 pRdEdgesPower,
687 IS_CHAN_2GHZ(chan),
688 AR5416_NUM_BAND_EDGES);
689
690 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
691 twiceMaxEdgePower = min(twiceMaxEdgePower,
692 twiceMinEdgePower);
693 } else {
694 twiceMaxEdgePower = twiceMinEdgePower;
695 break;
696 }
697 }
698 }
699
700 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
701
702
703 switch (pCtlMode[ctlMode]) {
704 case CTL_11B:
705 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
706 targetPowerCck.tPow2x[i] =
707 (u8)min((u16)targetPowerCck.tPow2x[i],
708 minCtlPower);
709 }
710 break;
711 case CTL_11A:
712 case CTL_11G:
713 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
714 targetPowerOfdm.tPow2x[i] =
715 (u8)min((u16)targetPowerOfdm.tPow2x[i],
716 minCtlPower);
717 }
718 break;
719 case CTL_5GHT20:
720 case CTL_2GHT20:
721 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
722 targetPowerHt20.tPow2x[i] =
723 (u8)min((u16)targetPowerHt20.tPow2x[i],
724 minCtlPower);
725 }
726 break;
727 case CTL_11B_EXT:
728 targetPowerCckExt.tPow2x[0] =
729 (u8)min((u16)targetPowerCckExt.tPow2x[0],
730 minCtlPower);
731 break;
732 case CTL_11A_EXT:
733 case CTL_11G_EXT:
734 targetPowerOfdmExt.tPow2x[0] =
735 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
736 minCtlPower);
737 break;
738 case CTL_5GHT40:
739 case CTL_2GHT40:
740 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
741 targetPowerHt40.tPow2x[i] =
742 (u8)min((u16)targetPowerHt40.tPow2x[i],
743 minCtlPower);
744 }
745 break;
746 default:
747 break;
748 }
749 }
750
751
752
753 ratesArray[rate6mb] =
754 ratesArray[rate9mb] =
755 ratesArray[rate12mb] =
756 ratesArray[rate18mb] =
757 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
758
759 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
760 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
761 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
762 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
763
764 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
765 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
766
767 if (IS_CHAN_2GHZ(chan)) {
768 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
769 ratesArray[rate2s] =
770 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
771 ratesArray[rate5_5s] =
772 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
773 ratesArray[rate11s] =
774 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
775 }
776 if (IS_CHAN_HT40(chan)) {
777 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
778 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
779
780 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
781 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
782 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
783
784 if (IS_CHAN_2GHZ(chan))
785 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
786 }
787
788#undef CMP_CTL
789#undef CMP_NO_CTL
790#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
791#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
792}
793
794static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
795 struct ath9k_channel *chan, u16 cfgCtl,
796 u8 twiceAntennaReduction,
797 u8 powerLimit, bool test)
798{
799 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
800 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
801 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
802 int16_t ratesArray[Ar5416RateSize];
803 u8 ht40PowerIncForPdadc = 2;
804 int i;
805
806 memset(ratesArray, 0, sizeof(ratesArray));
807
808 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
809 AR9287_EEP_MINOR_VER_2)
810 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
811
812 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
813 &ratesArray[0], cfgCtl,
814 twiceAntennaReduction,
815 powerLimit);
816
817 ath9k_hw_set_ar9287_power_cal_table(ah, chan);
818
819 regulatory->max_power_level = 0;
820 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
821 if (ratesArray[i] > MAX_RATE_POWER)
822 ratesArray[i] = MAX_RATE_POWER;
823
824 if (ratesArray[i] > regulatory->max_power_level)
825 regulatory->max_power_level = ratesArray[i];
826 }
827
828 if (test)
829 return;
830
831 for (i = 0; i < Ar5416RateSize; i++)
832 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
833
834 ENABLE_REGWRITE_BUFFER(ah);
835
836
837 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
838 ATH9K_POW_SM(ratesArray[rate18mb], 24)
839 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
840 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
841 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
842
843 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
844 ATH9K_POW_SM(ratesArray[rate54mb], 24)
845 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
846 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
847 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
848
849
850 if (IS_CHAN_2GHZ(chan)) {
851 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
852 ATH9K_POW_SM(ratesArray[rate2s], 24)
853 | ATH9K_POW_SM(ratesArray[rate2l], 16)
854 | ATH9K_POW_SM(ratesArray[rateXr], 8)
855 | ATH9K_POW_SM(ratesArray[rate1l], 0));
856 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
857 ATH9K_POW_SM(ratesArray[rate11s], 24)
858 | ATH9K_POW_SM(ratesArray[rate11l], 16)
859 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
860 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
861 }
862
863
864 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
865 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
866 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
867 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
868 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
869
870 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
871 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
872 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
873 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
874 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
875
876
877 if (IS_CHAN_HT40(chan)) {
878 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
879 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
880 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
881 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
882 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
883 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
884
885 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
886 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
887 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
888 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
889 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
890 } else {
891 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
892 ATH9K_POW_SM(ratesArray[rateHt40_3] +
893 ht40PowerIncForPdadc, 24)
894 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
895 ht40PowerIncForPdadc, 16)
896 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
897 ht40PowerIncForPdadc, 8)
898 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
899 ht40PowerIncForPdadc, 0));
900
901 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
902 ATH9K_POW_SM(ratesArray[rateHt40_7] +
903 ht40PowerIncForPdadc, 24)
904 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
905 ht40PowerIncForPdadc, 16)
906 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
907 ht40PowerIncForPdadc, 8)
908 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
909 ht40PowerIncForPdadc, 0));
910 }
911
912
913 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
914 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
915 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
916 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
917 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
918 }
919 REGWRITE_BUFFER_FLUSH(ah);
920}
921
922static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
923 struct ath9k_channel *chan)
924{
925 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
926 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
927 u32 regChainOffset, regval;
928 u8 txRxAttenLocal;
929 int i;
930
931 pModal = &eep->modalHeader;
932
933 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
934
935 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
936 regChainOffset = i * 0x1000;
937
938 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
939 pModal->antCtrlChain[i]);
940
941 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
942 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
943 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
944 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
945 SM(pModal->iqCalICh[i],
946 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
947 SM(pModal->iqCalQCh[i],
948 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
949
950 txRxAttenLocal = pModal->txRxAttenCh[i];
951
952 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
953 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
954 pModal->bswMargin[i]);
955 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
956 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
957 pModal->bswAtten[i]);
958 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
959 AR9280_PHY_RXGAIN_TXRX_ATTEN,
960 txRxAttenLocal);
961 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
962 AR9280_PHY_RXGAIN_TXRX_MARGIN,
963 pModal->rxTxMarginCh[i]);
964 }
965
966
967 if (IS_CHAN_HT40(chan))
968 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
969 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
970 else
971 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
972 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
973
974 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
975 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
976
977 REG_WRITE(ah, AR_PHY_RF_CTL4,
978 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
979 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
980 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
981 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
982
983 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
984 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
985
986 REG_RMW_FIELD(ah, AR_PHY_CCA,
987 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
988 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
989 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
990
991 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
992 regval &= ~(AR9287_AN_RF2G3_DB1 |
993 AR9287_AN_RF2G3_DB2 |
994 AR9287_AN_RF2G3_OB_CCK |
995 AR9287_AN_RF2G3_OB_PSK |
996 AR9287_AN_RF2G3_OB_QAM |
997 AR9287_AN_RF2G3_OB_PAL_OFF);
998 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
999 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1000 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1001 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1002 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1003 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1004
1005 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
1006
1007 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
1008 regval &= ~(AR9287_AN_RF2G3_DB1 |
1009 AR9287_AN_RF2G3_DB2 |
1010 AR9287_AN_RF2G3_OB_CCK |
1011 AR9287_AN_RF2G3_OB_PSK |
1012 AR9287_AN_RF2G3_OB_QAM |
1013 AR9287_AN_RF2G3_OB_PAL_OFF);
1014 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1015 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1016 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1017 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1018 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1019 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1020
1021 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
1022
1023 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1024 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1025 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1026 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1027
1028 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1029 AR9287_AN_TOP2_XPABIAS_LVL,
1030 AR9287_AN_TOP2_XPABIAS_LVL_S,
1031 pModal->xpaBiasLvl);
1032}
1033
1034static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1035 u16 i, bool is2GHz)
1036{
1037#define EEP_MAP9287_SPURCHAN \
1038 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1039
1040 struct ath_common *common = ath9k_hw_common(ah);
1041 u16 spur_val = AR_NO_SPUR;
1042
1043 ath_dbg(common, ATH_DBG_ANI,
1044 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1045 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1046
1047 switch (ah->config.spurmode) {
1048 case SPUR_DISABLE:
1049 break;
1050 case SPUR_ENABLE_IOCTL:
1051 spur_val = ah->config.spurchans[i][is2GHz];
1052 ath_dbg(common, ATH_DBG_ANI,
1053 "Getting spur val from new loc. %d\n", spur_val);
1054 break;
1055 case SPUR_ENABLE_EEPROM:
1056 spur_val = EEP_MAP9287_SPURCHAN;
1057 break;
1058 }
1059
1060 return spur_val;
1061
1062#undef EEP_MAP9287_SPURCHAN
1063}
1064
1065const struct eeprom_ops eep_ar9287_ops = {
1066 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1067 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1068 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1069 .dump_eeprom = ath9k_hw_ar9287_dump_eeprom,
1070 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1071 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1072 .set_board_values = ath9k_hw_ar9287_set_board_values,
1073 .set_txpower = ath9k_hw_ar9287_set_txpower,
1074 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1075};
1076
