/*
 *      Intel IO-APIC support for multi-Pentium hosts.
 *
 *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *
 *      Many thanks to Stig Venaas for trying out countless experimental
 *      patches and reporting/debugging problems patiently!
 *
 *      (c) 1999, Multiple IO-APIC support, developed by
 *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 *      further tested and cleaned up by Zach Brown <zab@redhat.com>
 *      and Ingo Molnar <mingo@redhat.com>
 *
 *      Fixes
 *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
 *                                      thanks to Eric Gilmore
 *                                      and Rolf G. Tews
 *                                      for testing these extensively
 *      Paul Diefenbaugh        :       Added full ACPI support
 */

#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/mc146818rtc.h>
#include <linux/compiler.h>
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/syscore_ops.h>
#include <linux/msi.h>
#include <linux/htirq.h>
#include <linux/freezer.h>
#include <linux/kthread.h>
#include <linux/jiffies.h>      /* time_after() */
#include <linux/slab.h>
#ifdef CONFIG_ACPI
#include <acpi/acpi_bus.h>
#endif
#include <linux/bootmem.h>
#include <linux/dmar.h>
#include <linux/hpet.h>

#include <asm/idle.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/cpu.h>
#include <asm/desc.h>
#include <asm/proto.h>
#include <asm/acpi.h>
#include <asm/dma.h>
#include <asm/timer.h>
#include <asm/i8259.h>
#include <asm/msidef.h>
#include <asm/hypertransport.h>
#include <asm/setup.h>
#include <asm/irq_remapping.h>
#include <asm/hpet.h>
#include <asm/hw_irq.h>

#include <asm/apic.h>

#define __apicdebuginit(type) static type __init
#define for_each_irq_pin(entry, head) \
        for (entry = head; entry; entry = entry->next)

/*
 *      Is the SiS APIC rmw bug present ?
 *      -1 = don't know, 0 = no, 1 = yes
 */
int sis_apic_bug = -1;

static DEFINE_RAW_SPINLOCK(ioapic_lock);
static DEFINE_RAW_SPINLOCK(vector_lock);

static struct ioapic {
        /*
         * # of IRQ routing registers
         */
        int nr_registers;
        /*
         * Saved state during suspend/resume, or while enabling intr-remap.
         */
        struct IO_APIC_route_entry *saved_registers;
        /* I/O APIC config */
        struct mpc_ioapic mp_config;
        /* IO APIC gsi routing info */
        struct mp_ioapic_gsi  gsi_config;
        DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
} ioapics[MAX_IO_APICS];

#define mpc_ioapic_ver(ioapic_idx)      ioapics[ioapic_idx].mp_config.apicver

int mpc_ioapic_id(int ioapic_idx)
{
        return ioapics[ioapic_idx].mp_config.apicid;
}

unsigned int mpc_ioapic_addr(int ioapic_idx)
{
        return ioapics[ioapic_idx].mp_config.apicaddr;
}

struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
{
        return &ioapics[ioapic_idx].gsi_config;
}

int nr_ioapics;

/* The one past the highest gsi number used */
u32 gsi_top;

/* MP IRQ source entries */
struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* # of MP IRQ source entries */
int mp_irq_entries;

/* GSI interrupts */
static int nr_irqs_gsi = NR_IRQS_LEGACY;

#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
int mp_bus_id_to_type[MAX_MP_BUSSES];
#endif

DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);

int skip_ioapic_setup;

/**
 * disable_ioapic_support() - disables ioapic support at runtime
 */
void disable_ioapic_support(void)
{
#ifdef CONFIG_PCI
        noioapicquirk = 1;
        noioapicreroute = -1;
#endif
        skip_ioapic_setup = 1;
}

static int __init parse_noapic(char *str)
{
        /* disable IO-APIC */
        disable_ioapic_support();
        return 0;
}
early_param("noapic", parse_noapic);

static int io_apic_setup_irq_pin(unsigned int irq, int node,
                                 struct io_apic_irq_attr *attr);

/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
void mp_save_irq(struct mpc_intsrc *m)
{
        int i;

        apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
                m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
                m->srcbusirq, m->dstapic, m->dstirq);

        for (i = 0; i < mp_irq_entries; i++) {
                if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
                        return;
        }

        memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
        if (++mp_irq_entries == MAX_IRQ_SOURCES)
                panic("Max # of irq sources exceeded!!\n");
}

struct irq_pin_list {
        int apic, pin;
        struct irq_pin_list *next;
};

static struct irq_pin_list *alloc_irq_pin_list(int node)
{
        return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
}


/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];

int __init arch_early_irq_init(void)
{
        struct irq_cfg *cfg;
        int count, node, i;

        if (!legacy_pic->nr_legacy_irqs)
                io_apic_irqs = ~0UL;

        for (i = 0; i < nr_ioapics; i++) {
                ioapics[i].saved_registers =
                        kzalloc(sizeof(struct IO_APIC_route_entry) *
                                ioapics[i].nr_registers, GFP_KERNEL);
                if (!ioapics[i].saved_registers)
                        pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
        }

        cfg = irq_cfgx;
        count = ARRAY_SIZE(irq_cfgx);
        node = cpu_to_node(0);

        /* Make sure the legacy interrupts are marked in the bitmap */
        irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);

        for (i = 0; i < count; i++) {
                irq_set_chip_data(i, &cfg[i]);
                zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
                zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
                /*
                 * For legacy IRQ's, start with assigning irq0 to irq15 to
                 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
                 */
                if (i < legacy_pic->nr_legacy_irqs) {
                        cfg[i].vector = IRQ0_VECTOR + i;
                        cpumask_set_cpu(0, cfg[i].domain);
                }
        }

        return 0;
}

static struct irq_cfg *irq_cfg(unsigned int irq)
{
        return irq_get_chip_data(irq);
}

static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
{
        struct irq_cfg *cfg;

        cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
        if (!cfg)
                return NULL;
        if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
                goto out_cfg;
        if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
                goto out_domain;
        return cfg;
out_domain:
        free_cpumask_var(cfg->domain);
out_cfg:
        kfree(cfg);
        return NULL;
}

static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
{
        if (!cfg)
                return;
        irq_set_chip_data(at, NULL);
        free_cpumask_var(cfg->domain);
        free_cpumask_var(cfg->old_domain);
        kfree(cfg);
}

static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
{
        int res = irq_alloc_desc_at(at, node);
        struct irq_cfg *cfg;

        if (res < 0) {
                if (res != -EEXIST)
                        return NULL;
                cfg = irq_get_chip_data(at);
                if (cfg)
                        return cfg;
        }

        cfg = alloc_irq_cfg(at, node);
        if (cfg)
                irq_set_chip_data(at, cfg);
        else
                irq_free_desc(at);
        return cfg;
}

static int alloc_irq_from(unsigned int from, int node)
{
        return irq_alloc_desc_from(from, node);
}

static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
{
        free_irq_cfg(at, cfg);
        irq_free_desc(at);
}

struct io_apic {
        unsigned int index;
        unsigned int unused[3];
        unsigned int data;
        unsigned int unused2[11];
        unsigned int eoi;
};

static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
{
        return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
                + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
}

static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
{
        struct io_apic __iomem *io_apic = io_apic_base(apic);
        writel(vector, &io_apic->eoi);
}

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
        struct io_apic __iomem *io_apic = io_apic_base(apic);
        writel(reg, &io_apic->index);
        return readl(&io_apic->data);
}

static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
{
        struct io_apic __iomem *io_apic = io_apic_base(apic);
        writel(reg, &io_apic->index);
        writel(value, &io_apic->data);
}

/*
 * Re-write a value: to be used for read-modify-write
 * cycles where the read already set up the index register.
 *
 * Older SiS APIC requires we rewrite the index register
 */
static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
{
        struct io_apic __iomem *io_apic = io_apic_base(apic);

        if (sis_apic_bug)
                writel(reg, &io_apic->index);
        writel(value, &io_apic->data);
}

static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
{
        struct irq_pin_list *entry;
        unsigned long flags;

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        for_each_irq_pin(entry, cfg->irq_2_pin) {
                unsigned int reg;
                int pin;

                pin = entry->pin;
                reg = io_apic_read(entry->apic, 0x10 + pin*2);
                /* Is the remote IRR bit set? */
                if (reg & IO_APIC_REDIR_REMOTE_IRR) {
                        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
                        return true;
                }
        }
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);

        return false;
}

union entry_union {
        struct { u32 w1, w2; };
        struct IO_APIC_route_entry entry;
};

static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
{
        union entry_union eu;

        eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
        eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
        return eu.entry;
}

static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
{
        union entry_union eu;
        unsigned long flags;
        raw_spin_lock_irqsave(&ioapic_lock, flags);
        eu.entry = __ioapic_read_entry(apic, pin);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
        return eu.entry;
}

/*
 * When we write a new IO APIC routing entry, we need to write the high
 * word first! If the mask bit in the low word is clear, we will enable
 * the interrupt, and we need to make sure the entry is fully populated
 * before that happens.
 */
static void
__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
{
        union entry_union eu = {{0, 0}};

        eu.entry = e;
        io_apic_write(apic, 0x11 + 2*pin, eu.w2);
        io_apic_write(apic, 0x10 + 2*pin, eu.w1);
}

static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
{
        unsigned long flags;
        raw_spin_lock_irqsave(&ioapic_lock, flags);
        __ioapic_write_entry(apic, pin, e);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

/*
 * When we mask an IO APIC routing entry, we need to write the low
 * word first, in order to set the mask bit before we change the
 * high bits!
 */
static void ioapic_mask_entry(int apic, int pin)
{
        unsigned long flags;
        union entry_union eu = { .entry.mask = 1 };

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        io_apic_write(apic, 0x10 + 2*pin, eu.w1);
        io_apic_write(apic, 0x11 + 2*pin, eu.w2);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

/*
 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 * shared ISA-space IRQs, so we have to support them. We are super
 * fast in the common case, and fast for shared ISA-space IRQs.
 */
static int
__add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
{
        struct irq_pin_list **last, *entry;

        /* don't allow duplicates */
        last = &cfg->irq_2_pin;
        for_each_irq_pin(entry, cfg->irq_2_pin) {
                if (entry->apic == apic && entry->pin == pin)
                        return 0;
                last = &entry->next;
        }

        entry = alloc_irq_pin_list(node);
        if (!entry) {
                printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
                                node, apic, pin);
                return -ENOMEM;
        }
        entry->apic = apic;
        entry->pin = pin;

        *last = entry;
        return 0;
}

static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
{
        if (__add_pin_to_irq_node(cfg, node, apic, pin))
                panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
}

/*
 * Reroute an IRQ to a different pin.
 */
static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
                                           int oldapic, int oldpin,
                                           int newapic, int newpin)
{
        struct irq_pin_list *entry;

        for_each_irq_pin(entry, cfg->irq_2_pin) {
                if (entry->apic == oldapic && entry->pin == oldpin) {
                        entry->apic = newapic;
                        entry->pin = newpin;
                        /* every one is different, right? */
                        return;
                }
        }

        /* old apic/pin didn't exist, so just add new ones */
        add_pin_to_irq_node(cfg, node, newapic, newpin);
}

static void __io_apic_modify_irq(struct irq_pin_list *entry,
                                 int mask_and, int mask_or,
                                 void (*final)(struct irq_pin_list *entry))
{
        unsigned int reg, pin;

        pin = entry->pin;
        reg = io_apic_read(entry->apic, 0x10 + pin * 2);
        reg &= mask_and;
        reg |= mask_or;
        io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
        if (final)
                final(entry);
}

static void io_apic_modify_irq(struct irq_cfg *cfg,
                               int mask_and, int mask_or,
                               void (*final)(struct irq_pin_list *entry))
{
        struct irq_pin_list *entry;

        for_each_irq_pin(entry, cfg->irq_2_pin)
                __io_apic_modify_irq(entry, mask_and, mask_or, final);
}

static void io_apic_sync(struct irq_pin_list *entry)
{
        /*
         * Synchronize the IO-APIC and the CPU by doing
         * a dummy read from the IO-APIC
         */
        struct io_apic __iomem *io_apic;
        io_apic = io_apic_base(entry->apic);
        readl(&io_apic->data);
}

static void mask_ioapic(struct irq_cfg *cfg)
{
        unsigned long flags;

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

static void mask_ioapic_irq(struct irq_data *data)
{
        mask_ioapic(data->chip_data);
}

static void __unmask_ioapic(struct irq_cfg *cfg)
{
        io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
}

static void unmask_ioapic(struct irq_cfg *cfg)
{
        unsigned long flags;

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        __unmask_ioapic(cfg);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

static void unmask_ioapic_irq(struct irq_data *data)
{
        unmask_ioapic(data->chip_data);
}

/*
 * IO-APIC versions below 0x20 don't support EOI register.
 * For the record, here is the information about various versions:
 *     0Xh     82489DX
 *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
 *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
 *     30h-FFh Reserved
 *
 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
 * version as 0x2. This is an error with documentation and these ICH chips
 * use io-apic's of version 0x20.
 *
 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
 * Otherwise, we simulate the EOI message manually by changing the trigger
 * mode to edge and then back to level, with RTE being masked during this.
 */
static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
{
        if (mpc_ioapic_ver(apic) >= 0x20) {
                /*
                 * Intr-remapping uses pin number as the virtual vector
                 * in the RTE. Actual vector is programmed in
                 * intr-remapping table entry. Hence for the io-apic
                 * EOI we use the pin number.
                 */
                if (cfg && irq_remapped(cfg))
                        io_apic_eoi(apic, pin);
                else
                        io_apic_eoi(apic, vector);
        } else {
                struct IO_APIC_route_entry entry, entry1;

                entry = entry1 = __ioapic_read_entry(apic, pin);

                /*
                 * Mask the entry and change the trigger mode to edge.
                 */
                entry1.mask = 1;
                entry1.trigger = IOAPIC_EDGE;

                __ioapic_write_entry(apic, pin, entry1);

                /*
                 * Restore the previous level triggered entry.
                 */
                __ioapic_write_entry(apic, pin, entry);
        }
}

static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
{
        struct irq_pin_list *entry;
        unsigned long flags;

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        for_each_irq_pin(entry, cfg->irq_2_pin)
                __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
{
        struct IO_APIC_route_entry entry;

        /* Check delivery_mode to be sure we're not clearing an SMI pin */
        entry = ioapic_read_entry(apic, pin);
        if (entry.delivery_mode == dest_SMI)
                return;

        /*
         * Make sure the entry is masked and re-read the contents to check
         * if it is a level triggered pin and if the remote-IRR is set.
         */
        if (!entry.mask) {
                entry.mask = 1;
                ioapic_write_entry(apic, pin, entry);
                entry = ioapic_read_entry(apic, pin);
        }

        if (entry.irr) {
                unsigned long flags;

                /*
                 * Make sure the trigger mode is set to level. Explicit EOI
                 * doesn't clear the remote-IRR if the trigger mode is not
                 * set to level.
                 */
                if (!entry.trigger) {
                        entry.trigger = IOAPIC_LEVEL;
                        ioapic_write_entry(apic, pin, entry);
                }

                raw_spin_lock_irqsave(&ioapic_lock, flags);
                __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
                raw_spin_unlock_irqrestore(&ioapic_lock, flags);
        }

        /*
         * Clear the rest of the bits in the IO-APIC RTE except for the mask
         * bit.
         */
        ioapic_mask_entry(apic, pin);
        entry = ioapic_read_entry(apic, pin);
        if (entry.irr)
                printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
                       mpc_ioapic_id(apic), pin);
}

static void clear_IO_APIC (void)
{
        int apic, pin;

        for (apic = 0; apic < nr_ioapics; apic++)
                for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
                        clear_IO_APIC_pin(apic, pin);
}

#ifdef CONFIG_X86_32
/*
 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 * specific CPU-side IRQs.
 */

#define MAX_PIRQS 8
static int pirq_entries[MAX_PIRQS] = {
        [0 ... MAX_PIRQS - 1] = -1
};

static int __init ioapic_pirq_setup(char *str)
{
        int i, max;
        int ints[MAX_PIRQS+1];

        get_options(str, ARRAY_SIZE(ints), ints);

        apic_printk(APIC_VERBOSE, KERN_INFO
                        "PIRQ redirection, working around broken MP-BIOS.\n");
        max = MAX_PIRQS;
        if (ints[0] < MAX_PIRQS)
                max = ints[0];

        for (i = 0; i < max; i++) {
                apic_printk(APIC_VERBOSE, KERN_DEBUG
                                "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
                /*
                 * PIRQs are mapped upside down, usually.
                 */
                pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
        }
        return 1;
}

__setup("pirq=", ioapic_pirq_setup);
#endif /* CONFIG_X86_32 */

/*
 * Saves all the IO-APIC RTE's
 */
int save_ioapic_entries(void)
{
        int apic, pin;
        int err = 0;

        for (apic = 0; apic < nr_ioapics; apic++) {
                if (!ioapics[apic].saved_registers) {
                        err = -ENOMEM;
                        continue;
                }

                for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
                        ioapics[apic].saved_registers[pin] =
                                ioapic_read_entry(apic, pin);
        }

        return err;
}

/*
 * Mask all IO APIC entries.
 */
void mask_ioapic_entries(void)
{
        int apic, pin;

        for (apic = 0; apic < nr_ioapics; apic++) {
                if (!ioapics[apic].saved_registers)
                        continue;

                for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
                        struct IO_APIC_route_entry entry;

                        entry = ioapics[apic].saved_registers[pin];
                        if (!entry.mask) {
                                entry.mask = 1;
                                ioapic_write_entry(apic, pin, entry);
                        }
                }
        }
}

/*
 * Restore IO APIC entries which was saved in the ioapic structure.
 */
int restore_ioapic_entries(void)
{
        int apic, pin;

        for (apic = 0; apic < nr_ioapics; apic++) {
                if (!ioapics[apic].saved_registers)
                        continue;

                for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
                        ioapic_write_entry(apic, pin,
                                           ioapics[apic].saved_registers[pin]);
        }
        return 0;
}

/*
 * Find the IRQ entry number of a certain pin.
 */
static int find_irq_entry(int ioapic_idx, int pin, int type)
{
        int i;

        for (i = 0; i < mp_irq_entries; i++)
                if (mp_irqs[i].irqtype == type &&
                    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
                     mp_irqs[i].dstapic == MP_APIC_ALL) &&
                    mp_irqs[i].dstirq == pin)
                        return i;

        return -1;
}

/*
 * Find the pin to which IRQ[irq] (ISA) is connected
 */
static int __init find_isa_irq_pin(int irq, int type)
{
        int i;

        for (i = 0; i < mp_irq_entries; i++) {
                int lbus = mp_irqs[i].srcbus;

                if (test_bit(lbus, mp_bus_not_pci) &&
                    (mp_irqs[i].irqtype == type) &&
                    (mp_irqs[i].srcbusirq == irq))

                        return mp_irqs[i].dstirq;
        }
        return -1;
}

static int __init find_isa_irq_apic(int irq, int type)
{
        int i;

        for (i = 0; i < mp_irq_entries; i++) {
                int lbus = mp_irqs[i].srcbus;

                if (test_bit(lbus, mp_bus_not_pci) &&
                    (mp_irqs[i].irqtype == type) &&
                    (mp_irqs[i].srcbusirq == irq))
                        break;
        }

        if (i < mp_irq_entries) {
                int ioapic_idx;

                for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
                        if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
                                return ioapic_idx;
        }

        return -1;
}

#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
/*
 * EISA Edge/Level control register, ELCR
 */
static int EISA_ELCR(unsigned int irq)
{
        if (irq < legacy_pic->nr_legacy_irqs) {
                unsigned int port = 0x4d0 + (irq >> 3);
                return (inb(port) >> (irq & 7)) & 1;
        }
        apic_printk(APIC_VERBOSE, KERN_INFO
                        "Broken MPtable reports ISA irq %d\n", irq);
        return 0;
}

#endif

/* ISA interrupts are always polarity zero edge triggered,
 * when listed as conforming in the MP table. */

#define default_ISA_trigger(idx)        (0)
#define default_ISA_polarity(idx)       (0)

/* EISA interrupts are always polarity zero and can be edge or level
 * trigger depending on the ELCR value.  If an interrupt is listed as
 * EISA conforming in the MP table, that means its trigger type must
 * be read in from the ELCR */

#define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
#define default_EISA_polarity(idx)      default_ISA_polarity(idx)

/* PCI interrupts are always polarity one level triggered,
 * when listed as conforming in the MP table. */

#define default_PCI_trigger(idx)        (1)
#define default_PCI_polarity(idx)       (1)

/* MCA interrupts are always polarity zero level triggered,
 * when listed as conforming in the MP table. */

#define default_MCA_trigger(idx)        (1)
#define default_MCA_polarity(idx)       default_ISA_polarity(idx)

static int irq_polarity(int idx)
{
        int bus = mp_irqs[idx].srcbus;
        int polarity;

        /*
         * Determine IRQ line polarity (high active or low active):
         */
        switch (mp_irqs[idx].irqflag & 3)
        {
                case 0: /* conforms, ie. bus-type dependent polarity */
                        if (test_bit(bus, mp_bus_not_pci))
                                polarity = default_ISA_polarity(idx);
                        else
                                polarity = default_PCI_polarity(idx);
                        break;
                case 1: /* high active */
                {
                        polarity = 0;
                        break;
                }
                case 2: /* reserved */
                {
                        printk(KERN_WARNING "broken BIOS!!\n");
                        polarity = 1;
                        break;
                }
                case 3: /* low active */
                {
                        polarity = 1;
                        break;
                }
                default: /* invalid */
                {
                        printk(KERN_WARNING "broken BIOS!!\n");
                        polarity = 1;
                        break;
                }
        }
        return polarity;
}

static int irq_trigger(int idx)
{
        int bus = mp_irqs[idx].srcbus;
        int trigger;

        /*
         * Determine IRQ trigger mode (edge or level sensitive):
         */
        switch ((mp_irqs[idx].irqflag>>2) & 3)
        {
                case 0: /* conforms, ie. bus-type dependent */
                        if (test_bit(bus, mp_bus_not_pci))
                                trigger = default_ISA_trigger(idx);
                        else
                                trigger = default_PCI_trigger(idx);
#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
                        switch (mp_bus_id_to_type[bus]) {
                                case MP_BUS_ISA: /* ISA pin */
                                {
                                        /* set before the switch */
                                        break;
                                }
                                case MP_BUS_EISA: /* EISA pin */
                                {
                                        trigger = default_EISA_trigger(idx);
                                        break;
                                }
                                case MP_BUS_PCI: /* PCI pin */
                                {
                                        /* set before the switch */
                                        break;
                                }
                                case MP_BUS_MCA: /* MCA pin */
                                {
                                        trigger = default_MCA_trigger(idx);
                                        break;
                                }
                                default:
                                {
                                        printk(KERN_WARNING "broken BIOS!!\n");
                                        trigger = 1;
                                        break;
                                }
                        }
#endif
                        break;
                case 1: /* edge */
                {
                        trigger = 0;
                        break;
                }
                case 2: /* reserved */
                {
                        printk(KERN_WARNING "broken BIOS!!\n");
                        trigger = 1;
                        break;
                }
                case 3: /* level */
                {
                        trigger = 1;
                        break;
                }
                default: /* invalid */
                {
                        printk(KERN_WARNING "broken BIOS!!\n");
                        trigger = 0;
                        break;
                }
        }
        return trigger;
}

static int pin_2_irq(int idx, int apic, int pin)
{
        int irq;
        int bus = mp_irqs[idx].srcbus;
        struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);

        /*
         * Debugging check, we are in big trouble if this message pops up!
         */
        if (mp_irqs[idx].dstirq != pin)
                printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");

        if (test_bit(bus, mp_bus_not_pci)) {
                irq = mp_irqs[idx].srcbusirq;
        } else {
                u32 gsi = gsi_cfg->gsi_base + pin;

                if (gsi >= NR_IRQS_LEGACY)
                        irq = gsi;
                else
                        irq = gsi_top + gsi;
        }

#ifdef CONFIG_X86_32
        /*
         * PCI IRQ command line redirection. Yes, limits are hardcoded.
         */
        if ((pin >= 16) && (pin <= 23)) {
                if (pirq_entries[pin-16] != -1) {
                        if (!pirq_entries[pin-16]) {
                                apic_printk(APIC_VERBOSE, KERN_DEBUG
                                                "disabling PIRQ%d\n", pin-16);
                        } else {
                                irq = pirq_entries[pin-16];
                                apic_printk(APIC_VERBOSE, KERN_DEBUG
                                                "using PIRQ%d -> IRQ %d\n",
                                                pin-16, irq);
                        }
                }
        }
#endif

        return irq;
}

/*
 * Find a specific PCI IRQ entry.
 * Not an __init, possibly needed by modules
 */
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
                                struct io_apic_irq_attr *irq_attr)
{
        int ioapic_idx, i, best_guess = -1;

        apic_printk(APIC_DEBUG,
                    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
                    bus, slot, pin);
        if (test_bit(bus, mp_bus_not_pci)) {
                apic_printk(APIC_VERBOSE,
                            "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
                return -1;
        }
        for (i = 0; i < mp_irq_entries; i++) {
                int lbus = mp_irqs[i].srcbus;

                for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
                        if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
                            mp_irqs[i].dstapic == MP_APIC_ALL)
                                break;

                if (!test_bit(lbus, mp_bus_not_pci) &&
                    !mp_irqs[i].irqtype &&
                    (bus == lbus) &&
                    (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
                        int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);

                        if (!(ioapic_idx || IO_APIC_IRQ(irq)))
                                continue;

                        if (pin == (mp_irqs[i].srcbusirq & 3)) {
                                set_io_apic_irq_attr(irq_attr, ioapic_idx,
                                                     mp_irqs[i].dstirq,
                                                     irq_trigger(i),
                                                     irq_polarity(i));
                                return irq;
                        }
                        /*
                         * Use the first all-but-pin matching entry as a
                         * best-guess fuzzy result for broken mptables.
                         */
                        if (best_guess < 0) {
                                set_io_apic_irq_attr(irq_attr, ioapic_idx,
                                                     mp_irqs[i].dstirq,
                                                     irq_trigger(i),
                                                     irq_polarity(i));
                                best_guess = irq;
                        }
                }
        }
        return best_guess;
}
EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);

void lock_vector_lock(void)
{
        /* Used to the online set of cpus does not change
         * during assign_irq_vector.
         */
        raw_spin_lock(&vector_lock);
}

void unlock_vector_lock(void)
{
        raw_spin_unlock(&vector_lock);
}

static int
__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
{
        /*
         * NOTE! The local APIC isn't very good at handling
         * multiple interrupts at the same interrupt level.
         * As the interrupt level is determined by taking the
         * vector number and shifting that right by 4, we
         * want to spread these out a bit so that they don't
         * all fall in the same interrupt level.
         *
         * Also, we've got to be careful not to trash gate
         * 0x80, because int 0x80 is hm, kind of importantish. ;)
         */
        static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
        static int current_offset = VECTOR_OFFSET_START % 8;
        unsigned int old_vector;
        int cpu, err;
        cpumask_var_t tmp_mask;

        if (cfg->move_in_progress)
                return -EBUSY;

        if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
                return -ENOMEM;

        old_vector = cfg->vector;
        if (old_vector) {
                cpumask_and(tmp_mask, mask, cpu_online_mask);
                cpumask_and(tmp_mask, cfg->domain, tmp_mask);
                if (!cpumask_empty(tmp_mask)) {
                        free_cpumask_var(tmp_mask);
                        return 0;
                }
        }

        /* Only try and allocate irqs on cpus that are present */
        err = -ENOSPC;
        for_each_cpu_and(cpu, mask, cpu_online_mask) {
                int new_cpu;
                int vector, offset;

                apic->vector_allocation_domain(cpu, tmp_mask);

                vector = current_vector;
                offset = current_offset;
next:
                vector += 8;
                if (vector >= first_system_vector) {
                        /* If out of vectors on large boxen, must share them. */
                        offset = (offset + 1) % 8;
                        vector = FIRST_EXTERNAL_VECTOR + offset;
                }
                if (unlikely(current_vector == vector))
                        continue;

                if (test_bit(vector, used_vectors))
                        goto next;

                for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
                        if (per_cpu(vector_irq, new_cpu)[vector] != -1)
                                goto next;
                /* Found one! */
                current_vector = vector;
                current_offset = offset;
                if (old_vector) {
                        cfg->move_in_progress = 1;
                        cpumask_copy(cfg->old_domain, cfg->domain);
                }
                for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
                        per_cpu(vector_irq, new_cpu)[vector] = irq;
                cfg->vector = vector;
                cpumask_copy(cfg->domain, tmp_mask);
                err = 0;
                break;
        }
        free_cpumask_var(tmp_mask);
        return err;
}

int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
{
        int err;
        unsigned long flags;

        raw_spin_lock_irqsave(&vector_lock, flags);
        err = __assign_irq_vector(irq, cfg, mask);
        raw_spin_unlock_irqrestore(&vector_lock, flags);
        return err;
}

static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
{
        int cpu, vector;

        BUG_ON(!cfg->vector);

        vector = cfg->vector;
        for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
                per_cpu(vector_irq, cpu)[vector] = -1;

        cfg->vector = 0;
        cpumask_clear(cfg->domain);

        if (likely(!cfg->move_in_progress))
                return;
        for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
                for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
                                                                vector++) {
                        if (per_cpu(vector_irq, cpu)[vector] != irq)
                                continue;
                        per_cpu(vector_irq, cpu)[vector] = -1;
                        break;
                }
        }
        cfg->move_in_progress = 0;
}

void __setup_vector_irq(int cpu)
{
        /* Initialize vector_irq on a new cpu */
        int irq, vector;
        struct irq_cfg *cfg;

        /*
         * vector_lock will make sure that we don't run into irq vector
         * assignments that might be happening on another cpu in parallel,
         * while we setup our initial vector to irq mappings.
         */
        raw_spin_lock(&vector_lock);
        /* Mark the inuse vectors */
        for_each_active_irq(irq) {
                cfg = irq_get_chip_data(irq);
                if (!cfg)
                        continue;
                /*
                 * If it is a legacy IRQ handled by the legacy PIC, this cpu
                 * will be part of the irq_cfg's domain.
                 */
                if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
                        cpumask_set_cpu(cpu, cfg->domain);

                if (!cpumask_test_cpu(cpu, cfg->domain))
                        continue;
                vector = cfg->vector;
                per_cpu(vector_irq, cpu)[vector] = irq;
        }
        /* Mark the free vectors */
        for (vector = 0; vector < NR_VECTORS; ++vector) {
                irq = per_cpu(vector_irq, cpu)[vector];
                if (irq < 0)
                        continue;

                cfg = irq_cfg(irq);
                if (!cpumask_test_cpu(cpu, cfg->domain))
                        per_cpu(vector_irq, cpu)[vector] = -1;
        }
        raw_spin_unlock(&vector_lock);
}

static struct irq_chip ioapic_chip;

#ifdef CONFIG_X86_32
static inline int IO_APIC_irq_trigger(int irq)
{
        int apic, idx, pin;

        for (apic = 0; apic < nr_ioapics; apic++) {
                for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
                        idx = find_irq_entry(apic, pin, mp_INT);
                        if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
                                return irq_trigger(idx);
                }
        }
        /*
         * nonexistent IRQs are edge default
         */
        return 0;
}
#else
static inline int IO_APIC_irq_trigger(int irq)
{
        return 1;
}
#endif

static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
                                 unsigned long trigger)
{
        struct irq_chip *chip = &ioapic_chip;
        irq_flow_handler_t hdl;
        bool fasteoi;

        if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
            trigger == IOAPIC_LEVEL) {
                irq_set_status_flags(irq, IRQ_LEVEL);
                fasteoi = true;
        } else {
                irq_clear_status_flags(irq, IRQ_LEVEL);
                fasteoi = false;
        }

        if (irq_remapped(cfg)) {
                irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
                irq_remap_modify_chip_defaults(chip);
                fasteoi = trigger != 0;
        }

        hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
        irq_set_chip_and_handler_name(irq, chip, hdl,
                                      fasteoi ? "fasteoi" : "edge");
}


static int setup_ir_ioapic_entry(int irq,
                              struct IR_IO_APIC_route_entry *entry,
                              unsigned int destination, int vector,
                              struct io_apic_irq_attr *attr)
{
        int index;
        struct irte irte;
        int ioapic_id = mpc_ioapic_id(attr->ioapic);
        struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);

        if (!iommu) {
                pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
                return -ENODEV;
        }

        index = alloc_irte(iommu, irq, 1);
        if (index < 0) {
                pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
                return -ENOMEM;
        }

        prepare_irte(&irte, vector, destination);

        /* Set source-id of interrupt request */
        set_ioapic_sid(&irte, ioapic_id);

        modify_irte(irq, &irte);

        apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
                "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
                "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
                "Avail:%X Vector:%02X Dest:%08X "
                "SID:%04X SQ:%X SVT:%X)\n",
                attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
                irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
                irte.avail, irte.vector, irte.dest_id,
                irte.sid, irte.sq, irte.svt);

        memset(entry, 0, sizeof(*entry));

        entry->index2   = (index >> 15) & 0x1;
        entry->zero     = 0;
        entry->format   = 1;
        entry->index    = (index & 0x7fff);
        /*
         * IO-APIC RTE will be configured with virtual vector.
         * irq handler will do the explicit EOI to the io-apic.
         */
        entry->vector   = attr->ioapic_pin;
        entry->mask     = 0;                    /* enable IRQ */
        entry->trigger  = attr->trigger;
        entry->polarity = attr->polarity;

        /* Mask level triggered irqs.
         * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
         */
        if (attr->trigger)
                entry->mask = 1;

        return 0;
}

static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
                               unsigned int destination, int vector,
                               struct io_apic_irq_attr *attr)
{
        if (intr_remapping_enabled)
                return setup_ir_ioapic_entry(irq,
                         (struct IR_IO_APIC_route_entry *)entry,
                         destination, vector, attr);

        memset(entry, 0, sizeof(*entry));

        entry->delivery_mode = apic->irq_delivery_mode;
        entry->dest_mode     = apic->irq_dest_mode;
        entry->dest          = destination;
        entry->vector        = vector;
        entry->mask          = 0;                       /* enable IRQ */
        entry->trigger       = attr->trigger;
        entry->polarity      = attr->polarity;

        /*
         * Mask level triggered irqs.
         * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
         */
        if (attr->trigger)
                entry->mask = 1;

        return 0;
}

static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
                                struct io_apic_irq_attr *attr)
{
        struct IO_APIC_route_entry entry;
        unsigned int dest;

        if (!IO_APIC_IRQ(irq))
                return;
        /*
         * For legacy irqs, cfg->domain starts with cpu 0 for legacy
         * controllers like 8259. Now that IO-APIC can handle this irq, update
         * the cfg->domain.
         */
        if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
                apic->vector_allocation_domain(0, cfg->domain);

        if (assign_irq_vector(irq, cfg, apic->target_cpus()))
                return;

        dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());

        apic_printk(APIC_VERBOSE,KERN_DEBUG
                    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
                    "IRQ %d Mode:%i Active:%i Dest:%d)\n",
                    attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
                    cfg->vector, irq, attr->trigger, attr->polarity, dest);

        if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
                pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
                        mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
                __clear_irq_vector(irq, cfg);

                return;
        }

        ioapic_register_intr(irq, cfg, attr->trigger);
        if (irq < legacy_pic->nr_legacy_irqs)
                legacy_pic->mask(irq);

        ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
}

static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
{
        if (idx != -1)
                return false;

        apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
                    mpc_ioapic_id(ioapic_idx), pin);
        return true;
}

static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
{
        int idx, node = cpu_to_node(0);
        struct io_apic_irq_attr attr;
        unsigned int pin, irq;

        for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
                idx = find_irq_entry(ioapic_idx, pin, mp_INT);
                if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
                        continue;

                irq = pin_2_irq(idx, ioapic_idx, pin);

                if ((ioapic_idx > 0) && (irq > 16))
                        continue;

                /*
                 * Skip the timer IRQ if there's a quirk handler
                 * installed and if it returns 1:
                 */
                if (apic->multi_timer_check &&
                    apic->multi_timer_check(ioapic_idx, irq))
                        continue;

                set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
                                     irq_polarity(idx));

                io_apic_setup_irq_pin(irq, node, &attr);
        }
}

static void __init setup_IO_APIC_irqs(void)
{
        unsigned int ioapic_idx;

        apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");

        for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
                __io_apic_setup_irqs(ioapic_idx);
}

/*
 * for the gsit that is not in first ioapic
 * but could not use acpi_register_gsi()
 * like some special sci in IBM x3330
 */
void setup_IO_APIC_irq_extra(u32 gsi)
{
        int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
        struct io_apic_irq_attr attr;

        /*
         * Convert 'gsi' to 'ioapic.pin'.
         */
        ioapic_idx = mp_find_ioapic(gsi);
        if (ioapic_idx < 0)
                return;

        pin = mp_find_ioapic_pin(ioapic_idx, gsi);
        idx = find_irq_entry(ioapic_idx, pin, mp_INT);
        if (idx == -1)
                return;

        irq = pin_2_irq(idx, ioapic_idx, pin);

        /* Only handle the non legacy irqs on secondary ioapics */
        if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
                return;

        set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
                             irq_polarity(idx));

        io_apic_setup_irq_pin_once(irq, node, &attr);
}

/*
 * Set up the timer pin, possibly with the 8259A-master behind.
 */
static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
                                         unsigned int pin, int vector)
{
        struct IO_APIC_route_entry entry;

        if (intr_remapping_enabled)
                return;

        memset(&entry, 0, sizeof(entry));

        /*
         * We use logical delivery to get the timer IRQ
         * to the first CPU.
         */
        entry.dest_mode = apic->irq_dest_mode;
        entry.mask = 0;                 /* don't mask IRQ for edge */
        entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
        entry.delivery_mode = apic->irq_delivery_mode;
        entry.polarity = 0;
        entry.trigger = 0;
        entry.vector = vector;

        /*
         * The timer IRQ doesn't have to know that behind the
         * scene we may have a 8259A-master in AEOI mode ...
         */
        irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
                                      "edge");

        /*
         * Add it to the IO-APIC irq-routing table:
         */
        ioapic_write_entry(ioapic_idx, pin, entry);
}

__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
{
        int i;
        union IO_APIC_reg_00 reg_00;
        union IO_APIC_reg_01 reg_01;
        union IO_APIC_reg_02 reg_02;
        union IO_APIC_reg_03 reg_03;
        unsigned long flags;

        raw_spin_lock_irqsave(&ioapic_lock, flags);
        reg_00.raw = io_apic_read(ioapic_idx, 0);
        reg_01.raw = io_apic_read(ioapic_idx, 1);
        if (reg_01.bits.version >= 0x10)
                reg_02.raw = io_apic_read(ioapic_idx, 2);
        if (reg_01.bits.version >= 0x20)
                reg_03.raw = io_apic_read(ioapic_idx, 3);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);

        printk("\n");
        printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
        printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
        printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
        printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
        printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);

        printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
        printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
                reg_01.bits.entries);

        printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
        printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
                reg_01.bits.version);

        /*
         * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
         * but the value of reg_02 is read as the previous read register
         * value, so ignore it if reg_02 == reg_01.
         */
        if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
                printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
                printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
        }

        /*
         * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
         * or reg_03, but the value of reg_0[23] is read as the previous read
         * register value, so ignore it if reg_03 == reg_0[12].
         */
        if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
            reg_03.raw != reg_01.raw) {
                printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
                printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
        }

        printk(KERN_DEBUG ".... IRQ redirection table:\n");

        if (intr_remapping_enabled) {
                printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
                        " Pol Stat Indx2 Zero Vect:\n");
        } else {
                printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
                        " Stat Dmod Deli Vect:\n");
        }

        for (i = 0; i <= reg_01.bits.entries; i++) {
                if (intr_remapping_enabled) {
                        struct IO_APIC_route_entry entry;
                        struct IR_IO_APIC_route_entry *ir_entry;

                        entry = ioapic_read_entry(ioapic_idx, i);
                        ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
                        printk(KERN_DEBUG " %02x %04X ",
                                i,
                                ir_entry->index
                        );
                        printk("%1d   %1d    %1d    %1d   %1d   "
                                "%1d    %1d     %X    %02X\n",
                                ir_entry->format,
                                ir_entry->mask,
                                ir_entry->trigger,
                                ir_entry->irr,
                                ir_entry->polarity,
                                ir_entry->delivery_status,
                                ir_entry->index2,
                                ir_entry->zero,
                                ir_entry->vector
                        );
                } else {
                        struct IO_APIC_route_entry entry;

                        entry = ioapic_read_entry(ioapic_idx, i);
                        printk(KERN_DEBUG " %02x %02X  ",
                                i,
                                entry.dest
                        );
                        printk("%1d    %1d    %1d   %1d   %1d    "
                                "%1d    %1d    %02X\n",
                                entry.mask,
                                entry.trigger,
                                entry.irr,
                                entry.polarity,
                                entry.delivery_status,
                                entry.dest_mode,
                                entry.delivery_mode,
                                entry.vector
                        );
                }
        }
}

__apicdebuginit(void) print_IO_APICs(void)
{
        int ioapic_idx;
        struct irq_cfg *cfg;
        unsigned int irq;
        struct irq_chip *chip;

        printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
        for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
                printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
                       mpc_ioapic_id(ioapic_idx),
                       ioapics[ioapic_idx].nr_registers);

        /*
         * We are a bit conservative about what we expect.  We have to
         * know about every hardware change ASAP.
         */
        printk(KERN_INFO "testing the IO APIC.......................\n");

        for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
                print_IO_APIC(ioapic_idx);

        printk(KERN_DEBUG "IRQ to pin mappings:\n");
        for_each_active_irq(irq) {
                struct irq_pin_list *entry;

                chip = irq_get_chip(irq);
                if (chip != &ioapic_chip)
                        continue;

                cfg = irq_get_chip_data(irq);
                if (!cfg)
                        continue;
                entry = cfg->irq_2_pin;
                if (!entry)
                        continue;
                printk(KERN_DEBUG "IRQ%d ", irq);
                for_each_irq_pin(entry, cfg->irq_2_pin)
                        printk("-> %d:%d", entry->apic, entry->pin);
                printk("\n");
        }

        printk(KERN_INFO ".................................... done.\n");
}

__apicdebuginit(void) print_APIC_field(int base)
{
        int i;

        printk(KERN_DEBUG);

        for (i = 0; i < 8; i++)
                printk(KERN_CONT "%08x", apic_read(base + i*0x10));

        printk(KERN_CONT "\n");
}

__apicdebuginit(void) print_local_APIC(void *dummy)
{
        unsigned int i, v, ver, maxlvt;
        u64 icr;

        printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
                smp_processor_id(), hard_smp_processor_id());
        v = apic_read(APIC_ID);
        printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
        v = apic_read(APIC_LVR);
        printk(KERN_INFO "... APIC VERSION: %08x\n", v);
        ver = GET_APIC_VERSION(v);
        maxlvt = lapic_get_maxlvt();

        v = apic_read(APIC_TASKPRI);
        printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);

        if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
                if (!APIC_XAPIC(ver)) {
                        v = apic_read(APIC_ARBPRI);
                        printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
                               v & APIC_ARBPRI_MASK);
                }
                v = apic_read(APIC_PROCPRI);
                printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
        }

        /*
         * Remote read supported only in the 82489DX and local APIC for
         * Pentium processors.
         */
        if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
                v = apic_read(APIC_RRR);
                printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
        }

        v = apic_read(APIC_LDR);
        printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
        if (!x2apic_enabled()) {
                v = apic_read(APIC_DFR);
                printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
        }
        v = apic_read(APIC_SPIV);
        printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);

        printk(KERN_DEBUG "... APIC ISR field:\n");
        print_APIC_field(APIC_ISR);
        printk(KERN_DEBUG "... APIC TMR field:\n");
        print_APIC_field(APIC_TMR);
        printk(KERN_DEBUG "... APIC IRR field:\n");
        print_APIC_field(APIC_IRR);

        if (APIC_INTEGRATED(ver)) {             /* !82489DX */
                if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
                        apic_write(APIC_ESR, 0);

                v = apic_read(APIC_ESR);
                printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
        }

        icr = apic_icr_read();
        printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
        printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));

        v = apic_read(APIC_LVTT);
        printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);

        if (maxlvt > 3) {                       /* PC is LVT#4. */
                v = apic_read(APIC_LVTPC);
                printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
        }
        v = apic_read(APIC_LVT0);
        printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
        v = apic_read(APIC_LVT1);
        printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);

        if (maxlvt > 2) {                       /* ERR is LVT#3. */
                v = apic_read(APIC_LVTERR);
                printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
        }

        v = apic_read(APIC_TMICT);
        printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
        v = apic_read(APIC_TMCCT);
        printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
        v = apic_read(APIC_TDCR);
        printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);

        if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
                v = apic_read(APIC_EFEAT);
                maxlvt = (v >> 16) & 0xff;
                printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
                v = apic_read(APIC_ECTRL);
                printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
                for (i = 0; i < maxlvt; i++) {
                        v = apic_read(APIC_EILVTn(i));
                        printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
                }
        }
        printk("\n");
}

__apicdebuginit(void) print_local_APICs(int maxcpu)
{
        int cpu;

        if (!maxcpu)
                return;

        preempt_disable();
        for_each_online_cpu(cpu) {
                if (cpu >= maxcpu)
                        break;
                smp_call_function_single(cpu, print_local_APIC, NULL, 1);
        }
        preempt_enable();
}

__apicdebuginit(void) print_PIC(void)
{
        unsigned int v;
        unsigned long flags;

        if (!legacy_pic->nr_legacy_irqs)
                return;

        printk(KERN_DEBUG "\nprinting PIC contents\n");

        raw_spin_lock_irqsave(&i8259A_lock, flags);

        v = inb(0xa1) << 8 | inb(0x21);
        printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);

        v = inb(0xa0) << 8 | inb(0x20);
        printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);

        outb(0x0b,0xa0);
        outb(0x0b,0x20);
        v = inb(0xa0) << 8 | inb(0x20);
        outb(0x0a,0xa0);
        outb(0x0a,0x20);

        raw_spin_unlock_irqrestore(&i8259A_lock, flags);

        printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);

        v = inb(0x4d1) << 8 | inb(0x4d0);
        printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
}

static int __initdata show_lapic = 1;
static __init int setup_show_lapic(char *arg)
{
        int num = -1;

        if (strcmp(arg, "all") == 0) {
                show_lapic = CONFIG_NR_CPUS;
        } else {
                get_option(&arg, &num);
                if (num >= 0)
                        show_lapic = num;
        }

        return 1;
}
__setup("show_lapic=", setup_show_lapic);

__apicdebuginit(int) print_ICs(void)
{
        if (apic_verbosity == APIC_QUIET)
                return 0;

        print_PIC();

        /* don't print out if apic is not there */
        if (!cpu_has_apic && !apic_from_smp_config())
                return 0;

        print_local_APICs(show_lapic);
        print_IO_APICs();

        return 0;
}

late_initcall(print_ICs);


/* Where if anywhere is the i8259 connect in external int mode */
static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };

void __init enable_IO_APIC(void)
{
        int i8259_apic, i8259_pin;
        int apic;

        if (!legacy_pic->nr_legacy_irqs)
                return;

        for(apic = 0; apic < nr_ioapics; apic++) {
                int pin;
                /* See if any of the pins is in ExtINT mode */
                for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
                        struct IO_APIC_route_entry entry;
                        entry = ioapic_read_entry(apic, pin);

                        /* If the interrupt line is enabled and in ExtInt mode
                         * I have found the pin where the i8259 is connected.
                         */
                        if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
                                ioapic_i8259.apic = apic;
                                ioapic_i8259.pin  = pin;
                                goto found_i8259;
                        }
                }
        }
 found_i8259:
        /* Look to see what if the MP table has reported the ExtINT */
        /* If we could not find the appropriate pin by looking at the ioapic
         * the i8259 probably is not connected the ioapic but give the
         * mptable a chance anyway.
         */
        i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
        i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
        /* Trust the MP table if nothing is setup in the hardware */
        if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
                printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
                ioapic_i8259.pin  = i8259_pin;
                ioapic_i8259.apic = i8259_apic;
        }
        /* Complain if the MP table and the hardware disagree */
        if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
                (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
        {
                printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
        }

        /*
         * Do not trust the IO-APIC being empty at bootup
         */
        clear_IO_APIC();
}

/*
 * Not an __init, needed by the reboot code
 */
void disable_IO_APIC(void)
{
        /*
         * Clear the IO-APIC before rebooting:
         */
        clear_IO_APIC();