LXR linux/arch/alpha/include/asm/pci.h

   1#ifndef __ALPHA_PCI_H
   2#define __ALPHA_PCI_H
   3
   4#ifdef __KERNEL__
   5
   6#include <linux/spinlock.h>
   7#include <linux/dma-mapping.h>
   8#include <asm/scatterlist.h>
   9#include <asm/machvec.h>
  10
  11/*
  12 * The following structure is used to manage multiple PCI busses.
  13 */
  14
  15struct pci_dev;
  16struct pci_bus;
  17struct resource;
  18struct pci_iommu_arena;
  19struct page;
  20
  21/* A controller.  Used to manage multiple PCI busses.  */
  22
  23struct pci_controller {
  24        struct pci_controller *next;
  25        struct pci_bus *bus;
  26        struct resource *io_space;
  27        struct resource *mem_space;
  28
  29        /* The following are for reporting to userland.  The invariant is
  30           that if we report a BWX-capable dense memory, we do not report
  31           a sparse memory at all, even if it exists.  */
  32        unsigned long sparse_mem_base;
  33        unsigned long dense_mem_base;
  34        unsigned long sparse_io_base;
  35        unsigned long dense_io_base;
  36
  37        /* This one's for the kernel only.  It's in KSEG somewhere.  */
  38        unsigned long config_space_base;
  39
  40        unsigned int index;
  41        /* For compatibility with current (as of July 2003) pciutils
  42           and XFree86. Eventually will be removed. */
  43        unsigned int need_domain_info;
  44
  45        struct pci_iommu_arena *sg_pci;
  46        struct pci_iommu_arena *sg_isa;
  47
  48        void *sysdata;
  49};
  50
  51/* Override the logic in pci_scan_bus for skipping already-configured
  52   bus numbers.  */
  53
  54#define pcibios_assign_all_busses()     1
  55
  56#define PCIBIOS_MIN_IO          alpha_mv.min_io_address
  57#define PCIBIOS_MIN_MEM         alpha_mv.min_mem_address
  58
  59extern void pcibios_set_master(struct pci_dev *dev);
  60
  61extern inline void pcibios_penalize_isa_irq(int irq, int active)
  62{
  63        /* We don't do dynamic PCI IRQ allocation */
  64}
  65
  66/* IOMMU controls.  */
  67
  68/* The PCI address space does not equal the physical memory address space.
  69   The networking and block device layers use this boolean for bounce buffer
  70   decisions.  */
  71#define PCI_DMA_BUS_IS_PHYS  0
  72
  73#ifdef CONFIG_PCI
  74
  75/* implement the pci_ DMA API in terms of the generic device dma_ one */
  76#include <asm-generic/pci-dma-compat.h>
  77
  78static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  79                                        enum pci_dma_burst_strategy *strat,
  80                                        unsigned long *strategy_parameter)
  81{
  82        unsigned long cacheline_size;
  83        u8 byte;
  84
  85        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  86        if (byte == 0)
  87                cacheline_size = 1024;
  88        else
  89                cacheline_size = (int) byte * 4;
  90
  91        *strat = PCI_DMA_BURST_BOUNDARY;
  92        *strategy_parameter = cacheline_size;
  93}
  94#endif
  95
  96/* TODO: integrate with include/asm-generic/pci.h ? */
  97static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  98{
  99        return channel ? 15 : 14;
 100}
 101
 102extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
 103                                    struct resource *);
 104
 105extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 106                                    struct pci_bus_region *region);
 107
 108#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 109
 110static inline int pci_proc_domain(struct pci_bus *bus)
 111{
 112        struct pci_controller *hose = bus->sysdata;
 113        return hose->need_domain_info;
 114}
 115
 116#endif /* __KERNEL__ */
 117
 118/* Values for the `which' argument to sys_pciconfig_iobase.  */
 119#define IOBASE_HOSE             0
 120#define IOBASE_SPARSE_MEM       1
 121#define IOBASE_DENSE_MEM        2
 122#define IOBASE_SPARSE_IO        3
 123#define IOBASE_DENSE_IO         4
 124#define IOBASE_ROOT_BUS         5
 125#define IOBASE_FROM_HOSE        0x10000
 126
 127extern struct pci_dev *isa_bridge;
 128
 129extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
 130                           size_t count);
 131extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
 132                            size_t count);
 133extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 134                                      struct vm_area_struct *vma,
 135                                      enum pci_mmap_state mmap_state);
 136extern void pci_adjust_legacy_attr(struct pci_bus *bus,
 137                                   enum pci_mmap_state mmap_type);
 138#define HAVE_PCI_LEGACY 1
 139
 140extern int pci_create_resource_files(struct pci_dev *dev);
 141extern void pci_remove_resource_files(struct pci_dev *dev);
 142
 143#endif /* __ALPHA_PCI_H */
 144