1
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9
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <linux/slab.h>
26#include <asm/div64.h>
27#include <sound/max98088.h>
28#include "max98088.h"
29
30enum max98088_type {
31 MAX98088,
32 MAX98089,
33};
34
35struct max98088_cdata {
36 unsigned int rate;
37 unsigned int fmt;
38 int eq_sel;
39};
40
41struct max98088_priv {
42 enum max98088_type devtype;
43 struct max98088_pdata *pdata;
44 unsigned int sysclk;
45 struct max98088_cdata dai[2];
46 int eq_textcnt;
47 const char **eq_texts;
48 struct soc_enum eq_enum;
49 u8 ina_state;
50 u8 inb_state;
51 unsigned int ex_mode;
52 unsigned int digmic;
53 unsigned int mic1pre;
54 unsigned int mic2pre;
55 unsigned int extmic_mode;
56};
57
58static const u8 max98088_reg[M98088_REG_CNT] = {
59 0x00,
60 0x00,
61 0x00,
62 0x00,
63 0x00,
64 0x00,
65 0x00,
66 0x00,
67 0x00,
68 0x00,
69 0x00,
70 0x00,
71 0x00,
72 0x00,
73 0x00,
74 0x00,
75
76 0x00,
77 0x00,
78 0x00,
79 0x00,
80 0x00,
81 0x00,
82 0x00,
83 0x00,
84 0x00,
85 0x00,
86 0x00,
87 0x00,
88 0x00,
89 0x00,
90 0x00,
91 0x00,
92
93 0x00,
94 0x00,
95 0x00,
96 0x00,
97 0x00,
98 0x00,
99 0x00,
100 0x00,
101 0x00,
102 0x00,
103 0x00,
104 0x00,
105 0x00,
106 0x00,
107 0x00,
108 0x00,
109
110 0x00,
111 0x00,
112 0x00,
113 0x00,
114 0x00,
115 0x00,
116 0x00,
117 0x00,
118 0x00,
119 0x00,
120 0x00,
121 0x00,
122 0x00,
123 0x00,
124 0x00,
125 0x00,
126
127 0x00,
128 0x00,
129 0x00,
130 0x00,
131 0x00,
132 0x00,
133 0x00,
134 0x00,
135 0x00,
136 0x00,
137 0x00,
138 0x00,
139 0x00,
140 0x00,
141 0xF0,
142 0x00,
143
144 0x0F,
145 0x00,
146 0x00,
147 0x00,
148 0x00,
149 0x00,
150 0x00,
151 0x00,
152 0x00,
153 0x00,
154 0x00,
155 0x00,
156 0x00,
157 0x00,
158 0x00,
159 0x00,
160
161 0x00,
162 0x00,
163 0x00,
164 0x00,
165 0x00,
166 0x00,
167 0x00,
168 0x00,
169 0x00,
170 0x00,
171 0x00,
172 0x00,
173 0x00,
174 0x00,
175 0x00,
176 0x00,
177
178 0x00,
179 0x00,
180 0x00,
181 0x00,
182 0x00,
183 0x00,
184 0x00,
185 0x00,
186 0x00,
187 0x00,
188 0x00,
189 0x00,
190 0x00,
191 0x00,
192 0x00,
193 0x00,
194
195 0x00,
196 0x00,
197 0x00,
198 0x00,
199 0x00,
200 0x00,
201 0x00,
202 0x00,
203 0x00,
204 0x00,
205 0x00,
206 0x00,
207 0x00,
208 0x00,
209 0x00,
210 0x00,
211
212 0x00,
213 0x00,
214 0x00,
215 0x00,
216 0x00,
217 0x00,
218 0x00,
219 0x00,
220 0x00,
221 0x00,
222 0x00,
223 0x00,
224 0x00,
225 0x00,
226 0x00,
227 0x00,
228
229 0x00,
230 0x00,
231 0x00,
232 0x00,
233 0x00,
234 0x00,
235 0x00,
236 0x00,
237 0x00,
238 0x00,
239 0x00,
240 0x00,
241 0x00,
242 0x00,
243 0x00,
244 0x00,
245
246 0x00,
247 0x00,
248 0x00,
249 0x00,
250 0x00,
251 0x00,
252 0x00,
253 0x00,
254 0x00,
255 0x00,
256 0x00,
257 0x00,
258 0x00,
259 0x00,
260 0x00,
261 0x00,
262
263 0x00,
264 0x00,
265 0x00,
266 0x00,
267 0x00,
268 0x00,
269 0x00,
270 0x00,
271 0x00,
272 0x00,
273 0x00,
274 0x00,
275 0x00,
276 0x00,
277 0x00,
278 0x00,
279
280 0x00,
281 0x00,
282 0x00,
283 0x00,
284 0x00,
285 0x00,
286 0x00,
287 0x00,
288 0x00,
289 0x00,
290 0x00,
291 0x70,
292 0x00,
293 0x00,
294 0x00,
295 0x00,
296
297 0x00,
298 0x00,
299 0x00,
300 0x00,
301 0x00,
302 0x00,
303 0x00,
304 0x00,
305 0x00,
306 0x00,
307 0x00,
308 0x00,
309 0x00,
310 0x00,
311 0x00,
312 0x00,
313
314 0x00,
315 0x00,
316 0x00,
317 0x00,
318 0x00,
319 0x00,
320 0x00,
321 0x00,
322 0x00,
323 0x00,
324 0x00,
325 0x00,
326 0x00,
327 0x00,
328 0x00,
329 0x00,
330};
331
332static struct {
333 int readable;
334 int writable;
335 int vol;
336} max98088_access[M98088_REG_CNT] = {
337 { 0xFF, 0xFF, 1 },
338 { 0xFF, 0x00, 1 },
339 { 0xFF, 0x00, 1 },
340 { 0x1F, 0x1F, 1 },
341 { 0xFF, 0xFF, 0 },
342 { 0xFF, 0xFF, 0 },
343 { 0xFF, 0xFF, 0 },
344 { 0xFF, 0xFF, 0 },
345 { 0xFF, 0xFF, 0 },
346 { 0xFF, 0xFF, 0 },
347 { 0xFF, 0xFF, 0 },
348 { 0xFF, 0xFF, 0 },
349 { 0xFF, 0xFF, 0 },
350 { 0xFF, 0xFF, 0 },
351 { 0xFF, 0xFF, 0 },
352 { 0xFF, 0xFF, 0 },
353
354 { 0xFF, 0xFF, 0 },
355 { 0xFF, 0xFF, 0 },
356 { 0xFF, 0xFF, 0 },
357 { 0xFF, 0xFF, 0 },
358 { 0xFF, 0xFF, 0 },
359 { 0xFF, 0xFF, 0 },
360 { 0xFF, 0xFF, 0 },
361 { 0xFF, 0xFF, 0 },
362 { 0xFF, 0xFF, 0 },
363 { 0xFF, 0xFF, 0 },
364 { 0xFF, 0xFF, 0 },
365 { 0xFF, 0xFF, 0 },
366 { 0xFF, 0xFF, 0 },
367 { 0xFF, 0xFF, 0 },
368 { 0xFF, 0xFF, 0 },
369 { 0xFF, 0xFF, 0 },
370
371 { 0xFF, 0xFF, 0 },
372 { 0xFF, 0xFF, 0 },
373 { 0xFF, 0xFF, 0 },
374 { 0xFF, 0xFF, 0 },
375 { 0xFF, 0xFF, 0 },
376 { 0xFF, 0xFF, 0 },
377 { 0xFF, 0xFF, 0 },
378 { 0xFF, 0xFF, 0 },
379 { 0xFF, 0xFF, 0 },
380 { 0xFF, 0xFF, 0 },
381 { 0xFF, 0xFF, 0 },
382 { 0xFF, 0xFF, 0 },
383 { 0xFF, 0xFF, 0 },
384 { 0xFF, 0xFF, 0 },
385 { 0xFF, 0xFF, 0 },
386 { 0xFF, 0xFF, 0 },
387
388 { 0xFF, 0xFF, 0 },
389 { 0xFF, 0xFF, 0 },
390 { 0xFF, 0xFF, 0 },
391 { 0xFF, 0xFF, 0 },
392 { 0xFF, 0xFF, 0 },
393 { 0xFF, 0xFF, 0 },
394 { 0xFF, 0xFF, 0 },
395 { 0xFF, 0xFF, 0 },
396 { 0xFF, 0xFF, 0 },
397 { 0xFF, 0xFF, 0 },
398 { 0xFF, 0xFF, 0 },
399 { 0xFF, 0xFF, 0 },
400 { 0xFF, 0xFF, 0 },
401 { 0xFF, 0xFF, 0 },
402 { 0xFF, 0xFF, 0 },
403 { 0xFF, 0xFF, 0 },
404
405 { 0xFF, 0xFF, 0 },
406 { 0xFF, 0xFF, 0 },
407 { 0xFF, 0xFF, 0 },
408 { 0xFF, 0xFF, 0 },
409 { 0xFF, 0xFF, 0 },
410 { 0xFF, 0xFF, 0 },
411 { 0xFF, 0xFF, 0 },
412 { 0xFF, 0xFF, 0 },
413 { 0xFF, 0xFF, 0 },
414 { 0xFF, 0xFF, 0 },
415 { 0xFF, 0xFF, 0 },
416 { 0xFF, 0xFF, 0 },
417 { 0xFF, 0xFF, 0 },
418 { 0xFF, 0xFF, 0 },
419 { 0xFF, 0xFF, 0 },
420 { 0xFF, 0xFF, 0 },
421
422 { 0xFF, 0xFF, 0 },
423 { 0xFF, 0xFF, 0 },
424 { 0xFF, 0xFF, 0 },
425 { 0xFF, 0xFF, 0 },
426 { 0xFF, 0xFF, 0 },
427 { 0xFF, 0xFF, 0 },
428 { 0xFF, 0xFF, 0 },
429 { 0xFF, 0xFF, 0 },
430 { 0xFF, 0xFF, 0 },
431 { 0xFF, 0xFF, 0 },
432 { 0xFF, 0xFF, 0 },
433 { 0xFF, 0xFF, 0 },
434 { 0xFF, 0xFF, 0 },
435 { 0xFF, 0xFF, 0 },
436 { 0xFF, 0xFF, 0 },
437 { 0xFF, 0xFF, 0 },
438
439 { 0xFF, 0xFF, 0 },
440 { 0xFF, 0xFF, 0 },
441 { 0xFF, 0xFF, 0 },
442 { 0xFF, 0xFF, 0 },
443 { 0xFF, 0xFF, 0 },
444 { 0xFF, 0xFF, 0 },
445 { 0xFF, 0xFF, 0 },
446 { 0xFF, 0xFF, 0 },
447 { 0xFF, 0xFF, 0 },
448 { 0xFF, 0xFF, 0 },
449 { 0xFF, 0xFF, 0 },
450 { 0xFF, 0xFF, 0 },
451 { 0xFF, 0xFF, 0 },
452 { 0xFF, 0xFF, 0 },
453 { 0xFF, 0xFF, 0 },
454 { 0xFF, 0xFF, 0 },
455
456 { 0xFF, 0xFF, 0 },
457 { 0xFF, 0xFF, 0 },
458 { 0xFF, 0xFF, 0 },
459 { 0xFF, 0xFF, 0 },
460 { 0xFF, 0xFF, 0 },
461 { 0xFF, 0xFF, 0 },
462 { 0xFF, 0xFF, 0 },
463 { 0xFF, 0xFF, 0 },
464 { 0xFF, 0xFF, 0 },
465 { 0xFF, 0xFF, 0 },
466 { 0xFF, 0xFF, 0 },
467 { 0xFF, 0xFF, 0 },
468 { 0xFF, 0xFF, 0 },
469 { 0xFF, 0xFF, 0 },
470 { 0xFF, 0xFF, 0 },
471 { 0xFF, 0xFF, 0 },
472
473 { 0xFF, 0xFF, 0 },
474 { 0xFF, 0xFF, 0 },
475 { 0xFF, 0xFF, 0 },
476 { 0xFF, 0xFF, 0 },
477 { 0xFF, 0xFF, 0 },
478 { 0xFF, 0xFF, 0 },
479 { 0xFF, 0xFF, 0 },
480 { 0xFF, 0xFF, 0 },
481 { 0xFF, 0xFF, 0 },
482 { 0xFF, 0xFF, 0 },
483 { 0xFF, 0xFF, 0 },
484 { 0xFF, 0xFF, 0 },
485 { 0xFF, 0xFF, 0 },
486 { 0xFF, 0xFF, 0 },
487 { 0xFF, 0xFF, 0 },
488 { 0xFF, 0xFF, 0 },
489
490 { 0xFF, 0xFF, 0 },
491 { 0xFF, 0xFF, 0 },
492 { 0xFF, 0xFF, 0 },
493 { 0xFF, 0xFF, 0 },
494 { 0xFF, 0xFF, 0 },
495 { 0xFF, 0xFF, 0 },
496 { 0xFF, 0xFF, 0 },
497 { 0xFF, 0xFF, 0 },
498 { 0xFF, 0xFF, 0 },
499 { 0xFF, 0xFF, 0 },
500 { 0xFF, 0xFF, 0 },
501 { 0xFF, 0xFF, 0 },
502 { 0xFF, 0xFF, 0 },
503 { 0xFF, 0xFF, 0 },
504 { 0xFF, 0xFF, 0 },
505 { 0xFF, 0xFF, 0 },
506
507 { 0xFF, 0xFF, 0 },
508 { 0xFF, 0xFF, 0 },
509 { 0xFF, 0xFF, 0 },
510 { 0xFF, 0xFF, 0 },
511 { 0xFF, 0xFF, 0 },
512 { 0xFF, 0xFF, 0 },
513 { 0xFF, 0xFF, 0 },
514 { 0xFF, 0xFF, 0 },
515 { 0xFF, 0xFF, 0 },
516 { 0xFF, 0xFF, 0 },
517 { 0xFF, 0xFF, 0 },
518 { 0xFF, 0xFF, 0 },
519 { 0xFF, 0xFF, 0 },
520 { 0xFF, 0xFF, 0 },
521 { 0xFF, 0xFF, 0 },
522 { 0xFF, 0xFF, 0 },
523
524 { 0xFF, 0xFF, 0 },
525 { 0xFF, 0xFF, 0 },
526 { 0xFF, 0xFF, 0 },
527 { 0xFF, 0xFF, 0 },
528 { 0xFF, 0xFF, 0 },
529 { 0xFF, 0xFF, 0 },
530 { 0xFF, 0xFF, 0 },
531 { 0xFF, 0xFF, 0 },
532 { 0xFF, 0xFF, 0 },
533 { 0xFF, 0xFF, 0 },
534 { 0xFF, 0xFF, 0 },
535 { 0xFF, 0xFF, 0 },
536 { 0xFF, 0xFF, 0 },
537 { 0xFF, 0xFF, 0 },
538 { 0xFF, 0xFF, 0 },
539 { 0xFF, 0xFF, 0 },
540
541 { 0xFF, 0xFF, 0 },
542 { 0xFF, 0xFF, 0 },
543 { 0xFF, 0xFF, 0 },
544 { 0xFF, 0xFF, 0 },
545 { 0xFF, 0xFF, 0 },
546 { 0xFF, 0xFF, 0 },
547 { 0xFF, 0xFF, 0 },
548 { 0xFF, 0xFF, 0 },
549 { 0xFF, 0xFF, 0 },
550 { 0xFF, 0xFF, 0 },
551 { 0x00, 0x00, 0 },
552 { 0x00, 0x00, 0 },
553 { 0x00, 0x00, 0 },
554 { 0x00, 0x00, 0 },
555 { 0x00, 0x00, 0 },
556 { 0x00, 0x00, 0 },
557
558 { 0x00, 0x00, 0 },
559 { 0x00, 0x00, 0 },
560 { 0x00, 0x00, 0 },
561 { 0x00, 0x00, 0 },
562 { 0x00, 0x00, 0 },
563 { 0x00, 0x00, 0 },
564 { 0x00, 0x00, 0 },
565 { 0x00, 0x00, 0 },
566 { 0x00, 0x00, 0 },
567 { 0x00, 0x00, 0 },
568 { 0x00, 0x00, 0 },
569 { 0x00, 0x00, 0 },
570 { 0x00, 0x00, 0 },
571 { 0x00, 0x00, 0 },
572 { 0x00, 0x00, 0 },
573 { 0x00, 0x00, 0 },
574
575 { 0x00, 0x00, 0 },
576 { 0x00, 0x00, 0 },
577 { 0x00, 0x00, 0 },
578 { 0x00, 0x00, 0 },
579 { 0x00, 0x00, 0 },
580 { 0x00, 0x00, 0 },
581 { 0x00, 0x00, 0 },
582 { 0x00, 0x00, 0 },
583 { 0x00, 0x00, 0 },
584 { 0x00, 0x00, 0 },
585 { 0x00, 0x00, 0 },
586 { 0x00, 0x00, 0 },
587 { 0x00, 0x00, 0 },
588 { 0x00, 0x00, 0 },
589 { 0x00, 0x00, 0 },
590 { 0x00, 0x00, 0 },
591
592 { 0x00, 0x00, 0 },
593 { 0x00, 0x00, 0 },
594 { 0x00, 0x00, 0 },
595 { 0x00, 0x00, 0 },
596 { 0x00, 0x00, 0 },
597 { 0x00, 0x00, 0 },
598 { 0x00, 0x00, 0 },
599 { 0x00, 0x00, 0 },
600 { 0x00, 0x00, 0 },
601 { 0x00, 0x00, 0 },
602 { 0x00, 0x00, 0 },
603 { 0x00, 0x00, 0 },
604 { 0x00, 0x00, 0 },
605 { 0x00, 0x00, 0 },
606 { 0x00, 0x00, 0 },
607 { 0xFF, 0x00, 1 },
608};
609
610static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
611{
612 return max98088_access[reg].vol;
613}
614
615
616
617
618
619static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
620 unsigned int band, u16 *coefs)
621{
622 unsigned int eq_reg;
623 unsigned int i;
624
625 BUG_ON(band > 4);
626 BUG_ON(dai > 1);
627
628
629 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
630
631
632 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
633
634
635 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
636 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
637 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
638 }
639}
640
641
642
643
644static const char *max98088_exmode_texts[] = {
645 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
646 "400-600Hz", "400-800Hz",
647};
648
649static const unsigned int max98088_exmode_values[] = {
650 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
651};
652
653static const struct soc_enum max98088_exmode_enum =
654 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
655 ARRAY_SIZE(max98088_exmode_texts),
656 max98088_exmode_texts,
657 max98088_exmode_values);
658
659static const char *max98088_ex_thresh[] = {
660 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
661static const struct soc_enum max98088_ex_thresh_enum[] = {
662 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
663 max98088_ex_thresh),
664};
665
666static const char *max98088_fltr_mode[] = {"Voice", "Music" };
667static const struct soc_enum max98088_filter_mode_enum[] = {
668 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
669};
670
671static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
672
673static const struct soc_enum max98088_extmic_enum =
674 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
675
676static const struct snd_kcontrol_new max98088_extmic_mux =
677 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
678
679static const char *max98088_dai1_fltr[] = {
680 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
681 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
682static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
683 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
684};
685static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
686 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
687};
688
689static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
690 struct snd_ctl_elem_value *ucontrol)
691{
692 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
693 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
694 unsigned int sel = ucontrol->value.integer.value[0];
695
696 max98088->mic1pre = sel;
697 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
698 (1+sel)<<M98088_MICPRE_SHIFT);
699
700 return 0;
701}
702
703static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
704 struct snd_ctl_elem_value *ucontrol)
705{
706 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
707 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
708
709 ucontrol->value.integer.value[0] = max98088->mic1pre;
710 return 0;
711}
712
713static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
714 struct snd_ctl_elem_value *ucontrol)
715{
716 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
717 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
718 unsigned int sel = ucontrol->value.integer.value[0];
719
720 max98088->mic2pre = sel;
721 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
722 (1+sel)<<M98088_MICPRE_SHIFT);
723
724 return 0;
725}
726
727static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_value *ucontrol)
729{
730 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
731 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
732
733 ucontrol->value.integer.value[0] = max98088->mic2pre;
734 return 0;
735}
736
737static const unsigned int max98088_micboost_tlv[] = {
738 TLV_DB_RANGE_HEAD(2),
739 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
740 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
741};
742
743static const struct snd_kcontrol_new max98088_snd_controls[] = {
744
745 SOC_DOUBLE_R("Headphone Volume", M98088_REG_39_LVL_HP_L,
746 M98088_REG_3A_LVL_HP_R, 0, 31, 0),
747 SOC_DOUBLE_R("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
748 M98088_REG_3E_LVL_SPK_R, 0, 31, 0),
749 SOC_DOUBLE_R("Receiver Volume", M98088_REG_3B_LVL_REC_L,
750 M98088_REG_3C_LVL_REC_R, 0, 31, 0),
751
752 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
753 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
754 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
755 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
756 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
757 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
758
759 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
760 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
761
762 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
763 M98088_REG_35_LVL_MIC1, 5, 2, 0,
764 max98088_mic1pre_get, max98088_mic1pre_set,
765 max98088_micboost_tlv),
766 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
767 M98088_REG_36_LVL_MIC2, 5, 2, 0,
768 max98088_mic2pre_get, max98088_mic2pre_set,
769 max98088_micboost_tlv),
770
771 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
772 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
773
774 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
775 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
776
777 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
778 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
779
780 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
781 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
782
783 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
784 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
785
786 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
787 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
788 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
789 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
790 0, 1, 0),
791
792 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
793 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
794 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
795 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
796
797 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
798 4, 15, 0),
799 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
800 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
801 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
802
803 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
804 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
805};
806
807
808static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
809 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
810 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
811 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
812 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
813 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
814 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
815 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
816 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
817 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
818 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
819};
820
821
822static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
823 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
824 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
825 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
826 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
827 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
828 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
829 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
830 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
831 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
832 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
833};
834
835
836static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
837 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
838 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
839 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
840 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
841 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
842 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
843 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
844 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
845 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
846 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
847};
848
849
850static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
851 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
852 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
853 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
854 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
855 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
856 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
857 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
858 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
859 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
860 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
861};
862
863
864static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
865 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
866 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
867 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
868 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
869 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
870 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
871 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
872 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
873 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
874 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
875};
876
877
878static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
879 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
880 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
881 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
882 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
883 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
884 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
885 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
886 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
887 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
888 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
889};
890
891
892static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
893 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
894 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
895 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
896 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
897 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
898 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
899};
900
901
902static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
903 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
904 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
905 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
906 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
907 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
908 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
909};
910
911static int max98088_mic_event(struct snd_soc_dapm_widget *w,
912 struct snd_kcontrol *kcontrol, int event)
913{
914 struct snd_soc_codec *codec = w->codec;
915 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
916
917 switch (event) {
918 case SND_SOC_DAPM_POST_PMU:
919 if (w->reg == M98088_REG_35_LVL_MIC1) {
920 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
921 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
922 } else {
923 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
924 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
925 }
926 break;
927 case SND_SOC_DAPM_POST_PMD:
928 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 return 0;
935}
936
937
938
939
940
941static int max98088_line_pga(struct snd_soc_dapm_widget *w,
942 int event, int line, u8 channel)
943{
944 struct snd_soc_codec *codec = w->codec;
945 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
946 u8 *state;
947
948 BUG_ON(!((channel == 1) || (channel == 2)));
949
950 switch (line) {
951 case LINE_INA:
952 state = &max98088->ina_state;
953 break;
954 case LINE_INB:
955 state = &max98088->inb_state;
956 break;
957 default:
958 return -EINVAL;
959 }
960
961 switch (event) {
962 case SND_SOC_DAPM_POST_PMU:
963 *state |= channel;
964 snd_soc_update_bits(codec, w->reg,
965 (1 << w->shift), (1 << w->shift));
966 break;
967 case SND_SOC_DAPM_POST_PMD:
968 *state &= ~channel;
969 if (*state == 0) {
970 snd_soc_update_bits(codec, w->reg,
971 (1 << w->shift), 0);
972 }
973 break;
974 default:
975 return -EINVAL;
976 }
977
978 return 0;
979}
980
981static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
982 struct snd_kcontrol *k, int event)
983{
984 return max98088_line_pga(w, event, LINE_INA, 1);
985}
986
987static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
988 struct snd_kcontrol *k, int event)
989{
990 return max98088_line_pga(w, event, LINE_INA, 2);
991}
992
993static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
994 struct snd_kcontrol *k, int event)
995{
996 return max98088_line_pga(w, event, LINE_INB, 1);
997}
998
999static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
1000 struct snd_kcontrol *k, int event)
1001{
1002 return max98088_line_pga(w, event, LINE_INB, 2);
1003}
1004
1005static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
1006
1007 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
1008 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
1009
1010 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
1011 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1012 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
1013 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1014 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
1015 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1016 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
1017 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1018
1019 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
1020 7, 0, NULL, 0),
1021 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
1022 6, 0, NULL, 0),
1023
1024 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
1025 5, 0, NULL, 0),
1026 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
1027 4, 0, NULL, 0),
1028
1029 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
1030 3, 0, NULL, 0),
1031 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
1032 2, 0, NULL, 0),
1033
1034 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1035 &max98088_extmic_mux),
1036
1037 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1038 &max98088_left_hp_mixer_controls[0],
1039 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1040
1041 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1042 &max98088_right_hp_mixer_controls[0],
1043 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1044
1045 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1046 &max98088_left_speaker_mixer_controls[0],
1047 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1048
1049 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1050 &max98088_right_speaker_mixer_controls[0],
1051 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1052
1053 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1054 &max98088_left_rec_mixer_controls[0],
1055 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1056
1057 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1058 &max98088_right_rec_mixer_controls[0],
1059 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1060
1061 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1062 &max98088_left_ADC_mixer_controls[0],
1063 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1064
1065 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1066 &max98088_right_ADC_mixer_controls[0],
1067 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1068
1069 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1070 5, 0, NULL, 0, max98088_mic_event,
1071 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1072
1073 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1074 5, 0, NULL, 0, max98088_mic_event,
1075 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1076
1077 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1078 7, 0, NULL, 0, max98088_pga_ina1_event,
1079 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1080
1081 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1082 7, 0, NULL, 0, max98088_pga_ina2_event,
1083 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1084
1085 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1086 6, 0, NULL, 0, max98088_pga_inb1_event,
1087 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1088
1089 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1090 6, 0, NULL, 0, max98088_pga_inb2_event,
1091 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1092
1093 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1094
1095 SND_SOC_DAPM_OUTPUT("HPL"),
1096 SND_SOC_DAPM_OUTPUT("HPR"),
1097 SND_SOC_DAPM_OUTPUT("SPKL"),
1098 SND_SOC_DAPM_OUTPUT("SPKR"),
1099 SND_SOC_DAPM_OUTPUT("RECL"),
1100 SND_SOC_DAPM_OUTPUT("RECR"),
1101
1102 SND_SOC_DAPM_INPUT("MIC1"),
1103 SND_SOC_DAPM_INPUT("MIC2"),
1104 SND_SOC_DAPM_INPUT("INA1"),
1105 SND_SOC_DAPM_INPUT("INA2"),
1106 SND_SOC_DAPM_INPUT("INB1"),
1107 SND_SOC_DAPM_INPUT("INB2"),
1108};
1109
1110static const struct snd_soc_dapm_route max98088_audio_map[] = {
1111
1112 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1113 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1114 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1115 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1116 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1117 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1118 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1119 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1120 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1121 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1122
1123
1124 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1125 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1126 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1127 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1128 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1129 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1130 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1131 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1132 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1133 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1134
1135
1136 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1137 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1138 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1139 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1140 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1141 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1142 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1143 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1144 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1145 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1146
1147
1148 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1149 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1150 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1151 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1152 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1153 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1154 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1155 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1156 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1157 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1158
1159
1160 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1161 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1162 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1163 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1164 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1165 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1166 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1167 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1168 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1169 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1170
1171
1172 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1173 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1174 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1175 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1176 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1177 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1178 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1179 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1180 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1181 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1182
1183 {"HP Left Out", NULL, "Left HP Mixer"},
1184 {"HP Right Out", NULL, "Right HP Mixer"},
1185 {"SPK Left Out", NULL, "Left SPK Mixer"},
1186 {"SPK Right Out", NULL, "Right SPK Mixer"},
1187 {"REC Left Out", NULL, "Left REC Mixer"},
1188 {"REC Right Out", NULL, "Right REC Mixer"},
1189
1190 {"HPL", NULL, "HP Left Out"},
1191 {"HPR", NULL, "HP Right Out"},
1192 {"SPKL", NULL, "SPK Left Out"},
1193 {"SPKR", NULL, "SPK Right Out"},
1194 {"RECL", NULL, "REC Left Out"},
1195 {"RECR", NULL, "REC Right Out"},
1196
1197
1198 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1199 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1200 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1201 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1202 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1203 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1204
1205
1206 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1207 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1208 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1209 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1210 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1211 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1212
1213
1214 {"ADCL", NULL, "Left ADC Mixer"},
1215 {"ADCR", NULL, "Right ADC Mixer"},
1216 {"INA1 Input", NULL, "INA1"},
1217 {"INA2 Input", NULL, "INA2"},
1218 {"INB1 Input", NULL, "INB1"},
1219 {"INB2 Input", NULL, "INB2"},
1220 {"MIC1 Input", NULL, "MIC1"},
1221 {"MIC2 Input", NULL, "MIC2"},
1222};
1223
1224
1225static const struct {
1226 u32 rate;
1227 u8 sr;
1228} rate_table[] = {
1229 {8000, 0x10},
1230 {11025, 0x20},
1231 {16000, 0x30},
1232 {22050, 0x40},
1233 {24000, 0x50},
1234 {32000, 0x60},
1235 {44100, 0x70},
1236 {48000, 0x80},
1237 {88200, 0x90},
1238 {96000, 0xA0},
1239};
1240
1241static inline int rate_value(int rate, u8 *value)
1242{
1243 int i;
1244
1245 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1246 if (rate_table[i].rate >= rate) {
1247 *value = rate_table[i].sr;
1248 return 0;
1249 }
1250 }
1251 *value = rate_table[0].sr;
1252 return -EINVAL;
1253}
1254
1255static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1256 struct snd_pcm_hw_params *params,
1257 struct snd_soc_dai *dai)
1258{
1259 struct snd_soc_codec *codec = dai->codec;
1260 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1261 struct max98088_cdata *cdata;
1262 unsigned long long ni;
1263 unsigned int rate;
1264 u8 regval;
1265
1266 cdata = &max98088->dai[0];
1267
1268 rate = params_rate(params);
1269
1270 switch (params_format(params)) {
1271 case SNDRV_PCM_FORMAT_S16_LE:
1272 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1273 M98088_DAI_WS, 0);
1274 break;
1275 case SNDRV_PCM_FORMAT_S24_LE:
1276 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1277 M98088_DAI_WS, M98088_DAI_WS);
1278 break;
1279 default:
1280 return -EINVAL;
1281 }
1282
1283 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1284
1285 if (rate_value(rate, ®val))
1286 return -EINVAL;
1287
1288 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1289 M98088_CLKMODE_MASK, regval);
1290 cdata->rate = rate;
1291
1292
1293 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1294 & M98088_DAI_MAS) {
1295 if (max98088->sysclk == 0) {
1296 dev_err(codec->dev, "Invalid system clock frequency\n");
1297 return -EINVAL;
1298 }
1299 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1300 * (unsigned long long int)rate;
1301 do_div(ni, (unsigned long long int)max98088->sysclk);
1302 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1303 (ni >> 8) & 0x7F);
1304 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1305 ni & 0xFF);
1306 }
1307
1308
1309 if (rate < 50000)
1310 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1311 M98088_DAI_DHF, 0);
1312 else
1313 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1314 M98088_DAI_DHF, M98088_DAI_DHF);
1315
1316 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1317 M98088_SHDNRUN);
1318
1319 return 0;
1320}
1321
1322static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1323 struct snd_pcm_hw_params *params,
1324 struct snd_soc_dai *dai)
1325{
1326 struct snd_soc_codec *codec = dai->codec;
1327 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1328 struct max98088_cdata *cdata;
1329 unsigned long long ni;
1330 unsigned int rate;
1331 u8 regval;
1332
1333 cdata = &max98088->dai[1];
1334
1335 rate = params_rate(params);
1336
1337 switch (params_format(params)) {
1338 case SNDRV_PCM_FORMAT_S16_LE:
1339 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1340 M98088_DAI_WS, 0);
1341 break;
1342 case SNDRV_PCM_FORMAT_S24_LE:
1343 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1344 M98088_DAI_WS, M98088_DAI_WS);
1345 break;
1346 default:
1347 return -EINVAL;
1348 }
1349
1350 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1351
1352 if (rate_value(rate, ®val))
1353 return -EINVAL;
1354
1355 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1356 M98088_CLKMODE_MASK, regval);
1357 cdata->rate = rate;
1358
1359
1360 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1361 & M98088_DAI_MAS) {
1362 if (max98088->sysclk == 0) {
1363 dev_err(codec->dev, "Invalid system clock frequency\n");
1364 return -EINVAL;
1365 }
1366 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1367 * (unsigned long long int)rate;
1368 do_div(ni, (unsigned long long int)max98088->sysclk);
1369 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1370 (ni >> 8) & 0x7F);
1371 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1372 ni & 0xFF);
1373 }
1374
1375
1376 if (rate < 50000)
1377 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1378 M98088_DAI_DHF, 0);
1379 else
1380 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1381 M98088_DAI_DHF, M98088_DAI_DHF);
1382
1383 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1384 M98088_SHDNRUN);
1385
1386 return 0;
1387}
1388
1389static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1390 int clk_id, unsigned int freq, int dir)
1391{
1392 struct snd_soc_codec *codec = dai->codec;
1393 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1394
1395
1396 if (freq == max98088->sysclk)
1397 return 0;
1398
1399
1400
1401
1402
1403 if ((freq >= 10000000) && (freq < 20000000)) {
1404 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1405 } else if ((freq >= 20000000) && (freq < 30000000)) {
1406 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1407 } else {
1408 dev_err(codec->dev, "Invalid master clock frequency\n");
1409 return -EINVAL;
1410 }
1411
1412 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1413 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1414 M98088_SHDNRUN, 0);
1415 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1416 M98088_SHDNRUN, M98088_SHDNRUN);
1417 }
1418
1419 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1420
1421 max98088->sysclk = freq;
1422 return 0;
1423}
1424
1425static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1426 unsigned int fmt)
1427{
1428 struct snd_soc_codec *codec = codec_dai->codec;
1429 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1430 struct max98088_cdata *cdata;
1431 u8 reg15val;
1432 u8 reg14val = 0;
1433
1434 cdata = &max98088->dai[0];
1435
1436 if (fmt != cdata->fmt) {
1437 cdata->fmt = fmt;
1438
1439 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1440 case SND_SOC_DAIFMT_CBS_CFS:
1441
1442 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1443 0x80);
1444 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1445 0x00);
1446 break;
1447 case SND_SOC_DAIFMT_CBM_CFM:
1448
1449 reg14val |= M98088_DAI_MAS;
1450 break;
1451 case SND_SOC_DAIFMT_CBS_CFM:
1452 case SND_SOC_DAIFMT_CBM_CFS:
1453 default:
1454 dev_err(codec->dev, "Clock mode unsupported");
1455 return -EINVAL;
1456 }
1457
1458 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1459 case SND_SOC_DAIFMT_I2S:
1460 reg14val |= M98088_DAI_DLY;
1461 break;
1462 case SND_SOC_DAIFMT_LEFT_J:
1463 break;
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1469 case SND_SOC_DAIFMT_NB_NF:
1470 break;
1471 case SND_SOC_DAIFMT_NB_IF:
1472 reg14val |= M98088_DAI_WCI;
1473 break;
1474 case SND_SOC_DAIFMT_IB_NF:
1475 reg14val |= M98088_DAI_BCI;
1476 break;
1477 case SND_SOC_DAIFMT_IB_IF:
1478 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1479 break;
1480 default:
1481 return -EINVAL;
1482 }
1483
1484 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1485 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1486 M98088_DAI_WCI, reg14val);
1487
1488 reg15val = M98088_DAI_BSEL64;
1489 if (max98088->digmic)
1490 reg15val |= M98088_DAI_OSR64;
1491 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1492 }
1493
1494 return 0;
1495}
1496
1497static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1498 unsigned int fmt)
1499{
1500 struct snd_soc_codec *codec = codec_dai->codec;
1501 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1502 struct max98088_cdata *cdata;
1503 u8 reg1Cval = 0;
1504
1505 cdata = &max98088->dai[1];
1506
1507 if (fmt != cdata->fmt) {
1508 cdata->fmt = fmt;
1509
1510 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1511 case SND_SOC_DAIFMT_CBS_CFS:
1512
1513 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1514 0x80);
1515 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1516 0x00);
1517 break;
1518 case SND_SOC_DAIFMT_CBM_CFM:
1519
1520 reg1Cval |= M98088_DAI_MAS;
1521 break;
1522 case SND_SOC_DAIFMT_CBS_CFM:
1523 case SND_SOC_DAIFMT_CBM_CFS:
1524 default:
1525 dev_err(codec->dev, "Clock mode unsupported");
1526 return -EINVAL;
1527 }
1528
1529 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1530 case SND_SOC_DAIFMT_I2S:
1531 reg1Cval |= M98088_DAI_DLY;
1532 break;
1533 case SND_SOC_DAIFMT_LEFT_J:
1534 break;
1535 default:
1536 return -EINVAL;
1537 }
1538
1539 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1540 case SND_SOC_DAIFMT_NB_NF:
1541 break;
1542 case SND_SOC_DAIFMT_NB_IF:
1543 reg1Cval |= M98088_DAI_WCI;
1544 break;
1545 case SND_SOC_DAIFMT_IB_NF:
1546 reg1Cval |= M98088_DAI_BCI;
1547 break;
1548 case SND_SOC_DAIFMT_IB_IF:
1549 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1550 break;
1551 default:
1552 return -EINVAL;
1553 }
1554
1555 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1556 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1557 M98088_DAI_WCI, reg1Cval);
1558
1559 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1560 M98088_DAI_BSEL64);
1561 }
1562
1563 return 0;
1564}
1565
1566static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1567{
1568 struct snd_soc_codec *codec = codec_dai->codec;
1569 int reg;
1570
1571 if (mute)
1572 reg = M98088_DAI_MUTE;
1573 else
1574 reg = 0;
1575
1576 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
1577 M98088_DAI_MUTE_MASK, reg);
1578 return 0;
1579}
1580
1581static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1582{
1583 struct snd_soc_codec *codec = codec_dai->codec;
1584 int reg;
1585
1586 if (mute)
1587 reg = M98088_DAI_MUTE;
1588 else
1589 reg = 0;
1590
1591 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
1592 M98088_DAI_MUTE_MASK, reg);
1593 return 0;
1594}
1595
1596static void max98088_sync_cache(struct snd_soc_codec *codec)
1597{
1598 u16 *reg_cache = codec->reg_cache;
1599 int i;
1600
1601 if (!codec->cache_sync)
1602 return;
1603
1604 codec->cache_only = 0;
1605
1606
1607
1608
1609 for (i = 1; i < codec->driver->reg_cache_size; i++) {
1610 if (!max98088_access[i].writable)
1611 continue;
1612
1613 if (reg_cache[i] == max98088_reg[i])
1614 continue;
1615
1616 snd_soc_write(codec, i, reg_cache[i]);
1617 }
1618
1619 codec->cache_sync = 0;
1620}
1621
1622static int max98088_set_bias_level(struct snd_soc_codec *codec,
1623 enum snd_soc_bias_level level)
1624{
1625 switch (level) {
1626 case SND_SOC_BIAS_ON:
1627 break;
1628
1629 case SND_SOC_BIAS_PREPARE:
1630 break;
1631
1632 case SND_SOC_BIAS_STANDBY:
1633 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1634 max98088_sync_cache(codec);
1635
1636 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1637 M98088_MBEN, M98088_MBEN);
1638 break;
1639
1640 case SND_SOC_BIAS_OFF:
1641 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1642 M98088_MBEN, 0);
1643 codec->cache_sync = 1;
1644 break;
1645 }
1646 codec->dapm.bias_level = level;
1647 return 0;
1648}
1649
1650#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1651#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1652
1653static struct snd_soc_dai_ops max98088_dai1_ops = {
1654 .set_sysclk = max98088_dai_set_sysclk,
1655 .set_fmt = max98088_dai1_set_fmt,
1656 .hw_params = max98088_dai1_hw_params,
1657 .digital_mute = max98088_dai1_digital_mute,
1658};
1659
1660static struct snd_soc_dai_ops max98088_dai2_ops = {
1661 .set_sysclk = max98088_dai_set_sysclk,
1662 .set_fmt = max98088_dai2_set_fmt,
1663 .hw_params = max98088_dai2_hw_params,
1664 .digital_mute = max98088_dai2_digital_mute,
1665};
1666
1667static struct snd_soc_dai_driver max98088_dai[] = {
1668{
1669 .name = "HiFi",
1670 .playback = {
1671 .stream_name = "HiFi Playback",
1672 .channels_min = 1,
1673 .channels_max = 2,
1674 .rates = MAX98088_RATES,
1675 .formats = MAX98088_FORMATS,
1676 },
1677 .capture = {
1678 .stream_name = "HiFi Capture",
1679 .channels_min = 1,
1680 .channels_max = 2,
1681 .rates = MAX98088_RATES,
1682 .formats = MAX98088_FORMATS,
1683 },
1684 .ops = &max98088_dai1_ops,
1685},
1686{
1687 .name = "Aux",
1688 .playback = {
1689 .stream_name = "Aux Playback",
1690 .channels_min = 1,
1691 .channels_max = 2,
1692 .rates = MAX98088_RATES,
1693 .formats = MAX98088_FORMATS,
1694 },
1695 .ops = &max98088_dai2_ops,
1696}
1697};
1698
1699static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1700
1701static int max98088_get_channel(struct snd_soc_codec *codec, const char *name)
1702{
1703 int i;
1704
1705 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++)
1706 if (strcmp(name, eq_mode_name[i]) == 0)
1707 return i;
1708
1709
1710 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name);
1711 return -EINVAL;
1712}
1713
1714static void max98088_setup_eq1(struct snd_soc_codec *codec)
1715{
1716 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1717 struct max98088_pdata *pdata = max98088->pdata;
1718 struct max98088_eq_cfg *coef_set;
1719 int best, best_val, save, i, sel, fs;
1720 struct max98088_cdata *cdata;
1721
1722 cdata = &max98088->dai[0];
1723
1724 if (!pdata || !max98088->eq_textcnt)
1725 return;
1726
1727
1728 fs = cdata->rate;
1729 sel = cdata->eq_sel;
1730
1731 best = 0;
1732 best_val = INT_MAX;
1733 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1734 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1735 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1736 best = i;
1737 best_val = abs(pdata->eq_cfg[i].rate - fs);
1738 }
1739 }
1740
1741 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1742 pdata->eq_cfg[best].name,
1743 pdata->eq_cfg[best].rate, fs);
1744
1745
1746 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1747 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1748
1749 coef_set = &pdata->eq_cfg[sel];
1750
1751 m98088_eq_band(codec, 0, 0, coef_set->band1);
1752 m98088_eq_band(codec, 0, 1, coef_set->band2);
1753 m98088_eq_band(codec, 0, 2, coef_set->band3);
1754 m98088_eq_band(codec, 0, 3, coef_set->band4);
1755 m98088_eq_band(codec, 0, 4, coef_set->band5);
1756
1757
1758 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1759}
1760
1761static void max98088_setup_eq2(struct snd_soc_codec *codec)
1762{
1763 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1764 struct max98088_pdata *pdata = max98088->pdata;
1765 struct max98088_eq_cfg *coef_set;
1766 int best, best_val, save, i, sel, fs;
1767 struct max98088_cdata *cdata;
1768
1769 cdata = &max98088->dai[1];
1770
1771 if (!pdata || !max98088->eq_textcnt)
1772 return;
1773
1774
1775 fs = cdata->rate;
1776
1777 sel = cdata->eq_sel;
1778 best = 0;
1779 best_val = INT_MAX;
1780 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1781 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1782 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1783 best = i;
1784 best_val = abs(pdata->eq_cfg[i].rate - fs);
1785 }
1786 }
1787
1788 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1789 pdata->eq_cfg[best].name,
1790 pdata->eq_cfg[best].rate, fs);
1791
1792
1793 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1794 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1795
1796 coef_set = &pdata->eq_cfg[sel];
1797
1798 m98088_eq_band(codec, 1, 0, coef_set->band1);
1799 m98088_eq_band(codec, 1, 1, coef_set->band2);
1800 m98088_eq_band(codec, 1, 2, coef_set->band3);
1801 m98088_eq_band(codec, 1, 3, coef_set->band4);
1802 m98088_eq_band(codec, 1, 4, coef_set->band5);
1803
1804
1805 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1806 save);
1807}
1808
1809static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1810 struct snd_ctl_elem_value *ucontrol)
1811{
1812 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1813 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1814 struct max98088_pdata *pdata = max98088->pdata;
1815 int channel = max98088_get_channel(codec, kcontrol->id.name);
1816 struct max98088_cdata *cdata;
1817 int sel = ucontrol->value.integer.value[0];
1818
1819 if (channel < 0)
1820 return channel;
1821
1822 cdata = &max98088->dai[channel];
1823
1824 if (sel >= pdata->eq_cfgcnt)
1825 return -EINVAL;
1826
1827 cdata->eq_sel = sel;
1828
1829 switch (channel) {
1830 case 0:
1831 max98088_setup_eq1(codec);
1832 break;
1833 case 1:
1834 max98088_setup_eq2(codec);
1835 break;
1836 }
1837
1838 return 0;
1839}
1840
1841static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1842 struct snd_ctl_elem_value *ucontrol)
1843{
1844 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1845 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1846 int channel = max98088_get_channel(codec, kcontrol->id.name);
1847 struct max98088_cdata *cdata;
1848
1849 if (channel < 0)
1850 return channel;
1851
1852 cdata = &max98088->dai[channel];
1853 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1854 return 0;
1855}
1856
1857static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1858{
1859 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1860 struct max98088_pdata *pdata = max98088->pdata;
1861 struct max98088_eq_cfg *cfg;
1862 unsigned int cfgcnt;
1863 int i, j;
1864 const char **t;
1865 int ret;
1866 struct snd_kcontrol_new controls[] = {
1867 SOC_ENUM_EXT((char *)eq_mode_name[0],
1868 max98088->eq_enum,
1869 max98088_get_eq_enum,
1870 max98088_put_eq_enum),
1871 SOC_ENUM_EXT((char *)eq_mode_name[1],
1872 max98088->eq_enum,
1873 max98088_get_eq_enum,
1874 max98088_put_eq_enum),
1875 };
1876 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
1877
1878 cfg = pdata->eq_cfg;
1879 cfgcnt = pdata->eq_cfgcnt;
1880
1881
1882
1883
1884 max98088->eq_textcnt = 0;
1885 max98088->eq_texts = NULL;
1886 for (i = 0; i < cfgcnt; i++) {
1887 for (j = 0; j < max98088->eq_textcnt; j++) {
1888 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1889 break;
1890 }
1891
1892 if (j != max98088->eq_textcnt)
1893 continue;
1894
1895
1896 t = krealloc(max98088->eq_texts,
1897 sizeof(char *) * (max98088->eq_textcnt + 1),
1898 GFP_KERNEL);
1899 if (t == NULL)
1900 continue;
1901
1902
1903 t[max98088->eq_textcnt] = cfg[i].name;
1904 max98088->eq_textcnt++;
1905 max98088->eq_texts = t;
1906 }
1907
1908
1909 max98088->eq_enum.texts = max98088->eq_texts;
1910 max98088->eq_enum.max = max98088->eq_textcnt;
1911
1912 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
1913 if (ret != 0)
1914 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1915}
1916
1917static void max98088_handle_pdata(struct snd_soc_codec *codec)
1918{
1919 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1920 struct max98088_pdata *pdata = max98088->pdata;
1921 u8 regval = 0;
1922
1923 if (!pdata) {
1924 dev_dbg(codec->dev, "No platform data\n");
1925 return;
1926 }
1927
1928
1929 if (pdata->digmic_left_mode)
1930 regval |= M98088_DIGMIC_L;
1931
1932 if (pdata->digmic_right_mode)
1933 regval |= M98088_DIGMIC_R;
1934
1935 max98088->digmic = (regval ? 1 : 0);
1936
1937 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1938
1939
1940 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1941 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1942 M98088_REC_LINEMODE_MASK, regval);
1943
1944
1945 if (pdata->eq_cfgcnt)
1946 max98088_handle_eq_pdata(codec);
1947}
1948
1949#ifdef CONFIG_PM
1950static int max98088_suspend(struct snd_soc_codec *codec, pm_message_t state)
1951{
1952 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
1953
1954 return 0;
1955}
1956
1957static int max98088_resume(struct snd_soc_codec *codec)
1958{
1959 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1960
1961 return 0;
1962}
1963#else
1964#define max98088_suspend NULL
1965#define max98088_resume NULL
1966#endif
1967
1968static int max98088_probe(struct snd_soc_codec *codec)
1969{
1970 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1971 struct max98088_cdata *cdata;
1972 int ret = 0;
1973
1974 codec->cache_sync = 1;
1975
1976 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1977 if (ret != 0) {
1978 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1979 return ret;
1980 }
1981
1982
1983
1984 max98088->sysclk = (unsigned)-1;
1985 max98088->eq_textcnt = 0;
1986
1987 cdata = &max98088->dai[0];
1988 cdata->rate = (unsigned)-1;
1989 cdata->fmt = (unsigned)-1;
1990 cdata->eq_sel = 0;
1991
1992 cdata = &max98088->dai[1];
1993 cdata->rate = (unsigned)-1;
1994 cdata->fmt = (unsigned)-1;
1995 cdata->eq_sel = 0;
1996
1997 max98088->ina_state = 0;
1998 max98088->inb_state = 0;
1999 max98088->ex_mode = 0;
2000 max98088->digmic = 0;
2001 max98088->mic1pre = 0;
2002 max98088->mic2pre = 0;
2003
2004 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
2005 if (ret < 0) {
2006 dev_err(codec->dev, "Failed to read device revision: %d\n",
2007 ret);
2008 goto err_access;
2009 }
2010 dev_info(codec->dev, "revision %c\n", ret + 'A');
2011
2012 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
2013
2014
2015 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2016
2017 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
2018
2019 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
2020 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
2021 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
2022
2023 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
2024 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
2025
2026 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
2027 M98088_S1NORMAL|M98088_SDATA);
2028
2029 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
2030 M98088_S2NORMAL|M98088_SDATA);
2031
2032 max98088_handle_pdata(codec);
2033
2034 snd_soc_add_controls(codec, max98088_snd_controls,
2035 ARRAY_SIZE(max98088_snd_controls));
2036
2037err_access:
2038 return ret;
2039}
2040
2041static int max98088_remove(struct snd_soc_codec *codec)
2042{
2043 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
2044
2045 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
2046 kfree(max98088->eq_texts);
2047
2048 return 0;
2049}
2050
2051static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
2052 .probe = max98088_probe,
2053 .remove = max98088_remove,
2054 .suspend = max98088_suspend,
2055 .resume = max98088_resume,
2056 .set_bias_level = max98088_set_bias_level,
2057 .reg_cache_size = ARRAY_SIZE(max98088_reg),
2058 .reg_word_size = sizeof(u8),
2059 .reg_cache_default = max98088_reg,
2060 .volatile_register = max98088_volatile_register,
2061 .dapm_widgets = max98088_dapm_widgets,
2062 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
2063 .dapm_routes = max98088_audio_map,
2064 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
2065};
2066
2067static int max98088_i2c_probe(struct i2c_client *i2c,
2068 const struct i2c_device_id *id)
2069{
2070 struct max98088_priv *max98088;
2071 int ret;
2072
2073 max98088 = kzalloc(sizeof(struct max98088_priv), GFP_KERNEL);
2074 if (max98088 == NULL)
2075 return -ENOMEM;
2076
2077 max98088->devtype = id->driver_data;
2078
2079 i2c_set_clientdata(i2c, max98088);
2080 max98088->pdata = i2c->dev.platform_data;
2081
2082 ret = snd_soc_register_codec(&i2c->dev,
2083 &soc_codec_dev_max98088, &max98088_dai[0], 2);
2084 if (ret < 0)
2085 kfree(max98088);
2086 return ret;
2087}
2088
2089static int __devexit max98088_i2c_remove(struct i2c_client *client)
2090{
2091 snd_soc_unregister_codec(&client->dev);
2092 kfree(i2c_get_clientdata(client));
2093 return 0;
2094}
2095
2096static const struct i2c_device_id max98088_i2c_id[] = {
2097 { "max98088", MAX98088 },
2098 { "max98089", MAX98089 },
2099 { }
2100};
2101MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2102
2103static struct i2c_driver max98088_i2c_driver = {
2104 .driver = {
2105 .name = "max98088",
2106 .owner = THIS_MODULE,
2107 },
2108 .probe = max98088_i2c_probe,
2109 .remove = __devexit_p(max98088_i2c_remove),
2110 .id_table = max98088_i2c_id,
2111};
2112
2113static int __init max98088_init(void)
2114{
2115 int ret;
2116
2117 ret = i2c_add_driver(&max98088_i2c_driver);
2118 if (ret)
2119 pr_err("Failed to register max98088 I2C driver: %d\n", ret);
2120
2121 return ret;
2122}
2123module_init(max98088_init);
2124
2125static void __exit max98088_exit(void)
2126{
2127 i2c_del_driver(&max98088_i2c_driver);
2128}
2129module_exit(max98088_exit);
2130
2131MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2132MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2133MODULE_LICENSE("GPL");
2134
