linux/drivers/ssb/driver_pcicore.c
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   1/*
   2 * Sonics Silicon Backplane
   3 * Broadcom PCI-core driver
   4 *
   5 * Copyright 2005, Broadcom Corporation
   6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
   7 *
   8 * Licensed under the GNU/GPL. See COPYING for details.
   9 */
  10
  11#include <linux/ssb/ssb.h>
  12#include <linux/pci.h>
  13#include <linux/export.h>
  14#include <linux/delay.h>
  15#include <linux/ssb/ssb_embedded.h>
  16
  17#include "ssb_private.h"
  18
  19static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
  20static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
  21static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
  22static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
  23                                u8 address, u16 data);
  24
  25static inline
  26u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
  27{
  28        return ssb_read32(pc->dev, offset);
  29}
  30
  31static inline
  32void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
  33{
  34        ssb_write32(pc->dev, offset, value);
  35}
  36
  37static inline
  38u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
  39{
  40        return ssb_read16(pc->dev, offset);
  41}
  42
  43static inline
  44void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
  45{
  46        ssb_write16(pc->dev, offset, value);
  47}
  48
  49/**************************************************
  50 * Code for hostmode operation.
  51 **************************************************/
  52
  53#ifdef CONFIG_SSB_PCICORE_HOSTMODE
  54
  55#include <asm/paccess.h>
  56/* Probe a 32bit value on the bus and catch bus exceptions.
  57 * Returns nonzero on a bus exception.
  58 * This is MIPS specific */
  59#define mips_busprobe32(val, addr)      get_dbe((val), ((u32 *)(addr)))
  60
  61/* Assume one-hot slot wiring */
  62#define SSB_PCI_SLOT_MAX        16
  63
  64/* Global lock is OK, as we won't have more than one extpci anyway. */
  65static DEFINE_SPINLOCK(cfgspace_lock);
  66/* Core to access the external PCI config space. Can only have one. */
  67static struct ssb_pcicore *extpci_core;
  68
  69
  70static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
  71                             unsigned int bus, unsigned int dev,
  72                             unsigned int func, unsigned int off)
  73{
  74        u32 addr = 0;
  75        u32 tmp;
  76
  77        /* We do only have one cardbus device behind the bridge. */
  78        if (pc->cardbusmode && (dev > 1))
  79                goto out;
  80
  81        if (bus == 0) {
  82                /* Type 0 transaction */
  83                if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  84                        goto out;
  85                /* Slide the window */
  86                tmp = SSB_PCICORE_SBTOPCI_CFG0;
  87                tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
  88                pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
  89                /* Calculate the address */
  90                addr = SSB_PCI_CFG;
  91                addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
  92                addr |= (func << 8);
  93                addr |= (off & ~3);
  94        } else {
  95                /* Type 1 transaction */
  96                pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
  97                                SSB_PCICORE_SBTOPCI_CFG1);
  98                /* Calculate the address */
  99                addr = SSB_PCI_CFG;
 100                addr |= (bus << 16);
 101                addr |= (dev << 11);
 102                addr |= (func << 8);
 103                addr |= (off & ~3);
 104        }
 105out:
 106        return addr;
 107}
 108
 109static int ssb_extpci_read_config(struct ssb_pcicore *pc,
 110                                  unsigned int bus, unsigned int dev,
 111                                  unsigned int func, unsigned int off,
 112                                  void *buf, int len)
 113{
 114        int err = -EINVAL;
 115        u32 addr, val;
 116        void __iomem *mmio;
 117
 118        SSB_WARN_ON(!pc->hostmode);
 119        if (unlikely(len != 1 && len != 2 && len != 4))
 120                goto out;
 121        addr = get_cfgspace_addr(pc, bus, dev, func, off);
 122        if (unlikely(!addr))
 123                goto out;
 124        err = -ENOMEM;
 125        mmio = ioremap_nocache(addr, len);
 126        if (!mmio)
 127                goto out;
 128
 129        if (mips_busprobe32(val, mmio)) {
 130                val = 0xffffffff;
 131                goto unmap;
 132        }
 133
 134        val = readl(mmio);
 135        val >>= (8 * (off & 3));
 136
 137        switch (len) {
 138        case 1:
 139                *((u8 *)buf) = (u8)val;
 140                break;
 141        case 2:
 142                *((u16 *)buf) = (u16)val;
 143                break;
 144        case 4:
 145                *((u32 *)buf) = (u32)val;
 146                break;
 147        }
 148        err = 0;
 149unmap:
 150        iounmap(mmio);
 151out:
 152        return err;
 153}
 154
 155static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 156                                   unsigned int bus, unsigned int dev,
 157                                   unsigned int func, unsigned int off,
 158                                   const void *buf, int len)
 159{
 160        int err = -EINVAL;
 161        u32 addr, val = 0;
 162        void __iomem *mmio;
 163
 164        SSB_WARN_ON(!pc->hostmode);
 165        if (unlikely(len != 1 && len != 2 && len != 4))
 166                goto out;
 167        addr = get_cfgspace_addr(pc, bus, dev, func, off);
 168        if (unlikely(!addr))
 169                goto out;
 170        err = -ENOMEM;
 171        mmio = ioremap_nocache(addr, len);
 172        if (!mmio)
 173                goto out;
 174
 175        if (mips_busprobe32(val, mmio)) {
 176                val = 0xffffffff;
 177                goto unmap;
 178        }
 179
 180        switch (len) {
 181        case 1:
 182                val = readl(mmio);
 183                val &= ~(0xFF << (8 * (off & 3)));
 184                val |= *((const u8 *)buf) << (8 * (off & 3));
 185                break;
 186        case 2:
 187                val = readl(mmio);
 188                val &= ~(0xFFFF << (8 * (off & 3)));
 189                val |= *((const u16 *)buf) << (8 * (off & 3));
 190                break;
 191        case 4:
 192                val = *((const u32 *)buf);
 193                break;
 194        }
 195        writel(val, mmio);
 196
 197        err = 0;
 198unmap:
 199        iounmap(mmio);
 200out:
 201        return err;
 202}
 203
 204static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
 205                                   int reg, int size, u32 *val)
 206{
 207        unsigned long flags;
 208        int err;
 209
 210        spin_lock_irqsave(&cfgspace_lock, flags);
 211        err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
 212                                     PCI_FUNC(devfn), reg, val, size);
 213        spin_unlock_irqrestore(&cfgspace_lock, flags);
 214
 215        return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 216}
 217
 218static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
 219                                    int reg, int size, u32 val)
 220{
 221        unsigned long flags;
 222        int err;
 223
 224        spin_lock_irqsave(&cfgspace_lock, flags);
 225        err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
 226                                      PCI_FUNC(devfn), reg, &val, size);
 227        spin_unlock_irqrestore(&cfgspace_lock, flags);
 228
 229        return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 230}
 231
 232static struct pci_ops ssb_pcicore_pciops = {
 233        .read   = ssb_pcicore_read_config,
 234        .write  = ssb_pcicore_write_config,
 235};
 236
 237static struct resource ssb_pcicore_mem_resource = {
 238        .name   = "SSB PCIcore external memory",
 239        .start  = SSB_PCI_DMA,
 240        .end    = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
 241        .flags  = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
 242};
 243
 244static struct resource ssb_pcicore_io_resource = {
 245        .name   = "SSB PCIcore external I/O",
 246        .start  = 0x100,
 247        .end    = 0x7FF,
 248        .flags  = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
 249};
 250
 251static struct pci_controller ssb_pcicore_controller = {
 252        .pci_ops        = &ssb_pcicore_pciops,
 253        .io_resource    = &ssb_pcicore_io_resource,
 254        .mem_resource   = &ssb_pcicore_mem_resource,
 255};
 256
 257/* This function is called when doing a pci_enable_device().
 258 * We must first check if the device is a device on the PCI-core bridge. */
 259int ssb_pcicore_plat_dev_init(struct pci_dev *d)
 260{
 261        if (d->bus->ops != &ssb_pcicore_pciops) {
 262                /* This is not a device on the PCI-core bridge. */
 263                return -ENODEV;
 264        }
 265
 266        ssb_info("PCI: Fixing up device %s\n", pci_name(d));
 267
 268        /* Fix up interrupt lines */
 269        d->irq = ssb_mips_irq(extpci_core->dev) + 2;
 270        pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
 271
 272        return 0;
 273}
 274
 275/* Early PCI fixup for a device on the PCI-core bridge. */
 276static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
 277{
 278        u8 lat;
 279
 280        if (dev->bus->ops != &ssb_pcicore_pciops) {
 281                /* This is not a device on the PCI-core bridge. */
 282                return;
 283        }
 284        if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
 285                return;
 286
 287        ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
 288
 289        /* Enable PCI bridge bus mastering and memory space */
 290        pci_set_master(dev);
 291        if (pcibios_enable_device(dev, ~0) < 0) {
 292                ssb_err("PCI: SSB bridge enable failed\n");
 293                return;
 294        }
 295
 296        /* Enable PCI bridge BAR1 prefetch and burst */
 297        pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
 298
 299        /* Make sure our latency is high enough to handle the devices behind us */
 300        lat = 168;
 301        ssb_info("PCI: Fixing latency timer of device %s to %u\n",
 302                 pci_name(dev), lat);
 303        pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 304}
 305DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
 306
 307/* PCI device IRQ mapping. */
 308int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 309{
 310        if (dev->bus->ops != &ssb_pcicore_pciops) {
 311                /* This is not a device on the PCI-core bridge. */
 312                return -ENODEV;
 313        }
 314        return ssb_mips_irq(extpci_core->dev) + 2;
 315}
 316
 317static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 318{
 319        u32 val;
 320
 321        if (WARN_ON(extpci_core))
 322                return;
 323        extpci_core = pc;
 324
 325        ssb_dbg("PCIcore in host mode found\n");
 326        /* Reset devices on the external PCI bus */
 327        val = SSB_PCICORE_CTL_RST_OE;
 328        val |= SSB_PCICORE_CTL_CLK_OE;
 329        pcicore_write32(pc, SSB_PCICORE_CTL, val);
 330        val |= SSB_PCICORE_CTL_CLK; /* Clock on */
 331        pcicore_write32(pc, SSB_PCICORE_CTL, val);
 332        udelay(150); /* Assertion time demanded by the PCI standard */
 333        val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 334        pcicore_write32(pc, SSB_PCICORE_CTL, val);
 335        val = SSB_PCICORE_ARBCTL_INTERN;
 336        pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
 337        udelay(1); /* Assertion time demanded by the PCI standard */
 338
 339        if (pc->dev->bus->has_cardbus_slot) {
 340                ssb_dbg("CardBus slot detected\n");
 341                pc->cardbusmode = 1;
 342                /* GPIO 1 resets the bridge */
 343                ssb_gpio_out(pc->dev->bus, 1, 1);
 344                ssb_gpio_outen(pc->dev->bus, 1, 1);
 345                pcicore_write16(pc, SSB_PCICORE_SPROM(0),
 346                                pcicore_read16(pc, SSB_PCICORE_SPROM(0))
 347                                | 0x0400);
 348        }
 349
 350        /* 64MB I/O window */
 351        pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
 352                        SSB_PCICORE_SBTOPCI_IO);
 353        /* 64MB config space */
 354        pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
 355                        SSB_PCICORE_SBTOPCI_CFG0);
 356        /* 1GB memory window */
 357        pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
 358                        SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
 359
 360        /* Enable PCI bridge BAR0 prefetch and burst */
 361        val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 362        ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
 363        /* Clear error conditions */
 364        val = 0;
 365        ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
 366
 367        /* Enable PCI interrupts */
 368        pcicore_write32(pc, SSB_PCICORE_IMASK,
 369                        SSB_PCICORE_IMASK_INTA);
 370
 371        /* Ok, ready to run, register it to the system.
 372         * The following needs change, if we want to port hostmode
 373         * to non-MIPS platform. */
 374        ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
 375        set_io_port_base(ssb_pcicore_controller.io_map_base);
 376        /* Give some time to the PCI controller to configure itself with the new
 377         * values. Not waiting at this point causes crashes of the machine. */
 378        mdelay(10);
 379        register_pci_controller(&ssb_pcicore_controller);
 380}
 381
 382static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 383{
 384        struct ssb_bus *bus = pc->dev->bus;
 385        u16 chipid_top;
 386        u32 tmp;
 387
 388        chipid_top = (bus->chip_id & 0xFF00);
 389        if (chipid_top != 0x4700 &&
 390            chipid_top != 0x5300)
 391                return 0;
 392
 393        if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
 394                return 0;
 395
 396        /* The 200-pin BCM4712 package does not bond out PCI. Even when
 397         * PCI is bonded out, some boards may leave the pins floating. */
 398        if (bus->chip_id == 0x4712) {
 399                if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
 400                        return 0;
 401                if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
 402                        return 0;
 403        }
 404        if (bus->chip_id == 0x5350)
 405                return 0;
 406
 407        return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
 408}
 409#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 410
 411/**************************************************
 412 * Workarounds.
 413 **************************************************/
 414
 415static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
 416{
 417        u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
 418        if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
 419                tmp &= ~0xF000;
 420                tmp |= (pc->dev->core_index << 12);
 421                pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
 422        }
 423}
 424
 425static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
 426{
 427        return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
 428}
 429
 430static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
 431{
 432        const u8 serdes_pll_device = 0x1D;
 433        const u8 serdes_rx_device = 0x1F;
 434        u16 tmp;
 435
 436        ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
 437                            ssb_pcicore_polarity_workaround(pc));
 438        tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
 439        if (tmp & 0x4000)
 440                ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
 441}
 442
 443static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
 444{
 445        struct ssb_device *pdev = pc->dev;
 446        struct ssb_bus *bus = pdev->bus;
 447        u32 tmp;
 448
 449        tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 450        tmp |= SSB_PCICORE_SBTOPCI_PREF;
 451        tmp |= SSB_PCICORE_SBTOPCI_BURST;
 452        pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 453
 454        if (pdev->id.revision < 5) {
 455                tmp = ssb_read32(pdev, SSB_IMCFGLO);
 456                tmp &= ~SSB_IMCFGLO_SERTO;
 457                tmp |= 2;
 458                tmp &= ~SSB_IMCFGLO_REQTO;
 459                tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
 460                ssb_write32(pdev, SSB_IMCFGLO, tmp);
 461                ssb_commit_settings(bus);
 462        } else if (pdev->id.revision >= 11) {
 463                tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 464                tmp |= SSB_PCICORE_SBTOPCI_MRM;
 465                pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 466        }
 467}
 468
 469static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
 470{
 471        u32 tmp;
 472        u8 rev = pc->dev->id.revision;
 473
 474        if (rev == 0 || rev == 1) {
 475                /* TLP Workaround register. */
 476                tmp = ssb_pcie_read(pc, 0x4);
 477                tmp |= 0x8;
 478                ssb_pcie_write(pc, 0x4, tmp);
 479        }
 480        if (rev == 1) {
 481                /* DLLP Link Control register. */
 482                tmp = ssb_pcie_read(pc, 0x100);
 483                tmp |= 0x40;
 484                ssb_pcie_write(pc, 0x100, tmp);
 485        }
 486
 487        if (rev == 0) {
 488                const u8 serdes_rx_device = 0x1F;
 489
 490                ssb_pcie_mdio_write(pc, serdes_rx_device,
 491                                        2 /* Timer */, 0x8128);
 492                ssb_pcie_mdio_write(pc, serdes_rx_device,
 493                                        6 /* CDR */, 0x0100);
 494                ssb_pcie_mdio_write(pc, serdes_rx_device,
 495                                        7 /* CDR BW */, 0x1466);
 496        } else if (rev == 3 || rev == 4 || rev == 5) {
 497                /* TODO: DLLP Power Management Threshold */
 498                ssb_pcicore_serdes_workaround(pc);
 499                /* TODO: ASPM */
 500        } else if (rev == 7) {
 501                /* TODO: No PLL down */
 502        }
 503
 504        if (rev >= 6) {
 505                /* Miscellaneous Configuration Fixup */
 506                tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
 507                if (!(tmp & 0x8000))
 508                        pcicore_write16(pc, SSB_PCICORE_SPROM(5),
 509                                        tmp | 0x8000);
 510        }
 511}
 512
 513/**************************************************
 514 * Generic and Clientmode operation code.
 515 **************************************************/
 516
 517static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
 518{
 519        struct ssb_device *pdev = pc->dev;
 520        struct ssb_bus *bus = pdev->bus;
 521
 522        if (bus->bustype == SSB_BUSTYPE_PCI)
 523                ssb_pcicore_fix_sprom_core_index(pc);
 524
 525        /* Disable PCI interrupts. */
 526        ssb_write32(pdev, SSB_INTVEC, 0);
 527
 528        /* Additional PCIe always once-executed workarounds */
 529        if (pc->dev->id.coreid == SSB_DEV_PCIE) {
 530                ssb_pcicore_serdes_workaround(pc);
 531                /* TODO: ASPM */
 532                /* TODO: Clock Request Update */
 533        }
 534}
 535
 536void ssb_pcicore_init(struct ssb_pcicore *pc)
 537{
 538        struct ssb_device *dev = pc->dev;
 539
 540        if (!dev)
 541                return;
 542        if (!ssb_device_is_enabled(dev))
 543                ssb_device_enable(dev, 0);
 544
 545#ifdef CONFIG_SSB_PCICORE_HOSTMODE
 546        pc->hostmode = pcicore_is_in_hostmode(pc);
 547        if (pc->hostmode)
 548                ssb_pcicore_init_hostmode(pc);
 549#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 550        if (!pc->hostmode)
 551                ssb_pcicore_init_clientmode(pc);
 552}
 553
 554static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
 555{
 556        pcicore_write32(pc, 0x130, address);
 557        return pcicore_read32(pc, 0x134);
 558}
 559
 560static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
 561{
 562        pcicore_write32(pc, 0x130, address);
 563        pcicore_write32(pc, 0x134, data);
 564}
 565
 566static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
 567{
 568        const u16 mdio_control = 0x128;
 569        const u16 mdio_data = 0x12C;
 570        u32 v;
 571        int i;
 572
 573        v = (1 << 30); /* Start of Transaction */
 574        v |= (1 << 28); /* Write Transaction */
 575        v |= (1 << 17); /* Turnaround */
 576        v |= (0x1F << 18);
 577        v |= (phy << 4);
 578        pcicore_write32(pc, mdio_data, v);
 579
 580        udelay(10);
 581        for (i = 0; i < 200; i++) {
 582                v = pcicore_read32(pc, mdio_control);
 583                if (v & 0x100 /* Trans complete */)
 584                        break;
 585                msleep(1);
 586        }
 587}
 588
 589static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
 590{
 591        const u16 mdio_control = 0x128;
 592        const u16 mdio_data = 0x12C;
 593        int max_retries = 10;
 594        u16 ret = 0;
 595        u32 v;
 596        int i;
 597
 598        v = 0x80; /* Enable Preamble Sequence */
 599        v |= 0x2; /* MDIO Clock Divisor */
 600        pcicore_write32(pc, mdio_control, v);
 601
 602        if (pc->dev->id.revision >= 10) {
 603                max_retries = 200;
 604                ssb_pcie_mdio_set_phy(pc, device);
 605        }
 606
 607        v = (1 << 30); /* Start of Transaction */
 608        v |= (1 << 29); /* Read Transaction */
 609        v |= (1 << 17); /* Turnaround */
 610        if (pc->dev->id.revision < 10)
 611                v |= (u32)device << 22;
 612        v |= (u32)address << 18;
 613        pcicore_write32(pc, mdio_data, v);
 614        /* Wait for the device to complete the transaction */
 615        udelay(10);
 616        for (i = 0; i < max_retries; i++) {
 617                v = pcicore_read32(pc, mdio_control);
 618                if (v & 0x100 /* Trans complete */) {
 619                        udelay(10);
 620                        ret = pcicore_read32(pc, mdio_data);
 621                        break;
 622                }
 623                msleep(1);
 624        }
 625        pcicore_write32(pc, mdio_control, 0);
 626        return ret;
 627}
 628
 629static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
 630                                u8 address, u16 data)
 631{
 632        const u16 mdio_control = 0x128;
 633        const u16 mdio_data = 0x12C;
 634        int max_retries = 10;
 635        u32 v;
 636        int i;
 637
 638        v = 0x80; /* Enable Preamble Sequence */
 639        v |= 0x2; /* MDIO Clock Divisor */
 640        pcicore_write32(pc, mdio_control, v);
 641
 642        if (pc->dev->id.revision >= 10) {
 643                max_retries = 200;
 644                ssb_pcie_mdio_set_phy(pc, device);
 645        }
 646
 647        v = (1 << 30); /* Start of Transaction */
 648        v |= (1 << 28); /* Write Transaction */
 649        v |= (1 << 17); /* Turnaround */
 650        if (pc->dev->id.revision < 10)
 651                v |= (u32)device << 22;
 652        v |= (u32)address << 18;
 653        v |= data;
 654        pcicore_write32(pc, mdio_data, v);
 655        /* Wait for the device to complete the transaction */
 656        udelay(10);
 657        for (i = 0; i < max_retries; i++) {
 658                v = pcicore_read32(pc, mdio_control);
 659                if (v & 0x100 /* Trans complete */)
 660                        break;
 661                msleep(1);
 662        }
 663        pcicore_write32(pc, mdio_control, 0);
 664}
 665
 666int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 667                                   struct ssb_device *dev)
 668{
 669        struct ssb_device *pdev = pc->dev;
 670        struct ssb_bus *bus;
 671        int err = 0;
 672        u32 tmp;
 673
 674        if (dev->bus->bustype != SSB_BUSTYPE_PCI) {
 675                /* This SSB device is not on a PCI host-bus. So the IRQs are
 676                 * not routed through the PCI core.
 677                 * So we must not enable routing through the PCI core. */
 678                goto out;
 679        }
 680
 681        if (!pdev)
 682                goto out;
 683        bus = pdev->bus;
 684
 685        might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
 686
 687        /* Enable interrupts for this device. */
 688        if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
 689                u32 coremask;
 690
 691                /* Calculate the "coremask" for the device. */
 692                coremask = (1 << dev->core_index);
 693
 694                SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
 695                err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
 696                if (err)
 697                        goto out;
 698                tmp |= coremask << 8;
 699                err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
 700                if (err)
 701                        goto out;
 702        } else {
 703                u32 intvec;
 704
 705                intvec = ssb_read32(pdev, SSB_INTVEC);
 706                tmp = ssb_read32(dev, SSB_TPSFLAG);
 707                tmp &= SSB_TPSFLAG_BPFLAG;
 708                intvec |= (1 << tmp);
 709                ssb_write32(pdev, SSB_INTVEC, intvec);
 710        }
 711
 712        /* Setup PCIcore operation. */
 713        if (pc->setup_done)
 714                goto out;
 715        if (pdev->id.coreid == SSB_DEV_PCI) {
 716                ssb_pcicore_pci_setup_workarounds(pc);
 717        } else {
 718                WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
 719                ssb_pcicore_pcie_setup_workarounds(pc);
 720        }
 721        pc->setup_done = 1;
 722out:
 723        return err;
 724}
 725EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
 726
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