linux/drivers/spi/spi-pxa2xx.c
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   1/*
   2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3 * Copyright (C) 2013, Intel Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/module.h>
  22#include <linux/device.h>
  23#include <linux/ioport.h>
  24#include <linux/errno.h>
  25#include <linux/err.h>
  26#include <linux/interrupt.h>
  27#include <linux/platform_device.h>
  28#include <linux/spi/pxa2xx_spi.h>
  29#include <linux/spi/spi.h>
  30#include <linux/workqueue.h>
  31#include <linux/delay.h>
  32#include <linux/gpio.h>
  33#include <linux/slab.h>
  34#include <linux/clk.h>
  35#include <linux/pm_runtime.h>
  36#include <linux/acpi.h>
  37
  38#include <asm/io.h>
  39#include <asm/irq.h>
  40#include <asm/delay.h>
  41
  42#include "spi-pxa2xx.h"
  43
  44MODULE_AUTHOR("Stephen Street");
  45MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  46MODULE_LICENSE("GPL");
  47MODULE_ALIAS("platform:pxa2xx-spi");
  48
  49#define MAX_BUSES 3
  50
  51#define TIMOUT_DFLT             1000
  52
  53/*
  54 * for testing SSCR1 changes that require SSP restart, basically
  55 * everything except the service and interrupt enables, the pxa270 developer
  56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  57 * list, but the PXA255 dev man says all bits without really meaning the
  58 * service and interrupt enables
  59 */
  60#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  65                                | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67#define LPSS_RX_THRESH_DFLT     64
  68#define LPSS_TX_LOTHRESH_DFLT   160
  69#define LPSS_TX_HITHRESH_DFLT   224
  70
  71/* Offset from drv_data->lpss_base */
  72#define GENERAL_REG             0x08
  73#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
  74#define SSP_REG                 0x0c
  75#define SPI_CS_CONTROL          0x18
  76#define SPI_CS_CONTROL_SW_MODE  BIT(0)
  77#define SPI_CS_CONTROL_CS_HIGH  BIT(1)
  78
  79static bool is_lpss_ssp(const struct driver_data *drv_data)
  80{
  81        return drv_data->ssp_type == LPSS_SSP;
  82}
  83
  84/*
  85 * Read and write LPSS SSP private registers. Caller must first check that
  86 * is_lpss_ssp() returns true before these can be called.
  87 */
  88static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
  89{
  90        WARN_ON(!drv_data->lpss_base);
  91        return readl(drv_data->lpss_base + offset);
  92}
  93
  94static void __lpss_ssp_write_priv(struct driver_data *drv_data,
  95                                  unsigned offset, u32 value)
  96{
  97        WARN_ON(!drv_data->lpss_base);
  98        writel(value, drv_data->lpss_base + offset);
  99}
 100
 101/*
 102 * lpss_ssp_setup - perform LPSS SSP specific setup
 103 * @drv_data: pointer to the driver private data
 104 *
 105 * Perform LPSS SSP specific setup. This function must be called first if
 106 * one is going to use LPSS SSP private registers.
 107 */
 108static void lpss_ssp_setup(struct driver_data *drv_data)
 109{
 110        unsigned offset = 0x400;
 111        u32 value, orig;
 112
 113        if (!is_lpss_ssp(drv_data))
 114                return;
 115
 116        /*
 117         * Perform auto-detection of the LPSS SSP private registers. They
 118         * can be either at 1k or 2k offset from the base address.
 119         */
 120        orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 121
 122        value = orig | SPI_CS_CONTROL_SW_MODE;
 123        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 124        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 125        if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
 126                offset = 0x800;
 127                goto detection_done;
 128        }
 129
 130        value &= ~SPI_CS_CONTROL_SW_MODE;
 131        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 132        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 133        if (value != orig) {
 134                offset = 0x800;
 135                goto detection_done;
 136        }
 137
 138detection_done:
 139        /* Now set the LPSS base */
 140        drv_data->lpss_base = drv_data->ioaddr + offset;
 141
 142        /* Enable software chip select control */
 143        value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
 144        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 145
 146        /* Enable multiblock DMA transfers */
 147        if (drv_data->master_info->enable_dma) {
 148                __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
 149
 150                value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
 151                value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 152                __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
 153        }
 154}
 155
 156static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 157{
 158        u32 value;
 159
 160        if (!is_lpss_ssp(drv_data))
 161                return;
 162
 163        value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
 164        if (enable)
 165                value &= ~SPI_CS_CONTROL_CS_HIGH;
 166        else
 167                value |= SPI_CS_CONTROL_CS_HIGH;
 168        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 169}
 170
 171static void cs_assert(struct driver_data *drv_data)
 172{
 173        struct chip_data *chip = drv_data->cur_chip;
 174
 175        if (drv_data->ssp_type == CE4100_SSP) {
 176                write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
 177                return;
 178        }
 179
 180        if (chip->cs_control) {
 181                chip->cs_control(PXA2XX_CS_ASSERT);
 182                return;
 183        }
 184
 185        if (gpio_is_valid(chip->gpio_cs)) {
 186                gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
 187                return;
 188        }
 189
 190        lpss_ssp_cs_control(drv_data, true);
 191}
 192
 193static void cs_deassert(struct driver_data *drv_data)
 194{
 195        struct chip_data *chip = drv_data->cur_chip;
 196
 197        if (drv_data->ssp_type == CE4100_SSP)
 198                return;
 199
 200        if (chip->cs_control) {
 201                chip->cs_control(PXA2XX_CS_DEASSERT);
 202                return;
 203        }
 204
 205        if (gpio_is_valid(chip->gpio_cs)) {
 206                gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
 207                return;
 208        }
 209
 210        lpss_ssp_cs_control(drv_data, false);
 211}
 212
 213int pxa2xx_spi_flush(struct driver_data *drv_data)
 214{
 215        unsigned long limit = loops_per_jiffy << 1;
 216
 217        void __iomem *reg = drv_data->ioaddr;
 218
 219        do {
 220                while (read_SSSR(reg) & SSSR_RNE) {
 221                        read_SSDR(reg);
 222                }
 223        } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
 224        write_SSSR_CS(drv_data, SSSR_ROR);
 225
 226        return limit;
 227}
 228
 229static int null_writer(struct driver_data *drv_data)
 230{
 231        void __iomem *reg = drv_data->ioaddr;
 232        u8 n_bytes = drv_data->n_bytes;
 233
 234        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 235                || (drv_data->tx == drv_data->tx_end))
 236                return 0;
 237
 238        write_SSDR(0, reg);
 239        drv_data->tx += n_bytes;
 240
 241        return 1;
 242}
 243
 244static int null_reader(struct driver_data *drv_data)
 245{
 246        void __iomem *reg = drv_data->ioaddr;
 247        u8 n_bytes = drv_data->n_bytes;
 248
 249        while ((read_SSSR(reg) & SSSR_RNE)
 250                && (drv_data->rx < drv_data->rx_end)) {
 251                read_SSDR(reg);
 252                drv_data->rx += n_bytes;
 253        }
 254
 255        return drv_data->rx == drv_data->rx_end;
 256}
 257
 258static int u8_writer(struct driver_data *drv_data)
 259{
 260        void __iomem *reg = drv_data->ioaddr;
 261
 262        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 263                || (drv_data->tx == drv_data->tx_end))
 264                return 0;
 265
 266        write_SSDR(*(u8 *)(drv_data->tx), reg);
 267        ++drv_data->tx;
 268
 269        return 1;
 270}
 271
 272static int u8_reader(struct driver_data *drv_data)
 273{
 274        void __iomem *reg = drv_data->ioaddr;
 275
 276        while ((read_SSSR(reg) & SSSR_RNE)
 277                && (drv_data->rx < drv_data->rx_end)) {
 278                *(u8 *)(drv_data->rx) = read_SSDR(reg);
 279                ++drv_data->rx;
 280        }
 281
 282        return drv_data->rx == drv_data->rx_end;
 283}
 284
 285static int u16_writer(struct driver_data *drv_data)
 286{
 287        void __iomem *reg = drv_data->ioaddr;
 288
 289        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 290                || (drv_data->tx == drv_data->tx_end))
 291                return 0;
 292
 293        write_SSDR(*(u16 *)(drv_data->tx), reg);
 294        drv_data->tx += 2;
 295
 296        return 1;
 297}
 298
 299static int u16_reader(struct driver_data *drv_data)
 300{
 301        void __iomem *reg = drv_data->ioaddr;
 302
 303        while ((read_SSSR(reg) & SSSR_RNE)
 304                && (drv_data->rx < drv_data->rx_end)) {
 305                *(u16 *)(drv_data->rx) = read_SSDR(reg);
 306                drv_data->rx += 2;
 307        }
 308
 309        return drv_data->rx == drv_data->rx_end;
 310}
 311
 312static int u32_writer(struct driver_data *drv_data)
 313{
 314        void __iomem *reg = drv_data->ioaddr;
 315
 316        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 317                || (drv_data->tx == drv_data->tx_end))
 318                return 0;
 319
 320        write_SSDR(*(u32 *)(drv_data->tx), reg);
 321        drv_data->tx += 4;
 322
 323        return 1;
 324}
 325
 326static int u32_reader(struct driver_data *drv_data)
 327{
 328        void __iomem *reg = drv_data->ioaddr;
 329
 330        while ((read_SSSR(reg) & SSSR_RNE)
 331                && (drv_data->rx < drv_data->rx_end)) {
 332                *(u32 *)(drv_data->rx) = read_SSDR(reg);
 333                drv_data->rx += 4;
 334        }
 335
 336        return drv_data->rx == drv_data->rx_end;
 337}
 338
 339void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
 340{
 341        struct spi_message *msg = drv_data->cur_msg;
 342        struct spi_transfer *trans = drv_data->cur_transfer;
 343
 344        /* Move to next transfer */
 345        if (trans->transfer_list.next != &msg->transfers) {
 346                drv_data->cur_transfer =
 347                        list_entry(trans->transfer_list.next,
 348                                        struct spi_transfer,
 349                                        transfer_list);
 350                return RUNNING_STATE;
 351        } else
 352                return DONE_STATE;
 353}
 354
 355/* caller already set message->status; dma and pio irqs are blocked */
 356static void giveback(struct driver_data *drv_data)
 357{
 358        struct spi_transfer* last_transfer;
 359        struct spi_message *msg;
 360
 361        msg = drv_data->cur_msg;
 362        drv_data->cur_msg = NULL;
 363        drv_data->cur_transfer = NULL;
 364
 365        last_transfer = list_entry(msg->transfers.prev,
 366                                        struct spi_transfer,
 367                                        transfer_list);
 368
 369        /* Delay if requested before any change in chip select */
 370        if (last_transfer->delay_usecs)
 371                udelay(last_transfer->delay_usecs);
 372
 373        /* Drop chip select UNLESS cs_change is true or we are returning
 374         * a message with an error, or next message is for another chip
 375         */
 376        if (!last_transfer->cs_change)
 377                cs_deassert(drv_data);
 378        else {
 379                struct spi_message *next_msg;
 380
 381                /* Holding of cs was hinted, but we need to make sure
 382                 * the next message is for the same chip.  Don't waste
 383                 * time with the following tests unless this was hinted.
 384                 *
 385                 * We cannot postpone this until pump_messages, because
 386                 * after calling msg->complete (below) the driver that
 387                 * sent the current message could be unloaded, which
 388                 * could invalidate the cs_control() callback...
 389                 */
 390
 391                /* get a pointer to the next message, if any */
 392                next_msg = spi_get_next_queued_message(drv_data->master);
 393
 394                /* see if the next and current messages point
 395                 * to the same chip
 396                 */
 397                if (next_msg && next_msg->spi != msg->spi)
 398                        next_msg = NULL;
 399                if (!next_msg || msg->state == ERROR_STATE)
 400                        cs_deassert(drv_data);
 401        }
 402
 403        spi_finalize_current_message(drv_data->master);
 404        drv_data->cur_chip = NULL;
 405}
 406
 407static void reset_sccr1(struct driver_data *drv_data)
 408{
 409        void __iomem *reg = drv_data->ioaddr;
 410        struct chip_data *chip = drv_data->cur_chip;
 411        u32 sccr1_reg;
 412
 413        sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
 414        sccr1_reg &= ~SSCR1_RFT;
 415        sccr1_reg |= chip->threshold;
 416        write_SSCR1(sccr1_reg, reg);
 417}
 418
 419static void int_error_stop(struct driver_data *drv_data, const char* msg)
 420{
 421        void __iomem *reg = drv_data->ioaddr;
 422
 423        /* Stop and reset SSP */
 424        write_SSSR_CS(drv_data, drv_data->clear_sr);
 425        reset_sccr1(drv_data);
 426        if (!pxa25x_ssp_comp(drv_data))
 427                write_SSTO(0, reg);
 428        pxa2xx_spi_flush(drv_data);
 429        write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 430
 431        dev_err(&drv_data->pdev->dev, "%s\n", msg);
 432
 433        drv_data->cur_msg->state = ERROR_STATE;
 434        tasklet_schedule(&drv_data->pump_transfers);
 435}
 436
 437static void int_transfer_complete(struct driver_data *drv_data)
 438{
 439        void __iomem *reg = drv_data->ioaddr;
 440
 441        /* Stop SSP */
 442        write_SSSR_CS(drv_data, drv_data->clear_sr);
 443        reset_sccr1(drv_data);
 444        if (!pxa25x_ssp_comp(drv_data))
 445                write_SSTO(0, reg);
 446
 447        /* Update total byte transferred return count actual bytes read */
 448        drv_data->cur_msg->actual_length += drv_data->len -
 449                                (drv_data->rx_end - drv_data->rx);
 450
 451        /* Transfer delays and chip select release are
 452         * handled in pump_transfers or giveback
 453         */
 454
 455        /* Move to next transfer */
 456        drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
 457
 458        /* Schedule transfer tasklet */
 459        tasklet_schedule(&drv_data->pump_transfers);
 460}
 461
 462static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 463{
 464        void __iomem *reg = drv_data->ioaddr;
 465
 466        u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 467                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 468
 469        u32 irq_status = read_SSSR(reg) & irq_mask;
 470
 471        if (irq_status & SSSR_ROR) {
 472                int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 473                return IRQ_HANDLED;
 474        }
 475
 476        if (irq_status & SSSR_TINT) {
 477                write_SSSR(SSSR_TINT, reg);
 478                if (drv_data->read(drv_data)) {
 479                        int_transfer_complete(drv_data);
 480                        return IRQ_HANDLED;
 481                }
 482        }
 483
 484        /* Drain rx fifo, Fill tx fifo and prevent overruns */
 485        do {
 486                if (drv_data->read(drv_data)) {
 487                        int_transfer_complete(drv_data);
 488                        return IRQ_HANDLED;
 489                }
 490        } while (drv_data->write(drv_data));
 491
 492        if (drv_data->read(drv_data)) {
 493                int_transfer_complete(drv_data);
 494                return IRQ_HANDLED;
 495        }
 496
 497        if (drv_data->tx == drv_data->tx_end) {
 498                u32 bytes_left;
 499                u32 sccr1_reg;
 500
 501                sccr1_reg = read_SSCR1(reg);
 502                sccr1_reg &= ~SSCR1_TIE;
 503
 504                /*
 505                 * PXA25x_SSP has no timeout, set up rx threshould for the
 506                 * remaining RX bytes.
 507                 */
 508                if (pxa25x_ssp_comp(drv_data)) {
 509
 510                        sccr1_reg &= ~SSCR1_RFT;
 511
 512                        bytes_left = drv_data->rx_end - drv_data->rx;
 513                        switch (drv_data->n_bytes) {
 514                        case 4:
 515                                bytes_left >>= 1;
 516                        case 2:
 517                                bytes_left >>= 1;
 518                        }
 519
 520                        if (bytes_left > RX_THRESH_DFLT)
 521                                bytes_left = RX_THRESH_DFLT;
 522
 523                        sccr1_reg |= SSCR1_RxTresh(bytes_left);
 524                }
 525                write_SSCR1(sccr1_reg, reg);
 526        }
 527
 528        /* We did something */
 529        return IRQ_HANDLED;
 530}
 531
 532static irqreturn_t ssp_int(int irq, void *dev_id)
 533{
 534        struct driver_data *drv_data = dev_id;
 535        void __iomem *reg = drv_data->ioaddr;
 536        u32 sccr1_reg;
 537        u32 mask = drv_data->mask_sr;
 538        u32 status;
 539
 540        /*
 541         * The IRQ might be shared with other peripherals so we must first
 542         * check that are we RPM suspended or not. If we are we assume that
 543         * the IRQ was not for us (we shouldn't be RPM suspended when the
 544         * interrupt is enabled).
 545         */
 546        if (pm_runtime_suspended(&drv_data->pdev->dev))
 547                return IRQ_NONE;
 548
 549        /*
 550         * If the device is not yet in RPM suspended state and we get an
 551         * interrupt that is meant for another device, check if status bits
 552         * are all set to one. That means that the device is already
 553         * powered off.
 554         */
 555        status = read_SSSR(reg);
 556        if (status == ~0)
 557                return IRQ_NONE;
 558
 559        sccr1_reg = read_SSCR1(reg);
 560
 561        /* Ignore possible writes if we don't need to write */
 562        if (!(sccr1_reg & SSCR1_TIE))
 563                mask &= ~SSSR_TFS;
 564
 565        if (!(status & mask))
 566                return IRQ_NONE;
 567
 568        if (!drv_data->cur_msg) {
 569
 570                write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 571                write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 572                if (!pxa25x_ssp_comp(drv_data))
 573                        write_SSTO(0, reg);
 574                write_SSSR_CS(drv_data, drv_data->clear_sr);
 575
 576                dev_err(&drv_data->pdev->dev, "bad message state "
 577                        "in interrupt handler\n");
 578
 579                /* Never fail */
 580                return IRQ_HANDLED;
 581        }
 582
 583        return drv_data->transfer_handler(drv_data);
 584}
 585
 586static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 587{
 588        unsigned long ssp_clk = drv_data->max_clk_rate;
 589        const struct ssp_device *ssp = drv_data->ssp;
 590
 591        rate = min_t(int, ssp_clk, rate);
 592
 593        if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 594                return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
 595        else
 596                return ((ssp_clk / rate - 1) & 0xfff) << 8;
 597}
 598
 599static void pump_transfers(unsigned long data)
 600{
 601        struct driver_data *drv_data = (struct driver_data *)data;
 602        struct spi_message *message = NULL;
 603        struct spi_transfer *transfer = NULL;
 604        struct spi_transfer *previous = NULL;
 605        struct chip_data *chip = NULL;
 606        void __iomem *reg = drv_data->ioaddr;
 607        u32 clk_div = 0;
 608        u8 bits = 0;
 609        u32 speed = 0;
 610        u32 cr0;
 611        u32 cr1;
 612        u32 dma_thresh = drv_data->cur_chip->dma_threshold;
 613        u32 dma_burst = drv_data->cur_chip->dma_burst_size;
 614
 615        /* Get current state information */
 616        message = drv_data->cur_msg;
 617        transfer = drv_data->cur_transfer;
 618        chip = drv_data->cur_chip;
 619
 620        /* Handle for abort */
 621        if (message->state == ERROR_STATE) {
 622                message->status = -EIO;
 623                giveback(drv_data);
 624                return;
 625        }
 626
 627        /* Handle end of message */
 628        if (message->state == DONE_STATE) {
 629                message->status = 0;
 630                giveback(drv_data);
 631                return;
 632        }
 633
 634        /* Delay if requested at end of transfer before CS change */
 635        if (message->state == RUNNING_STATE) {
 636                previous = list_entry(transfer->transfer_list.prev,
 637                                        struct spi_transfer,
 638                                        transfer_list);
 639                if (previous->delay_usecs)
 640                        udelay(previous->delay_usecs);
 641
 642                /* Drop chip select only if cs_change is requested */
 643                if (previous->cs_change)
 644                        cs_deassert(drv_data);
 645        }
 646
 647        /* Check if we can DMA this transfer */
 648        if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
 649
 650                /* reject already-mapped transfers; PIO won't always work */
 651                if (message->is_dma_mapped
 652                                || transfer->rx_dma || transfer->tx_dma) {
 653                        dev_err(&drv_data->pdev->dev,
 654                                "pump_transfers: mapped transfer length "
 655                                "of %u is greater than %d\n",
 656                                transfer->len, MAX_DMA_LEN);
 657                        message->status = -EINVAL;
 658                        giveback(drv_data);
 659                        return;
 660                }
 661
 662                /* warn ... we force this to PIO mode */
 663                if (printk_ratelimit())
 664                        dev_warn(&message->spi->dev, "pump_transfers: "
 665                                "DMA disabled for transfer length %ld "
 666                                "greater than %d\n",
 667                                (long)drv_data->len, MAX_DMA_LEN);
 668        }
 669
 670        /* Setup the transfer state based on the type of transfer */
 671        if (pxa2xx_spi_flush(drv_data) == 0) {
 672                dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 673                message->status = -EIO;
 674                giveback(drv_data);
 675                return;
 676        }
 677        drv_data->n_bytes = chip->n_bytes;
 678        drv_data->tx = (void *)transfer->tx_buf;
 679        drv_data->tx_end = drv_data->tx + transfer->len;
 680        drv_data->rx = transfer->rx_buf;
 681        drv_data->rx_end = drv_data->rx + transfer->len;
 682        drv_data->rx_dma = transfer->rx_dma;
 683        drv_data->tx_dma = transfer->tx_dma;
 684        drv_data->len = transfer->len;
 685        drv_data->write = drv_data->tx ? chip->write : null_writer;
 686        drv_data->read = drv_data->rx ? chip->read : null_reader;
 687
 688        /* Change speed and bit per word on a per transfer */
 689        cr0 = chip->cr0;
 690        if (transfer->speed_hz || transfer->bits_per_word) {
 691
 692                bits = chip->bits_per_word;
 693                speed = chip->speed_hz;
 694
 695                if (transfer->speed_hz)
 696                        speed = transfer->speed_hz;
 697
 698                if (transfer->bits_per_word)
 699                        bits = transfer->bits_per_word;
 700
 701                clk_div = ssp_get_clk_div(drv_data, speed);
 702
 703                if (bits <= 8) {
 704                        drv_data->n_bytes = 1;
 705                        drv_data->read = drv_data->read != null_reader ?
 706                                                u8_reader : null_reader;
 707                        drv_data->write = drv_data->write != null_writer ?
 708                                                u8_writer : null_writer;
 709                } else if (bits <= 16) {
 710                        drv_data->n_bytes = 2;
 711                        drv_data->read = drv_data->read != null_reader ?
 712                                                u16_reader : null_reader;
 713                        drv_data->write = drv_data->write != null_writer ?
 714                                                u16_writer : null_writer;
 715                } else if (bits <= 32) {
 716                        drv_data->n_bytes = 4;
 717                        drv_data->read = drv_data->read != null_reader ?
 718                                                u32_reader : null_reader;
 719                        drv_data->write = drv_data->write != null_writer ?
 720                                                u32_writer : null_writer;
 721                }
 722                /* if bits/word is changed in dma mode, then must check the
 723                 * thresholds and burst also */
 724                if (chip->enable_dma) {
 725                        if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
 726                                                        message->spi,
 727                                                        bits, &dma_burst,
 728                                                        &dma_thresh))
 729                                if (printk_ratelimit())
 730                                        dev_warn(&message->spi->dev,
 731                                                "pump_transfers: "
 732                                                "DMA burst size reduced to "
 733                                                "match bits_per_word\n");
 734                }
 735
 736                cr0 = clk_div
 737                        | SSCR0_Motorola
 738                        | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 739                        | SSCR0_SSE
 740                        | (bits > 16 ? SSCR0_EDSS : 0);
 741        }
 742
 743        message->state = RUNNING_STATE;
 744
 745        drv_data->dma_mapped = 0;
 746        if (pxa2xx_spi_dma_is_possible(drv_data->len))
 747                drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
 748        if (drv_data->dma_mapped) {
 749
 750                /* Ensure we have the correct interrupt handler */
 751                drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
 752
 753                pxa2xx_spi_dma_prepare(drv_data, dma_burst);
 754
 755                /* Clear status and start DMA engine */
 756                cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
 757                write_SSSR(drv_data->clear_sr, reg);
 758
 759                pxa2xx_spi_dma_start(drv_data);
 760        } else {
 761                /* Ensure we have the correct interrupt handler */
 762                drv_data->transfer_handler = interrupt_transfer;
 763
 764                /* Clear status  */
 765                cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
 766                write_SSSR_CS(drv_data, drv_data->clear_sr);
 767        }
 768
 769        if (is_lpss_ssp(drv_data)) {
 770                if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
 771                        write_SSIRF(chip->lpss_rx_threshold, reg);
 772                if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
 773                        write_SSITF(chip->lpss_tx_threshold, reg);
 774        }
 775
 776        /* see if we need to reload the config registers */
 777        if ((read_SSCR0(reg) != cr0)
 778                || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
 779                        (cr1 & SSCR1_CHANGE_MASK)) {
 780
 781                /* stop the SSP, and update the other bits */
 782                write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 783                if (!pxa25x_ssp_comp(drv_data))
 784                        write_SSTO(chip->timeout, reg);
 785                /* first set CR1 without interrupt and service enables */
 786                write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
 787                /* restart the SSP */
 788                write_SSCR0(cr0, reg);
 789
 790        } else {
 791                if (!pxa25x_ssp_comp(drv_data))
 792                        write_SSTO(chip->timeout, reg);
 793        }
 794
 795        cs_assert(drv_data);
 796
 797        /* after chip select, release the data by enabling service
 798         * requests and interrupts, without changing any mode bits */
 799        write_SSCR1(cr1, reg);
 800}
 801
 802static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
 803                                           struct spi_message *msg)
 804{
 805        struct driver_data *drv_data = spi_master_get_devdata(master);
 806
 807        drv_data->cur_msg = msg;
 808        /* Initial message state*/
 809        drv_data->cur_msg->state = START_STATE;
 810        drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 811                                                struct spi_transfer,
 812                                                transfer_list);
 813
 814        /* prepare to setup the SSP, in pump_transfers, using the per
 815         * chip configuration */
 816        drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 817
 818        /* Mark as busy and launch transfers */
 819        tasklet_schedule(&drv_data->pump_transfers);
 820        return 0;
 821}
 822
 823static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
 824{
 825        struct driver_data *drv_data = spi_master_get_devdata(master);
 826
 827        /* Disable the SSP now */
 828        write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
 829                    drv_data->ioaddr);
 830
 831        return 0;
 832}
 833
 834static int setup_cs(struct spi_device *spi, struct chip_data *chip,
 835                    struct pxa2xx_spi_chip *chip_info)
 836{
 837        int err = 0;
 838
 839        if (chip == NULL || chip_info == NULL)
 840                return 0;
 841
 842        /* NOTE: setup() can be called multiple times, possibly with
 843         * different chip_info, release previously requested GPIO
 844         */
 845        if (gpio_is_valid(chip->gpio_cs))
 846                gpio_free(chip->gpio_cs);
 847
 848        /* If (*cs_control) is provided, ignore GPIO chip select */
 849        if (chip_info->cs_control) {
 850                chip->cs_control = chip_info->cs_control;
 851                return 0;
 852        }
 853
 854        if (gpio_is_valid(chip_info->gpio_cs)) {
 855                err = gpio_request(chip_info->gpio_cs, "SPI_CS");
 856                if (err) {
 857                        dev_err(&spi->dev, "failed to request chip select "
 858                                        "GPIO%d\n", chip_info->gpio_cs);
 859                        return err;
 860                }
 861
 862                chip->gpio_cs = chip_info->gpio_cs;
 863                chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
 864
 865                err = gpio_direction_output(chip->gpio_cs,
 866                                        !chip->gpio_cs_inverted);
 867        }
 868
 869        return err;
 870}
 871
 872static int setup(struct spi_device *spi)
 873{
 874        struct pxa2xx_spi_chip *chip_info = NULL;
 875        struct chip_data *chip;
 876        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 877        unsigned int clk_div;
 878        uint tx_thres, tx_hi_thres, rx_thres;
 879
 880        if (is_lpss_ssp(drv_data)) {
 881                tx_thres = LPSS_TX_LOTHRESH_DFLT;
 882                tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
 883                rx_thres = LPSS_RX_THRESH_DFLT;
 884        } else {
 885                tx_thres = TX_THRESH_DFLT;
 886                tx_hi_thres = 0;
 887                rx_thres = RX_THRESH_DFLT;
 888        }
 889
 890        /* Only alloc on first setup */
 891        chip = spi_get_ctldata(spi);
 892        if (!chip) {
 893                chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 894                if (!chip) {
 895                        dev_err(&spi->dev,
 896                                "failed setup: can't allocate chip data\n");
 897                        return -ENOMEM;
 898                }
 899
 900                if (drv_data->ssp_type == CE4100_SSP) {
 901                        if (spi->chip_select > 4) {
 902                                dev_err(&spi->dev, "failed setup: "
 903                                "cs number must not be > 4.\n");
 904                                kfree(chip);
 905                                return -EINVAL;
 906                        }
 907
 908                        chip->frm = spi->chip_select;
 909                } else
 910                        chip->gpio_cs = -1;
 911                chip->enable_dma = 0;
 912                chip->timeout = TIMOUT_DFLT;
 913        }
 914
 915        /* protocol drivers may change the chip settings, so...
 916         * if chip_info exists, use it */
 917        chip_info = spi->controller_data;
 918
 919        /* chip_info isn't always needed */
 920        chip->cr1 = 0;
 921        if (chip_info) {
 922                if (chip_info->timeout)
 923                        chip->timeout = chip_info->timeout;
 924                if (chip_info->tx_threshold)
 925                        tx_thres = chip_info->tx_threshold;
 926                if (chip_info->tx_hi_threshold)
 927                        tx_hi_thres = chip_info->tx_hi_threshold;
 928                if (chip_info->rx_threshold)
 929                        rx_thres = chip_info->rx_threshold;
 930                chip->enable_dma = drv_data->master_info->enable_dma;
 931                chip->dma_threshold = 0;
 932                if (chip_info->enable_loopback)
 933                        chip->cr1 = SSCR1_LBM;
 934        } else if (ACPI_HANDLE(&spi->dev)) {
 935                /*
 936                 * Slave devices enumerated from ACPI namespace don't
 937                 * usually have chip_info but we still might want to use
 938                 * DMA with them.
 939                 */
 940                chip->enable_dma = drv_data->master_info->enable_dma;
 941        }
 942
 943        chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
 944                        (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
 945
 946        chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
 947        chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
 948                                | SSITF_TxHiThresh(tx_hi_thres);
 949
 950        /* set dma burst and threshold outside of chip_info path so that if
 951         * chip_info goes away after setting chip->enable_dma, the
 952         * burst and threshold can still respond to changes in bits_per_word */
 953        if (chip->enable_dma) {
 954                /* set up legal burst and threshold for dma */
 955                if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
 956                                                spi->bits_per_word,
 957                                                &chip->dma_burst_size,
 958                                                &chip->dma_threshold)) {
 959                        dev_warn(&spi->dev, "in setup: DMA burst size reduced "
 960                                        "to match bits_per_word\n");
 961                }
 962        }
 963
 964        clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
 965        chip->speed_hz = spi->max_speed_hz;
 966
 967        chip->cr0 = clk_div
 968                        | SSCR0_Motorola
 969                        | SSCR0_DataSize(spi->bits_per_word > 16 ?
 970                                spi->bits_per_word - 16 : spi->bits_per_word)
 971                        | SSCR0_SSE
 972                        | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
 973        chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
 974        chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
 975                        | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
 976
 977        if (spi->mode & SPI_LOOP)
 978                chip->cr1 |= SSCR1_LBM;
 979
 980        /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 981        if (!pxa25x_ssp_comp(drv_data))
 982                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 983                        drv_data->max_clk_rate
 984                                / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
 985                        chip->enable_dma ? "DMA" : "PIO");
 986        else
 987                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 988                        drv_data->max_clk_rate / 2
 989                                / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
 990                        chip->enable_dma ? "DMA" : "PIO");
 991
 992        if (spi->bits_per_word <= 8) {
 993                chip->n_bytes = 1;
 994                chip->read = u8_reader;
 995                chip->write = u8_writer;
 996        } else if (spi->bits_per_word <= 16) {
 997                chip->n_bytes = 2;
 998                chip->read = u16_reader;
 999                chip->write = u16_writer;
1000        } else if (spi->bits_per_word <= 32) {
1001                chip->cr0 |= SSCR0_EDSS;
1002                chip->n_bytes = 4;
1003                chip->read = u32_reader;
1004                chip->write = u32_writer;
1005        }
1006        chip->bits_per_word = spi->bits_per_word;
1007
1008        spi_set_ctldata(spi, chip);
1009
1010        if (drv_data->ssp_type == CE4100_SSP)
1011                return 0;
1012
1013        return setup_cs(spi, chip, chip_info);
1014}
1015
1016static void cleanup(struct spi_device *spi)
1017{
1018        struct chip_data *chip = spi_get_ctldata(spi);
1019        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1020
1021        if (!chip)
1022                return;
1023
1024        if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1025                gpio_free(chip->gpio_cs);
1026
1027        kfree(chip);
1028}
1029
1030#ifdef CONFIG_ACPI
1031static struct pxa2xx_spi_master *
1032pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1033{
1034        struct pxa2xx_spi_master *pdata;
1035        struct acpi_device *adev;
1036        struct ssp_device *ssp;
1037        struct resource *res;
1038        int devid;
1039
1040        if (!ACPI_HANDLE(&pdev->dev) ||
1041            acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1042                return NULL;
1043
1044        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1045        if (!pdata) {
1046                dev_err(&pdev->dev,
1047                        "failed to allocate memory for platform data\n");
1048                return NULL;
1049        }
1050
1051        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052        if (!res)
1053                return NULL;
1054
1055        ssp = &pdata->ssp;
1056
1057        ssp->phys_base = res->start;
1058        ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1059        if (IS_ERR(ssp->mmio_base))
1060                return NULL;
1061
1062        ssp->clk = devm_clk_get(&pdev->dev, NULL);
1063        ssp->irq = platform_get_irq(pdev, 0);
1064        ssp->type = LPSS_SSP;
1065        ssp->pdev = pdev;
1066
1067        ssp->port_id = -1;
1068        if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1069                ssp->port_id = devid;
1070
1071        pdata->num_chipselect = 1;
1072        pdata->enable_dma = true;
1073
1074        return pdata;
1075}
1076
1077static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1078        { "INT33C0", 0 },
1079        { "INT33C1", 0 },
1080        { "80860F0E", 0 },
1081        { },
1082};
1083MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1084#else
1085static inline struct pxa2xx_spi_master *
1086pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1087{
1088        return NULL;
1089}
1090#endif
1091
1092static int pxa2xx_spi_probe(struct platform_device *pdev)
1093{
1094        struct device *dev = &pdev->dev;
1095        struct pxa2xx_spi_master *platform_info;
1096        struct spi_master *master;
1097        struct driver_data *drv_data;
1098        struct ssp_device *ssp;
1099        int status;
1100
1101        platform_info = dev_get_platdata(dev);
1102        if (!platform_info) {
1103                platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1104                if (!platform_info) {
1105                        dev_err(&pdev->dev, "missing platform data\n");
1106                        return -ENODEV;
1107                }
1108        }
1109
1110        ssp = pxa_ssp_request(pdev->id, pdev->name);
1111        if (!ssp)
1112                ssp = &platform_info->ssp;
1113
1114        if (!ssp->mmio_base) {
1115                dev_err(&pdev->dev, "failed to get ssp\n");
1116                return -ENODEV;
1117        }
1118
1119        /* Allocate master with space for drv_data and null dma buffer */
1120        master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1121        if (!master) {
1122                dev_err(&pdev->dev, "cannot alloc spi_master\n");
1123                pxa_ssp_free(ssp);
1124                return -ENOMEM;
1125        }
1126        drv_data = spi_master_get_devdata(master);
1127        drv_data->master = master;
1128        drv_data->master_info = platform_info;
1129        drv_data->pdev = pdev;
1130        drv_data->ssp = ssp;
1131
1132        master->dev.parent = &pdev->dev;
1133        master->dev.of_node = pdev->dev.of_node;
1134        /* the spi->mode bits understood by this driver: */
1135        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1136
1137        master->bus_num = ssp->port_id;
1138        master->num_chipselect = platform_info->num_chipselect;
1139        master->dma_alignment = DMA_ALIGNMENT;
1140        master->cleanup = cleanup;
1141        master->setup = setup;
1142        master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1143        master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1144        master->auto_runtime_pm = true;
1145
1146        drv_data->ssp_type = ssp->type;
1147        drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1148
1149        drv_data->ioaddr = ssp->mmio_base;
1150        drv_data->ssdr_physical = ssp->phys_base + SSDR;
1151        if (pxa25x_ssp_comp(drv_data)) {
1152                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1153                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1154                drv_data->dma_cr1 = 0;
1155                drv_data->clear_sr = SSSR_ROR;
1156                drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1157        } else {
1158                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1159                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1160                drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1161                drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1162                drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1163        }
1164
1165        status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1166                        drv_data);
1167        if (status < 0) {
1168                dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1169                goto out_error_master_alloc;
1170        }
1171
1172        /* Setup DMA if requested */
1173        drv_data->tx_channel = -1;
1174        drv_data->rx_channel = -1;
1175        if (platform_info->enable_dma) {
1176                status = pxa2xx_spi_dma_setup(drv_data);
1177                if (status) {
1178                        dev_dbg(dev, "no DMA channels available, using PIO\n");
1179                        platform_info->enable_dma = false;
1180                }
1181        }
1182
1183        /* Enable SOC clock */
1184        clk_prepare_enable(ssp->clk);
1185
1186        drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1187
1188        /* Load default SSP configuration */
1189        write_SSCR0(0, drv_data->ioaddr);
1190        write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1191                                SSCR1_TxTresh(TX_THRESH_DFLT),
1192                                drv_data->ioaddr);
1193        write_SSCR0(SSCR0_SCR(2)
1194                        | SSCR0_Motorola
1195                        | SSCR0_DataSize(8),
1196                        drv_data->ioaddr);
1197        if (!pxa25x_ssp_comp(drv_data))
1198                write_SSTO(0, drv_data->ioaddr);
1199        write_SSPSP(0, drv_data->ioaddr);
1200
1201        lpss_ssp_setup(drv_data);
1202
1203        tasklet_init(&drv_data->pump_transfers, pump_transfers,
1204                     (unsigned long)drv_data);
1205
1206        /* Register with the SPI framework */
1207        platform_set_drvdata(pdev, drv_data);
1208        status = spi_register_master(master);
1209        if (status != 0) {
1210                dev_err(&pdev->dev, "problem registering spi master\n");
1211                goto out_error_clock_enabled;
1212        }
1213
1214        pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1215        pm_runtime_use_autosuspend(&pdev->dev);
1216        pm_runtime_set_active(&pdev->dev);
1217        pm_runtime_enable(&pdev->dev);
1218
1219        return status;
1220
1221out_error_clock_enabled:
1222        clk_disable_unprepare(ssp->clk);
1223        pxa2xx_spi_dma_release(drv_data);
1224        free_irq(ssp->irq, drv_data);
1225
1226out_error_master_alloc:
1227        spi_master_put(master);
1228        pxa_ssp_free(ssp);
1229        return status;
1230}
1231
1232static int pxa2xx_spi_remove(struct platform_device *pdev)
1233{
1234        struct driver_data *drv_data = platform_get_drvdata(pdev);
1235        struct ssp_device *ssp;
1236
1237        if (!drv_data)
1238                return 0;
1239        ssp = drv_data->ssp;
1240
1241        pm_runtime_get_sync(&pdev->dev);
1242
1243        /* Disable the SSP at the peripheral and SOC level */
1244        write_SSCR0(0, drv_data->ioaddr);
1245        clk_disable_unprepare(ssp->clk);
1246
1247        /* Release DMA */
1248        if (drv_data->master_info->enable_dma)
1249                pxa2xx_spi_dma_release(drv_data);
1250
1251        pm_runtime_put_noidle(&pdev->dev);
1252        pm_runtime_disable(&pdev->dev);
1253
1254        /* Release IRQ */
1255        free_irq(ssp->irq, drv_data);
1256
1257        /* Release SSP */
1258        pxa_ssp_free(ssp);
1259
1260        /* Disconnect from the SPI framework */
1261        spi_unregister_master(drv_data->master);
1262
1263        return 0;
1264}
1265
1266static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1267{
1268        int status = 0;
1269
1270        if ((status = pxa2xx_spi_remove(pdev)) != 0)
1271                dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1272}
1273
1274#ifdef CONFIG_PM
1275static int pxa2xx_spi_suspend(struct device *dev)
1276{
1277        struct driver_data *drv_data = dev_get_drvdata(dev);
1278        struct ssp_device *ssp = drv_data->ssp;
1279        int status = 0;
1280
1281        status = spi_master_suspend(drv_data->master);
1282        if (status != 0)
1283                return status;
1284        write_SSCR0(0, drv_data->ioaddr);
1285        clk_disable_unprepare(ssp->clk);
1286
1287        return 0;
1288}
1289
1290static int pxa2xx_spi_resume(struct device *dev)
1291{
1292        struct driver_data *drv_data = dev_get_drvdata(dev);
1293        struct ssp_device *ssp = drv_data->ssp;
1294        int status = 0;
1295
1296        pxa2xx_spi_dma_resume(drv_data);
1297
1298        /* Enable the SSP clock */
1299        clk_prepare_enable(ssp->clk);
1300
1301        /* Start the queue running */
1302        status = spi_master_resume(drv_data->master);
1303        if (status != 0) {
1304                dev_err(dev, "problem starting queue (%d)\n", status);
1305                return status;
1306        }
1307
1308        return 0;
1309}
1310#endif
1311
1312#ifdef CONFIG_PM_RUNTIME
1313static int pxa2xx_spi_runtime_suspend(struct device *dev)
1314{
1315        struct driver_data *drv_data = dev_get_drvdata(dev);
1316
1317        clk_disable_unprepare(drv_data->ssp->clk);
1318        return 0;
1319}
1320
1321static int pxa2xx_spi_runtime_resume(struct device *dev)
1322{
1323        struct driver_data *drv_data = dev_get_drvdata(dev);
1324
1325        clk_prepare_enable(drv_data->ssp->clk);
1326        return 0;
1327}
1328#endif
1329
1330static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1331        SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1332        SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1333                           pxa2xx_spi_runtime_resume, NULL)
1334};
1335
1336static struct platform_driver driver = {
1337        .driver = {
1338                .name   = "pxa2xx-spi",
1339                .owner  = THIS_MODULE,
1340                .pm     = &pxa2xx_spi_pm_ops,
1341                .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1342        },
1343        .probe = pxa2xx_spi_probe,
1344        .remove = pxa2xx_spi_remove,
1345        .shutdown = pxa2xx_spi_shutdown,
1346};
1347
1348static int __init pxa2xx_spi_init(void)
1349{
1350        return platform_driver_register(&driver);
1351}
1352subsys_initcall(pxa2xx_spi_init);
1353
1354static void __exit pxa2xx_spi_exit(void)
1355{
1356        platform_driver_unregister(&driver);
1357}
1358module_exit(pxa2xx_spi_exit);
1359
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