linux/drivers/spi/spi-bcm63xx.c
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   1/*
   2 * Broadcom BCM63xx SPI controller support
   3 *
   4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version 2
  10 * of the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the
  19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20 */
  21
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24#include <linux/clk.h>
  25#include <linux/io.h>
  26#include <linux/module.h>
  27#include <linux/platform_device.h>
  28#include <linux/delay.h>
  29#include <linux/interrupt.h>
  30#include <linux/spi/spi.h>
  31#include <linux/completion.h>
  32#include <linux/err.h>
  33#include <linux/workqueue.h>
  34#include <linux/pm_runtime.h>
  35
  36#include <bcm63xx_dev_spi.h>
  37
  38#define PFX             KBUILD_MODNAME
  39
  40#define BCM63XX_SPI_MAX_PREPEND         15
  41
  42struct bcm63xx_spi {
  43        struct completion       done;
  44
  45        void __iomem            *regs;
  46        int                     irq;
  47
  48        /* Platform data */
  49        unsigned                fifo_size;
  50        unsigned int            msg_type_shift;
  51        unsigned int            msg_ctl_width;
  52
  53        /* data iomem */
  54        u8 __iomem              *tx_io;
  55        const u8 __iomem        *rx_io;
  56
  57        struct clk              *clk;
  58        struct platform_device  *pdev;
  59};
  60
  61static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  62                                unsigned int offset)
  63{
  64        return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  65}
  66
  67static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  68                                unsigned int offset)
  69{
  70        return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  71}
  72
  73static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  74                                  u8 value, unsigned int offset)
  75{
  76        bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  77}
  78
  79static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  80                                  u16 value, unsigned int offset)
  81{
  82        bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  83}
  84
  85static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  86        { 20000000, SPI_CLK_20MHZ },
  87        { 12500000, SPI_CLK_12_50MHZ },
  88        {  6250000, SPI_CLK_6_250MHZ },
  89        {  3125000, SPI_CLK_3_125MHZ },
  90        {  1563000, SPI_CLK_1_563MHZ },
  91        {   781000, SPI_CLK_0_781MHZ },
  92        {   391000, SPI_CLK_0_391MHZ }
  93};
  94
  95static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  96                                      struct spi_transfer *t)
  97{
  98        struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  99        u8 clk_cfg, reg;
 100        int i;
 101
 102        /* Find the closest clock configuration */
 103        for (i = 0; i < SPI_CLK_MASK; i++) {
 104                if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 105                        clk_cfg = bcm63xx_spi_freq_table[i][1];
 106                        break;
 107                }
 108        }
 109
 110        /* No matching configuration found, default to lowest */
 111        if (i == SPI_CLK_MASK)
 112                clk_cfg = SPI_CLK_0_391MHZ;
 113
 114        /* clear existing clock configuration bits of the register */
 115        reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 116        reg &= ~SPI_CLK_MASK;
 117        reg |= clk_cfg;
 118
 119        bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 120        dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 121                clk_cfg, t->speed_hz);
 122}
 123
 124/* the spi->mode bits understood by this driver: */
 125#define MODEBITS (SPI_CPOL | SPI_CPHA)
 126
 127static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 128                                unsigned int num_transfers)
 129{
 130        struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 131        u16 msg_ctl;
 132        u16 cmd;
 133        u8 rx_tail;
 134        unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 135        struct spi_transfer *t = first;
 136        bool do_rx = false;
 137        bool do_tx = false;
 138
 139        /* Disable the CMD_DONE interrupt */
 140        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 141
 142        dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 143                t->tx_buf, t->rx_buf, t->len);
 144
 145        if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 146                prepend_len = t->len;
 147
 148        /* prepare the buffer */
 149        for (i = 0; i < num_transfers; i++) {
 150                if (t->tx_buf) {
 151                        do_tx = true;
 152                        memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 153
 154                        /* don't prepend more than one tx */
 155                        if (t != first)
 156                                prepend_len = 0;
 157                }
 158
 159                if (t->rx_buf) {
 160                        do_rx = true;
 161                        /* prepend is half-duplex write only */
 162                        if (t == first)
 163                                prepend_len = 0;
 164                }
 165
 166                len += t->len;
 167
 168                t = list_entry(t->transfer_list.next, struct spi_transfer,
 169                               transfer_list);
 170        }
 171
 172        len -= prepend_len;
 173
 174        init_completion(&bs->done);
 175
 176        /* Fill in the Message control register */
 177        msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 178
 179        if (do_rx && do_tx && prepend_len == 0)
 180                msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 181        else if (do_rx)
 182                msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 183        else if (do_tx)
 184                msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 185
 186        switch (bs->msg_ctl_width) {
 187        case 8:
 188                bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 189                break;
 190        case 16:
 191                bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 192                break;
 193        }
 194
 195        /* Issue the transfer */
 196        cmd = SPI_CMD_START_IMMEDIATE;
 197        cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 198        cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 199        bcm_spi_writew(bs, cmd, SPI_CMD);
 200
 201        /* Enable the CMD_DONE interrupt */
 202        bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 203
 204        timeout = wait_for_completion_timeout(&bs->done, HZ);
 205        if (!timeout)
 206                return -ETIMEDOUT;
 207
 208        /* read out all data */
 209        rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 210
 211        if (do_rx && rx_tail != len)
 212                return -EIO;
 213
 214        if (!rx_tail)
 215                return 0;
 216
 217        len = 0;
 218        t = first;
 219        /* Read out all the data */
 220        for (i = 0; i < num_transfers; i++) {
 221                if (t->rx_buf)
 222                        memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 223
 224                if (t != first || prepend_len == 0)
 225                        len += t->len;
 226
 227                t = list_entry(t->transfer_list.next, struct spi_transfer,
 228                               transfer_list);
 229        }
 230
 231        return 0;
 232}
 233
 234static int bcm63xx_spi_transfer_one(struct spi_master *master,
 235                                        struct spi_message *m)
 236{
 237        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 238        struct spi_transfer *t, *first = NULL;
 239        struct spi_device *spi = m->spi;
 240        int status = 0;
 241        unsigned int n_transfers = 0, total_len = 0;
 242        bool can_use_prepend = false;
 243
 244        /*
 245         * This SPI controller does not support keeping CS active after a
 246         * transfer.
 247         * Work around this by merging as many transfers we can into one big
 248         * full-duplex transfers.
 249         */
 250        list_for_each_entry(t, &m->transfers, transfer_list) {
 251                if (!first)
 252                        first = t;
 253
 254                n_transfers++;
 255                total_len += t->len;
 256
 257                if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 258                    first->len <= BCM63XX_SPI_MAX_PREPEND)
 259                        can_use_prepend = true;
 260                else if (can_use_prepend && t->tx_buf)
 261                        can_use_prepend = false;
 262
 263                /* we can only transfer one fifo worth of data */
 264                if ((can_use_prepend &&
 265                     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 266                    (!can_use_prepend && total_len > bs->fifo_size)) {
 267                        dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 268                                total_len, bs->fifo_size);
 269                        status = -EINVAL;
 270                        goto exit;
 271                }
 272
 273                /* all combined transfers have to have the same speed */
 274                if (t->speed_hz != first->speed_hz) {
 275                        dev_err(&spi->dev, "unable to change speed between transfers\n");
 276                        status = -EINVAL;
 277                        goto exit;
 278                }
 279
 280                /* CS will be deasserted directly after transfer */
 281                if (t->delay_usecs) {
 282                        dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 283                        status = -EINVAL;
 284                        goto exit;
 285                }
 286
 287                if (t->cs_change ||
 288                    list_is_last(&t->transfer_list, &m->transfers)) {
 289                        /* configure adapter for a new transfer */
 290                        bcm63xx_spi_setup_transfer(spi, first);
 291
 292                        /* send the data */
 293                        status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 294                        if (status)
 295                                goto exit;
 296
 297                        m->actual_length += total_len;
 298
 299                        first = NULL;
 300                        n_transfers = 0;
 301                        total_len = 0;
 302                        can_use_prepend = false;
 303                }
 304        }
 305exit:
 306        m->status = status;
 307        spi_finalize_current_message(master);
 308
 309        return 0;
 310}
 311
 312/* This driver supports single master mode only. Hence
 313 * CMD_DONE is the only interrupt we care about
 314 */
 315static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 316{
 317        struct spi_master *master = (struct spi_master *)dev_id;
 318        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 319        u8 intr;
 320
 321        /* Read interupts and clear them immediately */
 322        intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 323        bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 324        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 325
 326        /* A transfer completed */
 327        if (intr & SPI_INTR_CMD_DONE)
 328                complete(&bs->done);
 329
 330        return IRQ_HANDLED;
 331}
 332
 333
 334static int bcm63xx_spi_probe(struct platform_device *pdev)
 335{
 336        struct resource *r;
 337        struct device *dev = &pdev->dev;
 338        struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
 339        int irq;
 340        struct spi_master *master;
 341        struct clk *clk;
 342        struct bcm63xx_spi *bs;
 343        int ret;
 344
 345        irq = platform_get_irq(pdev, 0);
 346        if (irq < 0) {
 347                dev_err(dev, "no irq\n");
 348                ret = -ENXIO;
 349                goto out;
 350        }
 351
 352        clk = clk_get(dev, "spi");
 353        if (IS_ERR(clk)) {
 354                dev_err(dev, "no clock for device\n");
 355                ret = PTR_ERR(clk);
 356                goto out;
 357        }
 358
 359        master = spi_alloc_master(dev, sizeof(*bs));
 360        if (!master) {
 361                dev_err(dev, "out of memory\n");
 362                ret = -ENOMEM;
 363                goto out_clk;
 364        }
 365
 366        bs = spi_master_get_devdata(master);
 367
 368        platform_set_drvdata(pdev, master);
 369        bs->pdev = pdev;
 370
 371        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 372        bs->regs = devm_ioremap_resource(&pdev->dev, r);
 373        if (IS_ERR(bs->regs)) {
 374                ret = PTR_ERR(bs->regs);
 375                goto out_err;
 376        }
 377
 378        bs->irq = irq;
 379        bs->clk = clk;
 380        bs->fifo_size = pdata->fifo_size;
 381
 382        ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 383                                                        pdev->name, master);
 384        if (ret) {
 385                dev_err(dev, "unable to request irq\n");
 386                goto out_err;
 387        }
 388
 389        master->bus_num = pdata->bus_num;
 390        master->num_chipselect = pdata->num_chipselect;
 391        master->transfer_one_message = bcm63xx_spi_transfer_one;
 392        master->mode_bits = MODEBITS;
 393        master->bits_per_word_mask = SPI_BPW_MASK(8);
 394        master->auto_runtime_pm = true;
 395        bs->msg_type_shift = pdata->msg_type_shift;
 396        bs->msg_ctl_width = pdata->msg_ctl_width;
 397        bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 398        bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 399
 400        switch (bs->msg_ctl_width) {
 401        case 8:
 402        case 16:
 403                break;
 404        default:
 405                dev_err(dev, "unsupported MSG_CTL width: %d\n",
 406                         bs->msg_ctl_width);
 407                goto out_err;
 408        }
 409
 410        /* Initialize hardware */
 411        clk_prepare_enable(bs->clk);
 412        bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 413
 414        /* register and we are done */
 415        ret = spi_register_master(master);
 416        if (ret) {
 417                dev_err(dev, "spi register failed\n");
 418                goto out_clk_disable;
 419        }
 420
 421        dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 422                 r->start, irq, bs->fifo_size);
 423
 424        return 0;
 425
 426out_clk_disable:
 427        clk_disable_unprepare(clk);
 428out_err:
 429        spi_master_put(master);
 430out_clk:
 431        clk_put(clk);
 432out:
 433        return ret;
 434}
 435
 436static int bcm63xx_spi_remove(struct platform_device *pdev)
 437{
 438        struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 439        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 440
 441        spi_unregister_master(master);
 442
 443        /* reset spi block */
 444        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 445
 446        /* HW shutdown */
 447        clk_disable_unprepare(bs->clk);
 448        clk_put(bs->clk);
 449
 450        spi_master_put(master);
 451
 452        return 0;
 453}
 454
 455#ifdef CONFIG_PM
 456static int bcm63xx_spi_suspend(struct device *dev)
 457{
 458        struct spi_master *master = dev_get_drvdata(dev);
 459        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 460
 461        spi_master_suspend(master);
 462
 463        clk_disable_unprepare(bs->clk);
 464
 465        return 0;
 466}
 467
 468static int bcm63xx_spi_resume(struct device *dev)
 469{
 470        struct spi_master *master = dev_get_drvdata(dev);
 471        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 472
 473        clk_prepare_enable(bs->clk);
 474
 475        spi_master_resume(master);
 476
 477        return 0;
 478}
 479
 480static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 481        .suspend        = bcm63xx_spi_suspend,
 482        .resume         = bcm63xx_spi_resume,
 483};
 484
 485#define BCM63XX_SPI_PM_OPS      (&bcm63xx_spi_pm_ops)
 486#else
 487#define BCM63XX_SPI_PM_OPS      NULL
 488#endif
 489
 490static struct platform_driver bcm63xx_spi_driver = {
 491        .driver = {
 492                .name   = "bcm63xx-spi",
 493                .owner  = THIS_MODULE,
 494                .pm     = BCM63XX_SPI_PM_OPS,
 495        },
 496        .probe          = bcm63xx_spi_probe,
 497        .remove         = bcm63xx_spi_remove,
 498};
 499
 500module_platform_driver(bcm63xx_spi_driver);
 501
 502MODULE_ALIAS("platform:bcm63xx_spi");
 503MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 504MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 505MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 506MODULE_LICENSE("GPL");
 507
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