linux/drivers/scsi/ipr.h
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   1/*
   2 * ipr.h -- driver for IBM Power Linux RAID adapters
   3 *
   4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
   5 *
   6 * Copyright (C) 2003, 2004 IBM Corporation
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 *
  22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
  23 *                              that broke 64bit platforms.
  24 */
  25
  26#ifndef _IPR_H
  27#define _IPR_H
  28
  29#include <asm/unaligned.h>
  30#include <linux/types.h>
  31#include <linux/completion.h>
  32#include <linux/libata.h>
  33#include <linux/list.h>
  34#include <linux/kref.h>
  35#include <linux/blk-iopoll.h>
  36#include <scsi/scsi.h>
  37#include <scsi/scsi_cmnd.h>
  38
  39/*
  40 * Literals
  41 */
  42#define IPR_DRIVER_VERSION "2.6.0"
  43#define IPR_DRIVER_DATE "(November 16, 2012)"
  44
  45/*
  46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  47 *      ops per device for devices not running tagged command queuing.
  48 *      This can be adjusted at runtime through sysfs device attributes.
  49 */
  50#define IPR_MAX_CMD_PER_LUN                             6
  51#define IPR_MAX_CMD_PER_ATA_LUN                 1
  52
  53/*
  54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  55 *      ops the mid-layer can send to the adapter.
  56 */
  57#define IPR_NUM_BASE_CMD_BLKS                   (ioa_cfg->max_cmds)
  58
  59#define PCI_DEVICE_ID_IBM_OBSIDIAN_E    0x0339
  60
  61#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
  62#define PCI_DEVICE_ID_IBM_CROCODILE             0x034A
  63
  64#define IPR_SUBS_DEV_ID_2780    0x0264
  65#define IPR_SUBS_DEV_ID_5702    0x0266
  66#define IPR_SUBS_DEV_ID_5703    0x0278
  67#define IPR_SUBS_DEV_ID_572E    0x028D
  68#define IPR_SUBS_DEV_ID_573E    0x02D3
  69#define IPR_SUBS_DEV_ID_573D    0x02D4
  70#define IPR_SUBS_DEV_ID_571A    0x02C0
  71#define IPR_SUBS_DEV_ID_571B    0x02BE
  72#define IPR_SUBS_DEV_ID_571E    0x02BF
  73#define IPR_SUBS_DEV_ID_571F    0x02D5
  74#define IPR_SUBS_DEV_ID_572A    0x02C1
  75#define IPR_SUBS_DEV_ID_572B    0x02C2
  76#define IPR_SUBS_DEV_ID_572F    0x02C3
  77#define IPR_SUBS_DEV_ID_574E    0x030A
  78#define IPR_SUBS_DEV_ID_575B    0x030D
  79#define IPR_SUBS_DEV_ID_575C    0x0338
  80#define IPR_SUBS_DEV_ID_57B3    0x033A
  81#define IPR_SUBS_DEV_ID_57B7    0x0360
  82#define IPR_SUBS_DEV_ID_57B8    0x02C2
  83
  84#define IPR_SUBS_DEV_ID_57B4    0x033B
  85#define IPR_SUBS_DEV_ID_57B2    0x035F
  86#define IPR_SUBS_DEV_ID_57C0    0x0352
  87#define IPR_SUBS_DEV_ID_57C3    0x0353
  88#define IPR_SUBS_DEV_ID_57C4    0x0354
  89#define IPR_SUBS_DEV_ID_57C6    0x0357
  90#define IPR_SUBS_DEV_ID_57CC    0x035C
  91
  92#define IPR_SUBS_DEV_ID_57B5    0x033C
  93#define IPR_SUBS_DEV_ID_57CE    0x035E
  94#define IPR_SUBS_DEV_ID_57B1    0x0355
  95
  96#define IPR_SUBS_DEV_ID_574D    0x0356
  97#define IPR_SUBS_DEV_ID_57C8    0x035D
  98
  99#define IPR_SUBS_DEV_ID_57D5    0x03FB
 100#define IPR_SUBS_DEV_ID_57D6    0x03FC
 101#define IPR_SUBS_DEV_ID_57D7    0x03FF
 102#define IPR_SUBS_DEV_ID_57D8    0x03FE
 103#define IPR_SUBS_DEV_ID_57D9    0x046D
 104#define IPR_SUBS_DEV_ID_57EB    0x0474
 105#define IPR_SUBS_DEV_ID_57EC    0x0475
 106#define IPR_SUBS_DEV_ID_57ED    0x0499
 107#define IPR_SUBS_DEV_ID_57EE    0x049A
 108#define IPR_SUBS_DEV_ID_57EF    0x049B
 109#define IPR_SUBS_DEV_ID_57F0    0x049C
 110#define IPR_NAME                                "ipr"
 111
 112/*
 113 * Return codes
 114 */
 115#define IPR_RC_JOB_CONTINUE             1
 116#define IPR_RC_JOB_RETURN               2
 117
 118/*
 119 * IOASCs
 120 */
 121#define IPR_IOASC_NR_INIT_CMD_REQUIRED          0x02040200
 122#define IPR_IOASC_NR_IOA_RESET_REQUIRED         0x02048000
 123#define IPR_IOASC_SYNC_REQUIRED                 0x023f0000
 124#define IPR_IOASC_MED_DO_NOT_REALLOC            0x03110C00
 125#define IPR_IOASC_HW_SEL_TIMEOUT                        0x04050000
 126#define IPR_IOASC_HW_DEV_BUS_STATUS                     0x04448500
 127#define IPR_IOASC_IOASC_MASK                    0xFFFFFF00
 128#define IPR_IOASC_SCSI_STATUS_MASK              0x000000FF
 129#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT    0x05240000
 130#define IPR_IOASC_IR_RESOURCE_HANDLE            0x05250000
 131#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA         0x05258100
 132#define IPR_IOASA_IR_DUAL_IOA_DISABLED          0x052C8000
 133#define IPR_IOASC_BUS_WAS_RESET                 0x06290000
 134#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER                0x06298000
 135#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST      0x0B5A0000
 136
 137#define IPR_FIRST_DRIVER_IOASC                  0x10000000
 138#define IPR_IOASC_IOA_WAS_RESET                 0x10000001
 139#define IPR_IOASC_PCI_ACCESS_ERROR                      0x10000002
 140
 141/* Driver data flags */
 142#define IPR_USE_LONG_TRANSOP_TIMEOUT            0x00000001
 143#define IPR_USE_PCI_WARM_RESET                  0x00000002
 144
 145#define IPR_DEFAULT_MAX_ERROR_DUMP                      984
 146#define IPR_NUM_LOG_HCAMS                               2
 147#define IPR_NUM_CFG_CHG_HCAMS                           2
 148#define IPR_NUM_HCAMS   (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
 149
 150#define IPR_MAX_SIS64_TARGETS_PER_BUS                   1024
 151#define IPR_MAX_SIS64_LUNS_PER_TARGET                   0xffffffff
 152
 153#define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 154#define IPR_MAX_NUM_LUNS_PER_TARGET                     256
 155#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET        8
 156#define IPR_VSET_BUS                                    0xff
 157#define IPR_IOA_BUS                                             0xff
 158#define IPR_IOA_TARGET                                  0xff
 159#define IPR_IOA_LUN                                             0xff
 160#define IPR_MAX_NUM_BUSES                               16
 161#define IPR_MAX_BUS_TO_SCAN                             IPR_MAX_NUM_BUSES
 162
 163#define IPR_NUM_RESET_RELOAD_RETRIES            3
 164
 165/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
 166#define IPR_NUM_INTERNAL_CMD_BLKS       (IPR_NUM_HCAMS + \
 167                                     ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 168
 169#define IPR_MAX_COMMANDS                100
 170#define IPR_NUM_CMD_BLKS                (IPR_NUM_BASE_CMD_BLKS + \
 171                                                IPR_NUM_INTERNAL_CMD_BLKS)
 172
 173#define IPR_MAX_PHYSICAL_DEVS                           192
 174#define IPR_DEFAULT_SIS64_DEVS                          1024
 175#define IPR_MAX_SIS64_DEVS                              4096
 176
 177#define IPR_MAX_SGLIST                                  64
 178#define IPR_IOA_MAX_SECTORS                             32767
 179#define IPR_VSET_MAX_SECTORS                            512
 180#define IPR_MAX_CDB_LEN                                 16
 181#define IPR_MAX_HRRQ_RETRIES                            3
 182
 183#define IPR_DEFAULT_BUS_WIDTH                           16
 184#define IPR_80MBs_SCSI_RATE             ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 185#define IPR_U160_SCSI_RATE      ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 186#define IPR_U320_SCSI_RATE      ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 187#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
 188
 189#define IPR_IOA_RES_HANDLE                              0xffffffff
 190#define IPR_INVALID_RES_HANDLE                  0
 191#define IPR_IOA_RES_ADDR                                0x00ffffff
 192
 193/*
 194 * Adapter Commands
 195 */
 196#define IPR_QUERY_RSRC_STATE                            0xC2
 197#define IPR_RESET_DEVICE                                0xC3
 198#define IPR_RESET_TYPE_SELECT                           0x80
 199#define IPR_LUN_RESET                                   0x40
 200#define IPR_TARGET_RESET                                        0x20
 201#define IPR_BUS_RESET                                   0x10
 202#define IPR_ATA_PHY_RESET                                       0x80
 203#define IPR_ID_HOST_RR_Q                                0xC4
 204#define IPR_QUERY_IOA_CONFIG                            0xC5
 205#define IPR_CANCEL_ALL_REQUESTS                 0xCE
 206#define IPR_HOST_CONTROLLED_ASYNC                       0xCF
 207#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE      0x01
 208#define IPR_HCAM_CDB_OP_CODE_LOG_DATA           0x02
 209#define IPR_SET_SUPPORTED_DEVICES                       0xFB
 210#define IPR_SET_ALL_SUPPORTED_DEVICES                   0x80
 211#define IPR_IOA_SHUTDOWN                                0xF7
 212#define IPR_WR_BUF_DOWNLOAD_AND_SAVE                    0x05
 213
 214/*
 215 * Timeouts
 216 */
 217#define IPR_SHUTDOWN_TIMEOUT                    (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
 218#define IPR_VSET_RW_TIMEOUT                     (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
 219#define IPR_ABBREV_SHUTDOWN_TIMEOUT             (10 * HZ)
 220#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO   (2 * 60 * HZ)
 221#define IPR_DEVICE_RESET_TIMEOUT                (ipr_fastfail ? 10 * HZ : 30 * HZ)
 222#define IPR_CANCEL_ALL_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 223#define IPR_ABORT_TASK_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 224#define IPR_INTERNAL_TIMEOUT                    (ipr_fastfail ? 10 * HZ : 30 * HZ)
 225#define IPR_WRITE_BUFFER_TIMEOUT                (30 * 60 * HZ)
 226#define IPR_SET_SUP_DEVICE_TIMEOUT              (2 * 60 * HZ)
 227#define IPR_REQUEST_SENSE_TIMEOUT               (10 * HZ)
 228#define IPR_OPERATIONAL_TIMEOUT         (5 * 60)
 229#define IPR_LONG_OPERATIONAL_TIMEOUT    (12 * 60)
 230#define IPR_WAIT_FOR_RESET_TIMEOUT              (2 * HZ)
 231#define IPR_CHECK_FOR_RESET_TIMEOUT             (HZ / 10)
 232#define IPR_WAIT_FOR_BIST_TIMEOUT               (2 * HZ)
 233#define IPR_PCI_RESET_TIMEOUT                   (HZ / 2)
 234#define IPR_SIS32_DUMP_TIMEOUT                  (15 * HZ)
 235#define IPR_SIS64_DUMP_TIMEOUT                  (40 * HZ)
 236#define IPR_DUMP_DELAY_SECONDS                  4
 237#define IPR_DUMP_DELAY_TIMEOUT                  (IPR_DUMP_DELAY_SECONDS * HZ)
 238
 239/*
 240 * SCSI Literals
 241 */
 242#define IPR_VENDOR_ID_LEN                       8
 243#define IPR_PROD_ID_LEN                         16
 244#define IPR_SERIAL_NUM_LEN                      8
 245
 246/*
 247 * Hardware literals
 248 */
 249#define IPR_FMT2_MBX_ADDR_MASK                          0x0fffffff
 250#define IPR_FMT2_MBX_BAR_SEL_MASK                       0xf0000000
 251#define IPR_FMT2_MKR_BAR_SEL_SHIFT                      28
 252#define IPR_GET_FMT2_BAR_SEL(mbx) \
 253(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
 254#define IPR_SDT_FMT2_BAR0_SEL                           0x0
 255#define IPR_SDT_FMT2_BAR1_SEL                           0x1
 256#define IPR_SDT_FMT2_BAR2_SEL                           0x2
 257#define IPR_SDT_FMT2_BAR3_SEL                           0x3
 258#define IPR_SDT_FMT2_BAR4_SEL                           0x4
 259#define IPR_SDT_FMT2_BAR5_SEL                           0x5
 260#define IPR_SDT_FMT2_EXP_ROM_SEL                        0x8
 261#define IPR_FMT2_SDT_READY_TO_USE                       0xC4D4E3F2
 262#define IPR_FMT3_SDT_READY_TO_USE                       0xC4D4E3F3
 263#define IPR_DOORBELL                                    0x82800000
 264#define IPR_RUNTIME_RESET                               0x40000000
 265
 266#define IPR_IPL_INIT_MIN_STAGE_TIME                     5
 267#define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 15
 268#define IPR_IPL_INIT_STAGE_UNKNOWN                      0x0
 269#define IPR_IPL_INIT_STAGE_TRANSOP                      0xB0000000
 270#define IPR_IPL_INIT_STAGE_MASK                         0xff000000
 271#define IPR_IPL_INIT_STAGE_TIME_MASK                    0x0000ffff
 272#define IPR_PCII_IPL_STAGE_CHANGE                       (0x80000000 >> 0)
 273
 274#define IPR_PCII_IOA_TRANS_TO_OPER                      (0x80000000 >> 0)
 275#define IPR_PCII_IOARCB_XFER_FAILED                     (0x80000000 >> 3)
 276#define IPR_PCII_IOA_UNIT_CHECKED                       (0x80000000 >> 4)
 277#define IPR_PCII_NO_HOST_RRQ                            (0x80000000 >> 5)
 278#define IPR_PCII_CRITICAL_OPERATION                     (0x80000000 >> 6)
 279#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE           (0x80000000 >> 7)
 280#define IPR_PCII_IOARRIN_LOST                           (0x80000000 >> 27)
 281#define IPR_PCII_MMIO_ERROR                             (0x80000000 >> 28)
 282#define IPR_PCII_PROC_ERR_STATE                 (0x80000000 >> 29)
 283#define IPR_PCII_HRRQ_UPDATED                           (0x80000000 >> 30)
 284#define IPR_PCII_CORE_ISSUED_RST_REQ            (0x80000000 >> 31)
 285
 286#define IPR_PCII_ERROR_INTERRUPTS \
 287(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
 288IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
 289
 290#define IPR_PCII_OPER_INTERRUPTS \
 291(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
 292
 293#define IPR_UPROCI_RESET_ALERT                  (0x80000000 >> 7)
 294#define IPR_UPROCI_IO_DEBUG_ALERT                       (0x80000000 >> 9)
 295#define IPR_UPROCI_SIS64_START_BIST                     (0x80000000 >> 23)
 296
 297#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC            200000  /* 200 ms */
 298#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC           200000  /* 200 ms */
 299
 300/*
 301 * Dump literals
 302 */
 303#define IPR_FMT2_MAX_IOA_DUMP_SIZE                      (4 * 1024 * 1024)
 304#define IPR_FMT3_MAX_IOA_DUMP_SIZE                      (32 * 1024 * 1024)
 305#define IPR_FMT2_NUM_SDT_ENTRIES                        511
 306#define IPR_FMT3_NUM_SDT_ENTRIES                        0xFFF
 307#define IPR_FMT2_MAX_NUM_DUMP_PAGES     ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 308#define IPR_FMT3_MAX_NUM_DUMP_PAGES     ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 309
 310/*
 311 * Misc literals
 312 */
 313#define IPR_NUM_IOADL_ENTRIES                   IPR_MAX_SGLIST
 314#define IPR_MAX_MSIX_VECTORS            0x5
 315#define IPR_MAX_HRRQ_NUM                0x10
 316#define IPR_INIT_HRRQ                   0x0
 317
 318/*
 319 * Adapter interface types
 320 */
 321
 322struct ipr_res_addr {
 323        u8 reserved;
 324        u8 bus;
 325        u8 target;
 326        u8 lun;
 327#define IPR_GET_PHYS_LOC(res_addr) \
 328        (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
 329}__attribute__((packed, aligned (4)));
 330
 331struct ipr_std_inq_vpids {
 332        u8 vendor_id[IPR_VENDOR_ID_LEN];
 333        u8 product_id[IPR_PROD_ID_LEN];
 334}__attribute__((packed));
 335
 336struct ipr_vpd {
 337        struct ipr_std_inq_vpids vpids;
 338        u8 sn[IPR_SERIAL_NUM_LEN];
 339}__attribute__((packed));
 340
 341struct ipr_ext_vpd {
 342        struct ipr_vpd vpd;
 343        __be32 wwid[2];
 344}__attribute__((packed));
 345
 346struct ipr_ext_vpd64 {
 347        struct ipr_vpd vpd;
 348        __be32 wwid[4];
 349}__attribute__((packed));
 350
 351struct ipr_std_inq_data {
 352        u8 peri_qual_dev_type;
 353#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
 354#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
 355
 356        u8 removeable_medium_rsvd;
 357#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
 358
 359#define IPR_IS_DASD_DEVICE(std_inq) \
 360((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
 361!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
 362
 363#define IPR_IS_SES_DEVICE(std_inq) \
 364(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
 365
 366        u8 version;
 367        u8 aen_naca_fmt;
 368        u8 additional_len;
 369        u8 sccs_rsvd;
 370        u8 bq_enc_multi;
 371        u8 sync_cmdq_flags;
 372
 373        struct ipr_std_inq_vpids vpids;
 374
 375        u8 ros_rsvd_ram_rsvd[4];
 376
 377        u8 serial_num[IPR_SERIAL_NUM_LEN];
 378}__attribute__ ((packed));
 379
 380#define IPR_RES_TYPE_AF_DASD            0x00
 381#define IPR_RES_TYPE_GENERIC_SCSI       0x01
 382#define IPR_RES_TYPE_VOLUME_SET         0x02
 383#define IPR_RES_TYPE_REMOTE_AF_DASD     0x03
 384#define IPR_RES_TYPE_GENERIC_ATA        0x04
 385#define IPR_RES_TYPE_ARRAY              0x05
 386#define IPR_RES_TYPE_IOAFP              0xff
 387
 388struct ipr_config_table_entry {
 389        u8 proto;
 390#define IPR_PROTO_SATA                  0x02
 391#define IPR_PROTO_SATA_ATAPI            0x03
 392#define IPR_PROTO_SAS_STP               0x06
 393#define IPR_PROTO_SAS_STP_ATAPI         0x07
 394        u8 array_id;
 395        u8 flags;
 396#define IPR_IS_IOA_RESOURCE             0x80
 397        u8 rsvd_subtype;
 398
 399#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
 400#define IPR_QUEUE_FROZEN_MODEL          0
 401#define IPR_QUEUE_NACA_MODEL            1
 402
 403        struct ipr_res_addr res_addr;
 404        __be32 res_handle;
 405        __be32 lun_wwn[2];
 406        struct ipr_std_inq_data std_inq_data;
 407}__attribute__ ((packed, aligned (4)));
 408
 409struct ipr_config_table_entry64 {
 410        u8 res_type;
 411        u8 proto;
 412        u8 vset_num;
 413        u8 array_id;
 414        __be16 flags;
 415        __be16 res_flags;
 416#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
 417        __be32 res_handle;
 418        u8 dev_id_type;
 419        u8 reserved[3];
 420        __be64 dev_id;
 421        __be64 lun;
 422        __be64 lun_wwn[2];
 423#define IPR_MAX_RES_PATH_LENGTH         48
 424        __be64 res_path;
 425        struct ipr_std_inq_data std_inq_data;
 426        u8 reserved2[4];
 427        __be64 reserved3[2];
 428        u8 reserved4[8];
 429}__attribute__ ((packed, aligned (8)));
 430
 431struct ipr_config_table_hdr {
 432        u8 num_entries;
 433        u8 flags;
 434#define IPR_UCODE_DOWNLOAD_REQ  0x10
 435        __be16 reserved;
 436}__attribute__((packed, aligned (4)));
 437
 438struct ipr_config_table_hdr64 {
 439        __be16 num_entries;
 440        __be16 reserved;
 441        u8 flags;
 442        u8 reserved2[11];
 443}__attribute__((packed, aligned (4)));
 444
 445struct ipr_config_table {
 446        struct ipr_config_table_hdr hdr;
 447        struct ipr_config_table_entry dev[0];
 448}__attribute__((packed, aligned (4)));
 449
 450struct ipr_config_table64 {
 451        struct ipr_config_table_hdr64 hdr64;
 452        struct ipr_config_table_entry64 dev[0];
 453}__attribute__((packed, aligned (8)));
 454
 455struct ipr_config_table_entry_wrapper {
 456        union {
 457                struct ipr_config_table_entry *cfgte;
 458                struct ipr_config_table_entry64 *cfgte64;
 459        } u;
 460};
 461
 462struct ipr_hostrcb_cfg_ch_not {
 463        union {
 464                struct ipr_config_table_entry cfgte;
 465                struct ipr_config_table_entry64 cfgte64;
 466        } u;
 467        u8 reserved[936];
 468}__attribute__((packed, aligned (4)));
 469
 470struct ipr_supported_device {
 471        __be16 data_length;
 472        u8 reserved;
 473        u8 num_records;
 474        struct ipr_std_inq_vpids vpids;
 475        u8 reserved2[16];
 476}__attribute__((packed, aligned (4)));
 477
 478struct ipr_hrr_queue {
 479        struct ipr_ioa_cfg *ioa_cfg;
 480        __be32 *host_rrq;
 481        dma_addr_t host_rrq_dma;
 482#define IPR_HRRQ_REQ_RESP_HANDLE_MASK   0xfffffffc
 483#define IPR_HRRQ_RESP_BIT_SET           0x00000002
 484#define IPR_HRRQ_TOGGLE_BIT             0x00000001
 485#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT  2
 486#define IPR_ID_HRRQ_SELE_ENABLE         0x02
 487        volatile __be32 *hrrq_start;
 488        volatile __be32 *hrrq_end;
 489        volatile __be32 *hrrq_curr;
 490
 491        struct list_head hrrq_free_q;
 492        struct list_head hrrq_pending_q;
 493        spinlock_t _lock;
 494        spinlock_t *lock;
 495
 496        volatile u32 toggle_bit;
 497        u32 size;
 498        u32 min_cmd_id;
 499        u32 max_cmd_id;
 500        u8 allow_interrupts:1;
 501        u8 ioa_is_dead:1;
 502        u8 allow_cmds:1;
 503        u8 removing_ioa:1;
 504
 505        struct blk_iopoll iopoll;
 506};
 507
 508/* Command packet structure */
 509struct ipr_cmd_pkt {
 510        u8 reserved;            /* Reserved by IOA */
 511        u8 hrrq_id;
 512        u8 request_type;
 513#define IPR_RQTYPE_SCSICDB              0x00
 514#define IPR_RQTYPE_IOACMD               0x01
 515#define IPR_RQTYPE_HCAM                 0x02
 516#define IPR_RQTYPE_ATA_PASSTHRU 0x04
 517
 518        u8 reserved2;
 519
 520        u8 flags_hi;
 521#define IPR_FLAGS_HI_WRITE_NOT_READ             0x80
 522#define IPR_FLAGS_HI_NO_ULEN_CHK                0x20
 523#define IPR_FLAGS_HI_SYNC_OVERRIDE              0x10
 524#define IPR_FLAGS_HI_SYNC_COMPLETE              0x08
 525#define IPR_FLAGS_HI_NO_LINK_DESC               0x04
 526
 527        u8 flags_lo;
 528#define IPR_FLAGS_LO_ALIGNED_BFR                0x20
 529#define IPR_FLAGS_LO_DELAY_AFTER_RST            0x10
 530#define IPR_FLAGS_LO_UNTAGGED_TASK              0x00
 531#define IPR_FLAGS_LO_SIMPLE_TASK                0x02
 532#define IPR_FLAGS_LO_ORDERED_TASK               0x04
 533#define IPR_FLAGS_LO_HEAD_OF_Q_TASK             0x06
 534#define IPR_FLAGS_LO_ACA_TASK                   0x08
 535
 536        u8 cdb[16];
 537        __be16 timeout;
 538}__attribute__ ((packed, aligned(4)));
 539
 540struct ipr_ioarcb_ata_regs {    /* 22 bytes */
 541        u8 flags;
 542#define IPR_ATA_FLAG_PACKET_CMD                 0x80
 543#define IPR_ATA_FLAG_XFER_TYPE_DMA                      0x40
 544#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION  0x20
 545        u8 reserved[3];
 546
 547        __be16 data;
 548        u8 feature;
 549        u8 nsect;
 550        u8 lbal;
 551        u8 lbam;
 552        u8 lbah;
 553        u8 device;
 554        u8 command;
 555        u8 reserved2[3];
 556        u8 hob_feature;
 557        u8 hob_nsect;
 558        u8 hob_lbal;
 559        u8 hob_lbam;
 560        u8 hob_lbah;
 561        u8 ctl;
 562}__attribute__ ((packed, aligned(2)));
 563
 564struct ipr_ioadl_desc {
 565        __be32 flags_and_data_len;
 566#define IPR_IOADL_FLAGS_MASK            0xff000000
 567#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
 568#define IPR_IOADL_DATA_LEN_MASK         0x00ffffff
 569#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
 570#define IPR_IOADL_FLAGS_READ            0x48000000
 571#define IPR_IOADL_FLAGS_READ_LAST       0x49000000
 572#define IPR_IOADL_FLAGS_WRITE           0x68000000
 573#define IPR_IOADL_FLAGS_WRITE_LAST      0x69000000
 574#define IPR_IOADL_FLAGS_LAST            0x01000000
 575
 576        __be32 address;
 577}__attribute__((packed, aligned (8)));
 578
 579struct ipr_ioadl64_desc {
 580        __be32 flags;
 581        __be32 data_len;
 582        __be64 address;
 583}__attribute__((packed, aligned (16)));
 584
 585struct ipr_ata64_ioadl {
 586        struct ipr_ioarcb_ata_regs regs;
 587        u16 reserved[5];
 588        struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
 589}__attribute__((packed, aligned (16)));
 590
 591struct ipr_ioarcb_add_data {
 592        union {
 593                struct ipr_ioarcb_ata_regs regs;
 594                struct ipr_ioadl_desc ioadl[5];
 595                __be32 add_cmd_parms[10];
 596        } u;
 597}__attribute__ ((packed, aligned (4)));
 598
 599struct ipr_ioarcb_sis64_add_addr_ecb {
 600        __be64 ioasa_host_pci_addr;
 601        __be64 data_ioadl_addr;
 602        __be64 reserved;
 603        __be32 ext_control_buf[4];
 604}__attribute__((packed, aligned (8)));
 605
 606/* IOA Request Control Block    128 bytes  */
 607struct ipr_ioarcb {
 608        union {
 609                __be32 ioarcb_host_pci_addr;
 610                __be64 ioarcb_host_pci_addr64;
 611        } a;
 612        __be32 res_handle;
 613        __be32 host_response_handle;
 614        __be32 reserved1;
 615        __be32 reserved2;
 616        __be32 reserved3;
 617
 618        __be32 data_transfer_length;
 619        __be32 read_data_transfer_length;
 620        __be32 write_ioadl_addr;
 621        __be32 ioadl_len;
 622        __be32 read_ioadl_addr;
 623        __be32 read_ioadl_len;
 624
 625        __be32 ioasa_host_pci_addr;
 626        __be16 ioasa_len;
 627        __be16 reserved4;
 628
 629        struct ipr_cmd_pkt cmd_pkt;
 630
 631        __be16 add_cmd_parms_offset;
 632        __be16 add_cmd_parms_len;
 633
 634        union {
 635                struct ipr_ioarcb_add_data add_data;
 636                struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
 637        } u;
 638
 639}__attribute__((packed, aligned (4)));
 640
 641struct ipr_ioasa_vset {
 642        __be32 failing_lba_hi;
 643        __be32 failing_lba_lo;
 644        __be32 reserved;
 645}__attribute__((packed, aligned (4)));
 646
 647struct ipr_ioasa_af_dasd {
 648        __be32 failing_lba;
 649        __be32 reserved[2];
 650}__attribute__((packed, aligned (4)));
 651
 652struct ipr_ioasa_gpdd {
 653        u8 end_state;
 654        u8 bus_phase;
 655        __be16 reserved;
 656        __be32 ioa_data[2];
 657}__attribute__((packed, aligned (4)));
 658
 659struct ipr_ioasa_gata {
 660        u8 error;
 661        u8 nsect;               /* Interrupt reason */
 662        u8 lbal;
 663        u8 lbam;
 664        u8 lbah;
 665        u8 device;
 666        u8 status;
 667        u8 alt_status;  /* ATA CTL */
 668        u8 hob_nsect;
 669        u8 hob_lbal;
 670        u8 hob_lbam;
 671        u8 hob_lbah;
 672}__attribute__((packed, aligned (4)));
 673
 674struct ipr_auto_sense {
 675        __be16 auto_sense_len;
 676        __be16 ioa_data_len;
 677        __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
 678};
 679
 680struct ipr_ioasa_hdr {
 681        __be32 ioasc;
 682#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
 683#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
 684#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
 685#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
 686
 687        __be16 ret_stat_len;    /* Length of the returned IOASA */
 688
 689        __be16 avail_stat_len;  /* Total Length of status available. */
 690
 691        __be32 residual_data_len;       /* number of bytes in the host data */
 692        /* buffers that were not used by the IOARCB command. */
 693
 694        __be32 ilid;
 695#define IPR_NO_ILID                     0
 696#define IPR_DRIVER_ILID         0xffffffff
 697
 698        __be32 fd_ioasc;
 699
 700        __be32 fd_phys_locator;
 701
 702        __be32 fd_res_handle;
 703
 704        __be32 ioasc_specific;  /* status code specific field */
 705#define IPR_ADDITIONAL_STATUS_FMT               0x80000000
 706#define IPR_AUTOSENSE_VALID                     0x40000000
 707#define IPR_ATA_DEVICE_WAS_RESET                0x20000000
 708#define IPR_IOASC_SPECIFIC_MASK         0x00ffffff
 709#define IPR_FIELD_POINTER_VALID         (0x80000000 >> 8)
 710#define IPR_FIELD_POINTER_MASK          0x0000ffff
 711
 712}__attribute__((packed, aligned (4)));
 713
 714struct ipr_ioasa {
 715        struct ipr_ioasa_hdr hdr;
 716
 717        union {
 718                struct ipr_ioasa_vset vset;
 719                struct ipr_ioasa_af_dasd dasd;
 720                struct ipr_ioasa_gpdd gpdd;
 721                struct ipr_ioasa_gata gata;
 722        } u;
 723
 724        struct ipr_auto_sense auto_sense;
 725}__attribute__((packed, aligned (4)));
 726
 727struct ipr_ioasa64 {
 728        struct ipr_ioasa_hdr hdr;
 729        u8 fd_res_path[8];
 730
 731        union {
 732                struct ipr_ioasa_vset vset;
 733                struct ipr_ioasa_af_dasd dasd;
 734                struct ipr_ioasa_gpdd gpdd;
 735                struct ipr_ioasa_gata gata;
 736        } u;
 737
 738        struct ipr_auto_sense auto_sense;
 739}__attribute__((packed, aligned (4)));
 740
 741struct ipr_mode_parm_hdr {
 742        u8 length;
 743        u8 medium_type;
 744        u8 device_spec_parms;
 745        u8 block_desc_len;
 746}__attribute__((packed));
 747
 748struct ipr_mode_pages {
 749        struct ipr_mode_parm_hdr hdr;
 750        u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
 751}__attribute__((packed));
 752
 753struct ipr_mode_page_hdr {
 754        u8 ps_page_code;
 755#define IPR_MODE_PAGE_PS        0x80
 756#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
 757        u8 page_length;
 758}__attribute__ ((packed));
 759
 760struct ipr_dev_bus_entry {
 761        struct ipr_res_addr res_addr;
 762        u8 flags;
 763#define IPR_SCSI_ATTR_ENABLE_QAS                        0x80
 764#define IPR_SCSI_ATTR_DISABLE_QAS                       0x40
 765#define IPR_SCSI_ATTR_QAS_MASK                          0xC0
 766#define IPR_SCSI_ATTR_ENABLE_TM                         0x20
 767#define IPR_SCSI_ATTR_NO_TERM_PWR                       0x10
 768#define IPR_SCSI_ATTR_TM_SUPPORTED                      0x08
 769#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED     0x04
 770
 771        u8 scsi_id;
 772        u8 bus_width;
 773        u8 extended_reset_delay;
 774#define IPR_EXTENDED_RESET_DELAY        7
 775
 776        __be32 max_xfer_rate;
 777
 778        u8 spinup_delay;
 779        u8 reserved3;
 780        __be16 reserved4;
 781}__attribute__((packed, aligned (4)));
 782
 783struct ipr_mode_page28 {
 784        struct ipr_mode_page_hdr hdr;
 785        u8 num_entries;
 786        u8 entry_length;
 787        struct ipr_dev_bus_entry bus[0];
 788}__attribute__((packed));
 789
 790struct ipr_mode_page24 {
 791        struct ipr_mode_page_hdr hdr;
 792        u8 flags;
 793#define IPR_ENABLE_DUAL_IOA_AF 0x80
 794}__attribute__((packed));
 795
 796struct ipr_ioa_vpd {
 797        struct ipr_std_inq_data std_inq_data;
 798        u8 ascii_part_num[12];
 799        u8 reserved[40];
 800        u8 ascii_plant_code[4];
 801}__attribute__((packed));
 802
 803struct ipr_inquiry_page3 {
 804        u8 peri_qual_dev_type;
 805        u8 page_code;
 806        u8 reserved1;
 807        u8 page_length;
 808        u8 ascii_len;
 809        u8 reserved2[3];
 810        u8 load_id[4];
 811        u8 major_release;
 812        u8 card_type;
 813        u8 minor_release[2];
 814        u8 ptf_number[4];
 815        u8 patch_number[4];
 816}__attribute__((packed));
 817
 818struct ipr_inquiry_cap {
 819        u8 peri_qual_dev_type;
 820        u8 page_code;
 821        u8 reserved1;
 822        u8 page_length;
 823        u8 ascii_len;
 824        u8 reserved2;
 825        u8 sis_version[2];
 826        u8 cap;
 827#define IPR_CAP_DUAL_IOA_RAID           0x80
 828        u8 reserved3[15];
 829}__attribute__((packed));
 830
 831#define IPR_INQUIRY_PAGE0_ENTRIES 20
 832struct ipr_inquiry_page0 {
 833        u8 peri_qual_dev_type;
 834        u8 page_code;
 835        u8 reserved1;
 836        u8 len;
 837        u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
 838}__attribute__((packed));
 839
 840struct ipr_hostrcb_device_data_entry {
 841        struct ipr_vpd vpd;
 842        struct ipr_res_addr dev_res_addr;
 843        struct ipr_vpd new_vpd;
 844        struct ipr_vpd ioa_last_with_dev_vpd;
 845        struct ipr_vpd cfc_last_with_dev_vpd;
 846        __be32 ioa_data[5];
 847}__attribute__((packed, aligned (4)));
 848
 849struct ipr_hostrcb_device_data_entry_enhanced {
 850        struct ipr_ext_vpd vpd;
 851        u8 ccin[4];
 852        struct ipr_res_addr dev_res_addr;
 853        struct ipr_ext_vpd new_vpd;
 854        u8 new_ccin[4];
 855        struct ipr_ext_vpd ioa_last_with_dev_vpd;
 856        struct ipr_ext_vpd cfc_last_with_dev_vpd;
 857}__attribute__((packed, aligned (4)));
 858
 859struct ipr_hostrcb64_device_data_entry_enhanced {
 860        struct ipr_ext_vpd vpd;
 861        u8 ccin[4];
 862        u8 res_path[8];
 863        struct ipr_ext_vpd new_vpd;
 864        u8 new_ccin[4];
 865        struct ipr_ext_vpd ioa_last_with_dev_vpd;
 866        struct ipr_ext_vpd cfc_last_with_dev_vpd;
 867}__attribute__((packed, aligned (4)));
 868
 869struct ipr_hostrcb_array_data_entry {
 870        struct ipr_vpd vpd;
 871        struct ipr_res_addr expected_dev_res_addr;
 872        struct ipr_res_addr dev_res_addr;
 873}__attribute__((packed, aligned (4)));
 874
 875struct ipr_hostrcb64_array_data_entry {
 876        struct ipr_ext_vpd vpd;
 877        u8 ccin[4];
 878        u8 expected_res_path[8];
 879        u8 res_path[8];
 880}__attribute__((packed, aligned (4)));
 881
 882struct ipr_hostrcb_array_data_entry_enhanced {
 883        struct ipr_ext_vpd vpd;
 884        u8 ccin[4];
 885        struct ipr_res_addr expected_dev_res_addr;
 886        struct ipr_res_addr dev_res_addr;
 887}__attribute__((packed, aligned (4)));
 888
 889struct ipr_hostrcb_type_ff_error {
 890        __be32 ioa_data[758];
 891}__attribute__((packed, aligned (4)));
 892
 893struct ipr_hostrcb_type_01_error {
 894        __be32 seek_counter;
 895        __be32 read_counter;
 896        u8 sense_data[32];
 897        __be32 ioa_data[236];
 898}__attribute__((packed, aligned (4)));
 899
 900struct ipr_hostrcb_type_02_error {
 901        struct ipr_vpd ioa_vpd;
 902        struct ipr_vpd cfc_vpd;
 903        struct ipr_vpd ioa_last_attached_to_cfc_vpd;
 904        struct ipr_vpd cfc_last_attached_to_ioa_vpd;
 905        __be32 ioa_data[3];
 906}__attribute__((packed, aligned (4)));
 907
 908struct ipr_hostrcb_type_12_error {
 909        struct ipr_ext_vpd ioa_vpd;
 910        struct ipr_ext_vpd cfc_vpd;
 911        struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
 912        struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
 913        __be32 ioa_data[3];
 914}__attribute__((packed, aligned (4)));
 915
 916struct ipr_hostrcb_type_03_error {
 917        struct ipr_vpd ioa_vpd;
 918        struct ipr_vpd cfc_vpd;
 919        __be32 errors_detected;
 920        __be32 errors_logged;
 921        u8 ioa_data[12];
 922        struct ipr_hostrcb_device_data_entry dev[3];
 923}__attribute__((packed, aligned (4)));
 924
 925struct ipr_hostrcb_type_13_error {
 926        struct ipr_ext_vpd ioa_vpd;
 927        struct ipr_ext_vpd cfc_vpd;
 928        __be32 errors_detected;
 929        __be32 errors_logged;
 930        struct ipr_hostrcb_device_data_entry_enhanced dev[3];
 931}__attribute__((packed, aligned (4)));
 932
 933struct ipr_hostrcb_type_23_error {
 934        struct ipr_ext_vpd ioa_vpd;
 935        struct ipr_ext_vpd cfc_vpd;
 936        __be32 errors_detected;
 937        __be32 errors_logged;
 938        struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
 939}__attribute__((packed, aligned (4)));
 940
 941struct ipr_hostrcb_type_04_error {
 942        struct ipr_vpd ioa_vpd;
 943        struct ipr_vpd cfc_vpd;
 944        u8 ioa_data[12];
 945        struct ipr_hostrcb_array_data_entry array_member[10];
 946        __be32 exposed_mode_adn;
 947        __be32 array_id;
 948        struct ipr_vpd incomp_dev_vpd;
 949        __be32 ioa_data2;
 950        struct ipr_hostrcb_array_data_entry array_member2[8];
 951        struct ipr_res_addr last_func_vset_res_addr;
 952        u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 953        u8 protection_level[8];
 954}__attribute__((packed, aligned (4)));
 955
 956struct ipr_hostrcb_type_14_error {
 957        struct ipr_ext_vpd ioa_vpd;
 958        struct ipr_ext_vpd cfc_vpd;
 959        __be32 exposed_mode_adn;
 960        __be32 array_id;
 961        struct ipr_res_addr last_func_vset_res_addr;
 962        u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 963        u8 protection_level[8];
 964        __be32 num_entries;
 965        struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
 966}__attribute__((packed, aligned (4)));
 967
 968struct ipr_hostrcb_type_24_error {
 969        struct ipr_ext_vpd ioa_vpd;
 970        struct ipr_ext_vpd cfc_vpd;
 971        u8 reserved[2];
 972        u8 exposed_mode_adn;
 973#define IPR_INVALID_ARRAY_DEV_NUM               0xff
 974        u8 array_id;
 975        u8 last_res_path[8];
 976        u8 protection_level[8];
 977        struct ipr_ext_vpd64 array_vpd;
 978        u8 description[16];
 979        u8 reserved2[3];
 980        u8 num_entries;
 981        struct ipr_hostrcb64_array_data_entry array_member[32];
 982}__attribute__((packed, aligned (4)));
 983
 984struct ipr_hostrcb_type_07_error {
 985        u8 failure_reason[64];
 986        struct ipr_vpd vpd;
 987        u32 data[222];
 988}__attribute__((packed, aligned (4)));
 989
 990struct ipr_hostrcb_type_17_error {
 991        u8 failure_reason[64];
 992        struct ipr_ext_vpd vpd;
 993        u32 data[476];
 994}__attribute__((packed, aligned (4)));
 995
 996struct ipr_hostrcb_config_element {
 997        u8 type_status;
 998#define IPR_PATH_CFG_TYPE_MASK  0xF0
 999#define IPR_PATH_CFG_NOT_EXIST  0x00
1000#define IPR_PATH_CFG_IOA_PORT           0x10
1001#define IPR_PATH_CFG_EXP_PORT           0x20
1002#define IPR_PATH_CFG_DEVICE_PORT        0x30
1003#define IPR_PATH_CFG_DEVICE_LUN 0x40
1004
1005#define IPR_PATH_CFG_STATUS_MASK        0x0F
1006#define IPR_PATH_CFG_NO_PROB            0x00
1007#define IPR_PATH_CFG_DEGRADED           0x01
1008#define IPR_PATH_CFG_FAILED             0x02
1009#define IPR_PATH_CFG_SUSPECT            0x03
1010#define IPR_PATH_NOT_DETECTED           0x04
1011#define IPR_PATH_INCORRECT_CONN 0x05
1012
1013        u8 cascaded_expander;
1014        u8 phy;
1015        u8 link_rate;
1016#define IPR_PHY_LINK_RATE_MASK  0x0F
1017
1018        __be32 wwid[2];
1019}__attribute__((packed, aligned (4)));
1020
1021struct ipr_hostrcb64_config_element {
1022        __be16 length;
1023        u8 descriptor_id;
1024#define IPR_DESCRIPTOR_MASK             0xC0
1025#define IPR_DESCRIPTOR_SIS64            0x00
1026
1027        u8 reserved;
1028        u8 type_status;
1029
1030        u8 reserved2[2];
1031        u8 link_rate;
1032
1033        u8 res_path[8];
1034        __be32 wwid[2];
1035}__attribute__((packed, aligned (8)));
1036
1037struct ipr_hostrcb_fabric_desc {
1038        __be16 length;
1039        u8 ioa_port;
1040        u8 cascaded_expander;
1041        u8 phy;
1042        u8 path_state;
1043#define IPR_PATH_ACTIVE_MASK            0xC0
1044#define IPR_PATH_NO_INFO                0x00
1045#define IPR_PATH_ACTIVE                 0x40
1046#define IPR_PATH_NOT_ACTIVE             0x80
1047
1048#define IPR_PATH_STATE_MASK             0x0F
1049#define IPR_PATH_STATE_NO_INFO  0x00
1050#define IPR_PATH_HEALTHY                0x01
1051#define IPR_PATH_DEGRADED               0x02
1052#define IPR_PATH_FAILED                 0x03
1053
1054        __be16 num_entries;
1055        struct ipr_hostrcb_config_element elem[1];
1056}__attribute__((packed, aligned (4)));
1057
1058struct ipr_hostrcb64_fabric_desc {
1059        __be16 length;
1060        u8 descriptor_id;
1061
1062        u8 reserved[2];
1063        u8 path_state;
1064
1065        u8 reserved2[2];
1066        u8 res_path[8];
1067        u8 reserved3[6];
1068        __be16 num_entries;
1069        struct ipr_hostrcb64_config_element elem[1];
1070}__attribute__((packed, aligned (8)));
1071
1072#define for_each_hrrq(hrrq, ioa_cfg) \
1073                for (hrrq = (ioa_cfg)->hrrq; \
1074                        hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1075
1076#define for_each_fabric_cfg(fabric, cfg) \
1077                for (cfg = (fabric)->elem; \
1078                        cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1079                        cfg++)
1080
1081struct ipr_hostrcb_type_20_error {
1082        u8 failure_reason[64];
1083        u8 reserved[3];
1084        u8 num_entries;
1085        struct ipr_hostrcb_fabric_desc desc[1];
1086}__attribute__((packed, aligned (4)));
1087
1088struct ipr_hostrcb_type_30_error {
1089        u8 failure_reason[64];
1090        u8 reserved[3];
1091        u8 num_entries;
1092        struct ipr_hostrcb64_fabric_desc desc[1];
1093}__attribute__((packed, aligned (4)));
1094
1095struct ipr_hostrcb_error {
1096        __be32 fd_ioasc;
1097        struct ipr_res_addr fd_res_addr;
1098        __be32 fd_res_handle;
1099        __be32 prc;
1100        union {
1101                struct ipr_hostrcb_type_ff_error type_ff_error;
1102                struct ipr_hostrcb_type_01_error type_01_error;
1103                struct ipr_hostrcb_type_02_error type_02_error;
1104                struct ipr_hostrcb_type_03_error type_03_error;
1105                struct ipr_hostrcb_type_04_error type_04_error;
1106                struct ipr_hostrcb_type_07_error type_07_error;
1107                struct ipr_hostrcb_type_12_error type_12_error;
1108                struct ipr_hostrcb_type_13_error type_13_error;
1109                struct ipr_hostrcb_type_14_error type_14_error;
1110                struct ipr_hostrcb_type_17_error type_17_error;
1111                struct ipr_hostrcb_type_20_error type_20_error;
1112        } u;
1113}__attribute__((packed, aligned (4)));
1114
1115struct ipr_hostrcb64_error {
1116        __be32 fd_ioasc;
1117        __be32 ioa_fw_level;
1118        __be32 fd_res_handle;
1119        __be32 prc;
1120        __be64 fd_dev_id;
1121        __be64 fd_lun;
1122        u8 fd_res_path[8];
1123        __be64 time_stamp;
1124        u8 reserved[16];
1125        union {
1126                struct ipr_hostrcb_type_ff_error type_ff_error;
1127                struct ipr_hostrcb_type_12_error type_12_error;
1128                struct ipr_hostrcb_type_17_error type_17_error;
1129                struct ipr_hostrcb_type_23_error type_23_error;
1130                struct ipr_hostrcb_type_24_error type_24_error;
1131                struct ipr_hostrcb_type_30_error type_30_error;
1132        } u;
1133}__attribute__((packed, aligned (8)));
1134
1135struct ipr_hostrcb_raw {
1136        __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1137}__attribute__((packed, aligned (4)));
1138
1139struct ipr_hcam {
1140        u8 op_code;
1141#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE                      0xE1
1142#define IPR_HOST_RCB_OP_CODE_LOG_DATA                           0xE2
1143
1144        u8 notify_type;
1145#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED        0x00
1146#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY                       0x01
1147#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY                       0x02
1148#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY         0x10
1149#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY       0x11
1150
1151        u8 notifications_lost;
1152#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST                      0
1153#define IPR_HOST_RCB_NOTIFICATIONS_LOST                         0x80
1154
1155        u8 flags;
1156#define IPR_HOSTRCB_INTERNAL_OPER       0x80
1157#define IPR_HOSTRCB_ERR_RESP_SENT       0x40
1158
1159        u8 overlay_id;
1160#define IPR_HOST_RCB_OVERLAY_ID_1                               0x01
1161#define IPR_HOST_RCB_OVERLAY_ID_2                               0x02
1162#define IPR_HOST_RCB_OVERLAY_ID_3                               0x03
1163#define IPR_HOST_RCB_OVERLAY_ID_4                               0x04
1164#define IPR_HOST_RCB_OVERLAY_ID_6                               0x06
1165#define IPR_HOST_RCB_OVERLAY_ID_7                               0x07
1166#define IPR_HOST_RCB_OVERLAY_ID_12                              0x12
1167#define IPR_HOST_RCB_OVERLAY_ID_13                              0x13
1168#define IPR_HOST_RCB_OVERLAY_ID_14                              0x14
1169#define IPR_HOST_RCB_OVERLAY_ID_16                              0x16
1170#define IPR_HOST_RCB_OVERLAY_ID_17                              0x17
1171#define IPR_HOST_RCB_OVERLAY_ID_20                              0x20
1172#define IPR_HOST_RCB_OVERLAY_ID_23                              0x23
1173#define IPR_HOST_RCB_OVERLAY_ID_24                              0x24
1174#define IPR_HOST_RCB_OVERLAY_ID_26                              0x26
1175#define IPR_HOST_RCB_OVERLAY_ID_30                              0x30
1176#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT                         0xFF
1177
1178        u8 reserved1[3];
1179        __be32 ilid;
1180        __be32 time_since_last_ioa_reset;
1181        __be32 reserved2;
1182        __be32 length;
1183
1184        union {
1185                struct ipr_hostrcb_error error;
1186                struct ipr_hostrcb64_error error64;
1187                struct ipr_hostrcb_cfg_ch_not ccn;
1188                struct ipr_hostrcb_raw raw;
1189        } u;
1190}__attribute__((packed, aligned (4)));
1191
1192struct ipr_hostrcb {
1193        struct ipr_hcam hcam;
1194        dma_addr_t hostrcb_dma;
1195        struct list_head queue;
1196        struct ipr_ioa_cfg *ioa_cfg;
1197        char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1198};
1199
1200/* IPR smart dump table structures */
1201struct ipr_sdt_entry {
1202        __be32 start_token;
1203        __be32 end_token;
1204        u8 reserved[4];
1205
1206        u8 flags;
1207#define IPR_SDT_ENDIAN          0x80
1208#define IPR_SDT_VALID_ENTRY     0x20
1209
1210        u8 resv;
1211        __be16 priority;
1212}__attribute__((packed, aligned (4)));
1213
1214struct ipr_sdt_header {
1215        __be32 state;
1216        __be32 num_entries;
1217        __be32 num_entries_used;
1218        __be32 dump_size;
1219}__attribute__((packed, aligned (4)));
1220
1221struct ipr_sdt {
1222        struct ipr_sdt_header hdr;
1223        struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1224}__attribute__((packed, aligned (4)));
1225
1226struct ipr_uc_sdt {
1227        struct ipr_sdt_header hdr;
1228        struct ipr_sdt_entry entry[1];
1229}__attribute__((packed, aligned (4)));
1230
1231/*
1232 * Driver types
1233 */
1234struct ipr_bus_attributes {
1235        u8 bus;
1236        u8 qas_enabled;
1237        u8 bus_width;
1238        u8 reserved;
1239        u32 max_xfer_rate;
1240};
1241
1242struct ipr_sata_port {
1243        struct ipr_ioa_cfg *ioa_cfg;
1244        struct ata_port *ap;
1245        struct ipr_resource_entry *res;
1246        struct ipr_ioasa_gata ioasa;
1247};
1248
1249struct ipr_resource_entry {
1250        u8 needs_sync_complete:1;
1251        u8 in_erp:1;
1252        u8 add_to_ml:1;
1253        u8 del_from_ml:1;
1254        u8 resetting_device:1;
1255
1256        u32 bus;                /* AKA channel */
1257        u32 target;             /* AKA id */
1258        u32 lun;
1259#define IPR_ARRAY_VIRTUAL_BUS                   0x1
1260#define IPR_VSET_VIRTUAL_BUS                    0x2
1261#define IPR_IOAFP_VIRTUAL_BUS                   0x3
1262
1263#define IPR_GET_RES_PHYS_LOC(res) \
1264        (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1265
1266        u8 ata_class;
1267
1268        u8 flags;
1269        __be16 res_flags;
1270
1271        u8 type;
1272
1273        u8 qmodel;
1274        struct ipr_std_inq_data std_inq_data;
1275
1276        __be32 res_handle;
1277        __be64 dev_id;
1278        __be64 lun_wwn;
1279        struct scsi_lun dev_lun;
1280        u8 res_path[8];
1281
1282        struct ipr_ioa_cfg *ioa_cfg;
1283        struct scsi_device *sdev;
1284        struct ipr_sata_port *sata_port;
1285        struct list_head queue;
1286}; /* struct ipr_resource_entry */
1287
1288struct ipr_resource_hdr {
1289        u16 num_entries;
1290        u16 reserved;
1291};
1292
1293struct ipr_misc_cbs {
1294        struct ipr_ioa_vpd ioa_vpd;
1295        struct ipr_inquiry_page0 page0_data;
1296        struct ipr_inquiry_page3 page3_data;
1297        struct ipr_inquiry_cap cap;
1298        struct ipr_mode_pages mode_pages;
1299        struct ipr_supported_device supp_dev;
1300};
1301
1302struct ipr_interrupt_offsets {
1303        unsigned long set_interrupt_mask_reg;
1304        unsigned long clr_interrupt_mask_reg;
1305        unsigned long clr_interrupt_mask_reg32;
1306        unsigned long sense_interrupt_mask_reg;
1307        unsigned long sense_interrupt_mask_reg32;
1308        unsigned long clr_interrupt_reg;
1309        unsigned long clr_interrupt_reg32;
1310
1311        unsigned long sense_interrupt_reg;
1312        unsigned long sense_interrupt_reg32;
1313        unsigned long ioarrin_reg;
1314        unsigned long sense_uproc_interrupt_reg;
1315        unsigned long sense_uproc_interrupt_reg32;
1316        unsigned long set_uproc_interrupt_reg;
1317        unsigned long set_uproc_interrupt_reg32;
1318        unsigned long clr_uproc_interrupt_reg;
1319        unsigned long clr_uproc_interrupt_reg32;
1320
1321        unsigned long init_feedback_reg;
1322
1323        unsigned long dump_addr_reg;
1324        unsigned long dump_data_reg;
1325
1326#define IPR_ENDIAN_SWAP_KEY             0x00080800
1327        unsigned long endian_swap_reg;
1328};
1329
1330struct ipr_interrupts {
1331        void __iomem *set_interrupt_mask_reg;
1332        void __iomem *clr_interrupt_mask_reg;
1333        void __iomem *clr_interrupt_mask_reg32;
1334        void __iomem *sense_interrupt_mask_reg;
1335        void __iomem *sense_interrupt_mask_reg32;
1336        void __iomem *clr_interrupt_reg;
1337        void __iomem *clr_interrupt_reg32;
1338
1339        void __iomem *sense_interrupt_reg;
1340        void __iomem *sense_interrupt_reg32;
1341        void __iomem *ioarrin_reg;
1342        void __iomem *sense_uproc_interrupt_reg;
1343        void __iomem *sense_uproc_interrupt_reg32;
1344        void __iomem *set_uproc_interrupt_reg;
1345        void __iomem *set_uproc_interrupt_reg32;
1346        void __iomem *clr_uproc_interrupt_reg;
1347        void __iomem *clr_uproc_interrupt_reg32;
1348
1349        void __iomem *init_feedback_reg;
1350
1351        void __iomem *dump_addr_reg;
1352        void __iomem *dump_data_reg;
1353
1354        void __iomem *endian_swap_reg;
1355};
1356
1357struct ipr_chip_cfg_t {
1358        u32 mailbox;
1359        u16 max_cmds;
1360        u8 cache_line_size;
1361        u8 clear_isr;
1362        u32 iopoll_weight;
1363        struct ipr_interrupt_offsets regs;
1364};
1365
1366struct ipr_chip_t {
1367        u16 vendor;
1368        u16 device;
1369        u16 intr_type;
1370#define IPR_USE_LSI                     0x00
1371#define IPR_USE_MSI                     0x01
1372#define IPR_USE_MSIX                    0x02
1373        u16 sis_type;
1374#define IPR_SIS32                       0x00
1375#define IPR_SIS64                       0x01
1376        u16 bist_method;
1377#define IPR_PCI_CFG                     0x00
1378#define IPR_MMIO                        0x01
1379        const struct ipr_chip_cfg_t *cfg;
1380};
1381
1382enum ipr_shutdown_type {
1383        IPR_SHUTDOWN_NORMAL = 0x00,
1384        IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1385        IPR_SHUTDOWN_ABBREV = 0x80,
1386        IPR_SHUTDOWN_NONE = 0x100
1387};
1388
1389struct ipr_trace_entry {
1390        u32 time;
1391
1392        u8 op_code;
1393        u8 ata_op_code;
1394        u8 type;
1395#define IPR_TRACE_START                 0x00
1396#define IPR_TRACE_FINISH                0xff
1397        u8 cmd_index;
1398
1399        __be32 res_handle;
1400        union {
1401                u32 ioasc;
1402                u32 add_data;
1403                u32 res_addr;
1404        } u;
1405};
1406
1407struct ipr_sglist {
1408        u32 order;
1409        u32 num_sg;
1410        u32 num_dma_sg;
1411        u32 buffer_len;
1412        struct scatterlist scatterlist[1];
1413};
1414
1415enum ipr_sdt_state {
1416        INACTIVE,
1417        WAIT_FOR_DUMP,
1418        GET_DUMP,
1419        READ_DUMP,
1420        ABORT_DUMP,
1421        DUMP_OBTAINED
1422};
1423
1424/* Per-controller data */
1425struct ipr_ioa_cfg {
1426        char eye_catcher[8];
1427#define IPR_EYECATCHER                  "iprcfg"
1428
1429        struct list_head queue;
1430
1431        u8 in_reset_reload:1;
1432        u8 in_ioa_bringdown:1;
1433        u8 ioa_unit_checked:1;
1434        u8 dump_taken:1;
1435        u8 allow_ml_add_del:1;
1436        u8 needs_hard_reset:1;
1437        u8 dual_raid:1;
1438        u8 needs_warm_reset:1;
1439        u8 msi_received:1;
1440        u8 sis64:1;
1441        u8 dump_timeout:1;
1442        u8 cfg_locked:1;
1443        u8 clear_isr:1;
1444
1445        u8 revid;
1446
1447        /*
1448         * Bitmaps for SIS64 generated target values
1449         */
1450        unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1451        unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1452        unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1453
1454        u16 type; /* CCIN of the card */
1455
1456        u8 log_level;
1457#define IPR_MAX_LOG_LEVEL                       4
1458#define IPR_DEFAULT_LOG_LEVEL           2
1459
1460#define IPR_NUM_TRACE_INDEX_BITS        8
1461#define IPR_NUM_TRACE_ENTRIES           (1 << IPR_NUM_TRACE_INDEX_BITS)
1462#define IPR_TRACE_SIZE  (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1463        char trace_start[8];
1464#define IPR_TRACE_START_LABEL                   "trace"
1465        struct ipr_trace_entry *trace;
1466        atomic_t trace_index;
1467
1468        char cfg_table_start[8];
1469#define IPR_CFG_TBL_START               "cfg"
1470        union {
1471                struct ipr_config_table *cfg_table;
1472                struct ipr_config_table64 *cfg_table64;
1473        } u;
1474        dma_addr_t cfg_table_dma;
1475        u32 cfg_table_size;
1476        u32 max_devs_supported;
1477
1478        char resource_table_label[8];
1479#define IPR_RES_TABLE_LABEL             "res_tbl"
1480        struct ipr_resource_entry *res_entries;
1481        struct list_head free_res_q;
1482        struct list_head used_res_q;
1483
1484        char ipr_hcam_label[8];
1485#define IPR_HCAM_LABEL                  "hcams"
1486        struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1487        dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1488        struct list_head hostrcb_free_q;
1489        struct list_head hostrcb_pending_q;
1490
1491        struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1492        u32 hrrq_num;
1493        atomic_t  hrrq_index;
1494        u16 identify_hrrq_index;
1495
1496        struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1497
1498        unsigned int transop_timeout;
1499        const struct ipr_chip_cfg_t *chip_cfg;
1500        const struct ipr_chip_t *ipr_chip;
1501
1502        void __iomem *hdw_dma_regs;     /* iomapped PCI memory space */
1503        unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1504        void __iomem *ioa_mailbox;
1505        struct ipr_interrupts regs;
1506
1507        u16 saved_pcix_cmd_reg;
1508        u16 reset_retries;
1509
1510        u32 errors_logged;
1511        u32 doorbell;
1512
1513        struct Scsi_Host *host;
1514        struct pci_dev *pdev;
1515        struct ipr_sglist *ucode_sglist;
1516        u8 saved_mode_page_len;
1517
1518        struct work_struct work_q;
1519
1520        wait_queue_head_t reset_wait_q;
1521        wait_queue_head_t msi_wait_q;
1522
1523        struct ipr_dump *dump;
1524        enum ipr_sdt_state sdt_state;
1525
1526        struct ipr_misc_cbs *vpd_cbs;
1527        dma_addr_t vpd_cbs_dma;
1528
1529        struct pci_pool *ipr_cmd_pool;
1530
1531        struct ipr_cmnd *reset_cmd;
1532        int (*reset) (struct ipr_cmnd *);
1533
1534        struct ata_host ata_host;
1535        char ipr_cmd_label[8];
1536#define IPR_CMD_LABEL           "ipr_cmd"
1537        u32 max_cmds;
1538        struct ipr_cmnd **ipr_cmnd_list;
1539        dma_addr_t *ipr_cmnd_list_dma;
1540
1541        u16 intr_flag;
1542        unsigned int nvectors;
1543
1544        struct {
1545                unsigned short vec;
1546                char desc[22];
1547        } vectors_info[IPR_MAX_MSIX_VECTORS];
1548
1549        u32 iopoll_weight;
1550
1551}; /* struct ipr_ioa_cfg */
1552
1553struct ipr_cmnd {
1554        struct ipr_ioarcb ioarcb;
1555        union {
1556                struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1557                struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1558                struct ipr_ata64_ioadl ata_ioadl;
1559        } i;
1560        union {
1561                struct ipr_ioasa ioasa;
1562                struct ipr_ioasa64 ioasa64;
1563        } s;
1564        struct list_head queue;
1565        struct scsi_cmnd *scsi_cmd;
1566        struct ata_queued_cmd *qc;
1567        struct completion completion;
1568        struct timer_list timer;
1569        void (*fast_done) (struct ipr_cmnd *);
1570        void (*done) (struct ipr_cmnd *);
1571        int (*job_step) (struct ipr_cmnd *);
1572        int (*job_step_failed) (struct ipr_cmnd *);
1573        u16 cmd_index;
1574        u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1575        dma_addr_t sense_buffer_dma;
1576        unsigned short dma_use_sg;
1577        dma_addr_t dma_addr;
1578        struct ipr_cmnd *sibling;
1579        union {
1580                enum ipr_shutdown_type shutdown_type;
1581                struct ipr_hostrcb *hostrcb;
1582                unsigned long time_left;
1583                unsigned long scratch;
1584                struct ipr_resource_entry *res;
1585                struct scsi_device *sdev;
1586        } u;
1587
1588        struct ipr_hrr_queue *hrrq;
1589        struct ipr_ioa_cfg *ioa_cfg;
1590};
1591
1592struct ipr_ses_table_entry {
1593        char product_id[17];
1594        char compare_product_id_byte[17];
1595        u32 max_bus_speed_limit;        /* MB/sec limit for this backplane */
1596};
1597
1598struct ipr_dump_header {
1599        u32 eye_catcher;
1600#define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1601        u32 len;
1602        u32 num_entries;
1603        u32 first_entry_offset;
1604        u32 status;
1605#define IPR_DUMP_STATUS_SUCCESS                 0
1606#define IPR_DUMP_STATUS_QUAL_SUCCESS            2
1607#define IPR_DUMP_STATUS_FAILED                  0xffffffff
1608        u32 os;
1609#define IPR_DUMP_OS_LINUX       0x4C4E5558
1610        u32 driver_name;
1611#define IPR_DUMP_DRIVER_NAME    0x49505232
1612}__attribute__((packed, aligned (4)));
1613
1614struct ipr_dump_entry_header {
1615        u32 eye_catcher;
1616#define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1617        u32 len;
1618        u32 num_elems;
1619        u32 offset;
1620        u32 data_type;
1621#define IPR_DUMP_DATA_TYPE_ASCII        0x41534349
1622#define IPR_DUMP_DATA_TYPE_BINARY       0x42494E41
1623        u32 id;
1624#define IPR_DUMP_IOA_DUMP_ID            0x494F4131
1625#define IPR_DUMP_LOCATION_ID            0x4C4F4341
1626#define IPR_DUMP_TRACE_ID               0x54524143
1627#define IPR_DUMP_DRIVER_VERSION_ID      0x44525652
1628#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1629#define IPR_DUMP_IOA_CTRL_BLK           0x494F4342
1630#define IPR_DUMP_PEND_OPS               0x414F5053
1631        u32 status;
1632}__attribute__((packed, aligned (4)));
1633
1634struct ipr_dump_location_entry {
1635        struct ipr_dump_entry_header hdr;
1636        u8 location[20];
1637}__attribute__((packed));
1638
1639struct ipr_dump_trace_entry {
1640        struct ipr_dump_entry_header hdr;
1641        u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1642}__attribute__((packed, aligned (4)));
1643
1644struct ipr_dump_version_entry {
1645        struct ipr_dump_entry_header hdr;
1646        u8 version[sizeof(IPR_DRIVER_VERSION)];
1647};
1648
1649struct ipr_dump_ioa_type_entry {
1650        struct ipr_dump_entry_header hdr;
1651        u32 type;
1652        u32 fw_version;
1653};
1654
1655struct ipr_driver_dump {
1656        struct ipr_dump_header hdr;
1657        struct ipr_dump_version_entry version_entry;
1658        struct ipr_dump_location_entry location_entry;
1659        struct ipr_dump_ioa_type_entry ioa_type_entry;
1660        struct ipr_dump_trace_entry trace_entry;
1661}__attribute__((packed));
1662
1663struct ipr_ioa_dump {
1664        struct ipr_dump_entry_header hdr;
1665        struct ipr_sdt sdt;
1666        __be32 **ioa_data;
1667        u32 reserved;
1668        u32 next_page_index;
1669        u32 page_offset;
1670        u32 format;
1671}__attribute__((packed, aligned (4)));
1672
1673struct ipr_dump {
1674        struct kref kref;
1675        struct ipr_ioa_cfg *ioa_cfg;
1676        struct ipr_driver_dump driver_dump;
1677        struct ipr_ioa_dump ioa_dump;
1678};
1679
1680struct ipr_error_table_t {
1681        u32 ioasc;
1682        int log_ioasa;
1683        int log_hcam;
1684        char *error;
1685};
1686
1687struct ipr_software_inq_lid_info {
1688        __be32 load_id;
1689        __be32 timestamp[3];
1690}__attribute__((packed, aligned (4)));
1691
1692struct ipr_ucode_image_header {
1693        __be32 header_length;
1694        __be32 lid_table_offset;
1695        u8 major_release;
1696        u8 card_type;
1697        u8 minor_release[2];
1698        u8 reserved[20];
1699        char eyecatcher[16];
1700        __be32 num_lids;
1701        struct ipr_software_inq_lid_info lid[1];
1702}__attribute__((packed, aligned (4)));
1703
1704/*
1705 * Macros
1706 */
1707#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1708
1709#ifdef CONFIG_SCSI_IPR_TRACE
1710#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1711#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1712#else
1713#define ipr_create_trace_file(kobj, attr) 0
1714#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1715#endif
1716
1717#ifdef CONFIG_SCSI_IPR_DUMP
1718#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1719#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1720#else
1721#define ipr_create_dump_file(kobj, attr) 0
1722#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1723#endif
1724
1725/*
1726 * Error logging macros
1727 */
1728#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1729#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1730#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1731
1732#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1733        printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1734                bus, target, lun, ##__VA_ARGS__)
1735
1736#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1737        ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1738
1739#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1740        printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1741                (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1742
1743#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1744        ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1745
1746#define ipr_phys_res_err(ioa_cfg, res, fmt, ...)                        \
1747{                                                                       \
1748        if ((res).bus >= IPR_MAX_NUM_BUSES) {                           \
1749                ipr_err(fmt": unknown\n", ##__VA_ARGS__);               \
1750        } else {                                                        \
1751                ipr_err(fmt": %d:%d:%d:%d\n",                           \
1752                        ##__VA_ARGS__, (ioa_cfg)->host->host_no,        \
1753                        (res).bus, (res).target, (res).lun);            \
1754        }                                                               \
1755}
1756
1757#define ipr_hcam_err(hostrcb, fmt, ...)                                 \
1758{                                                                       \
1759        if (ipr_is_device(hostrcb)) {                                   \
1760                if ((hostrcb)->ioa_cfg->sis64) {                        \
1761                        printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
1762                                ipr_format_res_path(hostrcb->ioa_cfg,   \
1763                                        hostrcb->hcam.u.error64.fd_res_path, \
1764                                        hostrcb->rp_buffer,             \
1765                                        sizeof(hostrcb->rp_buffer)),    \
1766                                __VA_ARGS__);                           \
1767                } else {                                                \
1768                        ipr_ra_err((hostrcb)->ioa_cfg,                  \
1769                                (hostrcb)->hcam.u.error.fd_res_addr,    \
1770                                fmt, __VA_ARGS__);                      \
1771                }                                                       \
1772        } else {                                                        \
1773                dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1774        }                                                               \
1775}
1776
1777#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1778        __FILE__, __func__, __LINE__)
1779
1780#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1781#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1782
1783#define ipr_err_separator \
1784ipr_err("----------------------------------------------------------\n")
1785
1786
1787/*
1788 * Inlines
1789 */
1790
1791/**
1792 * ipr_is_ioa_resource - Determine if a resource is the IOA
1793 * @res:        resource entry struct
1794 *
1795 * Return value:
1796 *      1 if IOA / 0 if not IOA
1797 **/
1798static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1799{
1800        return res->type == IPR_RES_TYPE_IOAFP;
1801}
1802
1803/**
1804 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1805 * @res:        resource entry struct
1806 *
1807 * Return value:
1808 *      1 if AF DASD / 0 if not AF DASD
1809 **/
1810static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1811{
1812        return res->type == IPR_RES_TYPE_AF_DASD ||
1813                res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1814}
1815
1816/**
1817 * ipr_is_vset_device - Determine if a resource is a VSET
1818 * @res:        resource entry struct
1819 *
1820 * Return value:
1821 *      1 if VSET / 0 if not VSET
1822 **/
1823static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1824{
1825        return res->type == IPR_RES_TYPE_VOLUME_SET;
1826}
1827
1828/**
1829 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1830 * @res:        resource entry struct
1831 *
1832 * Return value:
1833 *      1 if GSCSI / 0 if not GSCSI
1834 **/
1835static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1836{
1837        return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1838}
1839
1840/**
1841 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1842 * @res:        resource entry struct
1843 *
1844 * Return value:
1845 *      1 if SCSI disk / 0 if not SCSI disk
1846 **/
1847static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1848{
1849        if (ipr_is_af_dasd_device(res) ||
1850            (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1851                return 1;
1852        else
1853                return 0;
1854}
1855
1856/**
1857 * ipr_is_gata - Determine if a resource is a generic ATA resource
1858 * @res:        resource entry struct
1859 *
1860 * Return value:
1861 *      1 if GATA / 0 if not GATA
1862 **/
1863static inline int ipr_is_gata(struct ipr_resource_entry *res)
1864{
1865        return res->type == IPR_RES_TYPE_GENERIC_ATA;
1866}
1867
1868/**
1869 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1870 * @res:        resource entry struct
1871 *
1872 * Return value:
1873 *      1 if NACA queueing model / 0 if not NACA queueing model
1874 **/
1875static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1876{
1877        if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1878                return 1;
1879        return 0;
1880}
1881
1882/**
1883 * ipr_is_device - Determine if the hostrcb structure is related to a device
1884 * @hostrcb:    host resource control blocks struct
1885 *
1886 * Return value:
1887 *      1 if AF / 0 if not AF
1888 **/
1889static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1890{
1891        struct ipr_res_addr *res_addr;
1892        u8 *res_path;
1893
1894        if (hostrcb->ioa_cfg->sis64) {
1895                res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1896                if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1897                    res_path[0] == 0x81) && res_path[2] != 0xFF)
1898                        return 1;
1899        } else {
1900                res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1901
1902                if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1903                    (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1904                        return 1;
1905        }
1906        return 0;
1907}
1908
1909/**
1910 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1911 * @sdt_word:   SDT address
1912 *
1913 * Return value:
1914 *      1 if format 2 / 0 if not
1915 **/
1916static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1917{
1918        u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1919
1920        switch (bar_sel) {
1921        case IPR_SDT_FMT2_BAR0_SEL:
1922        case IPR_SDT_FMT2_BAR1_SEL:
1923        case IPR_SDT_FMT2_BAR2_SEL:
1924        case IPR_SDT_FMT2_BAR3_SEL:
1925        case IPR_SDT_FMT2_BAR4_SEL:
1926        case IPR_SDT_FMT2_BAR5_SEL:
1927        case IPR_SDT_FMT2_EXP_ROM_SEL:
1928                return 1;
1929        };
1930
1931        return 0;
1932}
1933
1934#ifndef writeq
1935static inline void writeq(u64 val, void __iomem *addr)
1936{
1937        writel(((u32) (val >> 32)), addr);
1938        writel(((u32) (val)), (addr + 4));
1939}
1940#endif
1941
1942#endif /* _IPR_H */
1943
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