linux/drivers/scsi/hpsa.h
<<
>>
Prefs
   1/*
   2 *    Disk Array driver for HP Smart Array SAS controllers
   3 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4 *
   5 *    This program is free software; you can redistribute it and/or modify
   6 *    it under the terms of the GNU General Public License as published by
   7 *    the Free Software Foundation; version 2 of the License.
   8 *
   9 *    This program is distributed in the hope that it will be useful,
  10 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13 *
  14 *    You should have received a copy of the GNU General Public License
  15 *    along with this program; if not, write to the Free Software
  16 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17 *
  18 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19 *
  20 */
  21#ifndef HPSA_H
  22#define HPSA_H
  23
  24#include <scsi/scsicam.h>
  25
  26#define IO_OK           0
  27#define IO_ERROR        1
  28
  29struct ctlr_info;
  30
  31struct access_method {
  32        void (*submit_command)(struct ctlr_info *h,
  33                struct CommandList *c);
  34        void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
  35        unsigned long (*fifo_full)(struct ctlr_info *h);
  36        bool (*intr_pending)(struct ctlr_info *h);
  37        unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
  38};
  39
  40struct hpsa_scsi_dev_t {
  41        int devtype;
  42        int bus, target, lun;           /* as presented to the OS */
  43        unsigned char scsi3addr[8];     /* as presented to the HW */
  44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
  45        unsigned char device_id[16];    /* from inquiry pg. 0x83 */
  46        unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
  47        unsigned char model[16];        /* bytes 16-31 of inquiry data */
  48        unsigned char raid_level;       /* from inquiry page 0xC1 */
  49};
  50
  51struct reply_pool {
  52        u64 *head;
  53        size_t size;
  54        u8 wraparound;
  55        u32 current_entry;
  56};
  57
  58struct ctlr_info {
  59        int     ctlr;
  60        char    devname[8];
  61        char    *product_name;
  62        struct pci_dev *pdev;
  63        u32     board_id;
  64        void __iomem *vaddr;
  65        unsigned long paddr;
  66        int     nr_cmds; /* Number of commands allowed on this controller */
  67        struct CfgTable __iomem *cfgtable;
  68        int     interrupts_enabled;
  69        int     major;
  70        int     max_commands;
  71        int     commands_outstanding;
  72        int     max_outstanding; /* Debug */
  73        int     usage_count;  /* number of opens all all minor devices */
  74#       define PERF_MODE_INT    0
  75#       define DOORBELL_INT     1
  76#       define SIMPLE_MODE_INT  2
  77#       define MEMQ_MODE_INT    3
  78        unsigned int intr[MAX_REPLY_QUEUES];
  79        unsigned int msix_vector;
  80        unsigned int msi_vector;
  81        int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
  82        struct access_method access;
  83
  84        /* queue and queue Info */
  85        struct list_head reqQ;
  86        struct list_head cmpQ;
  87        unsigned int Qdepth;
  88        unsigned int maxSG;
  89        spinlock_t lock;
  90        int maxsgentries;
  91        u8 max_cmd_sg_entries;
  92        int chainsize;
  93        struct SGDescriptor **cmd_sg_list;
  94
  95        /* pointers to command and error info pool */
  96        struct CommandList      *cmd_pool;
  97        dma_addr_t              cmd_pool_dhandle;
  98        struct ErrorInfo        *errinfo_pool;
  99        dma_addr_t              errinfo_pool_dhandle;
 100        unsigned long           *cmd_pool_bits;
 101        int                     scan_finished;
 102        spinlock_t              scan_lock;
 103        wait_queue_head_t       scan_wait_queue;
 104
 105        struct Scsi_Host *scsi_host;
 106        spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
 107        int ndevices; /* number of used elements in .dev[] array. */
 108        struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
 109        /*
 110         * Performant mode tables.
 111         */
 112        u32 trans_support;
 113        u32 trans_offset;
 114        struct TransTable_struct *transtable;
 115        unsigned long transMethod;
 116
 117        /*
 118         * Performant mode completion buffers
 119         */
 120        u64 *reply_pool;
 121        size_t reply_pool_size;
 122        struct reply_pool reply_queue[MAX_REPLY_QUEUES];
 123        u8 nreply_queues;
 124        dma_addr_t reply_pool_dhandle;
 125        u32 *blockFetchTable;
 126        unsigned char *hba_inquiry_data;
 127        u64 last_intr_timestamp;
 128        u32 last_heartbeat;
 129        u64 last_heartbeat_timestamp;
 130        u32 heartbeat_sample_interval;
 131        atomic_t firmware_flash_in_progress;
 132        u32 lockup_detected;
 133        struct list_head lockup_list;
 134        /* Address of h->q[x] is passed to intr handler to know which queue */
 135        u8 q[MAX_REPLY_QUEUES];
 136        u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
 137#define HPSATMF_BITS_SUPPORTED  (1 << 0)
 138#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
 139#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
 140#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
 141#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
 142#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
 143#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
 144#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
 145#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
 146#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
 147#define HPSATMF_MASK_SUPPORTED  (1 << 16)
 148#define HPSATMF_LOG_LUN_RESET   (1 << 17)
 149#define HPSATMF_LOG_NEX_RESET   (1 << 18)
 150#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
 151#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
 152#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
 153#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
 154#define HPSATMF_LOG_QRY_TASK    (1 << 23)
 155#define HPSATMF_LOG_QRY_TSET    (1 << 24)
 156#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
 157};
 158#define HPSA_ABORT_MSG 0
 159#define HPSA_DEVICE_RESET_MSG 1
 160#define HPSA_RESET_TYPE_CONTROLLER 0x00
 161#define HPSA_RESET_TYPE_BUS 0x01
 162#define HPSA_RESET_TYPE_TARGET 0x03
 163#define HPSA_RESET_TYPE_LUN 0x04
 164#define HPSA_MSG_SEND_RETRY_LIMIT 10
 165#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
 166
 167/* Maximum time in seconds driver will wait for command completions
 168 * when polling before giving up.
 169 */
 170#define HPSA_MAX_POLL_TIME_SECS (20)
 171
 172/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 173 * how many times to retry TEST UNIT READY on a device
 174 * while waiting for it to become ready before giving up.
 175 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 176 * between sending TURs while waiting for a device
 177 * to become ready.
 178 */
 179#define HPSA_TUR_RETRY_LIMIT (20)
 180#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
 181
 182/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 183 * to become ready, in seconds, before giving up on it.
 184 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 185 * between polling the board to see if it is ready, in
 186 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 187 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 188 */
 189#define HPSA_BOARD_READY_WAIT_SECS (120)
 190#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
 191#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
 192#define HPSA_BOARD_READY_POLL_INTERVAL \
 193        ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
 194#define HPSA_BOARD_READY_ITERATIONS \
 195        ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
 196                HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
 197#define HPSA_BOARD_NOT_READY_ITERATIONS \
 198        ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
 199                HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
 200#define HPSA_POST_RESET_PAUSE_MSECS (3000)
 201#define HPSA_POST_RESET_NOOP_RETRIES (12)
 202
 203/*  Defining the diffent access_menthods */
 204/*
 205 * Memory mapped FIFO interface (SMART 53xx cards)
 206 */
 207#define SA5_DOORBELL    0x20
 208#define SA5_REQUEST_PORT_OFFSET 0x40
 209#define SA5_REPLY_INTR_MASK_OFFSET      0x34
 210#define SA5_REPLY_PORT_OFFSET           0x44
 211#define SA5_INTR_STATUS         0x30
 212#define SA5_SCRATCHPAD_OFFSET   0xB0
 213
 214#define SA5_CTCFG_OFFSET        0xB4
 215#define SA5_CTMEM_OFFSET        0xB8
 216
 217#define SA5_INTR_OFF            0x08
 218#define SA5B_INTR_OFF           0x04
 219#define SA5_INTR_PENDING        0x08
 220#define SA5B_INTR_PENDING       0x04
 221#define FIFO_EMPTY              0xffffffff
 222#define HPSA_FIRMWARE_READY     0xffff0000 /* value in scratchpad register */
 223
 224#define HPSA_ERROR_BIT          0x02
 225
 226/* Performant mode flags */
 227#define SA5_PERF_INTR_PENDING   0x04
 228#define SA5_PERF_INTR_OFF       0x05
 229#define SA5_OUTDB_STATUS_PERF_BIT       0x01
 230#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
 231#define SA5_OUTDB_CLEAR         0xA0
 232#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
 233#define SA5_OUTDB_STATUS        0x9C
 234
 235
 236#define HPSA_INTR_ON    1
 237#define HPSA_INTR_OFF   0
 238/*
 239        Send the command to the hardware
 240*/
 241static void SA5_submit_command(struct ctlr_info *h,
 242        struct CommandList *c)
 243{
 244        dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
 245                c->Header.Tag.lower);
 246        writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 247        (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
 248}
 249
 250/*
 251 *  This card is the opposite of the other cards.
 252 *   0 turns interrupts on...
 253 *   0x08 turns them off...
 254 */
 255static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
 256{
 257        if (val) { /* Turn interrupts on */
 258                h->interrupts_enabled = 1;
 259                writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 260                (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 261        } else { /* Turn them off */
 262                h->interrupts_enabled = 0;
 263                writel(SA5_INTR_OFF,
 264                        h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 265                (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 266        }
 267}
 268
 269static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
 270{
 271        if (val) { /* turn on interrupts */
 272                h->interrupts_enabled = 1;
 273                writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 274                (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 275        } else {
 276                h->interrupts_enabled = 0;
 277                writel(SA5_PERF_INTR_OFF,
 278                        h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 279                (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 280        }
 281}
 282
 283static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
 284{
 285        struct reply_pool *rq = &h->reply_queue[q];
 286        unsigned long flags, register_value = FIFO_EMPTY;
 287
 288        /* msi auto clears the interrupt pending bit. */
 289        if (!(h->msi_vector || h->msix_vector)) {
 290                /* flush the controller write of the reply queue by reading
 291                 * outbound doorbell status register.
 292                 */
 293                register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 294                writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
 295                /* Do a read in order to flush the write to the controller
 296                 * (as per spec.)
 297                 */
 298                register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 299        }
 300
 301        if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
 302                register_value = rq->head[rq->current_entry];
 303                rq->current_entry++;
 304                spin_lock_irqsave(&h->lock, flags);
 305                h->commands_outstanding--;
 306                spin_unlock_irqrestore(&h->lock, flags);
 307        } else {
 308                register_value = FIFO_EMPTY;
 309        }
 310        /* Check for wraparound */
 311        if (rq->current_entry == h->max_commands) {
 312                rq->current_entry = 0;
 313                rq->wraparound ^= 1;
 314        }
 315        return register_value;
 316}
 317
 318/*
 319 *  Returns true if fifo is full.
 320 *
 321 */
 322static unsigned long SA5_fifo_full(struct ctlr_info *h)
 323{
 324        if (h->commands_outstanding >= h->max_commands)
 325                return 1;
 326        else
 327                return 0;
 328
 329}
 330/*
 331 *   returns value read from hardware.
 332 *     returns FIFO_EMPTY if there is nothing to read
 333 */
 334static unsigned long SA5_completed(struct ctlr_info *h,
 335        __attribute__((unused)) u8 q)
 336{
 337        unsigned long register_value
 338                = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 339        unsigned long flags;
 340
 341        if (register_value != FIFO_EMPTY) {
 342                spin_lock_irqsave(&h->lock, flags);
 343                h->commands_outstanding--;
 344                spin_unlock_irqrestore(&h->lock, flags);
 345        }
 346
 347#ifdef HPSA_DEBUG
 348        if (register_value != FIFO_EMPTY)
 349                dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
 350                        register_value);
 351        else
 352                dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
 353#endif
 354
 355        return register_value;
 356}
 357/*
 358 *      Returns true if an interrupt is pending..
 359 */
 360static bool SA5_intr_pending(struct ctlr_info *h)
 361{
 362        unsigned long register_value  =
 363                readl(h->vaddr + SA5_INTR_STATUS);
 364        dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
 365        return register_value & SA5_INTR_PENDING;
 366}
 367
 368static bool SA5_performant_intr_pending(struct ctlr_info *h)
 369{
 370        unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
 371
 372        if (!register_value)
 373                return false;
 374
 375        if (h->msi_vector || h->msix_vector)
 376                return true;
 377
 378        /* Read outbound doorbell to flush */
 379        register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 380        return register_value & SA5_OUTDB_STATUS_PERF_BIT;
 381}
 382
 383static struct access_method SA5_access = {
 384        SA5_submit_command,
 385        SA5_intr_mask,
 386        SA5_fifo_full,
 387        SA5_intr_pending,
 388        SA5_completed,
 389};
 390
 391static struct access_method SA5_performant_access = {
 392        SA5_submit_command,
 393        SA5_performant_intr_mask,
 394        SA5_fifo_full,
 395        SA5_performant_intr_pending,
 396        SA5_performant_completed,
 397};
 398
 399struct board_type {
 400        u32     board_id;
 401        char    *product_name;
 402        struct access_method *access;
 403};
 404
 405#endif /* HPSA_H */
 406
 407
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.