linux/drivers/pwm/pwm-renesas-tpu.c
<<
>>
Prefs
   1/*
   2 * R-Mobile TPU PWM driver
   3 *
   4 * Copyright (C) 2012 Renesas Solutions Corp.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#include <linux/clk.h>
  17#include <linux/err.h>
  18#include <linux/io.h>
  19#include <linux/init.h>
  20#include <linux/ioport.h>
  21#include <linux/module.h>
  22#include <linux/mutex.h>
  23#include <linux/of.h>
  24#include <linux/platform_data/pwm-renesas-tpu.h>
  25#include <linux/platform_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/pwm.h>
  28#include <linux/slab.h>
  29#include <linux/spinlock.h>
  30
  31#define TPU_TSTR                0x00    /* Timer start register (shared) */
  32
  33#define TPU_TCRn                0x00    /* Timer control register */
  34#define TPU_TCR_CCLR_NONE       (0 << 5)
  35#define TPU_TCR_CCLR_TGRA       (1 << 5)
  36#define TPU_TCR_CCLR_TGRB       (2 << 5)
  37#define TPU_TCR_CCLR_TGRC       (5 << 5)
  38#define TPU_TCR_CCLR_TGRD       (6 << 5)
  39#define TPU_TCR_CKEG_RISING     (0 << 3)
  40#define TPU_TCR_CKEG_FALLING    (1 << 3)
  41#define TPU_TCR_CKEG_BOTH       (2 << 3)
  42#define TPU_TMDRn               0x04    /* Timer mode register */
  43#define TPU_TMDR_BFWT           (1 << 6)
  44#define TPU_TMDR_BFB            (1 << 5)
  45#define TPU_TMDR_BFA            (1 << 4)
  46#define TPU_TMDR_MD_NORMAL      (0 << 0)
  47#define TPU_TMDR_MD_PWM         (2 << 0)
  48#define TPU_TIORn               0x08    /* Timer I/O control register */
  49#define TPU_TIOR_IOA_0          (0 << 0)
  50#define TPU_TIOR_IOA_0_CLR      (1 << 0)
  51#define TPU_TIOR_IOA_0_SET      (2 << 0)
  52#define TPU_TIOR_IOA_0_TOGGLE   (3 << 0)
  53#define TPU_TIOR_IOA_1          (4 << 0)
  54#define TPU_TIOR_IOA_1_CLR      (5 << 0)
  55#define TPU_TIOR_IOA_1_SET      (6 << 0)
  56#define TPU_TIOR_IOA_1_TOGGLE   (7 << 0)
  57#define TPU_TIERn               0x0c    /* Timer interrupt enable register */
  58#define TPU_TSRn                0x10    /* Timer status register */
  59#define TPU_TCNTn               0x14    /* Timer counter */
  60#define TPU_TGRAn               0x18    /* Timer general register A */
  61#define TPU_TGRBn               0x1c    /* Timer general register B */
  62#define TPU_TGRCn               0x20    /* Timer general register C */
  63#define TPU_TGRDn               0x24    /* Timer general register D */
  64
  65#define TPU_CHANNEL_OFFSET      0x10
  66#define TPU_CHANNEL_SIZE        0x40
  67
  68enum tpu_pin_state {
  69        TPU_PIN_INACTIVE,               /* Pin is driven inactive */
  70        TPU_PIN_PWM,                    /* Pin is driven by PWM */
  71        TPU_PIN_ACTIVE,                 /* Pin is driven active */
  72};
  73
  74struct tpu_device;
  75
  76struct tpu_pwm_device {
  77        bool timer_on;                  /* Whether the timer is running */
  78
  79        struct tpu_device *tpu;
  80        unsigned int channel;           /* Channel number in the TPU */
  81
  82        enum pwm_polarity polarity;
  83        unsigned int prescaler;
  84        u16 period;
  85        u16 duty;
  86};
  87
  88struct tpu_device {
  89        struct platform_device *pdev;
  90        enum pwm_polarity polarities[TPU_CHANNEL_MAX];
  91        struct pwm_chip chip;
  92        spinlock_t lock;
  93
  94        void __iomem *base;
  95        struct clk *clk;
  96};
  97
  98#define to_tpu_device(c)        container_of(c, struct tpu_device, chip)
  99
 100static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value)
 101{
 102        void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET
 103                           + pwm->channel * TPU_CHANNEL_SIZE;
 104
 105        iowrite16(value, base + reg_nr);
 106}
 107
 108static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm,
 109                            enum tpu_pin_state state)
 110{
 111        static const char * const states[] = { "inactive", "PWM", "active" };
 112
 113        dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n",
 114                pwm->channel, states[state]);
 115
 116        switch (state) {
 117        case TPU_PIN_INACTIVE:
 118                tpu_pwm_write(pwm, TPU_TIORn,
 119                              pwm->polarity == PWM_POLARITY_INVERSED ?
 120                              TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
 121                break;
 122        case TPU_PIN_PWM:
 123                tpu_pwm_write(pwm, TPU_TIORn,
 124                              pwm->polarity == PWM_POLARITY_INVERSED ?
 125                              TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
 126                break;
 127        case TPU_PIN_ACTIVE:
 128                tpu_pwm_write(pwm, TPU_TIORn,
 129                              pwm->polarity == PWM_POLARITY_INVERSED ?
 130                              TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
 131                break;
 132        }
 133}
 134
 135static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start)
 136{
 137        unsigned long flags;
 138        u16 value;
 139
 140        spin_lock_irqsave(&pwm->tpu->lock, flags);
 141        value = ioread16(pwm->tpu->base + TPU_TSTR);
 142
 143        if (start)
 144                value |= 1 << pwm->channel;
 145        else
 146                value &= ~(1 << pwm->channel);
 147
 148        iowrite16(value, pwm->tpu->base + TPU_TSTR);
 149        spin_unlock_irqrestore(&pwm->tpu->lock, flags);
 150}
 151
 152static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm)
 153{
 154        int ret;
 155
 156        if (!pwm->timer_on) {
 157                /* Wake up device and enable clock. */
 158                pm_runtime_get_sync(&pwm->tpu->pdev->dev);
 159                ret = clk_prepare_enable(pwm->tpu->clk);
 160                if (ret) {
 161                        dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n");
 162                        return ret;
 163                }
 164                pwm->timer_on = true;
 165        }
 166
 167        /*
 168         * Make sure the channel is stopped, as we need to reconfigure it
 169         * completely. First drive the pin to the inactive state to avoid
 170         * glitches.
 171         */
 172        tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
 173        tpu_pwm_start_stop(pwm, false);
 174
 175        /*
 176         * - Clear TCNT on TGRB match
 177         * - Count on rising edge
 178         * - Set prescaler
 179         * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
 180         * - Output 1 until TGRA, output 0 until TGRB (active high polarity
 181         * - PWM mode
 182         */
 183        tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
 184                      pwm->prescaler);
 185        tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM);
 186        tpu_pwm_set_pin(pwm, TPU_PIN_PWM);
 187        tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
 188        tpu_pwm_write(pwm, TPU_TGRBn, pwm->period);
 189
 190        dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
 191                pwm->channel, pwm->duty, pwm->period);
 192
 193        /* Start the channel. */
 194        tpu_pwm_start_stop(pwm, true);
 195
 196        return 0;
 197}
 198
 199static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm)
 200{
 201        if (!pwm->timer_on)
 202                return;
 203
 204        /* Disable channel. */
 205        tpu_pwm_start_stop(pwm, false);
 206
 207        /* Stop clock and mark device as idle. */
 208        clk_disable_unprepare(pwm->tpu->clk);
 209        pm_runtime_put(&pwm->tpu->pdev->dev);
 210
 211        pwm->timer_on = false;
 212}
 213
 214/* -----------------------------------------------------------------------------
 215 * PWM API
 216 */
 217
 218static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm)
 219{
 220        struct tpu_device *tpu = to_tpu_device(chip);
 221        struct tpu_pwm_device *pwm;
 222
 223        if (_pwm->hwpwm >= TPU_CHANNEL_MAX)
 224                return -EINVAL;
 225
 226        pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
 227        if (pwm == NULL)
 228                return -ENOMEM;
 229
 230        pwm->tpu = tpu;
 231        pwm->channel = _pwm->hwpwm;
 232        pwm->polarity = tpu->polarities[pwm->channel];
 233        pwm->prescaler = 0;
 234        pwm->period = 0;
 235        pwm->duty = 0;
 236
 237        pwm->timer_on = false;
 238
 239        pwm_set_chip_data(_pwm, pwm);
 240
 241        return 0;
 242}
 243
 244static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm)
 245{
 246        struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
 247
 248        tpu_pwm_timer_stop(pwm);
 249        kfree(pwm);
 250}
 251
 252static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm,
 253                          int duty_ns, int period_ns)
 254{
 255        static const unsigned int prescalers[] = { 1, 4, 16, 64 };
 256        struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
 257        struct tpu_device *tpu = to_tpu_device(chip);
 258        unsigned int prescaler;
 259        bool duty_only = false;
 260        u32 clk_rate;
 261        u32 period;
 262        u32 duty;
 263        int ret;
 264
 265        /*
 266         * Pick a prescaler to avoid overflowing the counter.
 267         * TODO: Pick the highest acceptable prescaler.
 268         */
 269        clk_rate = clk_get_rate(tpu->clk);
 270
 271        for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
 272                period = clk_rate / prescalers[prescaler]
 273                       / (NSEC_PER_SEC / period_ns);
 274                if (period <= 0xffff)
 275                        break;
 276        }
 277
 278        if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
 279                dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
 280                return -ENOTSUPP;
 281        }
 282
 283        if (duty_ns) {
 284                duty = clk_rate / prescalers[prescaler]
 285                     / (NSEC_PER_SEC / duty_ns);
 286                if (duty > period)
 287                        return -EINVAL;
 288        } else {
 289                duty = 0;
 290        }
 291
 292        dev_dbg(&tpu->pdev->dev,
 293                "rate %u, prescaler %u, period %u, duty %u\n",
 294                clk_rate, prescalers[prescaler], period, duty);
 295
 296        if (pwm->prescaler == prescaler && pwm->period == period)
 297                duty_only = true;
 298
 299        pwm->prescaler = prescaler;
 300        pwm->period = period;
 301        pwm->duty = duty;
 302
 303        /* If the channel is disabled we're done. */
 304        if (!test_bit(PWMF_ENABLED, &_pwm->flags))
 305                return 0;
 306
 307        if (duty_only && pwm->timer_on) {
 308                /*
 309                 * If only the duty cycle changed and the timer is already
 310                 * running, there's no need to reconfigure it completely, Just
 311                 * modify the duty cycle.
 312                 */
 313                tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
 314                dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
 315                        pwm->duty);
 316        } else {
 317                /* Otherwise perform a full reconfiguration. */
 318                ret = tpu_pwm_timer_start(pwm);
 319                if (ret < 0)
 320                        return ret;
 321        }
 322
 323        if (duty == 0 || duty == period) {
 324                /*
 325                 * To avoid running the timer when not strictly required, handle
 326                 * 0% and 100% duty cycles as fixed levels and stop the timer.
 327                 */
 328                tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
 329                tpu_pwm_timer_stop(pwm);
 330        }
 331
 332        return 0;
 333}
 334
 335static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm,
 336                                enum pwm_polarity polarity)
 337{
 338        struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
 339
 340        pwm->polarity = polarity;
 341
 342        return 0;
 343}
 344
 345static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm)
 346{
 347        struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
 348        int ret;
 349
 350        ret = tpu_pwm_timer_start(pwm);
 351        if (ret < 0)
 352                return ret;
 353
 354        /*
 355         * To avoid running the timer when not strictly required, handle 0% and
 356         * 100% duty cycles as fixed levels and stop the timer.
 357         */
 358        if (pwm->duty == 0 || pwm->duty == pwm->period) {
 359                tpu_pwm_set_pin(pwm, pwm->duty ?
 360                                TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
 361                tpu_pwm_timer_stop(pwm);
 362        }
 363
 364        return 0;
 365}
 366
 367static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm)
 368{
 369        struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
 370
 371        /* The timer must be running to modify the pin output configuration. */
 372        tpu_pwm_timer_start(pwm);
 373        tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
 374        tpu_pwm_timer_stop(pwm);
 375}
 376
 377static const struct pwm_ops tpu_pwm_ops = {
 378        .request = tpu_pwm_request,
 379        .free = tpu_pwm_free,
 380        .config = tpu_pwm_config,
 381        .set_polarity = tpu_pwm_set_polarity,
 382        .enable = tpu_pwm_enable,
 383        .disable = tpu_pwm_disable,
 384        .owner = THIS_MODULE,
 385};
 386
 387/* -----------------------------------------------------------------------------
 388 * Probe and remove
 389 */
 390
 391static void tpu_parse_pdata(struct tpu_device *tpu)
 392{
 393        struct tpu_pwm_platform_data *pdata = tpu->pdev->dev.platform_data;
 394        unsigned int i;
 395
 396        for (i = 0; i < ARRAY_SIZE(tpu->polarities); ++i)
 397                tpu->polarities[i] = pdata ? pdata->channels[i].polarity
 398                                   : PWM_POLARITY_NORMAL;
 399}
 400
 401static int tpu_probe(struct platform_device *pdev)
 402{
 403        struct tpu_device *tpu;
 404        struct resource *res;
 405        int ret;
 406
 407        tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
 408        if (tpu == NULL) {
 409                dev_err(&pdev->dev, "failed to allocate driver data\n");
 410                return -ENOMEM;
 411        }
 412
 413        spin_lock_init(&tpu->lock);
 414        tpu->pdev = pdev;
 415
 416        /* Initialize device configuration from platform data. */
 417        tpu_parse_pdata(tpu);
 418
 419        /* Map memory, get clock and pin control. */
 420        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 421        tpu->base = devm_ioremap_resource(&pdev->dev, res);
 422        if (IS_ERR(tpu->base))
 423                return PTR_ERR(tpu->base);
 424
 425        tpu->clk = devm_clk_get(&pdev->dev, NULL);
 426        if (IS_ERR(tpu->clk)) {
 427                dev_err(&pdev->dev, "cannot get clock\n");
 428                return PTR_ERR(tpu->clk);
 429        }
 430
 431        /* Initialize and register the device. */
 432        platform_set_drvdata(pdev, tpu);
 433
 434        tpu->chip.dev = &pdev->dev;
 435        tpu->chip.ops = &tpu_pwm_ops;
 436        tpu->chip.of_xlate = of_pwm_xlate_with_flags;
 437        tpu->chip.of_pwm_n_cells = 3;
 438        tpu->chip.base = -1;
 439        tpu->chip.npwm = TPU_CHANNEL_MAX;
 440
 441        ret = pwmchip_add(&tpu->chip);
 442        if (ret < 0) {
 443                dev_err(&pdev->dev, "failed to register PWM chip\n");
 444                return ret;
 445        }
 446
 447        dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id);
 448
 449        pm_runtime_enable(&pdev->dev);
 450
 451        return 0;
 452}
 453
 454static int tpu_remove(struct platform_device *pdev)
 455{
 456        struct tpu_device *tpu = platform_get_drvdata(pdev);
 457        int ret;
 458
 459        ret = pwmchip_remove(&tpu->chip);
 460        if (ret)
 461                return ret;
 462
 463        pm_runtime_disable(&pdev->dev);
 464
 465        return 0;
 466}
 467
 468#ifdef CONFIG_OF
 469static const struct of_device_id tpu_of_table[] = {
 470        { .compatible = "renesas,tpu-r8a73a4", },
 471        { .compatible = "renesas,tpu-r8a7740", },
 472        { .compatible = "renesas,tpu-r8a7790", },
 473        { .compatible = "renesas,tpu-sh7372", },
 474        { .compatible = "renesas,tpu", },
 475        { },
 476};
 477
 478MODULE_DEVICE_TABLE(of, tpu_of_table);
 479#endif
 480
 481static struct platform_driver tpu_driver = {
 482        .probe          = tpu_probe,
 483        .remove         = tpu_remove,
 484        .driver         = {
 485                .name   = "renesas-tpu-pwm",
 486                .owner  = THIS_MODULE,
 487                .of_match_table = of_match_ptr(tpu_of_table),
 488        }
 489};
 490
 491module_platform_driver(tpu_driver);
 492
 493MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 494MODULE_DESCRIPTION("Renesas TPU PWM Driver");
 495MODULE_LICENSE("GPL v2");
 496MODULE_ALIAS("platform:renesas-tpu-pwm");
 497
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.