linux/drivers/pinctrl/pinctrl-tegra20.c
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   1/*
   2 * Pinctrl data for the NVIDIA Tegra20 pinmux
   3 *
   4 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * Derived from code:
   7 * Copyright (C) 2010 Google, Inc.
   8 * Copyright (C) 2010 NVIDIA Corporation
   9 *
  10 * This program is free software; you can redistribute it and/or modify it
  11 * under the terms and conditions of the GNU General Public License,
  12 * version 2, as published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope it will be useful, but WITHOUT
  15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17 * more details.
  18 */
  19
  20#include <linux/module.h>
  21#include <linux/of.h>
  22#include <linux/platform_device.h>
  23#include <linux/pinctrl/pinctrl.h>
  24#include <linux/pinctrl/pinmux.h>
  25
  26#include "pinctrl-tegra.h"
  27
  28/*
  29 * Most pins affected by the pinmux can also be GPIOs. Define these first.
  30 * These must match how the GPIO driver names/numbers its pins.
  31 */
  32#define _GPIO(offset)                   (offset)
  33
  34#define TEGRA_PIN_VI_GP6_PA0            _GPIO(0)
  35#define TEGRA_PIN_UART3_CTS_N_PA1       _GPIO(1)
  36#define TEGRA_PIN_DAP2_FS_PA2           _GPIO(2)
  37#define TEGRA_PIN_DAP2_SCLK_PA3         _GPIO(3)
  38#define TEGRA_PIN_DAP2_DIN_PA4          _GPIO(4)
  39#define TEGRA_PIN_DAP2_DOUT_PA5         _GPIO(5)
  40#define TEGRA_PIN_SDIO3_CLK_PA6         _GPIO(6)
  41#define TEGRA_PIN_SDIO3_CMD_PA7         _GPIO(7)
  42#define TEGRA_PIN_GMI_AD17_PB0          _GPIO(8)
  43#define TEGRA_PIN_GMI_AD18_PB1          _GPIO(9)
  44#define TEGRA_PIN_LCD_PWR0_PB2          _GPIO(10)
  45#define TEGRA_PIN_LCD_PCLK_PB3          _GPIO(11)
  46#define TEGRA_PIN_SDIO3_DAT3_PB4        _GPIO(12)
  47#define TEGRA_PIN_SDIO3_DAT2_PB5        _GPIO(13)
  48#define TEGRA_PIN_SDIO3_DAT1_PB6        _GPIO(14)
  49#define TEGRA_PIN_SDIO3_DAT0_PB7        _GPIO(15)
  50#define TEGRA_PIN_UART3_RTS_N_PC0       _GPIO(16)
  51#define TEGRA_PIN_LCD_PWR1_PC1          _GPIO(17)
  52#define TEGRA_PIN_UART2_TXD_PC2         _GPIO(18)
  53#define TEGRA_PIN_UART2_RXD_PC3         _GPIO(19)
  54#define TEGRA_PIN_GEN1_I2C_SCL_PC4      _GPIO(20)
  55#define TEGRA_PIN_GEN1_I2C_SDA_PC5      _GPIO(21)
  56#define TEGRA_PIN_LCD_PWR2_PC6          _GPIO(22)
  57#define TEGRA_PIN_GMI_WP_N_PC7          _GPIO(23)
  58#define TEGRA_PIN_SDIO3_DAT5_PD0        _GPIO(24)
  59#define TEGRA_PIN_SDIO3_DAT4_PD1        _GPIO(25)
  60#define TEGRA_PIN_VI_GP5_PD2            _GPIO(26)
  61#define TEGRA_PIN_SDIO3_DAT6_PD3        _GPIO(27)
  62#define TEGRA_PIN_SDIO3_DAT7_PD4        _GPIO(28)
  63#define TEGRA_PIN_VI_D1_PD5             _GPIO(29)
  64#define TEGRA_PIN_VI_VSYNC_PD6          _GPIO(30)
  65#define TEGRA_PIN_VI_HSYNC_PD7          _GPIO(31)
  66#define TEGRA_PIN_LCD_D0_PE0            _GPIO(32)
  67#define TEGRA_PIN_LCD_D1_PE1            _GPIO(33)
  68#define TEGRA_PIN_LCD_D2_PE2            _GPIO(34)
  69#define TEGRA_PIN_LCD_D3_PE3            _GPIO(35)
  70#define TEGRA_PIN_LCD_D4_PE4            _GPIO(36)
  71#define TEGRA_PIN_LCD_D5_PE5            _GPIO(37)
  72#define TEGRA_PIN_LCD_D6_PE6            _GPIO(38)
  73#define TEGRA_PIN_LCD_D7_PE7            _GPIO(39)
  74#define TEGRA_PIN_LCD_D8_PF0            _GPIO(40)
  75#define TEGRA_PIN_LCD_D9_PF1            _GPIO(41)
  76#define TEGRA_PIN_LCD_D10_PF2           _GPIO(42)
  77#define TEGRA_PIN_LCD_D11_PF3           _GPIO(43)
  78#define TEGRA_PIN_LCD_D12_PF4           _GPIO(44)
  79#define TEGRA_PIN_LCD_D13_PF5           _GPIO(45)
  80#define TEGRA_PIN_LCD_D14_PF6           _GPIO(46)
  81#define TEGRA_PIN_LCD_D15_PF7           _GPIO(47)
  82#define TEGRA_PIN_GMI_AD0_PG0           _GPIO(48)
  83#define TEGRA_PIN_GMI_AD1_PG1           _GPIO(49)
  84#define TEGRA_PIN_GMI_AD2_PG2           _GPIO(50)
  85#define TEGRA_PIN_GMI_AD3_PG3           _GPIO(51)
  86#define TEGRA_PIN_GMI_AD4_PG4           _GPIO(52)
  87#define TEGRA_PIN_GMI_AD5_PG5           _GPIO(53)
  88#define TEGRA_PIN_GMI_AD6_PG6           _GPIO(54)
  89#define TEGRA_PIN_GMI_AD7_PG7           _GPIO(55)
  90#define TEGRA_PIN_GMI_AD8_PH0           _GPIO(56)
  91#define TEGRA_PIN_GMI_AD9_PH1           _GPIO(57)
  92#define TEGRA_PIN_GMI_AD10_PH2          _GPIO(58)
  93#define TEGRA_PIN_GMI_AD11_PH3          _GPIO(59)
  94#define TEGRA_PIN_GMI_AD12_PH4          _GPIO(60)
  95#define TEGRA_PIN_GMI_AD13_PH5          _GPIO(61)
  96#define TEGRA_PIN_GMI_AD14_PH6          _GPIO(62)
  97#define TEGRA_PIN_GMI_AD15_PH7          _GPIO(63)
  98#define TEGRA_PIN_GMI_HIOW_N_PI0        _GPIO(64)
  99#define TEGRA_PIN_GMI_HIOR_N_PI1        _GPIO(65)
 100#define TEGRA_PIN_GMI_CS5_N_PI2         _GPIO(66)
 101#define TEGRA_PIN_GMI_CS6_N_PI3         _GPIO(67)
 102#define TEGRA_PIN_GMI_RST_N_PI4         _GPIO(68)
 103#define TEGRA_PIN_GMI_IORDY_PI5         _GPIO(69)
 104#define TEGRA_PIN_GMI_CS7_N_PI6         _GPIO(70)
 105#define TEGRA_PIN_GMI_WAIT_PI7          _GPIO(71)
 106#define TEGRA_PIN_GMI_CS0_N_PJ0         _GPIO(72)
 107#define TEGRA_PIN_LCD_DE_PJ1            _GPIO(73)
 108#define TEGRA_PIN_GMI_CS1_N_PJ2         _GPIO(74)
 109#define TEGRA_PIN_LCD_HSYNC_PJ3         _GPIO(75)
 110#define TEGRA_PIN_LCD_VSYNC_PJ4         _GPIO(76)
 111#define TEGRA_PIN_UART2_CTS_N_PJ5       _GPIO(77)
 112#define TEGRA_PIN_UART2_RTS_N_PJ6       _GPIO(78)
 113#define TEGRA_PIN_GMI_AD16_PJ7          _GPIO(79)
 114#define TEGRA_PIN_GMI_ADV_N_PK0         _GPIO(80)
 115#define TEGRA_PIN_GMI_CLK_PK1           _GPIO(81)
 116#define TEGRA_PIN_GMI_CS4_N_PK2         _GPIO(82)
 117#define TEGRA_PIN_GMI_CS2_N_PK3         _GPIO(83)
 118#define TEGRA_PIN_GMI_CS3_N_PK4         _GPIO(84)
 119#define TEGRA_PIN_SPDIF_OUT_PK5         _GPIO(85)
 120#define TEGRA_PIN_SPDIF_IN_PK6          _GPIO(86)
 121#define TEGRA_PIN_GMI_AD19_PK7          _GPIO(87)
 122#define TEGRA_PIN_VI_D2_PL0             _GPIO(88)
 123#define TEGRA_PIN_VI_D3_PL1             _GPIO(89)
 124#define TEGRA_PIN_VI_D4_PL2             _GPIO(90)
 125#define TEGRA_PIN_VI_D5_PL3             _GPIO(91)
 126#define TEGRA_PIN_VI_D6_PL4             _GPIO(92)
 127#define TEGRA_PIN_VI_D7_PL5             _GPIO(93)
 128#define TEGRA_PIN_VI_D8_PL6             _GPIO(94)
 129#define TEGRA_PIN_VI_D9_PL7             _GPIO(95)
 130#define TEGRA_PIN_LCD_D16_PM0           _GPIO(96)
 131#define TEGRA_PIN_LCD_D17_PM1           _GPIO(97)
 132#define TEGRA_PIN_LCD_D18_PM2           _GPIO(98)
 133#define TEGRA_PIN_LCD_D19_PM3           _GPIO(99)
 134#define TEGRA_PIN_LCD_D20_PM4           _GPIO(100)
 135#define TEGRA_PIN_LCD_D21_PM5           _GPIO(101)
 136#define TEGRA_PIN_LCD_D22_PM6           _GPIO(102)
 137#define TEGRA_PIN_LCD_D23_PM7           _GPIO(103)
 138#define TEGRA_PIN_DAP1_FS_PN0           _GPIO(104)
 139#define TEGRA_PIN_DAP1_DIN_PN1          _GPIO(105)
 140#define TEGRA_PIN_DAP1_DOUT_PN2         _GPIO(106)
 141#define TEGRA_PIN_DAP1_SCLK_PN3         _GPIO(107)
 142#define TEGRA_PIN_LCD_CS0_N_PN4         _GPIO(108)
 143#define TEGRA_PIN_LCD_SDOUT_PN5         _GPIO(109)
 144#define TEGRA_PIN_LCD_DC0_PN6           _GPIO(110)
 145#define TEGRA_PIN_HDMI_INT_N_PN7        _GPIO(111)
 146#define TEGRA_PIN_ULPI_DATA7_PO0        _GPIO(112)
 147#define TEGRA_PIN_ULPI_DATA0_PO1        _GPIO(113)
 148#define TEGRA_PIN_ULPI_DATA1_PO2        _GPIO(114)
 149#define TEGRA_PIN_ULPI_DATA2_PO3        _GPIO(115)
 150#define TEGRA_PIN_ULPI_DATA3_PO4        _GPIO(116)
 151#define TEGRA_PIN_ULPI_DATA4_PO5        _GPIO(117)
 152#define TEGRA_PIN_ULPI_DATA5_PO6        _GPIO(118)
 153#define TEGRA_PIN_ULPI_DATA6_PO7        _GPIO(119)
 154#define TEGRA_PIN_DAP3_FS_PP0           _GPIO(120)
 155#define TEGRA_PIN_DAP3_DIN_PP1          _GPIO(121)
 156#define TEGRA_PIN_DAP3_DOUT_PP2         _GPIO(122)
 157#define TEGRA_PIN_DAP3_SCLK_PP3         _GPIO(123)
 158#define TEGRA_PIN_DAP4_FS_PP4           _GPIO(124)
 159#define TEGRA_PIN_DAP4_DIN_PP5          _GPIO(125)
 160#define TEGRA_PIN_DAP4_DOUT_PP6         _GPIO(126)
 161#define TEGRA_PIN_DAP4_SCLK_PP7         _GPIO(127)
 162#define TEGRA_PIN_KB_COL0_PQ0           _GPIO(128)
 163#define TEGRA_PIN_KB_COL1_PQ1           _GPIO(129)
 164#define TEGRA_PIN_KB_COL2_PQ2           _GPIO(130)
 165#define TEGRA_PIN_KB_COL3_PQ3           _GPIO(131)
 166#define TEGRA_PIN_KB_COL4_PQ4           _GPIO(132)
 167#define TEGRA_PIN_KB_COL5_PQ5           _GPIO(133)
 168#define TEGRA_PIN_KB_COL6_PQ6           _GPIO(134)
 169#define TEGRA_PIN_KB_COL7_PQ7           _GPIO(135)
 170#define TEGRA_PIN_KB_ROW0_PR0           _GPIO(136)
 171#define TEGRA_PIN_KB_ROW1_PR1           _GPIO(137)
 172#define TEGRA_PIN_KB_ROW2_PR2           _GPIO(138)
 173#define TEGRA_PIN_KB_ROW3_PR3           _GPIO(139)
 174#define TEGRA_PIN_KB_ROW4_PR4           _GPIO(140)
 175#define TEGRA_PIN_KB_ROW5_PR5           _GPIO(141)
 176#define TEGRA_PIN_KB_ROW6_PR6           _GPIO(142)
 177#define TEGRA_PIN_KB_ROW7_PR7           _GPIO(143)
 178#define TEGRA_PIN_KB_ROW8_PS0           _GPIO(144)
 179#define TEGRA_PIN_KB_ROW9_PS1           _GPIO(145)
 180#define TEGRA_PIN_KB_ROW10_PS2          _GPIO(146)
 181#define TEGRA_PIN_KB_ROW11_PS3          _GPIO(147)
 182#define TEGRA_PIN_KB_ROW12_PS4          _GPIO(148)
 183#define TEGRA_PIN_KB_ROW13_PS5          _GPIO(149)
 184#define TEGRA_PIN_KB_ROW14_PS6          _GPIO(150)
 185#define TEGRA_PIN_KB_ROW15_PS7          _GPIO(151)
 186#define TEGRA_PIN_VI_PCLK_PT0           _GPIO(152)
 187#define TEGRA_PIN_VI_MCLK_PT1           _GPIO(153)
 188#define TEGRA_PIN_VI_D10_PT2            _GPIO(154)
 189#define TEGRA_PIN_VI_D11_PT3            _GPIO(155)
 190#define TEGRA_PIN_VI_D0_PT4             _GPIO(156)
 191#define TEGRA_PIN_GEN2_I2C_SCL_PT5      _GPIO(157)
 192#define TEGRA_PIN_GEN2_I2C_SDA_PT6      _GPIO(158)
 193#define TEGRA_PIN_GMI_DPD_PT7           _GPIO(159)
 194#define TEGRA_PIN_PU0                   _GPIO(160)
 195#define TEGRA_PIN_PU1                   _GPIO(161)
 196#define TEGRA_PIN_PU2                   _GPIO(162)
 197#define TEGRA_PIN_PU3                   _GPIO(163)
 198#define TEGRA_PIN_PU4                   _GPIO(164)
 199#define TEGRA_PIN_PU5                   _GPIO(165)
 200#define TEGRA_PIN_PU6                   _GPIO(166)
 201#define TEGRA_PIN_JTAG_RTCK_PU7         _GPIO(167)
 202#define TEGRA_PIN_PV0                   _GPIO(168)
 203#define TEGRA_PIN_PV1                   _GPIO(169)
 204#define TEGRA_PIN_PV2                   _GPIO(170)
 205#define TEGRA_PIN_PV3                   _GPIO(171)
 206#define TEGRA_PIN_PV4                   _GPIO(172)
 207#define TEGRA_PIN_PV5                   _GPIO(173)
 208#define TEGRA_PIN_PV6                   _GPIO(174)
 209#define TEGRA_PIN_LCD_DC1_PV7           _GPIO(175)
 210#define TEGRA_PIN_LCD_CS1_N_PW0         _GPIO(176)
 211#define TEGRA_PIN_LCD_M1_PW1            _GPIO(177)
 212#define TEGRA_PIN_SPI2_CS1_N_PW2        _GPIO(178)
 213#define TEGRA_PIN_SPI2_CS2_N_PW3        _GPIO(179)
 214#define TEGRA_PIN_DAP_MCLK1_PW4         _GPIO(180)
 215#define TEGRA_PIN_DAP_MCLK2_PW5         _GPIO(181)
 216#define TEGRA_PIN_UART3_TXD_PW6         _GPIO(182)
 217#define TEGRA_PIN_UART3_RXD_PW7         _GPIO(183)
 218#define TEGRA_PIN_SPI2_MOSI_PX0         _GPIO(184)
 219#define TEGRA_PIN_SPI2_MISO_PX1         _GPIO(185)
 220#define TEGRA_PIN_SPI2_SCK_PX2          _GPIO(186)
 221#define TEGRA_PIN_SPI2_CS0_N_PX3        _GPIO(187)
 222#define TEGRA_PIN_SPI1_MOSI_PX4         _GPIO(188)
 223#define TEGRA_PIN_SPI1_SCK_PX5          _GPIO(189)
 224#define TEGRA_PIN_SPI1_CS0_N_PX6        _GPIO(190)
 225#define TEGRA_PIN_SPI1_MISO_PX7         _GPIO(191)
 226#define TEGRA_PIN_ULPI_CLK_PY0          _GPIO(192)
 227#define TEGRA_PIN_ULPI_DIR_PY1          _GPIO(193)
 228#define TEGRA_PIN_ULPI_NXT_PY2          _GPIO(194)
 229#define TEGRA_PIN_ULPI_STP_PY3          _GPIO(195)
 230#define TEGRA_PIN_SDIO1_DAT3_PY4        _GPIO(196)
 231#define TEGRA_PIN_SDIO1_DAT2_PY5        _GPIO(197)
 232#define TEGRA_PIN_SDIO1_DAT1_PY6        _GPIO(198)
 233#define TEGRA_PIN_SDIO1_DAT0_PY7        _GPIO(199)
 234#define TEGRA_PIN_SDIO1_CLK_PZ0         _GPIO(200)
 235#define TEGRA_PIN_SDIO1_CMD_PZ1         _GPIO(201)
 236#define TEGRA_PIN_LCD_SDIN_PZ2          _GPIO(202)
 237#define TEGRA_PIN_LCD_WR_N_PZ3          _GPIO(203)
 238#define TEGRA_PIN_LCD_SCK_PZ4           _GPIO(204)
 239#define TEGRA_PIN_SYS_CLK_REQ_PZ5       _GPIO(205)
 240#define TEGRA_PIN_PWR_I2C_SCL_PZ6       _GPIO(206)
 241#define TEGRA_PIN_PWR_I2C_SDA_PZ7       _GPIO(207)
 242#define TEGRA_PIN_GMI_AD20_PAA0         _GPIO(208)
 243#define TEGRA_PIN_GMI_AD21_PAA1         _GPIO(209)
 244#define TEGRA_PIN_GMI_AD22_PAA2         _GPIO(210)
 245#define TEGRA_PIN_GMI_AD23_PAA3         _GPIO(211)
 246#define TEGRA_PIN_GMI_AD24_PAA4         _GPIO(212)
 247#define TEGRA_PIN_GMI_AD25_PAA5         _GPIO(213)
 248#define TEGRA_PIN_GMI_AD26_PAA6         _GPIO(214)
 249#define TEGRA_PIN_GMI_AD27_PAA7         _GPIO(215)
 250#define TEGRA_PIN_LED_BLINK_PBB0        _GPIO(216)
 251#define TEGRA_PIN_VI_GP0_PBB1           _GPIO(217)
 252#define TEGRA_PIN_CAM_I2C_SCL_PBB2      _GPIO(218)
 253#define TEGRA_PIN_CAM_I2C_SDA_PBB3      _GPIO(219)
 254#define TEGRA_PIN_VI_GP3_PBB4           _GPIO(220)
 255#define TEGRA_PIN_VI_GP4_PBB5           _GPIO(221)
 256#define TEGRA_PIN_PBB6                  _GPIO(222)
 257#define TEGRA_PIN_PBB7                  _GPIO(223)
 258
 259/* All non-GPIO pins follow */
 260#define NUM_GPIOS                       (TEGRA_PIN_PBB7 + 1)
 261#define _PIN(offset)                    (NUM_GPIOS + (offset))
 262
 263#define TEGRA_PIN_CRT_HSYNC             _PIN(30)
 264#define TEGRA_PIN_CRT_VSYNC             _PIN(31)
 265#define TEGRA_PIN_DDC_SCL               _PIN(32)
 266#define TEGRA_PIN_DDC_SDA               _PIN(33)
 267#define TEGRA_PIN_OWC                   _PIN(34)
 268#define TEGRA_PIN_CORE_PWR_REQ          _PIN(35)
 269#define TEGRA_PIN_CPU_PWR_REQ           _PIN(36)
 270#define TEGRA_PIN_PWR_INT_N             _PIN(37)
 271#define TEGRA_PIN_CLK_32_K_IN           _PIN(38)
 272#define TEGRA_PIN_DDR_COMP_PD           _PIN(39)
 273#define TEGRA_PIN_DDR_COMP_PU           _PIN(40)
 274#define TEGRA_PIN_DDR_A0                _PIN(41)
 275#define TEGRA_PIN_DDR_A1                _PIN(42)
 276#define TEGRA_PIN_DDR_A2                _PIN(43)
 277#define TEGRA_PIN_DDR_A3                _PIN(44)
 278#define TEGRA_PIN_DDR_A4                _PIN(45)
 279#define TEGRA_PIN_DDR_A5                _PIN(46)
 280#define TEGRA_PIN_DDR_A6                _PIN(47)
 281#define TEGRA_PIN_DDR_A7                _PIN(48)
 282#define TEGRA_PIN_DDR_A8                _PIN(49)
 283#define TEGRA_PIN_DDR_A9                _PIN(50)
 284#define TEGRA_PIN_DDR_A10               _PIN(51)
 285#define TEGRA_PIN_DDR_A11               _PIN(52)
 286#define TEGRA_PIN_DDR_A12               _PIN(53)
 287#define TEGRA_PIN_DDR_A13               _PIN(54)
 288#define TEGRA_PIN_DDR_A14               _PIN(55)
 289#define TEGRA_PIN_DDR_CAS_N             _PIN(56)
 290#define TEGRA_PIN_DDR_BA0               _PIN(57)
 291#define TEGRA_PIN_DDR_BA1               _PIN(58)
 292#define TEGRA_PIN_DDR_BA2               _PIN(59)
 293#define TEGRA_PIN_DDR_DQS0P             _PIN(60)
 294#define TEGRA_PIN_DDR_DQS0N             _PIN(61)
 295#define TEGRA_PIN_DDR_DQS1P             _PIN(62)
 296#define TEGRA_PIN_DDR_DQS1N             _PIN(63)
 297#define TEGRA_PIN_DDR_DQS2P             _PIN(64)
 298#define TEGRA_PIN_DDR_DQS2N             _PIN(65)
 299#define TEGRA_PIN_DDR_DQS3P             _PIN(66)
 300#define TEGRA_PIN_DDR_DQS3N             _PIN(67)
 301#define TEGRA_PIN_DDR_CKE0              _PIN(68)
 302#define TEGRA_PIN_DDR_CKE1              _PIN(69)
 303#define TEGRA_PIN_DDR_CLK               _PIN(70)
 304#define TEGRA_PIN_DDR_CLK_N             _PIN(71)
 305#define TEGRA_PIN_DDR_DM0               _PIN(72)
 306#define TEGRA_PIN_DDR_DM1               _PIN(73)
 307#define TEGRA_PIN_DDR_DM2               _PIN(74)
 308#define TEGRA_PIN_DDR_DM3               _PIN(75)
 309#define TEGRA_PIN_DDR_ODT               _PIN(76)
 310#define TEGRA_PIN_DDR_QUSE0             _PIN(77)
 311#define TEGRA_PIN_DDR_QUSE1             _PIN(78)
 312#define TEGRA_PIN_DDR_QUSE2             _PIN(79)
 313#define TEGRA_PIN_DDR_QUSE3             _PIN(80)
 314#define TEGRA_PIN_DDR_RAS_N             _PIN(81)
 315#define TEGRA_PIN_DDR_WE_N              _PIN(82)
 316#define TEGRA_PIN_DDR_DQ0               _PIN(83)
 317#define TEGRA_PIN_DDR_DQ1               _PIN(84)
 318#define TEGRA_PIN_DDR_DQ2               _PIN(85)
 319#define TEGRA_PIN_DDR_DQ3               _PIN(86)
 320#define TEGRA_PIN_DDR_DQ4               _PIN(87)
 321#define TEGRA_PIN_DDR_DQ5               _PIN(88)
 322#define TEGRA_PIN_DDR_DQ6               _PIN(89)
 323#define TEGRA_PIN_DDR_DQ7               _PIN(90)
 324#define TEGRA_PIN_DDR_DQ8               _PIN(91)
 325#define TEGRA_PIN_DDR_DQ9               _PIN(92)
 326#define TEGRA_PIN_DDR_DQ10              _PIN(93)
 327#define TEGRA_PIN_DDR_DQ11              _PIN(94)
 328#define TEGRA_PIN_DDR_DQ12              _PIN(95)
 329#define TEGRA_PIN_DDR_DQ13              _PIN(96)
 330#define TEGRA_PIN_DDR_DQ14              _PIN(97)
 331#define TEGRA_PIN_DDR_DQ15              _PIN(98)
 332#define TEGRA_PIN_DDR_DQ16              _PIN(99)
 333#define TEGRA_PIN_DDR_DQ17              _PIN(100)
 334#define TEGRA_PIN_DDR_DQ18              _PIN(101)
 335#define TEGRA_PIN_DDR_DQ19              _PIN(102)
 336#define TEGRA_PIN_DDR_DQ20              _PIN(103)
 337#define TEGRA_PIN_DDR_DQ21              _PIN(104)
 338#define TEGRA_PIN_DDR_DQ22              _PIN(105)
 339#define TEGRA_PIN_DDR_DQ23              _PIN(106)
 340#define TEGRA_PIN_DDR_DQ24              _PIN(107)
 341#define TEGRA_PIN_DDR_DQ25              _PIN(108)
 342#define TEGRA_PIN_DDR_DQ26              _PIN(109)
 343#define TEGRA_PIN_DDR_DQ27              _PIN(110)
 344#define TEGRA_PIN_DDR_DQ28              _PIN(111)
 345#define TEGRA_PIN_DDR_DQ29              _PIN(112)
 346#define TEGRA_PIN_DDR_DQ30              _PIN(113)
 347#define TEGRA_PIN_DDR_DQ31              _PIN(114)
 348#define TEGRA_PIN_DDR_CS0_N             _PIN(115)
 349#define TEGRA_PIN_DDR_CS1_N             _PIN(116)
 350#define TEGRA_PIN_SYS_RESET             _PIN(117)
 351#define TEGRA_PIN_JTAG_TRST_N           _PIN(118)
 352#define TEGRA_PIN_JTAG_TDO              _PIN(119)
 353#define TEGRA_PIN_JTAG_TMS              _PIN(120)
 354#define TEGRA_PIN_JTAG_TCK              _PIN(121)
 355#define TEGRA_PIN_JTAG_TDI              _PIN(122)
 356#define TEGRA_PIN_TEST_MODE_EN          _PIN(123)
 357
 358static const struct pinctrl_pin_desc tegra20_pins[] = {
 359        PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
 360        PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 361        PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 362        PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 363        PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 364        PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 365        PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
 366        PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
 367        PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
 368        PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
 369        PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
 370        PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
 371        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
 372        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
 373        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
 374        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
 375        PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 376        PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
 377        PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 378        PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 379        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 380        PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 381        PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
 382        PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
 383        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
 384        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
 385        PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
 386        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
 387        PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
 388        PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
 389        PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
 390        PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
 391        PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
 392        PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
 393        PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
 394        PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
 395        PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
 396        PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
 397        PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
 398        PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
 399        PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
 400        PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
 401        PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
 402        PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
 403        PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
 404        PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
 405        PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
 406        PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
 407        PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
 408        PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
 409        PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
 410        PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
 411        PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
 412        PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
 413        PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
 414        PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
 415        PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
 416        PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
 417        PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
 418        PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
 419        PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
 420        PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
 421        PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
 422        PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
 423        PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
 424        PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
 425        PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
 426        PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
 427        PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
 428        PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
 429        PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
 430        PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
 431        PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
 432        PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
 433        PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
 434        PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
 435        PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
 436        PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 437        PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 438        PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
 439        PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
 440        PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
 441        PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
 442        PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
 443        PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
 444        PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 445        PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 446        PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
 447        PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
 448        PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
 449        PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
 450        PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
 451        PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
 452        PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
 453        PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
 454        PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
 455        PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
 456        PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
 457        PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
 458        PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
 459        PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
 460        PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
 461        PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
 462        PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
 463        PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 464        PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 465        PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 466        PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 467        PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
 468        PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
 469        PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
 470        PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
 471        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 472        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 473        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 474        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 475        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 476        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 477        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 478        PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 479        PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 480        PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 481        PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 482        PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 483        PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 484        PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 485        PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 486        PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 487        PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 488        PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 489        PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 490        PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 491        PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 492        PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 493        PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 494        PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 495        PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 496        PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 497        PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 498        PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 499        PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 500        PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 501        PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 502        PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 503        PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 504        PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 505        PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 506        PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
 507        PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
 508        PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
 509        PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
 510        PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
 511        PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
 512        PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
 513        PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
 514        PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
 515        PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
 516        PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 517        PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 518        PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
 519        /* PU0..6: GPIO only */
 520        PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 521        PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 522        PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 523        PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 524        PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 525        PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 526        PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 527        PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
 528        /* PV0..1: GPIO only */
 529        PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 530        PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 531        /* PV2..3: Balls are named after GPIO not function */
 532        PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
 533        PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
 534        /* PV4..6: GPIO only */
 535        PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
 536        PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
 537        PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
 538        PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
 539        PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
 540        PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
 541        PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
 542        PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
 543        PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 544        PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
 545        PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 546        PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 547        PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
 548        PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
 549        PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
 550        PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
 551        PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
 552        PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
 553        PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
 554        PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
 555        PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 556        PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 557        PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 558        PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 559        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
 560        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
 561        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
 562        PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
 563        PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
 564        PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
 565        PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
 566        PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
 567        PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
 568        PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
 569        PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 570        PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 571        PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
 572        PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
 573        PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
 574        PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
 575        PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
 576        PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
 577        PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
 578        PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
 579        PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
 580        PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
 581        PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
 582        PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
 583        PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
 584        PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
 585        PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 586        PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 587        PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
 588        PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
 589        PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
 590        PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
 591        PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
 592        PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 593        PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 594        PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 595        PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
 596        PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
 597        PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
 598        PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
 599        PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
 600        PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
 601        PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
 602        PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
 603        PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
 604        PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
 605        PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
 606        PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
 607        PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
 608        PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
 609        PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
 610        PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
 611        PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
 612        PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
 613        PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
 614        PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
 615        PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
 616        PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
 617        PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
 618        PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
 619        PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
 620        PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
 621        PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
 622        PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
 623        PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
 624        PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
 625        PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
 626        PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
 627        PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
 628        PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
 629        PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
 66L630" id="L630" class="line" name="L630"> c#L628" id="L628" class="line" name="L628"> 62f="drivers/pinctrl/pinctrl-tegra20.c#L619" id="L619" class=tegs="string">"DDR_DM0"),
 531   6    <63href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"),
 532   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"),
 533   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"ODT 534   6    <63href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"QUS>T 535   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(gs="string">"DDR_DM0"QUS>
 536   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"QUS>
 537   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN("DDR_DM0"QUS>
 538   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(Rf">TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
 539   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, Ts="string">"DDR_CAS_N"T 540   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0")QT 541   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Qgra20.c#L619" id="L619" class=tQgs="string">"DDR_DM0")Q
 542   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_BA2, "DDR_DM0")Q
 543   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A13, "DDR_DM0")Q
 544   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A14, "DDR_DM0")Q
 545   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A5, "DDR_DM0")Q
 546   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A6, "DDR_DM0")Q
 547   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A7, "DDR_DM0")Q
 548   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A8, "DDR_DM0")Q
 549   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QTEGRA_PIN_DDR_A9, "DDR_DM0")Q
 550   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q
TEGRA_PIN_DDR_DM0, "DDR_A10"lQas 551   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(lQagra20.c#L619" id="L619" class=tQggs="string">"DDR_DM0")Q

 552   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q
TEGRA_PIN_DDR_BA2, "DDR_A12"eQas 553   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(eQaTEGRA_PIN_DDR_A13, "DDR_A13")Qas 554   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QaTEGRA_PIN_DDR_A14, "DDR_A14")Qas 555   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()QaTEGRA_PIN_DDR_A5, "DDR_DM0")Q1
 556   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q1TEGRA_PIN_DDR_A6, "DDR_DM0")Q1
 557   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q1TEGRA_PIN_DDR_A7, "DDR_DM0")Q1
 558   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q1TEGRA_PIN_DDR_A8, "DDR_DM0")Q1
 559   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q1TEGRA_PIN_DDR_A9, "DDR_DM0")Q1
 560   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q
TEGRA_PIN_DDR_DM0, "DDR_A10"lQ2s 561   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(lQ2gra20.c#L619" id="L619" class=tQ2gs="string">"DDR_DM0")Q2
 562   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_BA2, "DDR_DM0")Q
s 563   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q
TEGRA_PIN_DDR_A13, "DDR_A13")Q2s 564   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A14, "DDR_A14")Q2s 565   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A5, "DDR_DM0")Q2
 566   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A6, "DDR_DM0")Q2
 567   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A7, "DDR_DM0")Q2
 568   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A8, "DDR_DM0")Q2
 569   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q2TEGRA_PIN_DDR_A9, "DDR_DM0")Q2
 570   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN()Q
TEGRA_PIN_DDR_DM0, "DDR_A10"lQ3s 571   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(lQ3gra20.c#L619" id="L619" class=tQ3gs="string">"DDR_DM0")Q3
 572   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(CS0>TEGRA_PIN_DDR_CLK_N, Ts="string">"DDR_DM0" S0>T 573   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN( S1>TEGRA_PIN_DDR_CLK_N, Ts="string">"DDR_DM0" S1>T 574   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(, "DDR_DM0" 575   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, Ts="string">"DDR_DM0"T 576   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(, "DDR_DM0" 577   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(, "DDR_DM0" 578   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(, "DDR_DM0" 579   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(, "DDR_DM0" 580   6    <6 href="+code=PINCTRL_PIN" class="sref">PINCTRL_PIN(MODE_ETEGRA_PIN_PWR_INT_N, MODE_ETs="string">"DDR_DM0"MODE_ET 581   6    <6 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L582"> 582   6    <6 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L583"> 583   6    <6 href=static const unsignedPINCTRL_PIN" claata_c#LsEGRA_PIN_PWR_INata_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L584"> 584   6    <6 href="+code=PINCTRL_PIN" claT_N, ,TEGRA_PIN_GMI_AD23_PAA3, ,Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L585"> 585   6    <6 href="+code=PINCTRL_PIN" cla23_PAA3, ,TEGRA_PIN_GMI_AD26_PAA6, ,Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L586"> 586   6    <6 href="+code=PINCTRL_PIN" cla26_PAA6, TA6, TA6 587   6    <6 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L588"> 588   6    <6 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L589"> 589   6    <6 href=static const unsignedPINCTRL_PIN" claatb_c#LsEGRA_PIN_PWR_INatb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L590"> 590   6    <6 href="+code=PINCTRL_PIN" cla26_PAA6, TA6, TA6 591   6    <6 href="+code=PINCTRL_PIN" cla22_PAA2, ,  592   6    <6 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L593"> 593   6    <6 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L594"> 594   6    <6 href=static const unsignedPINCTRL_PIN" claatc_c#LsEGRA_PIN_PWR_INatc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L595"> 595   6    <6 href="+code=PINCTRL_PIN" cla27_PAA7, , ,  596   6    <6 href="+code=PINCTRL_PIN" cla, , ,  597   6    <6 href="+code=PINCTRL_PIN" cla27_PAA7, TA6KTEGRA_PIN_DDR_DM0, , TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" class="line6 name="L598"> 598   6    <6 href="+code=PINCTRL_PIN" cla22_PAA2, ,  599   6    <6 href="+code=PINCTRL_PIN" cla22_PAA2, TA6KTEGRA_PIN_GMI_AD23_PAA3, TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L600"> 600   7    <7 href="+code=PINCTRL_PIN" cla23_PAA3, TA6KTEGRA_PIN_GMI_AD24_PAA4, TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a1s="line7 name="L591"> 591   7    <7 href="+code=PINCTRL_PIN" cla24_PAA4, TA6KTEGRA_PIN_GMI_AD22_PAA2, TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a2s="line7 name="L592"> 592   7    <7 href="+code=PINCTRL_PIN" cla0, , , ,  593   7    <7 href="+code=PINCTRL_PIN" cla0, , ,  594   7    <7 href="+code=PINCTRL_PIN" cla="L619" cl>, ,  595   7    <7 href="+code=PINCTRL_PIN" cla22_PAA2, ,  596   7    <7 href="+code=PINCTRL_PIN" cla23_PAA3, ,  597   7    <7 href="+code=PINCTRL_PIN" cla24_PAA4, , ,  598   7    <7 href="+code=PINCTRL_PIN" cla, , ,  599   7    <7 href="+code=PINCTRL_PIN" cla26_PAA6, ,  610   7    <7 href="+code=PINCTRL_PIN" cla27_PAA7, TA6, , TA6 611   7    <7 href="+code=PINCTRL_PIN" cla0, , TA6, TA6 612   7    <71href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L613"> 613   7    <71href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L614"> 614   7    <71href=static const unsignedPINCTRL_PIN" claatd_c#LsEGRA_PIN_PWR_INatd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L615"> 615   7    <7 href="+code=PINCTRL_PIN" cla27_PAA7, , ,  616   7    <7 href="+code=PINCTRL_PIN" cla0, , ,  617   7    <7 href="+code=PINCTRL_PIN" cla="L619" cl>, ,  618   7    <7 href="+code=PINCTRL_PIN" cla22_PAA2, ,  619   7    <71Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L620"> 620   7    <72ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a1s="line7 name="L621"> 621   7    <72gs="sstatic const unsignedPINCTRL_PIN" claate_c#LsEGRA_PIN_PWR_INate_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L622"> 622   7    <7 href="+code=PINCTRL_PIN" cla23_PAA3, ,  623   7    <7 href="+code=PINCTRL_PIN" cla24_PAA4, , ,  624   7    <7 href="+code=PINCTRL_PIN" cla, , ,  625   7    <7 href="+code=PINCTRL_PIN" cla26_PAA6, ,  626   7    <72Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a7s="line7 name="L627"> 627   7    <72Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a8s="line7 name="L628"> 628   7    <72Ts="sstatic const unsignedPINCTRL_PIN" clacdev1_c#LsEGRA_PIN_PWR_INcdev1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a9s="line7 name="L629"> 629   7    <7 href="+code=PINCTRL_PIN" claK_N, ,  66L630" id7"L63073ss="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L531"> 531   7    <73gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L532"> 532   7    <7 href=static const unsignedPINCTRL_PIN" clacdev2_c#LsEGRA_PIN_PWR_INcdev2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L533"> 533   7    <7 href="+code=PINCTRL_PIN" cla4, ,  534   7    <73href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L535"> 535   7    <7 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a6s="line7 name="L536"> 536   7    <7 href=static const unsignedPINCTRL_PIN" clacrtp_c#LsEGRA_PIN_PWR_INcrtp_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a7s="line7 name="L537"> 537   7    <7 href="+code=PINCTRL_PIN" cla, ,  538   7    <7 href="+code=PINCTRL_PIN" cla, ,  539   7    <73Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L540"> 540   7    <74ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L541"> 541   7    <74gs="sstatic const unsignedPINCTRL_PIN" clacsus_c#LsEGRA_PIN_PWR_INcsus_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L542"> 542   7    <7 href="+code=PINCTRL_PIN" cla,  543   7    <7 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L544"> 544   7    <7 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L545"> 545   7    <7 href=static const unsignedPINCTRL_PIN" cladap1_c#LsEGRA_PIN_PWR_INdap1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a6s="line7 name="L546"> 546   7    <7 href="+code=PINCTRL_PIN" cla, ,  547   7    <7 href="+code=PINCTRL_PIN" cla0,  548   7    <7 href="+code=PINCTRL_PIN" cla="L619" claAP1_DOUTpPNTEGRA_PIN_DDR_BA2,  549   7    <7 href="+code=PINCTRL_PIN" cla2, ,  550   7    <75ss="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L551"> 551   7    <75gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L552"> 552   7    <75href=static const unsignedPINCTRL_PIN" cladap2_c#LsEGRA_PIN_PWR_INdap2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L553"> 553   7    <7 href="+code=PINCTRL_PIN" cla3, TEGRA_PIN_DDR_BA2, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L554"> 554   7    <7 href="+code=PINCTRL_PIN" cla2, ,  555   7    <7 href="+code=PINCTRL_PIN" cla3, ,  556   7    <7 href="+code=PINCTRL_PIN" cla4, ,  557   7    <75href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L558"> 558   7    <75href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L559"> 559   7    <75href=static const unsignedPINCTRL_PIN" cladap3_c#LsEGRA_PIN_PWR_INdap3_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L560"> 560   7    <7 href="+code=PINCTRL_PIN" cla, ,  561   7    <7 href="+code=PINCTRL_PIN" cla0,  562   7    <7 href="+code=PINCTRL_PIN" cla="L619" claAP3_DOUTpPPTEGRA_PIN_DDR_BA2,  563   7    <7 href="+code=PINCTRL_PIN" cla2, ,  564   7    <76href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L565"> 565   7    <76href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L566"> 566   7    <76href=static const unsignedPINCTRL_PIN" cladap4_c#LsEGRA_PIN_PWR_INdap4_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7a7s="line7 name="L567"> 567   7    <7 href="+code=PINCTRL_PIN" cla3, ,  568   7    <7 href="+code=PINCTRL_PIN" cla4, ,  569   7    <7 href="+code=PINCTRL_PIN" cla, ,  570   7    <7 href="+code=PINCTRL_PIN" cla, ,  571   7    <77href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L572"> 572   7    <77href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L573"> 573   7    <77href=static const unsignedPINCTRL_PIN" claddc_c#LsEGRA_PIN_PWR_INddc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L574"> 574   7    <7 href="+code=PINCTRL_PIN" claK_N, ,  575   7    <7 href="+code=PINCTRL_PIN" cla, ,  576   7    <77Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L577"> 577   7    <77Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L578"> 578   7    <77Ts="sstatic const unsignedPINCTRL_PIN" cladta_c#LsEGRA_PIN_PWR_INdta_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L579"> 579   7    <7 href="+code=PINCTRL_PIN" cla="L619" clVI_D0_PTTEGRA_PIN_DDR_A14,  580   7    <7 href="+code=PINCTRL_PIN" cla4, ,  581   7    <7 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L582"> 582   7    <7 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L583"> 583   7    <7 href=static const unsignedPINCTRL_PIN" cladtb_c#LsEGRA_PIN_PWR_INdtb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L584"> 584   7    <7 href="+code=PINCTRL_PIN" claT_N, ,  585   7    <7 href="+code=PINCTRL_PIN" cla23_PAA3,  586   7    <78Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L587"> 587   7    <78Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L588"> 588   7    <78Ts="sstatic const unsignedPINCTRL_PIN" cladtc_c#LsEGRA_PIN_PWR_INdtc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L589"> 589   7    <78href="+code=PINCTRL_PIN" cla="L619" clVI_HSYNC_PDTEGRA_PIN_DDR_A7,  590   7    <7 href="+code=PINCTRL_PIN" cla26_PAA6,  591   7    <79href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L592"> 592   7    <79href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L593"> 593   7    <79href=static const unsignedPINCTRL_PIN" cladtd_c#LsEGRA_PIN_PWR_INdtd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c7ass="line7 name="L594"> 594   7    <79href="+code=PINCTRL_PIN" claT_N, ,  595   7    <7 href="+code=PINCTRL_PIN" cla27_PAA7,  596   7    <7 href="+code=PINCTRL_PIN" cla,  597   7    <7 href="+code=PINCTRL_PIN" cla27_PAA7,  598   7    <7 href="+code=PINCTRL_PIN" cla22_PAA2,  599   7    <7 href="+code=PINCTRL_PIN" cla22_PAA2,  600   8    <8 href="+code=PINCTRL_PIN" cla23_PAA3,  591   8    <8 href="+code=PINCTRL_PIN" cla24_PAA4,  592   8    <8 href="+code=PINCTRL_PIN" cla0, ,  593   8    <80href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a4s="line8 name="L594"> 594   8    <80href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a5s="line8 name="L595"> 595   8    <80href=static const unsignedPINCTRL_PIN" cladte_c#LsEGRA_PIN_PWR_INdte_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a6s="line8 name="L596"> 596   8    <8 href="+code=PINCTRL_PIN" cla23_PAA3 597   8    <8 href="+code=PINCTRL_PIN" cla24_PAA4,  598   8    <8 href="+code=PINCTRL_PIN" cla, ,  599   8    <8 href="+code=PINCTRL_PIN" cla26_PAA6,  610   8    <8 href="+code=PINCTRL_PIN" cla27_PAA7,  611   8    <81href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a2s="line8 name="L612"> 612   8    <81href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L613"> 613   8    <81href=static const unsignedPINCTRL_PIN" cladtf_c#LsEGRA_PIN_PWR_INdtf_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L614"> 614   8    <81href="+code=PINCTRL_PIN" claT_N, ,  615   8    <8 href="+code=PINCTRL_PIN" cla27_PAA7,  616   8    <81Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L617"> 617   8    <81Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a8s="line8 name="L618"> 618   8    <81Ts="sstatic const unsignedPINCTRL_PIN" clagma_c#LsEGRA_PIN_PWR_INgma_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a9s="line8 name="L619"> 619   8    <81href="+code=PINCTRL_PIN" cla26_PAA6, , ,  620   8    <82href="+code=PINCTRL_PIN" cla27_PAA7, ,  621   8    <82href="+code=PINCTRL_PIN" cla0, , ,  622   8    <8 href="+code=PINCTRL_PIN" cla23_PAA3, ,  623   8    <82href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L624"> 624   8    <82href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L625"> 625   8    <82href=static const unsignedPINCTRL_PIN" clagmb_c#LsEGRA_PIN_PWR_INgmb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a6s="line8 name="L626"> 626   8    <82href="+code=PINCTRL_PIN" cla, , TA6CTEGRA_PIN_GMI_AD27_PAA7, TA6CTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L627"> 627   8    <82href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a8s="line8 name="L628"> 628   8    <82href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a9s="line8 name="L629"> 629   8    <82href=static const unsignedPINCTRL_PIN" clagmc_c#LsEGRA_PIN_PWR_INgmc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L630"> 66L630" id8"L63083href="+code=PINCTRL_PIN" cla27_PAA7, ,  531   8    <83href="+code=PINCTRL_PIN" cla0, , , ,  532   8    <83href="+code=PINCTRL_PIN" cla23_PAA3, ,  533   8    <8 href="+code=PINCTRL_PIN" cla4, , ,  534   8    <83href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L535"> 535   8    <8 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a6s="line8 name="L536"> 536   8    <8 href=static const unsignedPINCTRL_PIN" clagmd_c#LsEGRA_PIN_PWR_INgmd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L537"> 537   8    <8 href="+code=PINCTRL_PIN" cla, , TA6JTEGRA_PIN_DDR_DM0, , TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a8s="line8 name="L538"> 538   8    <8 href="+code=PINCTRL_PIN" cla, , TA6JTEGRA_PIN_GMI_AD22_PAA2, TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a9s="line8 name="L539"> 539   8    <83Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L540"> 540   8    <84ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L541"> 541   8    <84gs="sstatic const unsignedPINCTRL_PIN" clagme_c#LsEGRA_PIN_PWR_INgme_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L542"> 542   8    <8 href="+code=PINCTRL_PIN" cla, , ,  543   8    <84href="+code=PINCTRL_PIN" cla4, , , ,  544   8    <84href="+code=PINCTRL_PIN" cla="L619" cl>, ,  545   8    <84href="+code=PINCTRL_PIN" cla26_PAA6, ,  546   8    <84Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L547"> 547   8    <84Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a8s="line8 name="L548"> 548   8    <84Ts="sstatic const unsignedPINCTRL_PIN" clagpu_c#LsEGRA_PIN_PWR_INgpu_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a9s="line8 name="L549"> 549   8    <8 href="+code=PINCTRL_PIN" cla2, ,  550   8    <85href="+code=PINCTRL_PIN" cla27_PAA7 551   8    <85href="+code=PINCTRL_PIN" cla0,  552   8    <85href="+code=PINCTRL_PIN" cla,  553   8    <8 href="+code=PINCTRL_PIN" cla3,  554   8    <8 href="+code=PINCTRL_PIN" cla2, ,  555   8    <8 href="+code=PINCTRL_PIN" cla3,  556   8    <85Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L557"> 557   8    <85Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L558"> 558   8    <85Ts="sstatic const unsignedPINCTRL_PIN" clagpu7_c#LsEGRA_PIN_PWR_INgpu7_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L559"> 559   8    <85href="+code=PINCTRL_PIN" cla2,  560   8    <86ss="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L561"> 561   8    <86gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L562"> 562   8    <86href=static const unsignedPINCTRL_PIN" clagpv_c#LsEGRA_PIN_PWR_INgpv_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L563"> 563   8    <8 href="+code=PINCTRL_PIN" cla2,  564   8    <8 href="+code=PINCTRL_PIN" cla24_PAA4,  565   8    <8 href="+code=PINCTRL_PIN" cla,  566   8    <86Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L567"> 567   8    <86Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L568"> 568   8    <86Ts="sstatic const unsignedPINCTRL_PIN" clahdint_c#LsEGRA_PIN_PWR_INhdint_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L569"> 569   8    <8 href="+code=PINCTRL_PIN" cla, TA6NTEGRA_PIN_GMI_AD27_PAA7TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L570"> 570   8    <87ss="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L571"> 571   8    <87gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L572"> 572   8    <87href=static const unsignedPINCTRL_PIN" clai2cp_c#LsEGRA_PIN_PWR_INi2cp_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L573"> 573   8    <8 href="+code=PINCTRL_PIN" cla26_PAA6 574   8    <8 href="+code=PINCTRL_PIN" claK_N,  575   8    <8 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L576"> 576   8    <87Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8a7s="line8 name="L577"> 577   8    <87Ts="sstatic const unsignedPINCTRL_PIN" clairrx_c#LsEGRA_PIN_PWR_INirrx_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L578"> 578   8    <8 href="+code=PINCTRL_PIN" cla27_PAA7TA6JTEGRA_PIN_GMI_AD26_PAA6TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L579"> 579   8    <87Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L580"> 580   8    <88ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L581"> 581   8    <88gs="sstatic const unsignedPINCTRL_PIN" clairtx_c#LsEGRA_PIN_PWR_INirtx_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L582"> 582   8    <88href="+code=PINCTRL_PIN" cla, TA6JTEGRA_PIN_DDR_A5, TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L583"> 583   8    <88href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L584"> 584   8    <88href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L585"> 585   8    <88href=static const unsignedPINCTRL_PIN" clakbca_c#LsEGRA_PIN_PWR_INkbca_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L586"> 586   8    <8 href="+code=PINCTRL_PIN" cla26_PAA6,  587   8    <88href="+code=PINCTRL_PIN" cla,  588   8    <88href="+code=PINCTRL_PIN" cla27_PAA7 589   8    <88Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L590"> 590   8    <89ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L591"> 591   8    <89gs="sstatic const unsignedPINCTRL_PIN" clakbcb_c#LsEGRA_PIN_PWR_INkbcb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c8ass="line8 name="L592"> 592   8    <89href="+code=PINCTRL_PIN" cla,  593   8    <89href="+code=PINCTRL_PIN" cla26_PAA6,  594   8    <89href="+code=PINCTRL_PIN" claT_N,  595   8    <8 href="+code=PINCTRL_PIN" cla27_PAA7 596   8    <8 href="+code=PINCTRL_PIN" cla,  597   8    <8 href="+code=PINCTRL_PIN" cla27_PAA7 598   8    <8 href="+code=PINCTRL_PIN" cla22_PAA2,  599   8    <8 href="+code=PINCTRL_PIN" cla22_PAA2 600   9    <9 href="+code=PINCTRL_PIN" cla23_PAA3 591   9    <90href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a2s="line9 name="L592"> 592   9    <90href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a3s="line9 name="L593"> 593   9    <90href=static const unsignedPINCTRL_PIN" clakbcc_c#LsEGRA_PIN_PWR_INkbcc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a4s="line9 name="L594"> 594   9    <9 href="+code=PINCTRL_PIN" cla="L619" clKB_COL0_PQTEGRA_PIN_DDR_DM0,  595   9    <9 href="+code=PINCTRL_PIN" cla22_PAA2 596   9    <90Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a7s="line9 name="L597"> 597   9    <90Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a8s="line9 name="L598"> 598   9    <90Ts="sstatic const unsignedPINCTRL_PIN" clakbcd_c#LsEGRA_PIN_PWR_INkbcd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a9s="line9 name="L599"> 599   9    <9 href="+code=PINCTRL_PIN" cla26_PAA6 610   9    <9 href="+code=PINCTRL_PIN" cla27_PAA7 611   9    <9 href="+code=PINCTRL_PIN" cla0, ,  612   9    <91href="+code=PINCTRL_PIN" cla,  613   9    <91href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L614"> 614   9    <91href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a5s="line9 name="L615"> 615   9    <91href=static const unsignedPINCTRL_PIN" clakbce_c#LsEGRA_PIN_PWR_INkbce_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a6s="line9 name="L616"> 616   9    <9 href="+code=PINCTRL_PIN" cla0,  617   9    <91href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a8s="line9 name="L618"> 618   9    <91href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a9s="line9 name="L619"> 619   9    <91href=static const unsignedPINCTRL_PIN" clakbcf_c#LsEGRA_PIN_PWR_INkbcf_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L620"> 620   9    <92href="+code=PINCTRL_PIN" cla27_PAA7 621   9    <92href="+code=PINCTRL_PIN" cla0,  622   9    <9 href="+code=PINCTRL_PIN" cla23_PAA3 623   9    <9 href="+code=PINCTRL_PIN" cla24_PAA4,  624   9    <9 href="+code=PINCTRL_PIN" cla,  625   9    <92href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a6s="line9 name="L626"> 626   9    <92Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a7s="line9 name="L627"> 627   9    <92Ts="sstatic const unsignedPINCTRL_PIN" clalcsn_c#LsEGRA_PIN_PWR_INlcsn_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a8s="line9 name="L628"> 628   9    <92href="+code=PINCTRL_PIN" cla22_PAA2TA6NTEGRA_PIN_GMI_AD24_PAA4TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a9s="line9 name="L629"> 629   9    <92Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L630"> 66L630" id9"L63093ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L531"> 531   9    <93gs="sstatic const unsignedPINCTRL_PIN" clald0_c#LsEGRA_PIN_PWR_INld0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a2s="line9 name="L532"> 532   9    <93href="+code=PINCTRL_PIN" cla23_PAA3,  533   9    <93href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L534"> 534   9    <93href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L535"> 535   9    <93href=static const unsignedPINCTRL_PIN" clald1_c#LsEGRA_PIN_PWR_INld1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a6s="line9 name="L536"> 536   9    <93href="+code=PINCTRL_PIN" cla0,  537   9    <93href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a8s="line9 name="L538"> 538   9    <93href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a9s="line9 name="L539"> 539   9    <93href=static const unsignedPINCTRL_PIN" clald2_c#LsEGRA_PIN_PWR_INld2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L540"> 540   9    <94href="+code=PINCTRL_PIN" cla27_PAA7 541   9    <94href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L542"> 542   9    <94href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L543"> 543   9    <94href=static const unsignedPINCTRL_PIN" clald3_c#LsEGRA_PIN_PWR_INld3_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L544"> 544   9    <94href="+code=PINCTRL_PIN" cla="L619" clLCD 545   9    <94href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a6s="line9 name="L546"> 546   9    <94Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a7s="line9 name="L547"> 547   9    <94Ts="sstatic const unsignedPINCTRL_PIN" clald4_c#LsEGRA_PIN_PWR_INld4_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a8s="line9 name="L548"> 548   9    <9 href="+code=PINCTRL_PIN" cla="L619" clLCD 549   9    <94Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L550"> 550   9    <95ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L551"> 551   9    <95gs="sstatic const unsignedPINCTRL_PIN" clald5_c#LsEGRA_PIN_PWR_INld5_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L552"> 552   9    <95href="+code=PINCTRL_PIN" cla, ,  553   9    <95href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L554"> 554   9    <95href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L555"> 555   9    <95href=static const unsignedPINCTRL_PIN" clald6_c#LsEGRA_PIN_PWR_INld6_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a6s="line9 name="L556"> 556   9    <9 href="+code=PINCTRL_PIN" cla4,  557   9    <95href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L558"> 558   9    <95href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L559"> 559   9    <95href=static const unsignedPINCTRL_PIN" clald7_c#LsEGRA_PIN_PWR_INld7_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L560"> 560   9    <9 href="+code=PINCTRL_PIN" cla,  561   9    <96href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L562"> 562   9    <96href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L563"> 563   9    <96href=static const unsignedPINCTRL_PIN" clald8_c#LsEGRA_PIN_PWR_INld8_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L564"> 564   9    <9 href="+code=PINCTRL_PIN" cla24_PAA4,  565   9    <96href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L566"> 566   9    <96Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a7s="line9 name="L567"> 567   9    <96Ts="sstatic const unsignedPINCTRL_PIN" clald9_c#LsEGRA_PIN_PWR_INld9_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L568"> 568   9    <9 href="+code=PINCTRL_PIN" cla4,  569   9    <96Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L570"> 570   9    <97ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L571"> 571   9    <97gs="sstatic const unsignedPINCTRL_PIN" clald10_c#LsEGRA_PIN_PWR_INld10_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L572"> 572   9    <97href="+code=PINCTRL_PIN" cla,  573   9    <97href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L574"> 574   9    <97href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L575"> 575   9    <97href=static const unsignedPINCTRL_PIN" clald11_c#LsEGRA_PIN_PWR_INld11_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L576"> 576   9    <97href="+code=PINCTRL_PIN" cla0,  577   9    <97href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L578"> 578   9    <97href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L579"> 579   9    <97href=static const unsignedPINCTRL_PIN" clald12_c#LsEGRA_PIN_PWR_INld12_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L580"> 580   9    <9 href="+code=PINCTRL_PIN" cla4,  581   9    <9 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L582"> 582   9    <9 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L583"> 583   9    <9 href=static const unsignedPINCTRL_PIN" clald13_c#LsEGRA_PIN_PWR_INld13_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L584"> 584   9    <9 href="+code=PINCTRL_PIN" claT_N, ,  585   9    <98href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L586"> 586   9    <98Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9a7s="line9 name="L587"> 587   9    <98Ts="sstatic const unsignedPINCTRL_PIN" clald14_c#LsEGRA_PIN_PWR_INld14_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L588"> 588   9    <98href="+code=PINCTRL_PIN" cla27_PAA7 589   9    <98Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L590"> 590   9    <99ss="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L591"> 591   9    <99gs="sstatic const unsignedPINCTRL_PIN" clald15_c#LsEGRA_PIN_PWR_INld15_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L592"> 592   9    <99href="+code=PINCTRL_PIN" cla,  593   9    <99href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L594"> 594   9    <99href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L595"> 595   9    <99href=static const unsignedPINCTRL_PIN" clald16_c#LsEGRA_PIN_PWR_INld16_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L596"> 596   9    <9 href="+code=PINCTRL_PIN" cla, ,  597   9    <99href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L598"> 598   9    <99href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c9ass="line9 name="L599"> 599   9    <99href=static const unsignedPINCTRL_PIN" clald17_c#LsEGRA_PIN_PWR_INld17_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10ass="line10ass=e="L599"> 599   10ass>10asref="+code=PINCTRL_PIN" cla, /pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a1s="line10aname="L591"> 591   10ana>10ahref=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a2s="line10aname="L592"> 592   10ana>10ahref=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a3s="line10aname="L593"> 593   10ana>10ahref=static const unsignedPINCTRL_PIN" claldc_c#LsEGRA_PIN_PWR_INldc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a4s="line10aname="L594"> 594   10ana>10ahref="+code=PINCTRL_PIN" claT_N,  595   10ana>10ahref=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a6s="line10aname="L596"> 596   10ana>10aTs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a7s="line10aname="L597"> 597   10ana>10aTs="sstatic const unsignedPINCTRL_PIN" claldi_c#LsEGRA_PIN_PWR_INldi_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10a8s="line10aname="L598"> 598   10ana>10ahref="+code=PINCTRL_PIN" cla27_PAA7 599   10ana>10aTs="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c101ss="line10 name="L610"> 610   10 na>10 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1011s="line10 name="L611"> 611   10 na>10 gs="sstatic const unsignedPINCTRL_PIN" clalhp0_c#LsEGRA_PIN_PWR_INlhp0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1012s="line10 name="L612"> 612   10 na>10 href="+code=PINCTRL_PIN" cla, ,  613   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10 4s="line10 name="L614"> 614   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10 5s="line10 name="L615"> 615   10 na>10 href=static const unsignedPINCTRL_PIN" clalhp1_c#LsEGRA_PIN_PWR_INlhp1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1016s="line10 name="L616"> 616   10 na>10 href="+code=PINCTRL_PIN" cla,  617   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10 8s="line10 name="L618"> 618   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10 9s="line10 name="L619"> 619   10 na>10 href=static const unsignedPINCTRL_PIN" clalhp2_c#LsEGRA_PIN_PWR_INlhp2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c102ss="line10 name="L620"> 620   10 na>10 nref="+code=PINCTRL_PIN" cla,  621   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1022s="line10 name="L622"> 622   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1023s="line10 name="L623"> 623   10 na>10 href=static const unsignedPINCTRL_PIN" clalhs_c#LsEGRA_PIN_PWR_INlhs_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1024s="line10 name="L624"> 624   10 na>10 href="+code=PINCTRL_PIN" claT_N,  625   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1026s="line10 name="L626"> 626   10 na>10 Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1027s="line10 name="L627"> 627   10 na>10 Ts="sstatic const unsignedPINCTRL_PIN" clalm0_c#LsEGRA_PIN_PWR_INlm0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1028s="line10 name="L628"> 628   10 na>10 href="+code=PINCTRL_PIN" cla22_PAA2TA6WTEGRA_PIN_DDR_DM0, TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1029s="line10 name="L629"> 629   10 na>10 Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c103ss="line10 name="L630"> 66L630" id10 na>10 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1031s="line10 name="L531"> 531   10 na>10 gs="sstatic const unsignedPINCTRL_PIN" clalm1_c#LsEGRA_PIN_PWR_INlm1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1032s="line10 name="L532"> 532   10 na>10 href="+code=PINCTRL_PIN" cla,  533   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1034s="line10 name="L534"> 534   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1035s="line10 name="L535"> 535   10 na>10 href=static const unsignedPINCTRL_PIN" clalpp_c#LsEGRA_PIN_PWR_INlpp_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1036s="line10 name="L536"> 536   10 na>10 href="+code=PINCTRL_PIN" cla,  537   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1038s="line10 name="L538"> 538   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1039s="line10 name="L539"> 539   10 na>10 href=static const unsignedPINCTRL_PIN" clalpw0_c#LsEGRA_PIN_PWR_INlpw0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c104ss="line10 name="L540"> 540   10 na>10 nref="+code=PINCTRL_PIN" cla, ,  541   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1042s="line10 name="L542"> 542   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1043s="line10 name="L543"> 543   10 na>10 href=static const unsignedPINCTRL_PIN" clalpw1_c#LsEGRA_PIN_PWR_INlpw1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1044s="line10 name="L544"> 544   10 na>10 href="+code=PINCTRL_PIN" claT_N,  545   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1046s="line10 name="L546"> 546   10 na>10 Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1047s="line10 name="L547"> 547   10 na>10 Ts="sstatic const unsignedPINCTRL_PIN" clalpw2_c#LsEGRA_PIN_PWR_INlpw2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1048s="line10 name="L548"> 548   10 na>10 href="+code=PINCTRL_PIN" cla22_PAA2 549   10 na>10 Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c105ss="line10 name="L550"> 550   10 na>10 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1051s="line10 name="L551"> 551   10 na>10 gs="sstatic const unsignedPINCTRL_PIN" clalsc0_c#LsEGRA_PIN_PWR_INlsc0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1052s="line10 name="L552"> 552   10 na>10 href="+code=PINCTRL_PIN" cla,  553   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1054s="line10 name="L554"> 554   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1055s="line10 name="L555"> 555   10 na>10 href=static const unsignedPINCTRL_PIN" clalsc1_c#LsEGRA_PIN_PWR_INlsc1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1056s="line10 name="L556"> 556   10 na>10 href="+code=PINCTRL_PIN" cla, TA6ZTEGRA_PIN_GMI_AD23_PAA3TA6ZTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1057s="line10 name="L557"> 557   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1058s="line10 name="L558"> 558   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1059s="line10 name="L559"> 559   10 na>10 href=static const unsignedPINCTRL_PIN" clalsck_c#LsEGRA_PIN_PWR_INlsck_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c106ss="line10 name="L560"> 560   10 na>10 nref="+code=PINCTRL_PIN" cla,  561   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1062s="line10 name="L562"> 562   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1063s="line10 name="L563"> 563   10 na>10 href=static const unsignedPINCTRL_PIN" clalsda_c#LsEGRA_PIN_PWR_INlsda_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1064s="line10 name="L564"> 564   10 na>10 href="+code=PINCTRL_PIN" claT_N, ,  565   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1066s="line10 name="L566"> 566   10 na>10 Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1067s="line10 name="L567"> 567   10 na>10 Ts="sstatic const unsignedPINCTRL_PIN" clalsdi_c#LsEGRA_PIN_PWR_INlsdi_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1068s="line10 name="L568"> 568   10 na>10 href="+code=PINCTRL_PIN" cla22_PAA2,  569   10 na>10 Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c107ss="line10 name="L570"> 570   10 na>10 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1071s="line10 name="L571"> 571   10 na>10 gs="sstatic const unsignedPINCTRL_PIN" clalspi_c#LsEGRA_PIN_PWR_INlspi_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1072s="line10 name="L572"> 572   10 na>10 href="+code=PINCTRL_PIN" cla,  573   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1074s="line10 name="L574"> 574   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1075s="line10 name="L575"> 575   10 na>10 href=static const unsignedPINCTRL_PIN" clalvp0_c#LsEGRA_PIN_PWR_INlvp0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1076s="line10 name="L576"> 576   10 na>10 href="+code=PINCTRL_PIN" cla,  577   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1078s="line10 name="L578"> 578   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1079s="line10 name="L579"> 579   10 na>10 href=static const unsignedPINCTRL_PIN" clalvp1_c#LsEGRA_PIN_PWR_INlvp1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c108ss="line10 name="L580"> 580   10 na>10 nref="+code=PINCTRL_PIN" cla,  581   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1082s="line10 name="L582"> 582   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1083s="line10 name="L583"> 583   10 na>10 href=static const unsignedPINCTRL_PIN" clalvs_c#LsEGRA_PIN_PWR_INlvs_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1084s="line10 name="L584"> 584   10 na>10 href="+code=PINCTRL_PIN" claT_N,  585   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1086s="line10 name="L586"> 586   10 na>10 Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1087s="line10 name="L587"> 587   10 na>10 Ts="sstatic const unsignedPINCTRL_PIN" clals_c#LsEGRA_PIN_PWR_INls_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1088s="line10 name="L588"> 588   10 na>10 href="+code=PINCTRL_PIN" cla22_PAA2,  589   10 na>10 href="+code=PINCTRL_PIN" cla26_PAA6 590   10 na>10 nref="+code=PINCTRL_PIN" cla22_PAA2 591   10 na>10 href="+code=PINCTRL_PIN" cla0, ,  592   10 na>10 href="+code=PINCTRL_PIN" cla, ,  593   10 na>10 href="+code=PINCTRL_PIN" cla24_PAA4TA6ZTEGRA_PIN_GMI_AD23_PAA3TA6ZTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1094s="line10 name="L594"> 594   10 na>10 href="+code=PINCTRL_PIN" claT_N, TA6NTEGRA_PIN_GMI_AD24_PAA4TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c10 5s="line10 name="L595"> 595   10 na>10 href="+code=PINCTRL_PIN" cla22_PAA2 596   10 na>10 href="+code=PINCTRL_PIN" cla,  597   10 na>10 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1098s="line10 name="L598"> 598   10 na>10 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1099s="line10 name="L599"> 599   10 na>10 href=static const unsignedPINCTRL_PIN" clalc_c#LsEGRA_PIN_PWR_INlc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c11ass="line11ass=e="L599"> 599   11ass>11asref="+code=PINCTRL_PIN" cla,  591   11ana>110href="+code=PINCTRL_PIN" cla0,  592   11ana>110href="+code=PINCTRL_PIN" cla,  593   11ana>110href="+code=PINCTRL_PIN" cla24_PAA4 594   11ana>11ahref="+code=PINCTRL_PIN" claT_N, TA6WTEGRA_PIN_DDR_DM0, TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c11a5s="line11aname="L595"> 595   11ana>11 href="+code=PINCTRL_PIN" cla22_PAA2 596   11ana>110href="+code=PINCTRL_PIN" cla,  597   11ana>110href="+code=PINCTRL_PIN" cla27_PAA7TA6NTEGRA_PIN_GMI_AD27_PAA7TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c11a8s="line11aname="L598"> 598   11ana>11ahref=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c11a9s="line11aname="L599"> 599   11ana>11aTs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c111ss="line11 name="L610"> 610   11 na>11 ns="sstatic const unsignedPINCTRL_PIN" clald17_0_c#LsEGRA_PIN_PWR_INld17_0_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1111s="line11 name="L611"> 611   11 na>11 href="+code=PINCTRL_PIN" cla0, ,  612   11 na>11 href="+code=PINCTRL_PIN" cla,  613   11 na>111href="+code=PINCTRL_PIN" cla24_PAA4 614   11 na>111href="+code=PINCTRL_PIN" cla="L619" clLCD 615   11 na>111href="+code=PINCTRL_PIN" cla22_PAA2 616   11 na>11 href="+code=PINCTRL_PIN" cla, ,  617   11 na>111href="+code=PINCTRL_PIN" cla27_PAA7 618   11 na>111href="+code=PINCTRL_PIN" cla27_PAA7 619   11 na>111href="+code=PINCTRL_PIN" cla26_PAA6,  620   11 na>11 nref="+code=PINCTRL_PIN" cla,  621   11 na>112href="+code=PINCTRL_PIN" cla0,  622   11 na>11 href="+code=PINCTRL_PIN" cla23_PAA3 623   11 na>11 href="+code=PINCTRL_PIN" cla24_PAA4 624   11 na>11 href="+code=PINCTRL_PIN" claT_N, ,  625   11 na>112href="+code=PINCTRL_PIN" cla22_PAA2 626   11 na>112href="+code=PINCTRL_PIN" cla,  627   11 na>112href="+code=PINCTRL_PIN" cla27_PAA7,  628   11 na>11 href="+code=PINCTRL_PIN" cla22_PAA2 629   11 na>11 Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c113ss="line11 name="L630"> 66L630" id11 na>11 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1131s="line11 name="L531"> 531   11 na>113gs="sstatic const unsignedPINCTRL_PIN" clald19_18_c#LsEGRA_PIN_PWR_INld19_18_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1132s="line11 name="L532"> 532   11 na>113href="+code=PINCTRL_PIN" cla23_PAA3 533   11 na>113href="+code=PINCTRL_PIN" cla24_PAA4 534   11 na>11 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1135s="line11 name="L535"> 535   11 na>11 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1136s="line11 name="L536"> 536   11 na>11 href=static const unsignedPINCTRL_PIN" clald21_20_c#LsEGRA_PIN_PWR_INld21_20_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1137s="line11 name="L537"> 537   11 na>113href="+code=PINCTRL_PIN" cla27_PAA7 538   11 na>113href="+code=PINCTRL_PIN" cla27_PAA7,  539   11 na>113Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c114ss="line11 name="L540"> 540   11 na>114ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1141s="line11 name="L541"> 541   11 na>114gs="sstatic const unsignedPINCTRL_PIN" clald23_22_c#LsEGRA_PIN_PWR_INld23_22_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1142s="line11 name="L542"> 542   11 na>114href="+code=PINCTRL_PIN" cla,  543   11 na>114href="+code=PINCTRL_PIN" cla24_PAA4 544   11 na>114href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1145s="line11 name="L545"> 545   11 na>114href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1146s="line11 name="L546"> 546   11 na>114href=static const unsignedPINCTRL_PIN" claowc_c#LsEGRA_PIN_PWR_INowc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1147s="line11 name="L547"> 547   11 na>114href="+code=PINCTRL_PIN" cla27_PAA7 548   11 na>114href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1149s="line11 name="L549"> 549   11 na>114Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c115ss="line11 name="L550"> 550   11 na>115ns="sstatic const unsignedPINCTRL_PIN" clapmc_c#LsEGRA_PIN_PWR_INpmc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1151s="line11 name="L551"> 551   11 na>115href="+code=PINCTRL_PIN" cla0, ,  552   11 na>11 href="+code=PINCTRL_PIN" cla, ,  553   11 na>115href="+code=PINCTRL_PIN" cla24_PAA4,  554   11 na>115href="+code=PINCTRL_PIN" claT_N, ,  555   11 na>115href="+code=PINCTRL_PIN" cla22_PAA2TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1156s="line11 name="L556"> 556   11 na>11 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1157s="line11 name="L557"> 557   11 na>11 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1158s="line11 name="L558"> 558   11 na>11 href=static const unsignedPINCTRL_PIN" clapta_c#LsEGRA_PIN_PWR_INpta_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1159s="line11 name="L559"> 559   11 na>115href="+code=PINCTRL_PIN" cla26_PAA6,  560   11 na>11 nref="+code=PINCTRL_PIN" cla,  561   11 na>11 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1162s="line11 name="L562"> 562   11 na>11 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1163s="line11 name="L563"> 563   11 na>11 href=static const unsignedPINCTRL_PIN" clarm_c#LsEGRA_PIN_PWR_INrm_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1164s="line11 name="L564"> 564   11 na>11 href="+code=PINCTRL_PIN" claT_N,  565   11 na>116href="+code=PINCTRL_PIN" cla22_PAA2,  566   11 na>116href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1167s="line11 name="L567"> 567   11 na>116href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1168s="line11 name="L568"> 568   11 na>116href=static const unsignedPINCTRL_PIN" clasdb_c#LsEGRA_PIN_PWR_INsdb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1169s="line11 name="L569"> 569   11 na>116href="+code=PINCTRL_PIN" cla26_PAA6 570   11 na>11 ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1171s="line11 name="L571"> 571   11 na>11 gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1172s="line11 name="L572"> 572   11 na>11 href=static const unsignedPINCTRL_PIN" clasdc_c#LsEGRA_PIN_PWR_INsdc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1173s="line11 name="L573"> 573   11 na>117href="+code=PINCTRL_PIN" cla24_PAA4 574   11 na>117href="+code=PINCTRL_PIN" claT_N,  575   11 na>117href="+code=PINCTRL_PIN" cla22_PAA2,  576   11 na>11 href="+code=PINCTRL_PIN" cla,  577   11 na>11 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1178s="line11 name="L578"> 578   11 na>11 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1179s="line11 name="L579"> 579   11 na>11 href=static const unsignedPINCTRL_PIN" clasdd_c#LsEGRA_PIN_PWR_INsdd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c118ss="line11 name="L580"> 580   11 na>11 nref="+code=PINCTRL_PIN" cla,  581   11 na>11 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1182s="line11 name="L582"> 582   11 na>11 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1183s="line11 name="L583"> 583   11 na>11 href=static const unsignedPINCTRL_PIN" clasdio1_c#LsEGRA_PIN_PWR_INsdio1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1184s="line11 name="L584"> 584   11 na>11 href="+code=PINCTRL_PIN" claT_N, ,  585   11 na>118href="+code=PINCTRL_PIN" cla22_PAA2 586   11 na>118href="+code=PINCTRL_PIN" cla,  587   11 na>118href="+code=PINCTRL_PIN" cla27_PAA7 588   11 na>11 href="+code=PINCTRL_PIN" cla22_PAA2,  589   11 na>11 href="+code=PINCTRL_PIN" cla26_PAA6 590   11 na>119ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1191s="line11 name="L591"> 591   11 na>119gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1192s="line11 name="L592"> 592   11 na>119href=static const unsignedPINCTRL_PIN" claslxa_c#LsEGRA_PIN_PWR_INslxa_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1193s="line11 name="L593"> 593   11 na>11 href="+code=PINCTRL_PIN" cla24_PAA4 594   11 na>119href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c11 5s="line11 name="L595"> 595   11 na>119href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1196s="line11 name="L596"> 596   11 na>119href=static const unsignedPINCTRL_PIN" claslxc_c#LsEGRA_PIN_PWR_INslxc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1197s="line11 name="L597"> 597   11 na>119href="+code=PINCTRL_PIN" cla27_PAA7 598   11 na>119href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1199s="line11 name="L599"> 599   11 na>119Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12ass="line12ass=e="L599"> 599   12ass>120ns="sstatic const unsignedPINCTRL_PIN" claslxd_c#LsEGRA_PIN_PWR_INslxd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a1s="line12aname="L591"> 591   12ana>120href="+code=PINCTRL_PIN" cla0,  592   12ana>120href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a3s="line12aname="L593"> 593   12ana>120href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a4s="line12aname="L594"> 594   12ana>12ahref=static const unsignedPINCTRL_PIN" claslxk_c#LsEGRA_PIN_PWR_INslxk_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a5s="line12aname="L595"> 595   12ana>12 href="+code=PINCTRL_PIN" cla22_PAA2,  596   12ana>120href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a7s="line12aname="L597"> 597   12ana>120href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a8s="line12aname="L598"> 598   12ana>120href=static const unsignedPINCTRL_PIN" claspdi_c#LsEGRA_PIN_PWR_INspdi_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12a9s="line12aname="L599"> 599   12ana>120href="+code=PINCTRL_PIN" cla26_PAA6 610   12 na>121ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1211s="line12 name="L611"> 611   12 na>121gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12h2s="line12 name="L612"> 612   12 na>121href=static const unsignedPINCTRL_PIN" claspdo_c#LsEGRA_PIN_PWR_INspdo_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 3s="line12 name="L613"> 613   12 na>121href="+code=PINCTRL_PIN" cla24_PAA4,  614   12 na>121href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1215s="line12 name="L615"> 615   12 na>121href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1216s="line12 name="L616"> 616   12 na>121href=static const unsignedPINCTRL_PIN" claspia_c#LsEGRA_PIN_PWR_INspia_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 7s="line12 name="L617"> 617   12 na>121href="+code=PINCTRL_PIN" cla27_PAA7,  618   12 na>121href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1219s="line12 name="L619"> 619   12 na>121Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12hss="line12 name="L620"> 620   12 na>122ns="sstatic const unsignedPINCTRL_PIN" claspib_c#LsEGRA_PIN_PWR_INspib_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 1s="line12 name="L621"> 621   12 na>122href="+code=PINCTRL_PIN" cla0,  622   12 na>122href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 3s="line12 name="L623"> 623   12 na>122href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 4s="line12 name="L624"> 624   12 na>122href=static const unsignedPINCTRL_PIN" claspic_c#LsEGRA_PIN_PWR_INspic_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c12 5s="line12 name="L625"> 625   12 na>122href="+code=PINCTRL_PIN" cla22_PAA2TA6XTEGRA_PIN_GMI_AD23_PAA3TA6XTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1226s="line12 name="L626"> 626   12 na>122href="+code=PINCTRL_PIN" cla,  627   12 na>122href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1228s="line12 name="L628"> 628   12 na>122href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1229s="line12 name="L629"> 629   12 na>122href=static const unsignedPINCTRL_PIN" claspid_c#LsEGRA_PIN_PWR_INspid_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c123ss="line12 name="L630"> 66L630" id12 na>123nref="+code=PINCTRL_PIN" cla,  531   12 na>123href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1232s="line12 name="L532"> 532   12 na>123href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1233s="line12 name="L533"> 533   12 na>123href=static const unsignedPINCTRL_PIN" claspie_c#LsEGRA_PIN_PWR_INspie_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1234s="line12 name="L534"> 534   12 na>123href="+code=PINCTRL_PIN" claT_N, TA6XTEGRA_PIN_GMI_AD26_PAA6TA6XTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1235s="line12 name="L535"> 535   12 na>123href="+code=PINCTRL_PIN" cla22_PAA2,  536   12 na>123href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1237s="line12 name="L537"> 537   12 na>123href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1238s="line12 name="L538"> 538   12 na>123href=static const unsignedPINCTRL_PIN" claspif_c#LsEGRA_PIN_PWR_INspif_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1239s="line12 name="L539"> 539   12 na>123href="+code=PINCTRL_PIN" cla26_PAA6 540   12 na>124ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1241s="line12 name="L541"> 541   12 na>124gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1242s="line12 name="L542"> 542   12 na>124href=static const unsignedPINCTRL_PIN" claspig_c#LsEGRA_PIN_PWR_INspig_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1243s="line12 name="L543"> 543   12 na>124href="+code=PINCTRL_PIN" cla24_PAA4TA6WTEGRA_PIN_GMI_AD22_PAA2TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1244s="line12 name="L544"> 544   12 na>124href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1245s="line12 name="L545"> 545   12 na>124href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1246s="line12 name="L546"> 546   12 na>124href=static const unsignedPINCTRL_PIN" claspih_c#LsEGRA_PIN_PWR_INspih_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1247s="line12 name="L547"> 547   12 na>124href="+code=PINCTRL_PIN" cla27_PAA7TA6WTEGRA_PIN_GMI_AD23_PAA3TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1248s="line12 name="L548"> 548   12 na>124href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1249s="line12 name="L549"> 549   12 na>124Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c125ss="line12 name="L550"> 550   12 na>125ns="sstatic const unsignedPINCTRL_PIN" clauaa_c#LsEGRA_PIN_PWR_INuaa_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1251s="line12 name="L551"> 551   12 na>125href="+code=PINCTRL_PIN" cla0,  552   12 na>12 href="+code=PINCTRL_PIN" cla,  553   12 na>125href="+code=PINCTRL_PIN" cla24_PAA4 554   12 na>125href="+code=PINCTRL_PIN" claT_N,  555   12 na>125href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1256s="line12 name="L556"> 556   12 na>125Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1257s="line12 name="L557"> 557   12 na>125Ts="sstatic const unsignedPINCTRL_PIN" clauab_c#LsEGRA_PIN_PWR_INuab_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1258s="line12 name="L558"> 558   12 na>125href="+code=PINCTRL_PIN" cla22_PAA2,  559   12 na>125href="+code=PINCTRL_PIN" cla26_PAA6 560   12 na>12 nref="+code=PINCTRL_PIN" cla,  561   12 na>126href="+code=PINCTRL_PIN" cla0, ,  562   12 na>126href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1263s="line12 name="L563"> 563   12 na>126href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1264s="line12 name="L564"> 564   12 na>126href=static const unsignedPINCTRL_PIN" clauac_c#LsEGRA_PIN_PWR_INuac_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1265s="line12 name="L565"> 565   12 na>126href="+code=PINCTRL_PIN" cla22_PAA2,  566   12 na>126href="+code=PINCTRL_PIN" cla,  567   12 na>126href="+code=PINCTRL_PIN" cla27_PAA7 568   12 na>12 href="+code=PINCTRL_PIN" cla22_PAA2 569   12 na>12 Ts="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c127ss="line12 name="L570"> 570   12 na>12 ns="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1271s="line12 name="L571"> 571   12 na>12 gs="sstatic const unsignedPINCTRL_PIN" clack32_c#LsEGRA_PIN_PWR_INck32_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1272s="line12 name="L572"> 572   12 na>12 href="+code=PINCTRL_PIN" cla, ,  573   12 na>12 href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1274s="line12 name="L574"> 574   12 na>12 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1275s="line12 name="L575"> 575   12 na>12 href=static const unsignedPINCTRL_PIN" clauad_c#LsEGRA_PIN_PWR_INuad_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1276s="line12 name="L576"> 576   12 na>12 href="+code=PINCTRL_PIN" cla,  577   12 na>127href="+code=PINCTRL_PIN" cla27_PAA7 578   12 na>127href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1279s="line12 name="L579"> 579   12 na>127Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c128ss="line12 name="L580"> 580   12 na>128ns="sstatic const unsignedPINCTRL_PIN" clauca_c#LsEGRA_PIN_PWR_INuca_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1281s="line12 name="L581"> 581   12 na>128href="+code=PINCTRL_PIN" cla0,  582   12 na>128href="+code=PINCTRL_PIN" cla,  583   12 na>128href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1284s="line12 name="L584"> 584   12 na>128href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1285s="line12 name="L585"> 585   12 na>128href=static const unsignedPINCTRL_PIN" claucb_c#LsEGRA_PIN_PWR_INucb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1286s="line12 name="L586"> 586   12 na>128href="+code=PINCTRL_PIN" cla, TA6Agra20.c#L619" id="L619" clUART3_CTS>TA6Ags="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1287s="line12 name="L587"> 587   12 na>128href="+code=PINCTRL_PIN" cla27_PAA7TA6CTEGRA_PIN_DDR_DM0, TA6CTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1288s="line12 name="L588"> 588   12 na>128href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1289s="line12 name="L589"> 589   12 na>128Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c129ss="line12 name="L590"> 590   12 na>129ns="sstatic const unsignedPINCTRL_PIN" clauda_c#LsEGRA_PIN_PWR_INuda_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1291s="line12 name="L591"> 591   12 na>12 href="+code=PINCTRL_PIN" cla0, ,  592   12 na>12 href="+code=PINCTRL_PIN" cla,  593   12 na>12 href="+code=PINCTRL_PIN" cla24_PAA4 594   12 na>12 href="+code=PINCTRL_PIN" claT_N,  595   12 na>129href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1296s="line12 name="L596"> 596   12 na>129Ts="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1297s="line12 name="L597"> 597   12 na>129Ts="sstatic const unsignedPINCTRL_PIN" claddrc_c#LsEGRA_PIN_PWR_INddrc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1298s="line12 name="L598"> 598   12 na>129href="+code=PINCTRL_PIN" cla22_PAA2 599   12 na>129href="+code=PINCTRL_PIN" cla26_PAA6 599   13ass>130ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a1s="line13aname="L591"> 591   13ana>130gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a2s="line13aname="L592"> 592   13ana>130href=static const unsignedPINCTRL_PIN" clapmca_c#LsEGRA_PIN_PWR_INpmca_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a3s="line13aname="L593"> 593   13ana>130href="+code=PINCTRL_PIN" cla24_PAA4,  594   13ana>130href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a5s="line13aname="L595"> 595   13ana>130href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a6s="line13aname="L596"> 596   13ana>130href=static const unsignedPINCTRL_PIN" clapmcb_c#LsEGRA_PIN_PWR_INpmcb_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a7s="line13aname="L597"> 597   13ana>130href="+code=PINCTRL_PIN" cla27_PAA7,  598   13ana>13ahref=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13a9s="line13aname="L599"> 599   13ana>13aTs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c131ss="line13 name="L610"> 610   13 na>13 ns="sstatic const unsignedPINCTRL_PIN" clapmcc_c#LsEGRA_PIN_PWR_INpmcc_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1311s="line13 name="L611"> 611   13 na>13 href="+code=PINCTRL_PIN" cla0, ,  612   13 na>131href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13 3s="line13 name="L613"> 613   13 na>131href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1314s="line13 name="L614"> 614   13 na>131href=static const unsignedPINCTRL_PIN" clapmcd_c#LsEGRA_PIN_PWR_INpmcd_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1315s="line13 name="L615"> 615   13 na>131href="+code=PINCTRL_PIN" cla22_PAA2,  616   13 na>131href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13 7s="line13 name="L617"> 617   13 na>131href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1318s="line13 name="L618"> 618   13 na>131href=static const unsignedPINCTRL_PIN" clapmce_c#LsEGRA_PIN_PWR_INpmce_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1319s="line13 name="L619"> 619   13 na>131href="+code=PINCTRL_PIN" cla26_PAA6TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13hss="line13 name="L620"> 620   13 na>132ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13 1s="line13 name="L621"> 621   13 na>132gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1322s="line13 name="L622"> 622   13 na>132href=static const unsignedPINCTRL_PIN" claxm2c_c#LsEGRA_PIN_PWR_INxm2c_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c13 3s="line13 name="L623"> 623   13 na>13 href="+code=PINCTRL_PIN" cla24_PAA4,  624   13 na>13 href="+code=PINCTRL_PIN" claT_N,  625   13 na>132href="+code=PINCTRL_PIN" cla22_PAA2 626   13 na>132href="+code=PINCTRL_PIN" cla,  627   13 na>132href="+code=PINCTRL_PIN" cla27_PAA7 628   13 na>13 href="+code=PINCTRL_PIN" cla22_PAA2,  629   13 na>132href="+code=PINCTRL_PIN" cla26_PAA6 66L630" id13 na>133nref="+code=PINCTRL_PIN" cla,  531   13 na>133href="+code=PINCTRL_PIN" cla0,  532   13 na>133href="+code=PINCTRL_PIN" cla23_PAA3 533   13 na>133href="+code=PINCTRL_PIN" cla24_PAA4,  534   13 na>133href="+code=PINCTRL_PIN" claT_N,  535   13 na>133href="+code=PINCTRL_PIN" cla22_PAA2 536   13 na>133href="+code=PINCTRL_PIN" cla,  537   13 na>133href="+code=PINCTRL_PIN" cla27_PAA7 538   13 na>133href="+code=PINCTRL_PIN" cla27_PAA7TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1339s="line13 name="L539"> 539   13 na>133href="+code=PINCTRL_PIN" cla26_PAA6,  540   13 na>134nref="+code=PINCTRL_PIN" cla,  541   13 na>134href="+code=PINCTRL_PIN" cla0,  542   13 na>134href="+code=PINCTRL_PIN" cla,  543   13 na>134href="+code=PINCTRL_PIN" cla24_PAA4,  544   13 na>134href="+code=PINCTRL_PIN" claT_N,  545   13 na>134href="+code=PINCTRL_PIN" cla22_PAA2,  546   13 na>134href="+code=PINCTRL_PIN" cla,  547   13 na>134href="+code=PINCTRL_PIN" cla27_PAA7,  548   13 na>134href="+code=PINCTRL_PIN" cla27_PAA7 549   13 na>134href="+code=PINCTRL_PIN" cla26_PAA6,  550   13 na>135nref="+code=PINCTRL_PIN" cla, TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1351s="line13 name="L551"> 551   13 na>135href="+code=PINCTRL_PIN" cla0, TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1352s="line13 name="L552"> 552   13 na>13 href="+code=PINCTRL_PIN" cla, ,  553   13 na>135href="+code=PINCTRL_PIN" cla24_PAA4 554   13 na>135href="+code=PINCTRL_PIN" claT_N,  555   13 na>135href="+code=PINCTRL_PIN" cla22_PAA2TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1356s="line13 name="L556"> 556   13 na>135href="+code=PINCTRL_PIN" cla, ,  557   13 na>135href="+code=PINCTRL_PIN" cla27_PAA7 558   13 na>135href="+code=PINCTRL_PIN" cla22_PAA2 559   13 na>135href="+code=PINCTRL_PIN" cla26_PAA6 560   13 na>13 nref="+code=PINCTRL_PIN" cla,  561   13 na>136href="+code=PINCTRL_PIN" cla0, TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1362s="line13 name="L562"> 562   13 na>136href="+code=PINCTRL_PIN" cla, TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1363s="line13 name="L563"> 563   13 na>136href="+code=PINCTRL_PIN" cla24_PAA4,  564   13 na>13 href="+code=PINCTRL_PIN" claT_N,  565   13 na>136href="+code=PINCTRL_PIN" cla22_PAA2 566   13 na>136href="+code=PINCTRL_PIN" cla,  567   13 na>136href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1368s="line13 name="L568"> 568   13 na>136href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1369s="line13 name="L569"> 569   13 na>136href=static const unsignedPINCTRL_PIN" claxm2d_c#LsEGRA_PIN_PWR_INxm2d_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c137ss="line13 name="L570"> 570   13 na>137nref="+code=PINCTRL_PIN" cla, ,  571   13 na>137href="+code=PINCTRL_PIN" cla0,  572   13 na>13 href="+code=PINCTRL_PIN" cla,  573   13 na>137href="+code=PINCTRL_PIN" cla24_PAA4 574   13 na>137href="+code=PINCTRL_PIN" claT_N,  575   13 na>137href="+code=PINCTRL_PIN" cla22_PAA2,  576   13 na>13 href="+code=PINCTRL_PIN" cla,  577   13 na>137href="+code=PINCTRL_PIN" cla27_PAA7 578   13 na>137href="+code=PINCTRL_PIN" cla27_PAA7 579   13 na>137href="+code=PINCTRL_PIN" cla26_PAA6 580   13 na>13 nref="+code=PINCTRL_PIN" cla, ,  581   13 na>138href="+code=PINCTRL_PIN" cla0,  582   13 na>138href="+code=PINCTRL_PIN" cla,  583   13 na>138href="+code=PINCTRL_PIN" cla24_PAA4 584   13 na>13 href="+code=PINCTRL_PIN" claT_N,  585   13 na>138href="+code=PINCTRL_PIN" cla22_PAA2,  586   13 na>138href="+code=PINCTRL_PIN" cla,  587   13 na>138href="+code=PINCTRL_PIN" cla27_PAA7 588   13 na>13 href="+code=PINCTRL_PIN" cla22_PAA2 589   13 na>13 href="+code=PINCTRL_PIN" cla26_PAA6 590   13 na>139nref="+code=PINCTRL_PIN" cla, ,  591   13 na>13 href="+code=PINCTRL_PIN" cla0,  592   13 na>13 href="+code=PINCTRL_PIN" cla,  593   13 na>13 href="+code=PINCTRL_PIN" cla24_PAA4 594   13 na>13 href="+code=PINCTRL_PIN" claT_N,  595   13 na>139href="+code=PINCTRL_PIN" cla22_PAA2,  596   13 na>139href="+code=PINCTRL_PIN" cla,  597   13 na>139href="+code=PINCTRL_PIN" cla27_PAA7 598   13 na>139href="+code=PINCTRL_PIN" cla22_PAA2 599   13 na>139href="+code=PINCTRL_PIN" cla26_PAA6 599   14ass>140nref="+code=PINCTRL_PIN" cla, ,  591   14ana>140href="+code=PINCTRL_PIN" cla0,  592   14ana>140href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c14a3s="line14aname="L593"> 593   14ana>140href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c14a4s="line14aname="L594"> 594   14ana>14ahref=static const unsignedPINCTRL_PIN" clapinct_ao1_c#LsEGRA_PIN_PWR_INpinct_ao1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c14a5s="line14aname="L595"> 595   14ana>14 href="+code=PINCTRL_PIN" cla22_PAA2 596   14ana>140href="+code=PINCTRL_PIN" cla,  597   14ana>140href="+code=PINCTRL_PIN" cla27_PAA7 598   14ana>140href="+code=PINCTRL_PIN" cla22_PAA2,  599   14ana>140href="+code=PINCTRL_PIN" cla26_PAA6 610   14 na>141nref="+code=PINCTRL_PIN" cla,  611   14 na>14 href="+code=PINCTRL_PIN" cla0,  612   14 na>141href="+code=PINCTRL_PIN" cla,  613   14 na>141href="+code=PINCTRL_PIN" cla24_PAA4,  614   14 na>141href="+code=PINCTRL_PIN" claT_N,  615   14 na>141href="+code=PINCTRL_PIN" cla22_PAA2 616   14 na>141href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c14 7s="line14 name="L617"> 617   14 na>141href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1418s="line14 name="L618"> 618   14 na>141href=static const unsignedPINCTRL_PIN" clapinct_ao2_c#LsEGRA_PIN_PWR_INpinct_ao2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1419s="line14 name="L619"> 619   14 na>141href="+code=PINCTRL_PIN" cla26_PAA6,  620   14 na>142nref="+code=PINCTRL_PIN" cla,  621   14 na>142href="+code=PINCTRL_PIN" cla0,  622   14 na>142href="+code=PINCTRL_PIN" cla,  623   14 na>14 href="+code=PINCTRL_PIN" cla24_PAA4 624   14 na>14 href="+code=PINCTRL_PIN" claT_N, ,  625   14 na>142href="+code=PINCTRL_PIN" cla22_PAA2 626   14 na>142href="+code=PINCTRL_PIN" cla,  627   14 na>142href="+code=PINCTRL_PIN" cla27_PAA7,  628   14 na>14 href="+code=PINCTRL_PIN" cla22_PAA2 629   14 na>142href="+code=PINCTRL_PIN" cla26_PAA6 66L630" id14 na>143nref="+code=PINCTRL_PIN" cla,  531   14 na>143href="+code=PINCTRL_PIN" cla0,  532   14 na>143href="+code=PINCTRL_PIN" cla23_PAA3,  533   14 na>143href="+code=PINCTRL_PIN" cla24_PAA4 534   14 na>143href="+code=PINCTRL_PIN" claT_N,  535   14 na>143href="+code=PINCTRL_PIN" cla22_PAA2,  536   14 na>143href="+code=PINCTRL_PIN" cla, ,  537   14 na>143href="+code=PINCTRL_PIN" cla27_PAA7,  538   14 na>143href="+code=PINCTRL_PIN" cla27_PAA7,  539   14 na>143href="+code=PINCTRL_PIN" cla26_PAA6TEGRA_PIN_DDR_A5, Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c144ss="line14 name="L540"> 540   14 na>144nref="+code=PINCTRL_PIN" cla, ,  541   14 na>144href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1442s="line14 name="L542"> 542   14 na>144href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1443s="line14 name="L543"> 543   14 na>144href=static const unsignedPINCTRL_PIN" clapinct_at1_c#LsEGRA_PIN_PWR_INpinct_at1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1444s="line14 name="L544"> 544   14 na>144href="+code=PINCTRL_PIN" claT_N, ,TEGRA_PIN_DDR_A5, ,Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1445s="line14 name="L545"> 545   14 na>144href="+code=PINCTRL_PIN" cla22_PAA2,  546   14 na>144href="+code=PINCTRL_PIN" cla,  547   14 na>144href="+code=PINCTRL_PIN" cla27_PAA7 548   14 na>144href="+code=PINCTRL_PIN" cla27_PAA7 549   14 na>144href="+code=PINCTRL_PIN" cla26_PAA6 550   14 na>145nref="+code=PINCTRL_PIN" cla, ,  551   14 na>145href="+code=PINCTRL_PIN" cla0,  552   14 na>14 href="+code=PINCTRL_PIN" cla,  553   14 na>145href="+code=PINCTRL_PIN" cla24_PAA4TA6ITEGRA_PIN_GMI_AD26_PAA6TA6ITs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1454s="line14 name="L554"> 554   14 na>145href="+code=PINCTRL_PIN" claT_N,  555   14 na>145href="+code=PINCTRL_PIN" cla22_PAA2,  556   14 na>145href="+code=PINCTRL_PIN" cla,  557   14 na>145href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1458s="line14 name="L558"> 558   14 na>145href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1459s="line14 name="L559"> 559   14 na>145href=static const unsignedPINCTRL_PIN" clapinct_at2_c#LsEGRA_PIN_PWR_INpinct_at2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c146ss="line14 name="L560"> 560   14 na>14 nref="+code=PINCTRL_PIN" cla,  561   14 na>146href="+code=PINCTRL_PIN" cla0, TA6KTEGRA_PIN_DDR_DM0, TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1462s="line14 name="L562"> 562   14 na>146href="+code=PINCTRL_PIN" cla,  563   14 na>146href="+code=PINCTRL_PIN" cla24_PAA4TA6ITEGRA_PIN_GMI_AD23_PAA3TA6ITs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1464s="line14 name="L564"> 564   14 na>14 href="+code=PINCTRL_PIN" claT_N, TA6ITEGRA_PIN_GMI_AD22_PAA2TA6ITs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1465s="line14 name="L565"> 565   14 na>146href="+code=PINCTRL_PIN" cla22_PAA2TA6KTEGRA_PIN_GMI_AD22_PAA2TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1466s="line14 name="L566"> 566   14 na>146href="+code=PINCTRL_PIN" cla, TA6KTEGRA_PIN_GMI_AD24_PAA4TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1467s="line14 name="L567"> 567   14 na>146href="+code=PINCTRL_PIN" cla27_PAA7TA6KTEGRA_PIN_GMI_AD23_PAA3TA6KTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1468s="line14 name="L568"> 568   14 na>146href="+code=PINCTRL_PIN" cla27_PAA7,  569   14 na>146href="+code=PINCTRL_PIN" cla26_PAA6 570   14 na>147nref="+code=PINCTRL_PIN" cla,  571   14 na>147href="+code=PINCTRL_PIN" cla0,  572   14 na>14 href="+code=PINCTRL_PIN" cla,  573   14 na>147href="+code=PINCTRL_PIN" cla24_PAA4,  574   14 na>147href="+code=PINCTRL_PIN" claT_N,  575   14 na>147href="+code=PINCTRL_PIN" cla22_PAA2 576   14 na>14 href="+code=PINCTRL_PIN" cla, TA6ITEGRA_PIN_DDR_DM0, TA6ITs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1477s="line14 name="L577"> 577   14 na>147href="+code=PINCTRL_PIN" cla27_PAA7TA6Igra20.c#L619" id="L619" clGMI_HIOR>TA6Igs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1478s="line14 name="L578"> 578   14 na>147href="+code=PINCTRL_PIN" cla27_PAA7TA6ITEGRA_PIN_GMI_AD24_PAA4TA6ITs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1479s="line14 name="L579"> 579   14 na>147href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c148ss="line14 name="L580"> 580   14 na>14 nref=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1481s="line14 name="L581"> 581   14 na>148href=static const unsignedPINCTRL_PIN" clapinct_cdev1_c#LsEGRA_PIN_PWR_INpinct_cdev1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1482s="line14 name="L582"> 582   14 na>148href="+code=PINCTRL_PIN" cla,  583   14 na>148href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1484s="line14 name="L584"> 584   14 na>14 href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1485s="line14 name="L585"> 585   14 na>148href=static const unsignedPINCTRL_PIN" clapinct_cdev2_c#LsEGRA_PIN_PWR_INpinct_cdev2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1486s="line14 name="L586"> 586   14 na>148href="+code=PINCTRL_PIN" cla, ,  587   14 na>148href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1488s="line14 name="L588"> 588   14 na>148href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1489s="line14 name="L589"> 589   14 na>148href=static const unsignedPINCTRL_PIN" clapinct_csus_c#LsEGRA_PIN_PWR_INpinct_csus_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c149ss="line14 name="L590"> 590   14 na>149nref="+code=PINCTRL_PIN" cla,  591   14 na>149href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1492s="line14 name="L592"> 592   14 na>149href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1493s="line14 name="L593"> 593   14 na>149href=static const unsignedPINCTRL_PIN" clapinct_dap1_c#LsEGRA_PIN_PWR_INpinct_dap1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1494s="line14 name="L594"> 594   14 na>14 href="+code=PINCTRL_PIN" claT_N, ,  595   14 na>149href="+code=PINCTRL_PIN" cla22_PAA2 596   14 na>149href="+code=PINCTRL_PIN" cla,  597   14 na>149href="+code=PINCTRL_PIN" cla27_PAA7 598   14 na>149href="+code=PINCTRL_PIN" cla22_PAA2,  599   14 na>149href="+code=PINCTRL_PIN" cla26_PAA6 599   15ass>150ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15a1s="line15aname="L591"> 591   15ana>150gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15a2s="line15aname="L592"> 592   15ana>150href=static const unsignedPINCTRL_PIN" clapinct_dap2_c#LsEGRA_PIN_PWR_INpinct_dap2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15a3s="line15aname="L593"> 593   15ana>150href="+code=PINCTRL_PIN" cla24_PAA4 594   15ana>150href="+code=PINCTRL_PIN" claT_N,  595   15ana>15 href="+code=PINCTRL_PIN" cla22_PAA2 596   15ana>150href="+code=PINCTRL_PIN" cla, ,  597   15ana>150href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15a8s="line15aname="L598"> 598   15ana>150href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15a9s="line15aname="L599"> 599   15ana>150href=static const unsignedPINCTRL_PIN" clapinct_dap3_c#LsEGRA_PIN_PWR_INpinct_dap3_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c151ss="line15 name="L610"> 610   15 na>151nref="+code=PINCTRL_PIN" cla, ,  611   15 na>15 href="+code=PINCTRL_PIN" cla0,  612   15 na>151href="+code=PINCTRL_PIN" cla,  613   15 na>151href="+code=PINCTRL_PIN" cla24_PAA4 614   15 na>151href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1515s="line15 name="L615"> 615   15 na>151href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1516s="line15 name="L616"> 616   15 na>151href=static const unsignedPINCTRL_PIN" clapinct_dap4_c#LsEGRA_PIN_PWR_INpinct_dap4_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1517s="line15 name="L617"> 617   15 na>151href="+code=PINCTRL_PIN" cla27_PAA7 618   15 na>151href="+code=PINCTRL_PIN" cla22_PAA2,  619   15 na>151href="+code=PINCTRL_PIN" cla26_PAA6 620   15 na>152nref="+code=PINCTRL_PIN" cla,  621   15 na>152href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15h2s="line15 name="L622"> 622   15 na>152href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15h3s="line15 name="L623"> 623   15 na>152href=static const unsignedPINCTRL_PIN" clapinct_dbg_c#LsEGRA_PIN_PWR_INpinct_dbg_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c15h4s="line15 name="L624"> 624   15 na>15 href="+code=PINCTRL_PIN" claT_N, ,  625   15 na>152href="+code=PINCTRL_PIN" cla22_PAA2 626   15 na>152href="+code=PINCTRL_PIN" cla,  627   15 na>152href="+code=PINCTRL_PIN" cla27_PAA7 628   15 na>15 href="+code=PINCTRL_PIN" cla22_PAA2 629   15 na>152href="+code=PINCTRL_PIN" cla26_PAA6,  66L630" id15 na>153nref="+code=PINCTRL_PIN" cla,  531   15 na>153href="+code=PINCTRL_PIN" cla0,  532   15 na>153href="+code=PINCTRL_PIN" cla23_PAA3,  533   15 na>153href="+code=PINCTRL_PIN" cla24_PAA4 534   15 na>153href="+code=PINCTRL_PIN" claT_N, TEGRA_PIN_GMI_AD27_PAA7Ts="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1535s="line15 name="L535"> 535   15 na>153href="+code=PINCTRL_PIN" cla22_PAA2 536   15 na>153href="+code=PINCTRL_PIN" cla,  537   15 na>153href="+code=PINCTRL_PIN" cla27_PAA7 538   15 na>153href="+code=PINCTRL_PIN" cla27_PAA7 539   15 na>153href="+code=PINCTRL_PIN" cla26_PAA6MODE_ETEGRA_PIN_GMI_AD27_PAA7MODE_ETs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c154ss="line15 name="L540"> 540   15 na>154ns="s};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1541s="line15 name="L541"> 541   15 na>154gs="ss/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1542s="line15 name="L542"> 542   15 na>154href=static const unsignedPINCTRL_PIN" clapinct_lcd1_c#LsEGRA_PIN_PWR_INpinct_lcd1_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1543s="line15 name="L543"> 543   15 na>154href="+code=PINCTRL_PIN" cla24_PAA4 544   15 na>154href="+code=PINCTRL_PIN" claT_N,  545   15 na>154href="+code=PINCTRL_PIN" cla22_PAA2 546   15 na>154href="+code=PINCTRL_PIN" cla, ,  547   15 na>154href="+code=PINCTRL_PIN" cla27_PAA7TA6ZTEGRA_PIN_GMI_AD23_PAA3TA6ZTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1548s="line15 name="L548"> 548   15 na>154href="+code=PINCTRL_PIN" cla27_PAA7TA6NTEGRA_PIN_GMI_AD24_PAA4TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1549s="line15 name="L549"> 549   15 na>154href="+code=PINCTRL_PIN" cla26_PAA6 550   15 na>155nref="+code=PINCTRL_PIN" cla,  551   15 na>155href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1552s="line15 name="L552"> 552   15 na>155href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1553s="line15 name="L553"> 553   15 na>155href=static const unsignedPINCTRL_PIN" clapinct_lcd2_c#LsEGRA_PIN_PWR_INpinct_lcd2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1554s="line15 name="L554"> 554   15 na>155href="+code=PINCTRL_PIN" claT_N,  555   15 na>155href="+code=PINCTRL_PIN" cla22_PAA2 556   15 na>155href="+code=PINCTRL_PIN" cla,  557   15 na>155href="+code=PINCTRL_PIN" cla27_PAA7 558   15 na>155href="+code=PINCTRL_PIN" cla27_PAA7 559   15 na>155href="+code=PINCTRL_PIN" cla26_PAA6,  560   15 na>15 nref="+code=PINCTRL_PIN" cla,  561   15 na>156href="+code=PINCTRL_PIN" cla0,  562   15 na>156href="+code=PINCTRL_PIN" cla,  563   15 na>156href="+code=PINCTRL_PIN" cla24_PAA4 564   15 na>15 href="+code=PINCTRL_PIN" claT_N, ,  565   15 na>156href="+code=PINCTRL_PIN" cla22_PAA2 566   15 na>156href="+code=PINCTRL_PIN" cla,  567   15 na>156href="+code=PINCTRL_PIN" cla27_PAA7,  568   15 na>156href="+code=PINCTRL_PIN" cla27_PAA7 569   15 na>156href="+code=PINCTRL_PIN" cla26_PAA6 570   15 na>157nref="+code=PINCTRL_PIN" cla,  571   15 na>157href="+code=PINCTRL_PIN" cla0,  572   15 na>15 href="+code=PINCTRL_PIN" cla, ,  573   15 na>157href="+code=PINCTRL_PIN" cla24_PAA4 574   15 na>157href="+code=PINCTRL_PIN" claT_N,  575   15 na>157href="+code=PINCTRL_PIN" cla22_PAA2,  576   15 na>15 href="+code=PINCTRL_PIN" cla,  577   15 na>157href="+code=PINCTRL_PIN" cla27_PAA7 578   15 na>157href="+code=PINCTRL_PIN" cla27_PAA7 579   15 na>157href="+code=PINCTRL_PIN" cla26_PAA6 580   15 na>158nref="+code=PINCTRL_PIN" cla, ,  581   15 na>158href="+code=PINCTRL_PIN" cla0,  582   15 na>158href="+code=PINCTRL_PIN" cla,  583   15 na>158href="+code=PINCTRL_PIN" cla24_PAA4TA6WTEGRA_PIN_DDR_DM0, TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1584s="line15 name="L584"> 584   15 na>158href="+code=PINCTRL_PIN" claT_N,  585   15 na>158href="+code=PINCTRL_PIN" cla22_PAA2 586   15 na>158href="+code=PINCTRL_PIN" cla, TA6NTEGRA_PIN_GMI_AD27_PAA7TA6NTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1587s="line15 name="L587"> 587   15 na>158href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1588s="line15 name="L588"> 588   15 na>158href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1589s="line15 name="L589"> 589   15 na>158href=static const unsignedPINCTRL_PIN" clapinct_sdmmc2_c#LsEGRA_PIN_PWR_INpinct_sdmmc2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c159ss="line15 name="L590"> 590   15 na>159nref="+code=PINCTRL_PIN" cla,  591   15 na>159href="+code=PINCTRL_PIN" cla0, ,  592   15 na>159href="+code=PINCTRL_PIN" cla,  593   15 na>159href="+code=PINCTRL_PIN" cla24_PAA4 594   15 na>159href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1595s="line15 name="L595"> 595   15 na>159href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1596s="line15 name="L596"> 596   15 na>159href=static const unsignedPINCTRL_PIN" clapinct_sdmmc3_c#LsEGRA_PIN_PWR_INpinct_sdmmc3_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1597s="line15 name="L597"> 597   15 na>159href="+code=PINCTRL_PIN" cla27_PAA7 598   15 na>159href="+code=PINCTRL_PIN" cla22_PAA2 599   15 na>159href="+code=PINCTRL_PIN" cla26_PAA6 599   16ass>160nref="+code=PINCTRL_PIN" cla,  591   16ana>160href="+code=PINCTRL_PIN" cla0, ,  592   16ana>160href="+code=PINCTRL_PIN" cla,  593   16ana>160href="+code=PINCTRL_PIN" cla24_PAA4 594   16ana>160href="+code=PINCTRL_PIN" claT_N, ,  595   16ana>16 href="+code=PINCTRL_PIN" cla22_PAA2 596   16ana>160href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16a7s="line16aname="L597"> 597   16ana>160href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16a8s="line16aname="L598"> 598   16ana>160href=static const unsignedPINCTRL_PIN" clapinct_spi_c#LsEGRA_PIN_PWR_INpinct_spi_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16a9s="line16aname="L599"> 599   16ana>160href="+code=PINCTRL_PIN" cla26_PAA6,  610   16 na>161nref="+code=PINCTRL_PIN" cla,  611   16 na>16 href="+code=PINCTRL_PIN" cla0,  612   16 na>161href="+code=PINCTRL_PIN" cla, TA6XTEGRA_PIN_GMI_AD23_PAA3TA6XTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1613s="line16 name="L613"> 613   16 na>161href="+code=PINCTRL_PIN" cla24_PAA4 614   16 na>161href="+code=PINCTRL_PIN" claT_N, ,  615   16 na>161href="+code=PINCTRL_PIN" cla22_PAA2TA6XTEGRA_PIN_GMI_AD26_PAA6TA6XTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1616s="line16 name="L616"> 616   16 na>161href="+code=PINCTRL_PIN" cla,  617   16 na>161href="+code=PINCTRL_PIN" cla27_PAA7TA6WTEGRA_PIN_GMI_AD22_PAA2TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1618s="line16 name="L618"> 618   16 na>161href="+code=PINCTRL_PIN" cla22_PAA2TA6WTEGRA_PIN_GMI_AD23_PAA3TA6WTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1619s="line16 name="L619"> 619   16 na>161href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 name="L620"> 620   16 na>162nref=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16h1s="line16 name="L621"> 621   16 na>162href=static const unsignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PIN_PWR_INpinct_uaa_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16h2s="line16 name="L622"> 622   16 na>162href="+code=PINCTRL_PIN" cla,  623   16 na>162href="+code=PINCTRL_PIN" cla24_PAA4 624   16 na>16 href="+code=PINCTRL_PIN" claT_N,  625   16 na>162href="+code=PINCTRL_PIN" cla22_PAA2 626   16 na>162href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 name="L627"> 627   16 na>162href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16h8s="line16 name="L628"> 628   16 na>162href=static const unsignedPINCTRL_PIN" clapinct_uab_c#LsEGRA_PIN_PWR_INpinct_uab_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c16h9s="line16 name="L629"> 629   16 na>162href="+code=PINCTRL_PIN" cla26_PAA6,  66L630" id16 na>163nref="+code=PINCTRL_PIN" cla,  531   16 na>163href="+code=PINCTRL_PIN" cla0,  532   16 na>163href="+code=PINCTRL_PIN" cla23_PAA3,  533   16 na>163href="+code=PINCTRL_PIN" cla24_PAA4,  534   16 na>163href="+code=PINCTRL_PIN" claT_N,  535   16 na>163href="+code=PINCTRL_PIN" cla22_PAA2 536   16 na>163href="+code=PINCTRL_PIN" cla,  537   16 na>163href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 name="L538"> 538   16 na>163href=s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1639s="line16 name="L539"> 539   16 na>163href=static const unsignedPINCTRL_PIN" clapinct_uart2_c#LsEGRA_PIN_PWR_INpinct_uart2_c#Lsref=[] = {s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c164ss="line16 name="L540"> 540   16 na>164nref="+code=PINCTRL_PIN" cla,  541   16 na>164href="+code=PINCTRL_PIN" cla0,  542   16 na>164href="+code=PINCTRL_PIN" cla23_PAA3TA6JTEGRA_PIN_GMI_AD26_PAA6TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1643s="line16 name="L543"> 543   16 na>164href="+code=PINCTRL_PIN" cla24_PAA4TA6JTEGRA_PIN_DDR_A5, TA6JTs="sts/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1644s="line16 name="L544"> 544   16 na>164href=};s/pinctrl/pinctrl-tegra20.c#L628" id="L628" c1645s="line16 name="L545"> 545   16L628"   15 na>159nref="+code=PINCTRL_PIN" cla, TA6WTs="sts/pinctrl/pinctrl-tegra8>MODEc#L628" id="sts/pinctrl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#L628" e6> 547   15 na>154href="+c6de=PI6CTRL_PIN" cla27_PAA7TA6ZTEGRA="st3inctrlW26_PAA6TA6JTs="st3inctrlW2inctrl-tegra20.c#L628" id="L628" c1644s="line16 name="L538"> 538   15 na>154href="+c6de=PI6CTRL_PIN" cla27_PAA7TA6NTEGR="st3inctrlW27_PAA7 539   15 na>154href="+c6de=PI6CTRL_PIN" cla26_PAA6,  560   15 na>155nref="+c6de=PI6CTRL_PIN" cla,  541   15 na>155href=};s6pinct6l/pinctrl-tegra20.c#L628" id="L628" c1552s="line15 nam6="L552"> 562   15 na>155href=s/p6nctrl6pinctrl-tegra20.c#L628" id="L628" c1553s="line15 nam6="L553"> 563   15 na>155href=sta6ic co6st unsignedPINCTRL_PIN" clapinct_lcd2_c#LsEGRA_PIviWR_INpinct_lcd1_c#Lsref=[] viWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#L="L554"> 564   15 na>155href="+c6de=PI6CTRL_PIN" claT_N,  545   15 na>155href="+c6de=PI6CTRL_PIN" cla22_PAA2, TA6JTsVInc1_PD   15 na>155href="+c6de=PI6CTRL_PIN" cla, ,  547   15 na>155href="+c6de=PI6CTRL_PIN" cla27_PAA7 538   15 na>155href="+c6de=PI6CTRL_PIN" cla27_PAA7 539   15 na>155href="+c6de=PI6CTRL_PIN" cla26_PAA6 560   15 na>15 nref="+c6de=PI6CTRL_PIN" cla,  541   15 na>156href="+c6de=PI6CTRL_PIN" cla0, , TA6JTsVInc7_PL 562   15 na>156href="+c6de=PI6CTRL_PIN" cla, TA6JTsVInc8_PL2inctrl-tegra20.c#L628" id="L628" c1644s="line16 name="L553"> 563   15 na>156href="+c6de=PI6CTRL_PIN" cla24_PAA4 564   15 na>15 href="+c6de=PI6CTRL_PIN" claT_N,  545   15 na>156href="+c6de=PI6CTRL_PIN" cla22_PAA2   15 na>156href="+c6de=PI6CTRL_PIN" cla, ,  547   15 na>156href="+c6de=PI6CTRL_PIN" cla27_PAA7TA6JTsVInpinctrlD2inctrl-tegra20.c#L628" id="L628" c1644s="line16 name="L538"> 538   15 na>156href="+c6de=PI6CTRL_PIN" cla27_PAA7 539   15 na>156href="+c6de=PI66/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 name="L570"> 560   15 na>157nref="+c6de=PI67inctrl-tegra20.c#L628" id="L628" c16h1s="line16 name="L571"> 561   15 na>157href="+c6de=PI67t unsignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINviWR_INpinct_uart2_c#Lsref=[]viWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#L="L572"> 562   15 na>15 href="+c6de=PI6CTRL_PIN" cla,  563   15 na>157href="+c6de=PI6CTRL_PIN" cla24_PAA4 564   15 na>157href="+c6de=PI6CTRL_PIN" claT_N,  545   15 na>157href="+c6de=PI6CTRL_PIN" cla22_PAA2   15 na>15 href="+c6de=PI6CTRL_PIN" cla, , TA6JTsVInGP4rl/D 547   15 na>157href="+c6de=PI6CTRL_PIN" cla27_PAA7 538   15 na>157href="+c6de=PI6CTRL_PIN" cla27_PAA7,  539   15 na>157href="+c6de=PI67/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 name="L580"> 560   15 na>158nref="+c6de=PI68inctrl-tegra20.c#L628" id="L628" c16h1s="line16 name="L581"> 561   15 na>158href="+c6de=PI68t unsignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINxm2WR_INpinct_uaa_c#Lsref=[] =xm2WR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#L="L582"> 562   15 na>158href="+c6de=PI6CTRL_PIN" cla, ,  563   15 na>158href="+c6de=PI6CTRL_PIN" cla24_PAA4TA6WTEGRDDR_A="L619" clDAP3_DspaPPgs="stDR_A=inctrl-tegra20.c#L628" id="L628" c1644s="line16 name="L554"> 564   15 na>158href="+c6de=PI6CTRL_PIN" claT_N,  545   15 na>158href="+c6de=PI6CTRL_PIN" cla22_PAA2   15 na>158href="+c6de=PI6CTRL_PIN" cla, TA6NTEGsDR_A24_PAA4 547   15 na>158href=};s6pinct68TRL_PIN" cla27_PAA7, TA6JTsPDR_A 538   15 na>158href=s/p6nctrl68TRL_PIN" cla22_PAA2 539   15 na>158href=sta6ic co68TRL_PIN" cla26_PAA6 560   15 na>159nref="+c6de=PI6CTRL_PIN" cla,  561   15 na>159href="+c6de=PI6CTRL_PIN" cla0,  562   15 na>159href="+c6de=PI6CTRL_PIN" cla, ,  563   15 na>159href="+c6de=PI6CTRL_PIN" cla24_PAA4 564   15 na>159href=};s6pinct69TRL_PIN" claT_N,  565   15 na>159href=s/p6nctrl69TRL_PIN" cla22_PAA2 566   15 na>159href=sta6ic co69TRL_PIN" cla, TA6NTEGsDR_A124_PAA4 567   15 na>159href="+c6de=PI6CTRL_PIN" cla27_PAA7,  568   15 na>159href="+c6de=PI6CTRL_PIN" cla22_PAA2 569   15 na>159href="+c6de=PI6CTRL_PIN" cla26_PAA6 579   16ass>160nref="+c7de=PI7CTRL_PIN" cla,  579   15 na>159href="+c7de=PI7CTRL_PIN" cla0,  579   15 na>159href="+c7de=PI7CTRL_PIN" cla,  579   15 na>159href="+c7de=PI7CTRL_PIN" cla24_PAA4 579   15 na>159href=};s7de=PI7CTRL_PIN" claT_N,  579   15 na>159href=s/p7de=PI7CTRL_PIN" cla22_PAA2 579   15 na>159href=sta7pinct70TRL_PIN" cla, TA6NTEGsDR_CKM0,  579   15 na>159href="+c7nctrl70TRL_PIN" cla27_PAA7 579   15 na>159href="+c7ic co7st unstrl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L599"> 579   16ana>160href="+c7de=PI7CTRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L610"> 670   16 na>161nref="+c7de=PI710inctignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINxm2cR_INpinct_uaa_c#Lsref=[] =xm2cR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L611"> 671   16 na>16 href="+c7de=PI7CTRL_PIN" cla0,  672   16 na>161href="+c7de=PI7CTRL_PIN" cla, TA6XTEGtDR_DQS0t2_PAA2 573   16 na>161href="+c7de=PI7CTRL_PIN" cla24_PAA4 574   16 na>161href="+c7de=PI7CTRL_PIN" claT_N,  575   16 na>161href="+c7de=PI7CTRL_PIN" cla22_PAA2TA6XTEGsDR_DQS2P"L619" clDAP3_DspaPPgs="stDR_DQS2Pinctrl-tegra20.c#L628" id="L628" c1644s="line16 nam7=6L599"> 576   16 na>161href="+c7de=PI7CTRL_PIN" cla,  577   16 na>161href="+c7de=PI7CTRL_PIN" cla27_PAA7TA6WTEGsDR_DQS3P"L619" clDAP3_DspaPPgs="stDR_DQS3Pinctrl-tegra20.c#L628" id="L628" c1644s="line16 nam7=8L599"> 578   16 na>161href="+c7de=PI7CTRL_PIN" cla22_PAA2TA6WTEGtDR_DQS3t2_PAA2 579   16 na>161href=};s7pinct71TRL_PIN" cla26_PAA6,  670   16 na>162nref=s/p7nctrl72TRL_PIN" cla,  671   16 na>162href=sta7ic co72TRL_PIN" cla0,  672   16 na>162href="+c7de=PI7CTRL_PIN" cla,  573   16 na>162href="+c7de=PI7CTRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L624"> 674   16 na>16 href="+c7de=PI7CTRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam7=5L599"> 575   16 na>162href="+c7de=PI7CTRL_PignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINxm2dR_INpinct_uaa_c#Lsref=[] =xm2dR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L626"> 676   16 na>162href=};s7pinct72TRL_PIN" cla, ,  577   16 na>162href=s/p7nctrl72TRL_PIN" cla27_PAA7TA6WTEGsDR_DQ="L619" clDAP3_DspaPPgs="stDR_DQ=inctrl-tegra20.c#L628" id="L628" c1644s="line16 nam7=8L599"> 578   16 na>162href=sta7ic co72TRL_PIN" cla22_PAA2TA6WTEGtDR_DQ22_PAA2 579   16 na>162href="+c7de=PI7CTRL_PIN" cla26_PAA6 67L630" id16 na>163nref="+c7de=PI7CTRL_PIN" cla,  671   16 na>163href="+c7de=PI7CTRL_PIN" cla0, , TA6JTsPDR_DQ 672   16 na>163href="+c7de=PI7CTRL_PIN" cla23_PAA3 573   16 na>163href="+c7de=PI7CTRL_PIN" cla24_PAA4 674   16 na>163href="+c7de=PI7CTRL_PIN" claT_N,  575   16 na>163href="+c7de=PI7CTRL_PIN" cla22_PAA2 676   16 na>163href="+c7de=PI7CTRL_PIN" cla, ,  577   16 na>163href=};s7pinct73TRL_PIN" cla27_PAA7TA6WTEGsDR_DQ=="L619" clDAP3_DspaPPgs="stDR_DQ==inctrl-tegra20.c#L628" id="L628" c1644s="line16 nam7="L538"> 578   16 na>163href=s/p7nctrl73TRL_PIN" cla22_PAA2TA6WTEGtDR_DQ122_PAA2 579   16 na>163href=sta7ic co73TRL_PIN" cla26_PAA6 570   16 na>164nref="+c7de=PI7CTRL_PIN" cla,  571   16 na>164href="+c7de=PI7CTRL_PIN" cla0, , TA6JTsPDR_DQ1 572   16 na>164href="+c7de=PI7CTRL_PIN" cla23_PAA3TA6JTEPDR_DQ126_PAA6 573   16 na>164href="+c7de=PI7CTRL_PIN" cla24_PAA4TA6JTEsDR_DQ127_PAA7 574   16 na>164href=};s7pinct74TRL_PIN" claT_N,  575   16L628"   15 na>179nref74TRL_PIN" cla22_PAA2TA6W74TRL_PIN" cla, ,  577   15 na>154href="+c7de=PI7CTRL_PIN" cla27_PAA7TA6ZTEGRAsDR_DQ2="L619" clDAP3_DspaPPgs="stDR_DQ2=inctrl-tegra20.c#L628" id="L628" c1644s="line16 nam7="L538"> 578   15 na>154href="+c7de=PI7CTRL_PIN" cla27_PAA7TA6NTEGRtDR_DQ222_PAA2 579   15 na>154href="+c7de=PI7CTRL_PIN" cla26_PAA6 570   15 na>155nref="+c7de=PI7CTRL_PIN" cla,  571   15 na>155href=};s7pinct75TRL_PIN" cla0, , TA6JTsPDR_DQ2 572   15 na>155href=s/p7nctrl75TRL_PIN" cla23_PAA3TA6JTEPDR_DQ226_PAA6 573   15 na>155href=sta7ic co75TRL_PIN" cla24_PAA4TA6JTEsDR_DQ227_PAA7 574   15 na>155href="+c7de=PI7CTRL_PIN" claT_N,  575   15 na>155href="+c7de=PI7CTRL_PIN" cla22_PAA2   15 na>155href="+c7de=PI7CTRL_PIN" cla, ,  577   15 na>155href="+c7de=PI7CTRL_PIN" cla27_PAA7 578   15 na>155href="+c7de=PI7CTRL_PIN" cla27_PAA7,  579   15 na>155href="+c7de=PI7CTRL_PIN" cla26_PAA6 570   15 na>15 nref="+c7de=PI7CTRL_PIN" cla,  571   15 na>156href="+c7de=PI7CTRL_PIN" cla0,  572   15 na>156href="+c7de=PI7CTRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L553"> 573   15 na>156href="+c7de=PI7CTRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L554"> 574   15 na>15 href="+c7de=PI7CTRL_PignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINxm2clkR_INpinct_uaa_c#Lsref=[] =xm2clkR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L545"> 575   15 na>156href="+c7de=PI7CTRL_PIN" cla22_PAA2   15 na>156href="+c7de=PI7CTRL_PIN" cla,  577   15 na>156href="+c7de=PI76/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 nam7="L538"> 578   15 na>156href="+c7de=PI76inctrl-tegra20.c#L628" id="L628" c1639s="line16 nam7="L539"> 579   15 na>156href="+c7de=PI76t unsignedPINCTRL_PIN" clapinct_sdmmc2_c#LsEGRA_PIioWR_INpinct_lcd1_c#Lsref=[] PIioWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L570"> 570   15 na>157nref="+c7de=PI77TRL_PIN" cla, ,  571   15 na>157href="+c7de=PI77TRL_PIN" cla0,  572   15 na>15 href="+c7de=PI7CTRL_PIN" cla,  573   15 na>157href="+c7de=PI7CTRL_PIN" cla24_PAA4 574   15 na>157href="+c7de=PI7CTRL_PIN" claT_N, , TA6JTs"sts1iinc2rlY 575   15 na>157href="+c7de=PI7CTRL_PIN" cla22_PAA2   15 na>15 href="+c7de=PI77/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 nam7=28" e6> 577   15 na>157href="+c7de=PI77inctrl-tegra20.c#L628" id="L628" c16h8s="line16 nam7="L538"> 578   15 na>157href="+c7de=PI77t unsignedPINCTRL_PIN" clapinct_uab_c#LsEGRA_PINcrtR_INpinct_lcd1_c#Lsref=[] crtR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L539"> 579   15 na>157href="+c7de=PI77TRL_PIN" cla26_PAA6 570   15 na>158nref="+c7de=PI78TRL_PIN" cla,  571   15 na>158href="+c7de=PI78/pinctrl-tegra20.c#L628" id="L628" c1552s="line15 nam7="L582"> 572   15 na>158href="+c7de=PI78inctrl-tegra20.c#L628" id="L628" c1553s="line15 nam7="L583"> 573   15 na>158href="+c7de=PI78t unsignedPINCTRL_PIN" clapinct_lcd2_c#LsEGRA_PIddcR_INpinct_uaa_c#Lsref=[] =ddcR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L554"> 574   15 na>158href="+c7de=PI7CTRL_PIN" claT_N,  575   15 na>158href="+c7de=PI7CTRL_PIN" cla22_PAA2   15 na>158href="+c7de=PI78/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 nam7=28" e6> 577   15 na>158href=};s7pinct78inctrl-tegra20.c#L628" id="L628" c16h8s="line16 nam7="L538"> 578   15 na>158href=s/p7nctrl78t unsignedPINCTRL_PIN" clapinct_uab_c#LsEGRA_PINgmWR_INpinct_uaa_c#Lsref=[] =gmWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L539"> 579   15 na>158href=sta7ic co78TRL_PIN" cla26_PAA6,  570   15 na>159nref="+c7de=PI7CTRL_PIN" cla,  571   15 na>159href="+c7de=PI7CTRL_PIN" cla0,  572   15 na>159href="+c7de=PI7CTRL_PIN" cla,  573   15 na>159href="+c7de=PI79TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L594"> 574   15 na>159href=};s7pinct79TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam7="L595"> 575   15 na>159href=s/p7nctrl79TRL_PignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINgmWR_INpinct_uab_c#Lsref=[] =gmWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#7="L596"> 576   15 na>159href=sta7ic co79TRL_PIN" cla, TA6NTEGGMI_WPctrlC27_PAA7 577   15 na>159href="+c7de=PI79/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 nam7="L598"> 578   15 na>159href="+c7de=PI79inctrl-tegra20.c#L628" id="L628" c1639s="line16 nam7="L599"> 579   15 na>159href="+c7de=PI79t unsignedPINCTRL_PIN" clapinct_sdmmc2_c#LsEGRA_gmcR_INpinct_uaa_c#Lsref=[] =gmcR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#8="L599"> 589   16ass>160nref="+c8de=PI8CTRL_PIN" cla,  589   15 na>159href="+c8de=PI8CTRL_PIN" cla0, ,  589   15 na>159href="+c8de=PI8CTRL_PIN" cla,  589   15 na>159href="+c8de=PI8CTRL_PIN" cla24_PAA4 589   15 na>159href=};s8de=PI80/pinctrl-tegra20.c#L628" id="L628" c1645s="line16 nam8=5L599"> 589   15 na>159href=s/p8de=PI80+code=PINCTRL_PIN" cla,  589   15 na>159href=sta8pinct80="sts/pinctrl/pinctrl-tegra8>MODEc#L628" id="stsgmdR_INpinct_uaa_c#Lsref=[] =gmdR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#8=7L599"> 589   15 na>159href="+c8nctrl80TRL_PIN" cla27_PAA7,  589   15 na>159href="+c8ic co80TRL_PIN" cla27_PAA7 589   15 na>159href="+c8de=PI80/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 nam8="L610"> 680   16 na>161nref="+c8de=PI81inctrl-tegra20.c#L628" id="L628" c16h1s="line16 nam8="L611"> 681   16 na>16 href="+c8de=PI81t unsignedPINCTRL_PIN" clapinct_uaa_c#LsEGRA_PINgmeR_INpinct_uaa_c#Lsref=[] =gmeR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#8="L612"> 682   16 na>161href="+c8de=PI8CTRL_PIN" cla, TA6XTEGGMI_AD24rlAA24_PAA4 583   16 na>161href="+c8de=PI8CTRL_PIN" cla24_PAA4, TA6JTsGMI_AD25rlAA 584   16 na>161href="+c8de=PI8CTRL_PIN" claT_N,  585   16 na>161href="+c8de=PI8CTRL_PIN" cla22_PAA2TA6XTEGGMI_AD27_PAA27_PAA7 586   16 na>161href="+c8de=PI81/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 nam8=7L599"> 587   16 na>161href="+c8de=PI81inctrl-tegra20.c#L628" id="L628" c16h8s="line16 nam8=8L599"> 588   16 na>161href="+c8de=PI81t unsignedPINCTRL_PIN" clapinct_uab_c#LsEGRA_PINowrR_INpinct_uaa_c#Lsref=[] =owrR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#8=9L599"> 589   16 na>161href=};s8pinct81TRL_PIN" cla26_PAA6 680   16 na>162nref=s/p8nctrl820incttrl-tegra20.c#L628" id="L628" c16h7s="line16 nam8="L611"> 681   16 na>162href=sta8ic co82=inctl-tegra20.c#L628" id="L628" c16h7s="line16 nam8="L612"> 682   16 na>162href="+c8de=PI822inct/pinctrl/pinctrl-tegra8>MODEc#L628" id="sts/dWR_INpinct_uaa_c#Lsref=[] =/dWR_INprl/pinctrl-tegra20.c#L628" id="LActrl/pinctrl-tegra20.c#8=3L599"> 583   16 na>162href="+c8de=PI82TRL_PIN" cla24_PAA4TA6JTEGsts/nctrlY0,  584   16 na>16 href="+c8de=PI82TRL_PIN" claT_N,  585   16 na>162href="+c8de=PI82TRL_PIN" cla22_PAA2TA6XTEG"sts/NXTrlY22_PAA2 586   16 na>162href=};s8pinct82TRL_PIN" cla,  587   16 na>162href=s/p8nctrl82/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 nam8=8L599"> 588   16 na>162href=sta8ic co82inctrl-tegra20.c#L628" id="L628" c1639s="line16 nam8="L599"> 589   16 na>162href="+c8de=PI829inctenum,  68L630" id16 na>163nref="+c8de=PI8CTRL_PIN" cla,  681   16 na>163href="+c8de=PI8CTRL_PIN" cla0,  682   16 na>163href="+c8de=PI8CTRL_PIN" cla23_PAA3 583   16 na>163href="+c8de=PI8CTRL_PIN" cla24_PAA4 584   16 na>163href="+c8de=PI8CTRL_PIN" claT_N,  585   16 na>163href="+c8de=PI8CTRL_PIN" cla22_PAA2 586   16 na>163href="+c8de=PI8CTRL_PIN" cla,  587   16 na>163href=};s8pinct83TRL_PIN" cla27_PAA7TA6MUX_DAP24_PAA4 588   16 na>163href=s/p8nctrl83TRL_PIN" cla22_PAA2TA6MUX_DAP, TAMUX_DAP 589   16 na>163href=sta8ic co83TRL_PIN" cla26_PAA6 580   16 na>164nref="+c8de=PI8CTRL_PIN" cla,  681   16 na>164href="+c8de=PI8CTRL_PIN" cla0,  682   16 na>164href="+c8de=PI8CTRL_PIN" cla23_PAA3TAMUX_EMC_TEST1_DLt2_PAA2 583   16 na>164href="+c8de=PI8CTRL_PIN" cla24_PAA4TAMUX_GMI2_PAA2 584   16 na>164href=};s8pinct84TRL_PIN" claT_N,  585   16L628"   15 na>189nref84TRL_PIN" cla22_PAA2 585I4 hreO22_PAA2TA6W84TRL_PIN" cla,  587   15 na>154href="+c8de=PI8CTRL_PIN" cla27_PAA7TA6ZTMUX_I2C="L619" clULPI_DATA0A6MUX_I2C=inctrl-tegra20.c#L628" id="L628" c1579s="line15 nam8=8L599"> 588   15 na>154href="+c8de=PI8CTRL_PIN" cla27_PAA7TA6NMUX_I2C22_PAA2 589   15 na>154href="+c8de=PI8CTRL_PIN" cla26_PAA6 580   15 na>155nref="+c8de=PI8CTRL_PIN" cla,  681   15 na>155href=};s8pinct85TRL_PIN" cla0,  682   15 na>155href=s/p8nctrl85TRL_PIN" cla23_PAA3TAMUX_KBt4_PAA4 583   15 na>155href=sta8ic co85TRL_PIN" cla24_PAA4TAMUX_MIO4_PAA4 584   15 na>155href="+c8de=PI8CTRL_PIN" claT_N,  585   15 na>155href="+c8de=PI8CTRL_PIN" cla22_PAA2 586   15 na>155href="+c8de=PI8CTRL_PIN" cla,  587   15 na>155href="+c8de=PI8CTRL_PIN" cla27_PAA7 588   15 na>155href="+c8de=PI8CTRL_PIN" cla27_PAA7 589   15 na>155href="+c8de=PI8CTRL_PIN" cla26_PAA6 580   15 na>15 nref="+c8de=PI8CTRL_PIN" cla,  681   15 na>156href="+c8de=PI8CTRL_PIN" cla0,  682   15 na>156href="+c8de=PI86TRL_PIN" cla23_PAA3TAMUX_PLLP_OUT22_PAA2 583   15 na>156href="+c8de=PI86TRL_PIN" cla24_PAA4TAMUX_PLLP_OUT23_PAA3 584   15 na>15 href="+c8de=PI86TRL_PIN" claT_N,  585   15 na>156href="+c8de=PI8CTRL_PIN" cla22_PAA2 586   15 na>156href="+c8de=PI8CTRL_PIN" cla,  587   15 na>156href="+c8de=PI86TRL_PIN" cla27_PAA7 588   15 na>156href="+c8de=PI86TRL_PIN" cla27_PAA7 589   15 na>156href="+c8de=PI86TRL_PIN" cla26_PAA6 580   15 na>157nref="+c8de=PI87TRL_PIN" cla,  681   15 na>157href="+c8de=PI87TRL_PIN" cla0,  682   15 na>15 href="+c8de=PI8CTRL_PIN" cla,  583   15 na>157href="+c8de=PI8CTRL_PIN" cla24_PAA4 584   15 na>157href="+c8de=PI8CTRL_PIN" claT_N,  585   15 na>157href="+c8de=PI8CTRL_PIN" cla22_PAA2 586   15 na>15 href="+c8de=PI87TRL_PIN" cla,  587   15 na>157href="+c8de=PI87TRL_PIN" cla27_PAA7 588   15 na>157href="+c8de=PI87TRL_PIN" cla27_PAA7 589   15 na>157href="+c8de=PI87TRL_PIN" cla26_PAA6 580   15 na>158nref="+c8de=PI88TRL_PIN" cla,  681   15 na>158href="+c8de=PI88TRL_PIN" cla0,  682   15 na>158href="+c8de=PI88TRL_PIN" cla,  583   15 na>158href="+c8de=PI88TRL_PIN" cla24_PAA4 584   15 na>158href="+c8de=PI8CTRL_PIN" claT_N,  585   15 na>158href="+c8de=PI8CTRL_PIN" cla22_PAA2 586   15 na>158href="+c8de=PI88TRL_PIN" cla,  587   15 na>158href=};s8pinct88TRL_PIN" cla27_PAA7 588   15 na>158href=s/p8nctrl88TRL_PIN" cla27_PAA7 589   15 na>158href=sta8ic co88TRL_PIN" cla26_PAA6 580   15 na>159nref="+c8de=PI8CTRL_PIN" cla,  681   15 na>159href="+c8de=PI8CTRL_PIN" cla0,  682   15 na>159href="+c8de=PI8CTRL_PIN" cla,  583   15 na>159href="+c8de=PI89TRL_PIN" cla24_PAA4 584   15 na>159href=};s8pinct89TRL_PIN" claT_N,  585   15 na>159href=s/p8nctrl89TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 nam8="L596"> 586   15 na>159href=sta8ic co89TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 nam8=7L599"> 587   15 na>159href="+c8de=PI89/pinc/pinctrl/pincchar *rl/pinc_N,  588   15 na>159href="+c8de=PI89TRL_PIN" cla27spannct_uaa_ctring">"cdev2" 589   15 na>159href="+c8de=PI89/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 nam9="L599"> 599   16ass>160nref="+c9de=PI90inctrl-tegra20.c#L628" id="L628" c16h1s="line16 nam9=1L599"> 599   15 na>159href="+c9de=PI90t unsignedPINCTRL_char *rl/pinc_N,  599   15 na>159href="+c9de=PI9CTRL_PIN" cla"cdev2" 599   15 na>159href="+c9de=PI90TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam9=4L599"> 599   15 na>159href=};s9de=PI90TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam9=5L599"> 599   15 na>159href=s/p9de=PI90TRL_PignedPINCTRL_char *rl/pinc_N,  599   15 na>159href=sta9pinct90TRL_PIN" cla"cdev1" 599   15 na>159href="+c9nctrl90/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 nam9=8L599"> 599   15 na>159href="+c9ic co90inctrl-tegra20.c#L628" id="L628" c1639s="line16 nam9=9L599"> 599   15 na>159href="+c9de=PI90t unsignedPINCTRL_char *rl/pinc_N,  690   16 na>161nref="+c9de=PI910RL_PIN" cla"crtp" 691   16 na>16 href="+c9de=PI9CTRL_PIN" cla0"lm1" 692   16 na>161href="+c9de=PI91TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam9=3L599"> 593   16 na>161href="+c9de=PI91TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam9=4L599"> 594   16 na>161href="+c9de=PI91TRL_PignedPINCTRL_char *rl/pinc_N,  595   16 na>161href="+c9de=PI9CTRL_PIN" cla22spannct_uaa_ctring">"dap1" 596   16 na>161href="+c9de=PI91/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 nam9=7L599"> 597   16 na>161href="+c9de=PI91inctrl-tegra20.c#L628" id="L628" c16h8s="line16 nam9=8L599"> 598   16 na>161href="+c9de=PI91t unsignedPINCTRL_char *rl/pinc_N,  599   16 na>161href=};s9pinct91TRL_PIN" cla26spannct_uaa_ctring">"dap2" 690   16 na>162nref=s/p9nctrl920incttrl-tegra20.c#L628" id="L628" c16h7s="line16 nam9="L611"> 691   16 na>162href=sta9ic co92=inctl-tegra20.c#L628" id="L628" c16h7s="line16 nam9="L612"> 692   16 na>162href="+c9de=PI922inct/pinctrl/pincchar *rl/pinc_N,  593   16 na>162href="+c9de=PI92TRL_PIN" cla24spannct_uaa_ctring">"dap3" 594   16 na>16 href="+c9de=PI92/pinctrl-tegra20.c#L628" id="L628" c1645s="line16 nam9=5L599"> 595   16 na>162href="+c9de=PI92+code=PINCTRL_PIN" cla,  596   16 na>162href=};s9pinct92="sts/pinctrl/pincchar *rl/pinc_N,  597   16 na>162href=s/p9nctrl92TRL_PIN" cla27spannct_uaa_ctring">"dap4" 598   16 na>162href=sta9ic co92inctrtrl-tegra20.c#L628" id="L628" c1645s="line16 nam9=9L599"> 599   16 na>162href="+c9de=PI929inctl-tegra20.c#L628" id="L628" c1645s="line16 nam9="L630"> 69L630" id16 na>163nref="+c9de=PI9CTRL_P/pinctrl/pincchar *rl/pinc_N,  691   16 na>163href="+c9de=PI93TRL_PIN" cla0"gme" 692   16 na>163href="+c9de=PI93TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 nam9=3L599"> 593   16 na>163href="+c9de=PI93TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 nam9=4L599"> 594   16 na>163href="+c9de=PI93TRL_PignedPINCTRL_char *rl/pinc_N,  595   16 na>163href="+c9de=PI93TRL_PIN" cla22spannct_uaa_ctring">"lcsn" 596   16 na>163href="+c9de=PI93TRL_PIN" cla"ld0" 597   16 na>163href=};s9pinct93TRL_PIN" cla27spannct_uaa_ctring">"ld1" 598   16 na>163href=s/p9nctrl93TRL_PIN" cla27spannct_uaa_ctring">"ld10" 599   16 na>163href=sta9ic co93TRL_PIN" cla26spannct_uaa_ctring">"ld11" 590   16 na>164nref="+c9de=PI940RL_PIN" cla"ld12" 691   16 na>164href="+c9de=PI94TRL_PIN" cla0"ld13" 692   16 na>164href="+c9de=PI94TRL_PIN" cla"ld14" 593   16 na>164href="+c9de=PI94TRL_PIN" cla24spannct_uaa_ctring">"ld15" 594   16 na>164href=};s9pinct94TRL_PIN" claT_spannct_uaa_ctring">"ld16" 595   16L628"   15 na>199nref94TRL_PIN" cla22spannct_uaa_ctring">"ld17" 595I4 hreO22_PAA2TA6W94TRL_PIN" cla"ld2" 597   15 na>154href="+c9de=PI94TRL_PIN" cla27spannct_uaa_ctring">"ld3" 598   15 na>154href="+c9de=PI94TRL_PIN" cla27spannct_uaa_ctring">"ld4" 599   15 na>154href="+c9de=PI94TRL_PIN" cla26spannct_uaa_ctring">"ld5" 590   15 na>155nref="+c9de=PI950RL_PIN" cla"ld6" 691   15 na>155href=};s9pinct95TRL_PIN" cla0"ld7" 692   15 na>155href=s/p9nctrl95TRL_PIN" cla"ld8" 593   15 na>155href=sta9ic co95TRL_PIN" cla24spannct_uaa_ctring">"ld9" 594   15 na>155href="+c9de=PI95TRL_PIN" claT_spannct_uaa_ctring">"ldc" 595   15 na>155href="+c9de=PI95TRL_PIN" cla22spannct_uaa_ctring">"ldi" 596   15 na>155href="+c9de=PI95TRL_PIN" cla"lhp0" 597   15 na>155href="+c9de=PI95TRL_PIN" cla27spannct_uaa_ctring">"lhp1" 598   15 na>155href="+c9de=PI95TRL_PIN" cla27spannct_uaa_ctring">"lhp2" 599   15 na>155href="+c9de=PI95TRL_PIN" cla26spannct_uaa_ctring">"lhs" 590   15 na>15 nref="+c9de=PI960RL_PIN" cla"lm0" 691   15 na>156href="+c9de=PI96TRL_PIN" cla0"lm1" 692   15 na>156href="+c9de=PI96TRL_PIN" cla"lpp" 593   15 na>156href="+c9de=PI96TRL_PIN" cla24spannct_uaa_ctring">"lpw0" 594   15 na>15 href="+c9de=PI96TRL_PIN" claT_spannct_uaa_ctring">"lpw1" 595   15 na>156href="+c9de=PI96TRL_PIN" cla22spannct_uaa_ctring">"lpw2" 596   15 na>156href="+c9de=PI96TRL_PIN" cla"lsc0" 597   15 na>156href="+c9de=PI96TRL_PIN" cla27spannct_uaa_ctring">"lsc1" 598   15 na>156href="+c9de=PI96TRL_PIN" cla27spannct_uaa_ctring">"lsck" 599   15 na>156href="+c9de=PI96TRL_PIN" cla26spannct_uaa_ctring">"lsda" 590   15 na>157nref="+c9de=PI970RL_PIN" cla"lsdi" 691   15 na>157href="+c9de=PI97TRL_PIN" cla0"lspi" 692   15 na>15 href="+c9de=PI97TRL_PIN" cla"lvp0" 593   15 na>157href="+c9de=PI97TRL_PIN" cla24spannct_uaa_ctring">"lvp1" 594   15 na>157href="+c9de=PI97TRL_PIN" claT_spannct_uaa_ctring">"lvs" 595   15 na>157href="+c9de=PI97TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 nam9=6L599"> 596   15 na>15 href="+c9de=PI97TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 nam9=7L599"> 597   15 na>157href="+c9de=PI97/pinc/pinctrl/pincchar *rl/pinc_N,  598   15 na>157href="+c9de=PI97TRL_PIN" cla27spannct_uaa_ctring">"lcsn" 599   15 na>157href="+c9de=PI97TRL_PIN" cla26spannct_uaa_ctring">"ld0" 590   15 na>158nref="+c9de=PI980RL_PIN" cla"ld1" 691   15 na>158href="+c9de=PI98TRL_PIN" cla0"ld10" 692   15 na>158href="+c9de=PI98TRL_PIN" cla"ld11" 593   15 na>158href="+c9de=PI98TRL_PIN" cla24spannct_uaa_ctring">"ld12" 594   15 na>158href="+c9de=PI98TRL_PIN" claT_spannct_uaa_ctring">"ld13" 595   15 na>158href="+c9de=PI98TRL_PIN" cla22spannct_uaa_ctring">"ld14" 596   15 na>158href="+c9de=PI98TRL_PIN" cla"ld15" 597   15 na>158href=};s9pinct98TRL_PIN" cla27spannct_uaa_ctring">"ld16" 598   15 na>158href=s/p9nctrl98TRL_PIN" cla27spannct_uaa_ctring">"ld17" 599   15 na>158href=sta9ic co98TRL_PIN" cla26spannct_uaa_ctring">"ld2" 590   15 na>159nref="+c9de=PI990RL_PIN" cla"ld3" 691   15 na>159href="+c9de=PI99TRL_PIN" cla0"ld4" 692   15 na>159href="+c9de=PI99TRL_PIN" cla"ld5" 593   15 na>159href="+c9de=PI99TRL_PIN" cla24spannct_uaa_ctring">"ld6" 594   15 na>159href=};s9pinct99TRL_PIN" claT_spannct_uaa_ctring">"ld7" 595   15 na>159href=s/p9nctrl99TRL_PIN" cla22spannct_uaa_ctring">"ld8" 596   15 na>159href=sta9ic co99TRL_PIN" cla"ld9" 597   15 na>159href="+c9de=PI99TRL_PIN" cla27spannct_uaa_ctring">"ldc" 598   15 na>159href="+c9de=PI99TRL_PIN" cla27spannct_uaa_ctring">"ldi" 599   15 na>159href="+c9de=PI99TRL_PIN" cla26spannct_uaa_ctring">"lhp0" 20="L5>   15 na>159href="+20="L>20="RL_PIN" cla27spannct_uaa_ctring">"lhp1"15999">29/55/a7f68750dc5fe54cdbea647b816eef1e9fb5_3/20="L>-tegra20.c#L628" id="L628" c1579s="line15 na20=1L599"> 20=   15 na>159href="+20=20=TRL_PIN" cla0"lhp2" 20=   15 na>159href="+20=20=TRL_PIN" cla"lhs" 20=   15 na>159href="+20=20=TRL_PIN" cla24spannct_uaa_ctring">"lm0" 20=   15 na>159href=};20=20=TRL_PIN" claT_spannct_uaa_ctring">"lm1" 20=   15 na>159href=s/20=20=TRL_PIN" cla22spannct_uaa_ctring">"lpp" 20=   15 na>159href=st20=20=TRL_PIN" cla"lpw0" 20=   15 na>159href="+20=20=TRL_PIN" cla27spannct_uaa_ctring">"lpw1" 20=   15 na>159href="+20=20=TRL_PIN" cla27spannct_uaa_ctring">"lpw2" 20=   15 na>159href="+20=20=TRL_PIN" cla26spannct_uaa_ctring">"lsc0" 200   16 na>161nref="+200200"lsc1" 201   16 na>16 href="+201200TRL_PIN" cla0"lsck" 202   16 na>161href="+202200TRL_PIN" cla"lsda" 203   16 na>161href="+203200TRL_PIN" cla24spannct_uaa_ctring">"lsdi" 204   16 na>161href="+204200TRL_PIN" claT_spannct_uaa_ctring">"lspi" 205   16 na>161href="+205200TRL_PIN" cla22spannct_uaa_ctring">"lvp0" 206   16 na>161href="+206200TRL_PIN" cla"lvp1" 207   16 na>161href="+207200TRL_PIN" cla27spannct_uaa_ctring">"lvs" 208   16 na>161href="+208200inctrtrl-tegra20.c#L628" id="L628" c1645s="line16 na2009L599"> 209   16 na>161href=};2092009inctl-tegra20.c#L628" id="L628" c1645s="line16 na202"L599"> 200   16 na>162nref=s/200200,  201   16 na>162href=st201200TRL_PIN" cla0"kbca" 202   16 na>162href="+202200TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2003L599"> 203   16 na>162href="+203200TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2004L599"> 204   16 na>16 href="+204200TRL_PignedPINCTRL_char *rl/pinc_N,  205   16 na>162href="+205200TRL_PIN" cla22spannct_uaa_ctring">"kbcc" 206   16 na>162href=};206200/pinctrl-tegra20.c#L628" id="L628" c16h7s="line16 na2007L599"> 207   16 na>162href=s/207200inctrl-tegra20.c#L628" id="L628" c16h8s="line16 na2008L599"> 208   16 na>162href=st208200t unsignedPINCTRL_char *rl/pinc_N,  209   16 na>162href="+209200TRL_PIN" cla26spannct_uaa_ctring">"ata" 20L630" id16 na>163nref="+20L63>20L6RL_PIN" cla26spannct_uaa_ctring">"atb" 201   16 na>163href="+20120LTRL_PIN" cla0"atc" 202   16 na>163href="+20220LTRL_PIN" cla"atd" 203   16 na>163href="+20320LTRL_PIN" cla24spannct_uaa_ctring">"ate" 204   16 na>163href="+20420LTRL_PIN" claT_spannct_uaa_ctring">"dap1" 205   16 na>163href="+20520LTRL_PIN" cla22spannct_uaa_ctring">"dap2" 206   16 na>163href="+20620LTRL_PIN" cla"dap4" 207   16 na>163href=};20720LTRL_PIN" cla27spannct_uaa_ctring">"gma" 208   16 na>163href=s/20820LTRL_PIN" cla27spannct_uaa_ctring">"gmb" 209   16 na>163href=st20920LTRL_PIN" cla26spannct_uaa_ctring">"gmc" 200   16 na>164nref="+200200"gmd" 201   16 na>164href="+201200TRL_PIN" cla0"gme" 202   16 na>164href="+202200TRL_PIN" cla"gpu" 203   16 na>164href="+203200TRL_PIN" cla24spannct_uaa_ctring">"irrx" 204   16 na>164href=};204200TRL_PIN" claT_spannct_uaa_ctring">"irtx" 205   16L628"   15 na>205200TRL_PIN" cla22spannct_uaa_ctring">"pta" 205I4 hreO22_PAA2200TRL_PIN" cla"spia" 207   15 na>154href="+207200TRL_PIN" cla27spannct_uaa_ctring">"spib" 208   15 na>154href="+208200TRL_PIN" cla27spannct_uaa_ctring">"spic" 209   15 na>154href="+209200TRL_PIN" cla26spannct_uaa_ctring">"spid" 200   15 na>155nref="+200200"spie" 201   15 na>155href=};201200TRL_PIN" cla0"uca" 202   15 na>155href=s/202200TRL_PIN" cla"ucb" 203   15 na>155href=st203200TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2004L599"> 204   15 na>155href="+204200TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2005L599"> 205   15 na>155href="+205200TRL_PignedPINCTRL_char *rl/pinc_N,  206   15 na>155href="+206200TRL_PIN" cla"gmb" 207   15 na>155href="+207200/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2008L599"> 208   15 na>155href="+208200inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2009L599"> 209   15 na>155href="+209200t unsignedPINCTRL_char *rl/pinc_N,  200   15 na>15 nref="+200200"hdint" 201   15 na>156href="+201200TRL_PIN" cla0"lpw0" 202   15 na>156href="+202200TRL_PIN" cla"lpw2" 203   15 na>156href="+203200TRL_PIN" cla24spannct_uaa_ctring">"lsc1" 204   15 na>15 href="+204200TRL_PIN" claT_spannct_uaa_ctring">"lsck" 205   15 na>156href="+205200TRL_PIN" cla22spannct_uaa_ctring">"lsda" 206   15 na>156href="+206200TRL_PIN" cla"lspi" 207   15 na>156href="+207200TRL_PIN" cla27spannct_uaa_ctring">"pta" 208   15 na>156href="+208200inctrtrl-tegra20.c#L628" id="L628" c1645s="line16 na2069L599"> 209   15 na>156href="+2092009inctl-tegra20.c#L628" id="L628" c1645s="line16 na207"L599"> 200   15 na>157nref="+200200< unsignedPINCTRL_char *rl/pinc_N,  201   15 na>157href="+201200TRL_PIN" cla0"i2cp" 202   15 na>15 href="+202200TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2073L599"> 203   15 na>157href="+203200TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2074L599"> 204   15 na>157href="+204200TRL_PignedPINCTRL_char *rl/pinc_N,  205   15 na>157href="+205200TRL_PIN" cla22spannct_uaa_ctring">"rm" 206   15 na>15 href="+206200TRL_PIN" cla"spdi" 207   15 na>157href="+207200TRL_PIN" cla27spannct_uaa_ctring">"spdo" 208   15 na>157href="+208200TRL_PIN" cla27spannct_uaa_ctring">"spig" 209   15 na>157href="+209200TRL_PIN" cla26spannct_uaa_ctring">"spih" 200   15 na>158nref="+200200 201   15 na>158href="+201200=inctl-tegra20.c#L628" id="L628" c16h7s="line16 na2002L599"> 202   15 na>158href="+2022002inct/pinctrl/pincchar *rl/pinc_N,  203   15 na>158href="+203200TRL_PIN" cla24spannct_uaa_ctring">"ddc" 204   15 na>158href="+204200TRL_PIN" claT_spannct_uaa_ctring">"pta" 205   15 na>158href="+205200TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2006L599"> 206   15 na>158href="+206200TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2007L599"> 207   15 na>158href=};207200/pinc/pinctrl/pincchar *rl/pinc_N,  208   15 na>158href=s/208200TRL_PIN" cla27spannct_uaa_ctring">"dtf" 209   15 na>158href=st209200/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na209"L599"> 200   15 na>159nref="+200200 201   15 na>159href="+201200t unsignedPINCTRL_char *rl/pinc_N,  202   15 na>159href="+202200TRL_PIN" cla"ata" 203   15 na>159href="+203200TRL_PIN" cla24spannct_uaa_ctring">"atb" 204   15 na>159href=};204200TRL_PIN" claT_spannct_uaa_ctring">"atc" 205   15 na>159href=s/205200TRL_PIN" cla22spannct_uaa_ctring">"atd" 206   15 na>159href=st206200TRL_PIN" cla"ate" 207   15 na>159href="+207200TRL_PIN" cla27spannct_uaa_ctring">"gmb" 208   15 na>159href="+208200inctrtrl-tegra20.c#L628" id="L628" c1645s="line16 na2099L599"> 209   15 na>159href="+2092009inctl-tegra20.c#L628" id="L628" c1645s="line16 na21="L599"> 21="L5>   15 na>159href="+21="L>210< unsignedPINCTRL_char *rl/pinc_N,  21=   15 na>159href="+21=21=TRL_PIN" cla0"uad" 21=   15 na>159href="+21=210TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na21=3L599"> 21=   15 na>159href="+21=210TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na21=4L599"> 21=   15 na>159href=};21=210TRL_PignedPINCTRL_char *rl/pinc_N,  21=   15 na>159href=s/21=21=TRL_PIN" cla22spannct_uaa_ctring">"kbca" 21=   15 na>159href=st21=21=TRL_PIN" cla"kbcb" 21=   15 na>159href="+21=21=TRL_PIN" cla27spannct_uaa_ctring">"kbcc" 21=   15 na>159href="+21=21=TRL_PIN" cla27spannct_uaa_ctring">"kbcd" 21=   15 na>159href="+21=21=TRL_PIN" cla26spannct_uaa_ctring">"kbce" 210   16 na>161nref="+210210"kbcf" 211   16 na>16 href="+211210TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2102L599"> 212   16 na>161href="+212210TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2103L599"> 213   16 na>161href="+213210TRL_PignedPINCTRL_char *rl/pinc_N,  214   16 na>161href="+214210TRL_PIN" claT_spannct_uaa_ctring">"kbcb" 215   16 na>161href="+215210TRL_PIN" cla22spannct_uaa_ctring">"kbcd" 216   16 na>161href="+216210TRL_PIN" cla"kbcf" 217   16 na>161href="+217211/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2108L599"> 218   16 na>161href="+218211inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2109L599"> 219   16 na>161href=};219211t unsignedPINCTRL_char *rl/pinc_N,  210   16 na>162nref=s/210212"uaa" 211   16 na>162href=st211210TRL_PIN" cla0"uab" 212   16 na>162href="+212210TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2103L599"> 213   16 na>162href="+213210TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2104L599"> 214   16 na>16 href="+214210TRL_PignedPINCTRL_char *rl/pinc_N,  215   16 na>162href="+215210TRL_PIN" cla22spannct_uaa_ctring">"ata" 216   16 na>162href=};216212TRL_PIN" cla"atb" 217   16 na>162href=s/217212TRL_PIN" cla27spannct_uaa_ctring">"atc" 218   16 na>162href=st218212TRL_PIN" cla27spannct_uaa_ctring">"atd" 219   16 na>162href="+219210TRL_PIN" cla26spannct_uaa_ctring">"ate" 21L630" id16 na>163nref="+21L63>21L6RL_PIN" cla26spannct_uaa_ctring">"gmb" 211   16 na>163href="+211213TRL_PIN" cla0"gmd" 212   16 na>163href="+21221LTRL_PIN" cla"kbca" 213   16 na>163href="+21321LTRL_PIN" cla24spannct_uaa_ctring">"kbcb" 214   16 na>163href="+21421LTRL_PIN" claT_spannct_uaa_ctring">"kbcc" 215   16 na>163href="+21521LTRL_PIN" cla22spannct_uaa_ctring">"kbcd" 216   16 na>163href="+21621LTRL_PIN" cla"kbce" 217   16 na>163href=};21721LTRL_PIN" cla27spannct_uaa_ctring">"kbcf" 218   16 na>163href=s/218213inctrtrl-tegra20.c#L628" id="L628" c1645s="line16 na2139L599"> 219   16 na>163href=st2192139inctl-tegra20.c#L628" id="L628" c1645s="line16 na214"L599"> 210   16 na>164nref="+210214< unsignedPINCTRL_char *rl/pinc_N,  211   16 na>164href="+211210TRL_PIN" cla0"cdev1" 212   16 na>164href="+212210TRL_PIN" cla"cdev2" 213   16 na>164href="+213214TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2104L599"> 214   16 na>164href=};214214TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2105L599"> 215   16L628"   15 na>215214TRL_PignedPINCTRL_char *rl/pinc_N,  215I4 hreO22_PAA2210TRL_PIN" cla"kbce" 217   15 na>154href="+217210TRL_PIN" cla27spannct_uaa_ctring">"owc" 218   15 na>154href="+218210TRL_PIN" cla27spannct_uaa_ctring">"uac" 219   15 na>154href="+219214/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na215"L599"> 210   15 na>155nref="+210215 211   15 na>155href=};211215t unsignedPINCTRL_char *rl/pinc_N,  212   15 na>155href=s/212210TRL_PIN" cla"gpv" 213   15 na>155href=st213215TRL_PIN" cla24spannct_uaa_ctring">"slxa" 214   15 na>155href="+214215TRL_PIN" claT_spannct_uaa_ctring">"slxk" 215   15 na>155href="+215215TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2156L599"> 216   15 na>155href="+216215TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2157L599"> 217   15 na>155href="+217215/pinc/pinctrl/pincchar *rl/pinc_N,  218   15 na>155href="+218215TRL_PIN" cla27spannct_uaa_ctring">"cdev1" 219   15 na>155href="+219215/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na216"L599"> 210   15 na>15 nref="+210216 211   15 na>156href="+211216t unsignedPINCTRL_char *rl/pinc_N,  212   15 na>156href="+212210TRL_PIN" cla"csus" 213   15 na>156href="+213216TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2164L599"> 214   15 na>15 href="+214216TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2165L599"> 215   15 na>156href="+215216TRL_PignedPINCTRL_char *rl/pinc_N,  216   15 na>156href="+216210TRL_PIN" cla"cdev1" 217   15 na>156href="+217216/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2168L599"> 218   15 na>156href="+218216inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2169L599"> 219   15 na>156href="+219216t unsignedPINCTRL_char *rl/pinc_N,  210   15 na>157nref="+2102170RL_PIN" cla"csus" 211   15 na>157href="+211217TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2172L599"> 212   15 na>15 href="+212217TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2173L599"> 213   15 na>157href="+213217TRL_PignedPINCTRL_char *rl/pinc_N,  214   15 na>157href="+214217TRL_PIN" claT_spannct_uaa_ctring">"csus" 215   15 na>157href="+215217TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2176L599"> 216   15 na>15 href="+216217TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2177L599"> 217   15 na>157href="+217217/pinc/pinctrl/pincchar *rl/pinc_N,  218   15 na>157href="+218210TRL_PIN" cla27spannct_uaa_ctring">"cdev2" 219   15 na>157href="+219217/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na218"L599"> 210   15 na>158nref="+210218 211   15 na>158href="+211218t unsignedPINCTRL_char *rl/pinc_N,  212   15 na>158href="+212218TRL_PIN" cla"gpu" 213   15 na>158href="+213210TRL_PIN" cla24spannct_uaa_ctring">"sdb" 214   15 na>158href="+214210TRL_PIN" claT_spannct_uaa_ctring">"sdc" 215   15 na>158href="+215218TRL_PIN" cla22spannct_uaa_ctring">"sdd" 216   15 na>158href="+216218TRL_PIN" cla"ucb" 217   15 na>158href=};217218/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2188L599"> 218   15 na>158href=s/218218inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2189L599"> 219   15 na>158href=st219218t unsignedPINCTRL_char *rl/pinc_N,  210   15 na>159nref="+2102190RL_PIN" cla"pmc" 211   15 na>159href="+211219TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2192L599"> 212   15 na>159href="+212219TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2193L599"> 213   15 na>159href="+213219TRL_PignedPINCTRL_char *rl/pinc_N,  214   15 na>159href=};214210TRL_PIN" claT_spannct_uaa_ctring">"pmc" 215   15 na>159href=s/215219TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2196L599"> 216   15 na>159href=st216219TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2197L599"> 217   15 na>159href="+217219/pinc/pinctrl/pincchar *rl/pinc_N,  218   15 na>159href="+218219TRL_PIN" cla27spannct_uaa_ctring">"dta" 219   15 na>159href="+219219TRL_PIN" cla26spannct_uaa_ctring">"dtb" 22="L5>   15 na>159href="+22="L>22="RL_PIN" cla27spannct_uaa_ctring">"dtc" 22=   15 na>159href="+22=22=TRL_PIN" cla0"dtd" 22=   15 na>159href="+22=22=TRL_PIN" cla"dte" 22=   15 na>159href="+22=22=TRL_PIN" cla24spannct_uaa_ctring">"gmd" 22=   15 na>159href=};22=22=TRL_PIN" claT_spannct_uaa_ctring">"gme" 22=   15 na>159href=s/22=220TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na22=6L599"> 22=   15 na>159href=st22=220TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na22=7L599"> 22=   15 na>159href="+22=220/pinc/pinctrl/pincchar *rl/pinc_N,  22=   15 na>159href="+22=22=TRL_PIN" cla27spannct_uaa_ctring">"crtp" 22=   15 na>159href="+22=22=TRL_PIN" cla26spannct_uaa_ctring">"dap1" 220   16 na>161nref="+220220"dap3" 221   16 na>16 href="+221220TRL_PIN" cla0"dap4" 222   16 na>161href="+222220TRL_PIN" cla"ddc" 223   16 na>161href="+223220TRL_PIN" cla24spannct_uaa_ctring">"dtb" 224   16 na>161href="+224220TRL_PIN" claT_spannct_uaa_ctring">"dtc" 225   16 na>161href="+225220TRL_PIN" cla22spannct_uaa_ctring">"dte" 226   16 na>161href="+226220TRL_PIN" cla"dtf" 227   16 na>161href="+227220TRL_PIN" cla27spannct_uaa_ctring">"gpu7" 228   16 na>161href="+228221TRL_PIN" cla27spannct_uaa_ctring">"gpv" 229   16 na>161href=};229221TRL_PIN" cla26spannct_uaa_ctring">"hdint" 220   16 na>162nref=s/220222"i2cp" 221   16 na>162href=st221220TRL_PIN" cla0"owc" 222   16 na>162href="+222222TRL_PIN" cla"rm" 223   16 na>162href="+223222TRL_PIN" cla24spannct_uaa_ctring">"sdio1" 224   16 na>16 href="+224222TRL_PIN" claT_spannct_uaa_ctring">"spdi" 225   16 na>162href="+225220TRL_PIN" cla22spannct_uaa_ctring">"spdo" 226   16 na>162href=};226222TRL_PIN" cla"uac" 227   16 na>162href=s/227222TRL_PIN" cla27spannct_uaa_ctring">"uca" 228   16 na>162href=st228222TRL_PIN" cla27spannct_uaa_ctring">"uda" 229   16 na>162href="+229222/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na223"L599"> 22L630" id16 na>163nref="+22L63>223 221   16 na>163href="+221223t unsignedPINCTRL_char *rl/pinc_N,  222   16 na>163href="+22222LTRL_PIN" cla"crtp" 223   16 na>163href="+22322LTRL_PIN" cla24spannct_uaa_ctring">"dap2" 224   16 na>163href="+22422LTRL_PIN" claT_spannct_uaa_ctring">"dap3" 225   16 na>163href="+22522LTRL_PIN" cla22spannct_uaa_ctring">"ddc" 226   16 na>163href="+22622LTRL_PIN" cla"gpu7" 227   16 na>163href=};22722LTRL_PIN" cla27spannct_uaa_ctring">"gpv" 228   16 na>163href=s/22822LTRL_PIN" cla27spannct_uaa_ctring">"hdint" 229   16 na>163href=st22922LTRL_PIN" cla26spannct_uaa_ctring">"i2cp" 220   16 na>164nref="+220220"ld17" 221   16 na>164href="+221220TRL_PIN" cla0"ldc" 222   16 na>164href="+222220TRL_PIN" cla"ldi" 223   16 na>164href="+223220TRL_PIN" cla24spannct_uaa_ctring">"lhp0" 224   16 na>164href=};224220TRL_PIN" claT_spannct_uaa_ctring">"lhp1" 225   16L628"   15 na>225220TRL_PIN" cla22spannct_uaa_ctring">"lhp2" 225I4 hreO22_PAA2220TRL_PIN" cla"lm1" 227   15 na>154href="+227220TRL_PIN" cla27spannct_uaa_ctring">"lpp" 228   15 na>154href="+228220TRL_PIN" cla27spannct_uaa_ctring">"lpw1" 229   15 na>154href="+229220TRL_PIN" cla26spannct_uaa_ctring">"lvp0" 220   15 na>155nref="+220220"lvp1" 221   15 na>155href=};221220TRL_PIN" cla0"owc" 222   15 na>155href=s/222220TRL_PIN" cla"pmc" 223   15 na>155href=st223225TRL_PIN" cla24spannct_uaa_ctring">"rm" 224   15 na>155href="+224225TRL_PIN" claT_spannct_uaa_ctring">"uac" 225   15 na>155href="+225225TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2256L599"> 226   15 na>155href="+226225TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2257L599"> 227   15 na>155href="+227225/pinc/pinctrl/pincchar *rl/pinc_N,  228   15 na>155href="+228225TRL_PIN" cla27spannct_uaa_ctring">"ata" 229   15 na>155href="+229225TRL_PIN" cla26spannct_uaa_ctring">"ate" 220   15 na>15 nref="+220220"crtp" 221   15 na>156href="+221220TRL_PIN" cla0"dap3" 222   15 na>156href="+222220TRL_PIN" cla"dap4" 223   15 na>156href="+223220TRL_PIN" cla24spannct_uaa_ctring">"ddc" 224   15 na>15 href="+224220TRL_PIN" claT_spannct_uaa_ctring">"dta" 225   15 na>156href="+225220TRL_PIN" cla22spannct_uaa_ctring">"dtc" 226   15 na>156href="+226220TRL_PIN" cla"dtd" 227   15 na>156href="+227220TRL_PIN" cla27spannct_uaa_ctring">"dtf" 228   15 na>156href="+228226TRL_PIN" cla27spannct_uaa_ctring">"gpu" 229   15 na>156href="+229226TRL_PIN" cla26spannct_uaa_ctring">"gpu7" 220   15 na>157nref="+2202270RL_PIN" cla"gpv" 221   15 na>157href="+221220TRL_PIN" cla0"hdint" 222   15 na>15 href="+222227TRL_PIN" cla"i2cp" 223   15 na>157href="+223227TRL_PIN" cla24spannct_uaa_ctring">"kbce" 224   15 na>157href="+224227TRL_PIN" claT_spannct_uaa_ctring">"lcsn" 225   15 na>157href="+225220TRL_PIN" cla22spannct_uaa_ctring">"ld0" 226   15 na>15 href="+226220TRL_PIN" cla"ld1" 227   15 na>157href="+227220TRL_PIN" cla27spannct_uaa_ctring">"ld2" 228   15 na>157href="+228220TRL_PIN" cla27spannct_uaa_ctring">"ld3" 229   15 na>157href="+229220TRL_PIN" cla26spannct_uaa_ctring">"ld4" 220   15 na>158nref="+220228"ld5" 221   15 na>158href="+221228TRL_PIN" cla0"ld6" 222   15 na>158href="+222228TRL_PIN" cla"ld7" 223   15 na>158href="+223220TRL_PIN" cla24spannct_uaa_ctring">"ld8" 224   15 na>158href="+224220TRL_PIN" claT_spannct_uaa_ctring">"ld9" 225   15 na>158href="+225228TRL_PIN" cla22spannct_uaa_ctring">"ld10" 226   15 na>158href="+226228TRL_PIN" cla"ld11" 227   15 na>158href=};227228TRL_PIN" cla27spannct_uaa_ctring">"ld12" 228   15 na>158href=s/228220TRL_PIN" cla27spannct_uaa_ctring">"ld13" 229   15 na>158href=st229228TRL_PIN" cla26spannct_uaa_ctring">"ld14" 220   15 na>159nref="+2202290RL_PIN" cla"ld15" 221   15 na>159href="+221229TRL_PIN" cla0"ld16" 222   15 na>159href="+222220TRL_PIN" cla"ld17" 223   15 na>159href="+223220TRL_PIN" cla24spannct_uaa_ctring">"ldc" 224   15 na>159href=};224220TRL_PIN" claT_spannct_uaa_ctring">"ldi" 225   15 na>159href=s/225220TRL_PIN" cla22spannct_uaa_ctring">"lhp0" 226   15 na>159href=st226220TRL_PIN" cla"lhp1" 227   15 na>159href="+227220TRL_PIN" cla27spannct_uaa_ctring">"lhp2" 228   15 na>159href="+228229TRL_PIN" cla27spannct_uaa_ctring">"lhs" 229   15 na>159href="+229229TRL_PIN" cla26spannct_uaa_ctring">"lm0" 23="L5>   15 na>159href="+23="L>23="RL_PIN" cla27spannct_uaa_ctring">"lpp" 23=   15 na>159href="+23=23=TRL_PIN" cla0"lpw1" 23=   15 na>159href="+23=23=TRL_PIN" cla"lsc0" 23=   15 na>159href="+23=23=TRL_PIN" cla24spannct_uaa_ctring">"lsdi" 23=   15 na>159href=};23=23=TRL_PIN" claT_spannct_uaa_ctring">"lvp0" 23=   15 na>159href=s/23=23=TRL_PIN" cla22spannct_uaa_ctring">"lvp1" 23=   15 na>159href=st23=23=TRL_PIN" cla"lvs" 23=   15 na>159href="+23=23=TRL_PIN" cla27spannct_uaa_ctring">"owc" 23=   15 na>159href="+23=23=TRL_PIN" cla27spannct_uaa_ctring">"pmc" 23=   15 na>159href="+23=23=TRL_PIN" cla26spannct_uaa_ctring">"pta" 230   16 na>161nref="+230230"rm" 231   16 na>16 href="+231230TRL_PIN" cla0"spif" 232   16 na>161href="+232230TRL_PIN" cla"uac" 233   16 na>161href="+233230TRL_PIN" cla24spannct_uaa_ctring">"uca" 234   16 na>161href="+234230TRL_PIN" claT_spannct_uaa_ctring">"ucb" 235   16 na>161href="+235231TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2306L599"> 236   16 na>161href="+236231TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2307L599"> 237   16 na>161href="+237231/pinc/pinctrl/pincchar *rl/pinc_N,  238   16 na>161href="+238231TRL_PIN" cla27spannct_uaa_ctring">"gpu7" 239   16 na>161href=};239231/pinctrl-tegra20.c#L628" id="L628" c16hss="line16 na232"L599"> 230   16 na>162nref=s/230232 231   16 na>162href=st231232t unsignedPINCTRL_char *rl/pinc_N,  232   16 na>162href="+232232TRL_PIN" cla"sdio1" 233   16 na>162href="+233232TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2304L599"> 234   16 na>16 href="+234232TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2325L599"> 235   16 na>162href="+235232TRL_PignedPINCTRL_char *rl/pinc_N,  236   16 na>162href=};236232TRL_PIN" cla"dap1" 237   16 na>162href=s/237232TRL_PIN" cla27spannct_uaa_ctring">"dta" 238   16 na>162href=st238232TRL_PIN" cla27spannct_uaa_ctring">"dtd" 239   16 na>162href="+239230TRL_PIN" cla26spannct_uaa_ctring">"kbca" 23L630" id16 na>163nref="+23L63>23L6RL_PIN" cla26spannct_uaa_ctring">"kbcb" 231   16 na>163href="+231233TRL_PIN" cla0"kbcd" 232   16 na>163href="+23223LTRL_PIN" cla"spdi" 233   16 na>163href="+23323LTRL_PIN" cla24spannct_uaa_ctring">"spdo" 234   16 na>163href="+23423LTRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na23L5L599"> 235   16 na>163href="+23523LTRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na23L6L599"> 236   16 na>163href="+23623LTRL_PignedPINCTRL_char *rl/pinc_N,  237   16 na>163href=};23723LTRL_PIN" cla27spannct_uaa_ctring">"sdb" 238   16 na>163href=s/23823LTRL_PIN" cla27spannct_uaa_ctring">"sdc" 239   16 na>163href=st23923LTRL_PIN" cla26spannct_uaa_ctring">"sdd" 230   16 na>164nref="+230230"slxa" 231   16 na>164href="+231230TRL_PIN" cla0"slxc" 232   16 na>164href="+232230TRL_PIN" cla"slxd" 233   16 na>164href="+233230TRL_PIN" cla24spannct_uaa_ctring">"slxk" 234   16 na>164href=};234234TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2305L599"> 235   16L628"   15 na>235234TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2346L599"> 235I4 hreO22_PAA2234TRL_PignedPINCTRL_char *rl/pinc_N,  237   15 na>154href="+237230TRL_PIN" cla27spannct_uaa_ctring">"atb" 238   15 na>154href="+238230TRL_PIN" cla27spannct_uaa_ctring">"atc" 239   15 na>154href="+239230TRL_PIN" cla26spannct_uaa_ctring">"atd" 230   15 na>155nref="+230230"gma" 231   15 na>155href=};231230TRL_PIN" cla0"gme" 232   15 na>155href=s/232230TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2353L599"> 233   15 na>155href=st233235TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2354L599"> 234   15 na>155href="+234235TRL_PignedPINCTRL_char *rl/pinc_N,  235   15 na>155href="+235235TRL_PIN" cla22spannct_uaa_ctring">"gmc" 236   15 na>155href="+236235TRL_PIN" cla"gmd" 237   15 na>155href="+237235/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2358L599"> 238   15 na>155href="+238235inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2309L599"> 239   15 na>155href="+239235t unsignedPINCTRL_char *rl/pinc_N,  230   15 na>15 nref="+230230"slxc" 231   15 na>156href="+231230TRL_PIN" cla0"slxd" 232   15 na>156href="+232230TRL_PIN" cla"spdi" 233   15 na>156href="+233230TRL_PIN" cla24spannct_uaa_ctring">"spdo" 234   15 na>15 href="+234230TRL_PIN" claT_spannct_uaa_ctring">"uad" 235   15 na>156href="+235236TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2366L599"> 236   15 na>156href="+236236TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2367L599"> 237   15 na>156href="+237236/pinc/pinctrl/pincchar *rl/pinc_N,  238   15 na>156href="+238236TRL_PIN" cla27spannct_uaa_ctring">"dtb" 239   15 na>156href="+239236TRL_PIN" cla26spannct_uaa_ctring">"dte" 230   15 na>157nref="+2302370RL_PIN" cla"spia" 231   15 na>157href="+231230TRL_PIN" cla0"spib" 232   15 na>15 href="+232237TRL_PIN" cla"spic" 233   15 na>157href="+233237TRL_PIN" cla24spannct_uaa_ctring">"spid" 234   15 na>157href="+234237TRL_PIN" claT_spannct_uaa_ctring">"spie" 235   15 na>157href="+235230TRL_PIN" cla22spannct_uaa_ctring">"spif" 236   15 na>15 href="+236230TRL_PIN" cla"uda" 237   15 na>157href="+237237/pinctrl-tegra20.c#L628" id="L628" c1638s="line16 na2378L599"> 238   15 na>157href="+238237inctrl-tegra20.c#L628" id="L628" c1639s="line16 na2379L599"> 239   15 na>157href="+239237t unsignedPINCTRL_char *rl/pinc_N,  230   15 na>158nref="+230238"sdb" 231   15 na>158href="+231238TRL_PIN" cla0"slxa" 232   15 na>158href="+232238TRL_PIN" cla"slxc" 233   15 na>158href="+233230TRL_PIN" cla24spannct_uaa_ctring">"slxd" 234   15 na>158href="+234230TRL_PIN" claT_spannct_uaa_ctring">"slxk" 235   15 na>158href="+235238TRL_PIN" cla22spannct_uaa_ctring">"spia" 236   15 na>158href="+236238TRL_PIN" cla"spib" 237   15 na>158href=};237238TRL_PIN" cla27spannct_uaa_ctring">"spic" 238   15 na>158href=s/238230TRL_PIN" cla27spannct_uaa_ctring">"spid" 239   15 na>158href=st239238TRL_PIN" cla26spannct_uaa_ctring">"spie" 230   15 na>159nref="+2302390RL_PIN" cla"spif" 231   15 na>159href="+231239TRL_PIN" cla0"spig" 232   15 na>159href="+232230TRL_PIN" cla"spih" 233   15 na>159href="+233230TRL_PIN" cla24spannct_uaa_ctring">"uab" 234   15 na>159href=};234239TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2395L599"> 235   15 na>159href=s/235239TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2396L599"> 236   15 na>159href=st236239TRL_PignedPINCTRL_char *rl/pinc_N,  237   15 na>159href="+237230TRL_PIN" cla27spannct_uaa_ctring">"spid" 238   15 na>159href="+238239TRL_PIN" cla27spannct_uaa_ctring">"spie" 239   15 na>159href="+239239TRL_PIN" cla26spannct_uaa_ctring">"spig" 24="L5>   15 na>159href="+24="L>24="RL_PIN" cla27spannct_uaa_ctring">"spih" 24=   15 na>159href="+24=240TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na24=2L599"> 24=   15 na>159href="+24=240TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na24=3L599"> 24=   15 na>159href="+24=240TRL_PignedPINCTRL_char *rl/pinc_N,  24=   15 na>159href=};24=24=TRL_PIN" claT_spannct_uaa_ctring">"gma" 24=   15 na>159href=s/24=24=TRL_PIN" cla22spannct_uaa_ctring">"lcsn" 24=   15 na>159href=st24=24=TRL_PIN" cla"lm0" 24=   15 na>159href="+24=24=TRL_PIN" cla27spannct_uaa_ctring">"lpw0" 24=   15 na>159href="+24=24=TRL_PIN" cla27spannct_uaa_ctring">"lpw2" 24=   15 na>159href="+24=24=TRL_PIN" cla26spannct_uaa_ctring">"lsc1" 240   16 na>161nref="+240240"lsck" 241   16 na>16 href="+241240TRL_PIN" cla0"lsda" 242   16 na>161href="+242240TRL_PIN" cla"lsdi" 243   16 na>161href="+243240TRL_PIN" cla24spannct_uaa_ctring">"sdc" 244   16 na>161href="+244240TRL_PIN" claT_spannct_uaa_ctring">"sdd" 245   16 na>161href="+245240TRL_PIN" cla22spannct_uaa_ctring">"spia" 246   16 na>161href="+246240TRL_PIN" cla"spib" 247   16 na>161href="+247240TRL_PIN" cla27spannct_uaa_ctring">"spic" 248   16 na>161href="+248241TRL_PIN" cla27spannct_uaa_ctring">"spif" 249   16 na>161href=};249241TRL_PIN" cla26spannct_uaa_ctring">"spig" 240   16 na>162nref=s/240242"spih" 241   16 na>162href=st241240TRL_PIN" cla0"uaa" 242   16 na>162href="+242242TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2403L599"> 243   16 na>162href="+243242TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2404L599"> 244   16 na>16 href="+244242TRL_PignedPINCTRL_char *rl/pinc_N,  245   16 na>162href="+245240TRL_PIN" cla22spannct_uaa_ctring">"gmc" 246   16 na>162href=};246242TRL_PIN" cla"irrx" 247   16 na>162href=s/247242TRL_PIN" cla27spannct_uaa_ctring">"irtx" 248   16 na>162href=st248242TRL_PIN" cla27spannct_uaa_ctring">"slxa" 249   16 na>162href="+249240TRL_PIN" cla26spannct_uaa_ctring">"slxc" 24L630" id16 na>163nref="+24L63>24L6RL_PIN" cla26spannct_uaa_ctring">"slxd" 241   16 na>163href="+241243TRL_PIN" cla0"slxk" 242   16 na>163href="+24224LTRL_PIN" cla"uad" 243   16 na>163href="+243243TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na24L4L599"> 244   16 na>163href="+244243TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na24L5L599"> 245   16 na>163href="+245243TRL_PignedPINCTRL_char *rl/pinc_N,  246   16 na>163href="+24624LTRL_PIN" cla"kbcc" 247   16 na>163href=};24724LTRL_PIN" cla27spannct_uaa_ctring">"kbcf" 248   16 na>163href=s/24824LTRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na24L9L599"> 249   16 na>163href=st24924LTRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na244"L599"> 240   16 na>164nref="+240240,  241   16 na>164href="+241240TRL_PIN" cla0"dap2" 242   16 na>164href="+242240TRL_PIN" cla"sdc" 243   16 na>164href="+243244TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2404L599"> 244   16 na>164href=};244244TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2405L599"> 245   16L628"   15 na>245244TRL_PignedPINCTRL_char *rl/pinc_N,  245I4 hreO22_PAA2240TRL_PIN" cla"gpu" 247   15 na>154href="+247240TRL_PIN" cla27spannct_uaa_ctring">"irrx" 248   15 na>154href="+248240TRL_PIN" cla27spannct_uaa_ctring">"irtx" 249   15 na>154href="+249240TRL_PIN" cla26spannct_uaa_ctring">"sdb" 240   15 na>155nref="+240240"sdd" 241   15 na>155href=};241240TRL_PIN" cla0"sdio1" 242   15 na>155href=s/242240TRL_PIN" cla"uaa" 243   15 na>155href=st243245TRL_PIN" cla24spannct_uaa_ctring">"uab" 244   15 na>155href="+244245TRL_PIN" claT_spannct_uaa_ctring">"uad" 245   15 na>155href="+245245TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2456L599"> 246   15 na>155href="+246245TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2457L599"> 247   15 na>155href="+247245/pinc/pinctrl/pincchar *rl/pinc_N,  248   15 na>155href="+248245TRL_PIN" cla27spannct_uaa_ctring">"irrx" 249   15 na>155href="+249245TRL_PIN" cla26spannct_uaa_ctring">"irtx" 240   15 na>15 nref="+240240 241   15 na>156href="+241240TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2462L599"> 242   15 na>156href="+242240TRL_P/pinctrl/pincchar *rl/pinc_N,  243   15 na>156href="+243240TRL_PIN" cla24spannct_uaa_ctring">"uca" 244   15 na>15 href="+244240TRL_PIN" claT_spannct_uaa_ctring">"ucb" 245   15 na>156href="+245246TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2466L599"> 246   15 na>156href="+246246TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2467L599"> 247   15 na>156href="+247246/pinc/pinctrl/pincchar *rl/pinc_N,  248   15 na>156href="+248246TRL_PIN" cla27spannct_uaa_ctring">"gmc" 249   15 na>156href="+249246TRL_PIN" cla26spannct_uaa_ctring">"uda" 240   15 na>157nref="+240247 241   15 na>157href="+241247TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2472L599"> 242   15 na>15 href="+242247TRL_P/pinctrl/pincchar *rl/pinc_N,  243   15 na>157href="+243247TRL_PIN" cla24spannct_uaa_ctring">"gma" 244   15 na>157href="+244247TRL_PIN" claT_spannct_uaa_ctring">"sdio1" 245   15 na>157href="+245247TRL_Ptrl-tegra20.c#L628" id="L628" c1638s="line16 na2476L599"> 246   15 na>15 href="+246247TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2477L599"> 247   15 na>157href="+247247/pinc/pinctrl/pincchar *rl/pinc_N,  248   15 na>157href="+248240TRL_PIN" cla27spannct_uaa_ctring">"uaa" 249   15 na>157href="+249240TRL_PIN" cla26spannct_uaa_ctring">"uab" 240   15 na>158nref="+240248"uda" 241   15 na>158href="+241248TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2482L599"> 242   15 na>158href="+242248TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2483L599"> 243   15 na>158href="+243248TRL_PignedPINCTRL_char *rl/pinc_N,  244   15 na>158href="+244240TRL_PIN" claT_spannct_uaa_ctring">"dta" 245   15 na>158href="+245248TRL_PIN" cla22spannct_uaa_ctring">"dtb" 246   15 na>158href="+246248TRL_PIN" cla"dtc" 247   15 na>158href=};247248TRL_PIN" cla27spannct_uaa_ctring">"dtd" 248   15 na>158href=s/248240TRL_PIN" cla27spannct_uaa_ctring">"dte" 249   15 na>158href=st249248TRL_PIN" cla26spannct_uaa_ctring">"dtf" 240   15 na>159nref="+240249 241   15 na>159href="+241249TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2492L599"> 242   15 na>159href="+242249TRL_P/pinctrl/pincchar *rl/pinc_N,  243   15 na>159href="+243240TRL_PIN" cla24spannct_uaa_ctring">"csus" 244   15 na>159href=};244249TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2495L599"> 245   15 na>159href=s/245249TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2496L599"> 246   15 na>159href=st246249TRL_PignedPINCTRL_char *rl/pinc_N,  247   15 na>159href="+247240TRL_PIN" cla27spannct_uaa_ctring">"ld0" 248   15 na>159href="+248249TRL_PIN" cla27spannct_uaa_ctring">"ld1" 249   15 na>159href="+249249TRL_PIN" cla26spannct_uaa_ctring">"ld10" 25="L5>   15 na>159href="+25="L>25="RL_PIN" cla27spannct_uaa_ctring">"ld11" 25=   15 na>159href="+25=25=TRL_PIN" cla0"ld12" 25=   15 na>159href="+25=25=TRL_PIN" cla"ld13" 25=   15 na>159href="+25=25=TRL_PIN" cla24spannct_uaa_ctring">"ld14" 25=   15 na>159href=};25=25=TRL_PIN" claT_spannct_uaa_ctring">"ld15" 25=   15 na>159href=s/25=25=TRL_PIN" cla22spannct_uaa_ctring">"ld16" 25=   15 na>159href=st25=25=TRL_PIN" cla"ld2" 25=   15 na>159href="+25=25=TRL_PIN" cla27spannct_uaa_ctring">"ld3" 25=   15 na>159href="+25=25=TRL_PIN" cla27spannct_uaa_ctring">"ld4" 25=   15 na>159href="+25=25=TRL_PIN" cla26spannct_uaa_ctring">"ld5" 250   16 na>161nref="+250250"ld6" 251   16 na>16 href="+251250TRL_PIN" cla0"ld7" 252   16 na>161href="+252250TRL_PIN" cla"ld8" 253   16 na>161href="+253250TRL_PIN" cla24spannct_uaa_ctring">"ld9" 254   16 na>161href="+254250TRL_PIN" claT_spannct_uaa_ctring">"lhs" 255   16 na>161href="+255250TRL_PIN" cla22spannct_uaa_ctring">"lsc0" 256   16 na>161href="+256250TRL_PIN" cla"lspi" 257   16 na>161href="+257250TRL_PIN" cla27spannct_uaa_ctring">"lvs" 258   16 na>161href="+258251TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2509L599"> 259   16 na>161href=};259251TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na252"L599"> 250   16 na>162nref=s/2502521c_N, ,  251   16 na>162href=st251250TRL_PIN" cla0{                                               \l-tegra20.c#L628" id="L628" c16hss="line16 na2522L599"> 252   16 na>162href="+252252TRL_PIN" cla<<<<<<<<<._N,  253   16 na>162href="+2532523RL_PIN" cla<<<<<<<<<._N, ,  254   16 na>16 href="+2542524RL_PIN" cla<<<<<<<<<._N, , ,  255   16 na>162href="+255250TRL_PIN" cla2}l-tegra20.c#L628" id="L628" c16hss="line16 na2526L599"> 256   16 na>162href=};256252TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2527L599"> 257   16 na>162href=s/257252/pinc/pinctrl/pincctrucnc_N, ,  258   16 na>162href=st258252TRL_PIN" cla27N, ,  259   16 na>162href="+259250TRL_PIN" cla26N, ,  25L630" id16 na>163nref="+25L63>25L6RL_PIN" cla26N, ,  251   16 na>163href="+251253TRL_PIN" cla0, ,  252   16 na>163href="+25225LTRL_PIN" cla, ,  253   16 na>163href="+25325LTRL_PIN" cla24N, ,  254   16 na>163href="+2542534RL_PIN" cla24N, ,  255   16 na>163href="+2552535RL_PIN" cla24N, ,  256   16 na>163href="+25625LTRL_PIN" cla, ,  257   16 na>163href=};25725LTRL_PIN" cla27N, ,  258   16 na>163href=s/258253TRL_PIN" cla27N, ,  259   16 na>163href=st259253TRL_PIN" cla26N, ,  250   16 na>164nref="+2502546RL_PIN" cla26N, ,  251   16 na>164href="+251254TRL_PIN" cla0, ,  252   16 na>164href="+252254TRL_PIN" cla, ,  253   16 na>164href="+253254TRL_PIN" cla24N, ,  254   16 na>164href=};2542544RL_PIN" cla24N, ,  255   16L628"   15 na>2552545RL_PIN" cla24N, ,  255I4 hreO22_PAA2254TRL_PIN" cla, ,  257   15 na>154href="+257254TRL_PIN" cla27N, ,  258   15 na>154href="+258254TRL_PIN" cla27N, ,  259   15 na>154href="+259254TRL_PIN" cla26N, ,  250   15 na>155nref="+2502556RL_PIN" cla26N, ,  251   15 na>155href=};251255TRL_PIN" cla0, ,  252   15 na>155href=s/252255TRL_PIN" cla, ,  253   15 na>155href=st253255TRL_PIN" cla24N, ,  254   15 na>155href="+2542554RL_PIN" cla24N, ,  255   15 na>155href="+2552555RL_PIN" cla24N, ,  256   15 na>155href="+256255TRL_PIN" cla, ,  257   15 na>155href="+257255TRL_PIN" cla27N, ,  258   15 na>155href="+258255TRL_PIN" cla27N, ,  259   15 na>155href="+259255TRL_PIN" cla26N, ,  250   15 na>15 nref="+2502566RL_PIN" cla26N, ,  251   15 na>156href="+251256TRL_PIN" cla0, ,  252   15 na>156href="+252256TRL_PIN" cla, ,  253   15 na>156href="+253256TRL_PIN" cla24N, ,  254   15 na>15 href="+2542564RL_PIN" cla24N, ,  255   15 na>156href="+2552565RL_PIN" cla24N, ,  256   15 na>156href="+256256TRL_PIN" cla, ,  257   15 na>156href="+257256TRL_PIN" cla27N, ,  258   15 na>156href="+258256TRL_PIN" cla27N, ,  259   15 na>156href="+259256TRL_PIN" cla26N, ,  250   15 na>157nref="+2502576RL_PIN" cla26N, ,  251   15 na>157href="+251257TRL_PIN" cla0, ,  252   15 na>15 href="+252257TRL_PIN" cla, ,  253   15 na>157href="+253257TRL_PIN" cla24N, ,  254   15 na>157href="+2542574RL_PIN" cla24N, ,  255   15 na>157href="+2552575RL_PIN" cla24N, ,  256   15 na>15 href="+256257TRL_PIN" cla, ,  257   15 na>157href="+257257TRL_PIN" cla27N, ,  258   15 na>157href="+258257TRL_PIN" cla27N, ,  259   15 na>157href="+259257TRL_PIN" cla26N, ,  250   15 na>158nref="+2502586RL_PIN" cla26N, ,  251   15 na>158href="+251258TRL_PIN" cla0, ,  252   15 na>158href="+252258TRL_PIN" cla, ,  253   15 na>158href="+253258TRL_PIN" cla24N, ,  254   15 na>158href="+2542584RL_PIN" cla24N, ,  255   15 na>158href="+2552585RL_PIN" cla24N, ,  256   15 na>158href="+256258TRL_PIN" cla, ,  257   15 na>158href=};257258TRL_PIN" cla27N, ,  258   15 na>158href=s/258258TRL_PIN" cla27N, ,  259   15 na>158href=st259258TRL_PIN" cla26N, ,  250   15 na>159nref="+2502596RL_PIN" cla26N, ,  251   15 na>159href="+251259TRL_PIN" cla0, ,  252   15 na>159href="+252259TRL_PIN" cla, ,  253   15 na>159href="+253259TRL_Ptrl-tegra20.c#L628" id="L628" c16hss="line16 na2594L599"> 254   15 na>159href=};254259TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2595L599"> 255   15 na>159href=s/255259TRL_P#defa>1c_N,  256   15 na>159href=st256259TRL_P#defa>1c_N,  257   15 na>159href="+257250TRL_P#defa>1c_N,  258   15 na>159href="+258259TRL_P#defa>1c_N,  259   15 na>159href="+259259TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na26="L599"> 26="L5>   15 na>159href="+26="L>26="RL_P7spannct_uaa_comment">/* Pin group with muxrl/ptrol, and typically tri-/pine and pull-up/down too */ 26=   15 na>159href="+26=26=TRL_P#defa>1c_N, , , , , , ,  26=   15 na>159href="+26=260TRL_PIN" cla<<<<<<<<_N, , , , , ,  26=   15 na>159href="+26=26=TRL_PIN" cla2{                                               rrrrrrrr\l-tegra20.c#L628" id="L628" c16hss="line16 na26=4L599"> 26=   15 na>159href=};26=2604RL_PIN" cla<<<<<<<<<._N,  26=   15 na>159href=s/26=26=TRL_PIN" cla2<<<<<<<<._N, ,  26=   15 na>159href=st26=26=TRL_PIN" cla<<<<<<<<<._N, , ,  26=   15 na>159href="+26=26=TRL_PIN" cla2<<<<<<<<._N,  26=   15 na>159href="+26=26=TRL_PIN" cla22222222222222222_N, ,  26=   15 na>159href="+26=26=TRL_PIN" cla22222222222222222_N, ,  260   16 na>161nref="+260260, ,  261   16 na>16 href="+261260TRL_PIN" cla02222222222222222_N, ,  262   16 na>161href="+262261TRL_PIN" cla<<<<<<<<<},                         rrrrrr               \l-tegra20.c#L628" id="L628" c16hss="line16 na2613L599"> 263   16 na>161href="+2632613RL_PIN" cla<<<<<<<<<._N, , ,  264   16 na>161href="+2642614RL_PIN" cla<<<<<<<<<._N, , ,  265   16 na>161href="+265261TRL_PIN" cla2<<<<<<<<._N,  266   16 na>161href="+266261TRL_PIN" cla<<<<<<<<<._N, ,  267   16 na>161href="+267261TRL_PIN" cla2<<<<<<<<._N, , ,  268   16 na>161href="+268261TRL_PIN" cla222222222._N,  269   16 na>161href=};269261TRL_PIN" cla222222222._N, ,  260   16 na>162nref=s/260262, , ,  261   16 na>162href=st261262TRL_PIN" cla022222222._N,  262   16 na>162href="+262262TRL_PIN" cla<<<<<<<<<._N, ,  263   16 na>162href="+2632623RL_PIN" cla<<<<<<<<<._N,  264   16 na>16 href="+2642624RL_PIN" cla<<<<<<<<<._N,  265   16 na>162href="+265262TRL_PIN" cla2<<<<<<<<._N,  266   16 na>162href=};266262TRL_PIN" cla<<<<<<<<<._N,  267   16 na>162href=s/267262TRL_PIN" cla2<<<<<<<<._N,  268   16 na>162href=st268262TRL_PIN" cla222222222._N,  269   16 na>162href="+269262TRL_PIN" cla222222222._N,  26L630" id16 na>163nref="+26L63>26L6RL_PIN" cla2}l-tegra20.c#L628" id="L628" c16hss="line16 na2631L599"> 261   16 na>163href="+261263TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2632L599"> 262   16 na>163href="+26226LTRL_P7spannct_uaa_comment">/* Pin groups with only pull up and pull down l/ptrol */ 263   16 na>163href="+26326LTRL_P#defa>1c_N, , , ,  264   16 na>163href="+2642634RL_PIN" cla2{                                               rrrrrrrr\l-tegra20.c#L628" id="L628" c16hss="line16 na2635L599"> 265   16 na>163href="+265263TRL_PIN" cla2<<<<<<<<._N,  266   16 na>163href="+266263TRL_PIN" cla<<<<<<<<<._N, ,  267   16 na>163href=};267263TRL_PIN" cla2<<<<<<<<._N, , ,  268   16 na>163href=s/268263TRL_PIN" cla222222222._N,  269   16 na>163href=st269263TRL_PIN" cla222222222._N, , ,  260   16 na>164nref="+260264,  261   16 na>164href="+261264TRL_PIN" cla022222222._N, ,  262   16 na>164href="+262264TRL_PIN" cla<<<<<<<<<._N,  263   16 na>164href="+2632643RL_PIN" cla<<<<<<<<<._N,  264   16 na>164href=};2642644RL_PIN" cla<<<<<<<<<._N,  265   16L628"   15 na>265264TRL_PIN" cla2<<<<<<<<._N,  265I4 hreO22_PAA2264TRL_PIN" cla<<<<<<<<<._N,  267   15 na>154href="+267264TRL_PIN" cla2<<<<<<<<._N,  268   15 na>154href="+268264TRL_PIN" cla222222222._N,  269   15 na>154href="+269264TRL_PIN" cla222222222._N,  260   15 na>155nref="+2602656RL_PIN" cla2}l-tegra20.c#L628" id="L628" c16hss="line16 na2651L599"> 261   15 na>155href=};261265TRL_Pl-tegra20.c#L628" id="L628" c1638s="line16 na2652L599"> 262   15 na>155href=s/262265TRL_P7spannct_uaa_comment">/* Pin groups for c#L62cctrength regist28" (configurable 628"ion) */ 263   15 na>155href=st263265TRL_P#defa>1c_N, , , , , ,  264   15 na>155href="+2642654RL_PIN" cla<<<<<<<<< 22_N, ,  265   15 na>155href="+265265TRL_PIN" cla2<<<<<<<< 22_N, , , ,  266   15 na>155href="+266265TRL_PIN" cla<{                                               rrrrrrrr\l-tegra20.c#L628" id="L628" c16hss="line16 na2657L599"> 267   15 na>155href="+267265TRL_PIN" cla2<<<<<<<<._N, "c#L62_" 268   15 na>155href="+268265TRL_PIN" cla222222222._N, ,  269   15 na>155href="+269265TRL_PIN" cla222222222._N, , ,  260   15 na>15 nref="+260266,  261   15 na>156href="+261266TRL_PIN" cla022222222._N,  262   15 na>156href="+262266TRL_PIN" cla<<<<<<<<<._N,  263   15 na>156href="+2632663RL_PIN" cla<<<<<<<<<._N,  264   15 na>15 href="+2642664RL_PIN" cla<<<<<<<<<._N,  265   15 na>156href="+265266TRL_PIN" cla2<<<<<<<<._N,  266   15 na>156href="+266266TRL_PIN" cla<<<<<<<<<._N,  267   15 na>156href="+267266TRL_PIN" cla2<<<<<<<<._N,  268   15 na>156href="+268266TRL_PIN" cla222222222._N, , ,  269   15 na>156href="+269266TRL_PIN" cla222222222._N,  260   15 na>157nref="+260267, ,  261   15 na>157href="+261267TRL_PIN" cla022222222._N, ,  262   15 na>15 href="+262267TRL_PIN" cla<<<<<<<<<._N, ,  263   15 na>157href="+2632673RL_PIN" cla<<<<<<<<<._N, ,  264   15 na>157href="+2642674RL_PIN" cla<<<<<<<<<._N,  265   15 na>157href="+265267TRL_PIN" cla2<<<<<<<<._N, ,  266   15 na>15 href="+266267TRL_PIN" cla<<<<<<<<<._N,  267   15 na>157href="+267267TRL_PIN" cla2<<<<<<<<._N, ,  268   15 na>157href="+268267TRL_PIN" cla222222222._N, ,  269   15 na>157href="+269267TRL_PIN" cla222222222._N, ,  260   15 na>158nref="+260268, ,  261   15 na>158href="+261268TRL_PIN" cla022222222._N,  262   15 na>158href="+262268TRL_PIN" cla<}l-tegra20.c#L628" id="L628" c16hss="line16 na2683L599"> 263   15 na>158href="+263268TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2684L599"> 264   15 na>158href="+2642684RL_P7spannct_uaa_comment">/* Pin groups for c#L62cctrength regist28" (simple 628"ion) */ 265   15 na>158href="+265268TRL_P#defa>1c_N, , ,  266   15 na>158href="+266268TRL_PIN" cla, , ,  267   15 na>158href=};267268TRL_Pl-tegra20.c#L628" id="L628" c16hss="line16 na2688L599"> 268   15 na>158href=s/268268TRL_P/pinic l/pstcctructr_N, ,  269   15 na>158href=st269268TRL_PIN" cla26spannct_uaa_comment">/*     nref,   f0,        f1,        f2,        f3,            f_saff,    tri r/b,  muxrr/b,  pupdrr/b */ 260   15 na>159nref="+2602696RL_PIN" cla26N, , , , , , ,  261   15 na>159href="+261269TRL_PIN" cla0, , , , , , ,  262   15 na>159href="+262269TRL_PIN" cla, , , , , , ,  263   15 na>159href="+263269TRL_PIN" cla24N, , , , , , ,  264   15 na>159href=};2642694RL_PIN" cla24N, , , , , , ,  265   15 na>159href=s/2652695RL_PIN" cla24N, , , , , , ,  266   15 na>159href=st266269TRL_PIN" cla, , , , , , ,  267   15 na>159href="+267269TRL_PIN" cla27N, , , , , , ,  268   15 na>159href="+268269TRL_PIN" cla27N, , , , , , ,  269   15 na>159href="+269269TRL_PIN" cla26N, , , , , , ,  27="L5>   15 na>159href="+27="L>2706RL_PIN" cla26N, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla0, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla24N, , , , , , ,  27=   15 na>159href=};27=2704RL_PIN" cla24N, , , , , , ,  27=   15 na>159href=s/27=2705RL_PIN" cla24N, , , , , , ,  27=   15 na>159href=st27=270TRL_PIN" cla, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla27N, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla27N, , , , , , ,  27=   15 na>159href="+27=270TRL_PIN" cla26N, , , , , , ,  270   16 na>161nref="+2702716RL_PIN" cla26N, , , , , , ,  271   16 na>16 href="+271271TRL_PIN" cla0, , , , , , ,  272   16 na>161href="+272271TRL_PIN" cla, , , , , , ,  273   16 na>161href="+273271TRL_PIN" cla24N, , , , , , ,  274   16 na>161href="+2742714RL_PIN" cla24N, , , , , , ,  275   16 na>161href="+2752715RL_PIN" cla24N, , , , , , ,  276   16 na>161href="+276271TRL_PIN" cla, , , , , , ,  277   16 na>161href="+277271TRL_PIN" cla27N, , , , , , ,  278   16 na>161href="+278271TRL_PIN" cla27N, , , , , , ,  279   16 na>161href=};279271TRL_PIN" cla26N, , , , , , ,  270   16 na>162nref=s/2702726RL_PIN" cla26N, , , , , , ,  271   16 na>162href=st271272TRL_PIN" cla0, , , , , , ,  272   16 na>162href="+272272TRL_PIN" cla, , , , , , ,  273   16 na>162href="+273272TRL_PIN" cla24N, , , , , , ,  274   16 na>16 href="+2742724RL_PIN" cla24N, , , , , , ,  275   16 na>162href="+2752725RL_PIN" cla24N, , , , , , ,  276   16 na>162href=};276272TRL_PIN" cla, , , , , , ,  277   16 na>162href=s/277272TRL_PIN" cla27N, , , , , , ,  278   16 na>162href=st278272TRL_PIN" cla27N, , , , , , ,  279   16 na>162href="+279272TRL_PIN" cla26N, , , , , , ,  27L630" id16 na>163nref="+27L63>2736RL_PIN" cla26N, , , , , , ,  271   16 na>163href="+271273TRL_PIN" cla0, , , , , , ,  273   16 na>162href="+273273TRL_PIN" cla, , , , , , ,  273   16 na>162href="+273273TRL_PIN" cla24N, , , , , , ,  273   16 na>16 href="+2732734RL_PIN" cla24N, , , , , , ,  273   16 na>162href="+2732735RL_PIN" cla24N, , , , , , ,  273   16 na>162href=};273273TRL_PIN" cla, , , , , , ,  273   16 na>162href=s/273273TRL_PIN" cla27N, , , , , , ,  273   16 na>162href=st273273TRL_PIN" cla27N, , , , , , ,  273   16 na>162href="+273273TRL_PIN" cla26N, , , , , , ,  274630" id16 na>163nref="+27463>2746RL_PIN" cla26N, , , , , , ,  274   16 na>163href="+274274TRL_PIN" cla0, , , , , , ,  274   16 na>162href="+274274TRL_PIN" cla, , , , , , ,  274   16 na>162href="+274274TRL_PIN" cla24N, , , , , , ,  274   16 na>16 href="+2742744RL_PIN" cla24N, , , , , , ,  274   16 na>162href="+2742745RL_PIN" cla24N, , , , , , ,  274   16 na>162href=};274274TRL_PIN" cla, , , , , , ,  274   16 na>162href=s/274274TRL_PIN" cla27N, , , , , , ,  274   16 na>162href=st274274TRL_PIN" cla27N, , , , , , ,  274   16 na>162href="+274274TRL_PIN" cla26N, , , , , , ,  275630" id16 na>163nref="+27563>2756RL_PIN" cla26N, , , , , , ,  275   16 na>163href="+275275TRL_PIN" cla0, , , , , , ,  275   16 na>162href="+275275TRL_PIN" cla, , , , , , ,  275   16 na>162href="+275275TRL_PIN" cla24N, , , , , , ,  275   16 na>16 href="+2752754RL_PIN" cla24N, , , , , , ,  275   16 na>162href="+2752755RL_PIN" cla24N, , , , , , ,  275   16 na>162href=};275275TRL_PIN" cla, , , , , , ,  275   16 na>162href=s/275275TRL_PIN" cla27N, , , , , , ,  275   16 na>162href=st275275TRL_PIN" cla27N, , , , , , ,  275   16 na>162href="+275275TRL_PIN" cla26N, , , , , , ,  276630" id16 na>163nref="+27663>2766RL_PIN" cla26N, , , , , , ,  276   16 na>163href="+276276TRL_PIN" cla0, , , , , , ,  276   16 na>162href="+276276TRL_PIN" cla, , , , , , ,  276   16 na>162href="+276276TRL_PIN" cla24N, , , , , , ,  276   16 na>16 href="+2762764RL_PIN" cla24N, , , , , , ,  276   16 na>162href="+2762765RL_PIN" cla24N, , , , , , ,  276   16 na>162href=};276276TRL_PIN" cla, , , , , , ,  276   16 na>162href=s/276276TRL_PIN" cla27N, , , , , , ,  276   16 na>162href=st276276TRL_PIN" cla27N, , , , , , ,  276   16 na>162href="+276276TRL_PIN" cla26N, , , , , , ,  277630" id16 na>163nref="+27763>2776RL_PIN" cla26N, , , , , , ,  277   16 na>163href="+277277TRL_PIN" cla0, , , , , , ,  277   16 na>162href="+277277TRL_PIN" cla, , , , , , ,  277   16 na>162href="+277277TRL_PIN" cla24N, , , , , , ,  277   16 na>16 href="+2772774RL_PIN" cla24N, , , , , , ,  277   16 na>162href="+2772775RL_PIN" cla24N, , , , , , ,  277   16 na>162href=};277277TRL_PIN" cla, , , , , , ,  277   16 na>162href=s/277277TRL_PIN" cla27N, , , , , , ,  277   16 na>162href=st277277TRL_PIN" cla27N, , , , , , ,  277   16 na>162href="+277277TRL_PIN" cla26N, , , , , , ,  278630" id16 na>163nref="+27863>2786RL_PIN" cla26N, , , , , , ,  278   16 na>163href="+278278TRL_PIN" cla0, , , , , , ,  278   16 na>162href="+278278TRL_PIN" cla, , , , , , ,  278   16 na>162href="+278278TRL_PIN" cla24N, , , , , , ,  278   16 na>16 href="+2782784RL_PIN" cla24N, , , , , , ,  278   16 na>162href="+2782785RL_PIN" cla24N, , , , , , ,  278   16 na>162href=};278278TRL_PIN" cla, , , , , , ,  278   16 na>162href=s/278278TRL_PIN" cla27N, , , , , , ,  278   16 na>162href=st278278TRL_PIN" cla27N, , , , , , ,  278   16 na>162href="+278278TRL_PIN" cla26N, , , , , , ,  279630" id16 na>163nref="+27963>2796RL_PIN" cla26N, , , , , , ,  279   16 na>163href="+279279TRL_PIN" cla0, , , , , , ,  279   16 na>162href="+279279TRL_PIN" cla, , , , , , ,  279   16 na>162href="+279279TRL_PIN" cla24N, , , , , , ,  279   16 na>16 href="+2792794RL_PIN" cla24N, , , , , , ,  279   16 na>162href="+2792795RL_PIN" cla24N, , , , , , ,  279   16 na>162href=};279279TRL_PIN" cla, , , , , , ,  279   16 na>162href=s/279279TRL_PIN" cla27spana>   16 comment">/*" cla2pg_href, pupd_r/b */l-tegra20.c#L628" id="L628" c1579s="line15 na2798L599"> 279   16 na>162href=st279279TRL_PIN" cla27N, ,  279   16 na>162href="+279279TRL_PIN" cla26N, ,  280"L5>   16 na>162href="+280"L>280"RL_PIN" cla26N, ,  280   16 na>163href="+280280TRL_PIN" cla0, ,  280   16 na>162href="+280280TRL_PIN" cla, ,  280   16 na>162href="+280280TRL_PIN" cla24N, ,  280   16 na>16 href="+2802804RL_PIN" cla24N, ,  280   16 na>162href="+2802805RL_PIN" cla24N, ,  280   16 na>162href=};280280TRL_PIN" cla, ,  280   16 na>162href=s/280280TRL_PIN" cla27N, ,  280   16 na>162href=st280280TRL_PIN" cla27N, ,  280   16 na>162href="+280280TRL_PIN" cla26N, ,  281"L5>   16 na>162href="+281"L>281"RL_PIN" cla26N, ,  281   16 na>163href="+281281TRL_PIN" cla0, ,  281   16 na>162href="+281281TRL_PIN" cla, ,  281   16 na>162href="+281281TRL_PIN" cla24spana>   16 comment">/*" clapg_href,    r */l-tegra20.c#L628" id="L628" c1579s="line15 na2814L599"> 281   16 na>16 href="+2812814RL_PIN" cla24N, ,  281   16 na>162href="+2812815RL_PIN" cla24N, ,  281   16 na>162href=};281281TRL_PIN" cla, ,  281   16 na>162href=s/281281TRL_PIN" cla27N, ,  281   16 na>162href=st281281TRL_PIN" cla27N, ,  281   16 na>162href="+281281TRL_PIN" cla26N, ,  282"L5>   16 na>162href="+282"L>282"RL_PIN" cla26N, ,  282   16 na>163href="+282282TRL_PIN" cla0, ,  282   16 na>162href="+282282TRL_PIN" cla, ,  282   16 na>162href="+282282TRL_PIN" cla24N, ,  282   16 na>16 href="+2822824RL_PIN" cla24N, ,  282   16 na>162href="+2822825RL_PIN" cla24N, ,  282   16 na>162href=};282282TRL_PIN" cla, ,  282   16 na>162href=s/282282TRL_PIN" cla27N, ,  282   16 na>162href=st282282TRL_PIN" cla27N, ,  282   16 na>162href="+282282TRL_PIN" cla26N, ,  283"L5>   16 na>162href="+283"L>283"RL_PIN" cla26N, ,  283   16 na>163href="+283283TRL_PIN" cla0, ,  283   16 na>162href="+283283TRL_PIN" cla, ,  283   16 na>162href="+283283TRL_PIN" cla24N, ,  283   16 na>16 href="+2832834RL_PIN" cla24N, ,  283   16 na>162href="+2832835RL_PIN" cla24N, ,  283   16 na>162href=};283283TRL_PIN" cla, ,  283   16 na>162href=s/283283TRL_PIN" cla27spana>   16 comment">/*" cla2 lapg_href, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */l-tegra20.c#L628" id="L628" c1579s="line15 na2838L599"> 283   16 na>162href=st283283TRL_PIN" cla27N, ,  283   16 na>162href="+283283TRL_PIN" cla26N, ,  284"L5>   16 na>162href="+284"L>284"RL_PIN" cla26N, ,  284   16 na>163href="+284284TRL_PIN" cla0, ,  284   16 na>162href="+2842842RL_PIN" cla27spana>   16 comment">/*" clapg_href,    r */l-tegra20.c#L628" id="L628" c1579s="line15 na2843L599"> 284   16 na>162href="+284284TRL_PIN" cla24N, ,  284   16 na>16 href="+2842844RL_PIN" cla24N, ,  284   16 na>162href="+2842845RL_PIN" cla24N, ,  284   16 na>162href=};284284TRL_PIN" cla, ,  284   16 na>162href=s/284284TRL_PIN" cla27N, ,  284   16 na>162href=st284284TRL_PIN" cla27N, ,  284   16 na>162href="+284284TRL_PIN" cla26N, ,  285"L5>   16 na>162href="+285"L>285"RL_PIN" cla26N, ,  285   16 na>163href="+285285TRL_PIN" cla0, ,  285   16 na>162href="+285285TRL_PIN" cla, ,  285   16 na>162href="+285285TRL_P};l-tegra20.c#L628" id="L628" c1579s="line15 na2854L599"> 285   16 na>16 href="+2852854RL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2855L599"> 285   16 na>162href="+2852855RL_Pstatic const struct, ,  285   16 na>162href=};285285TRL_PIN" cla<./N, ,  285   16 na>162href=s/285285TRL_PIN" cla2./N, ,  285   16 na>162href=st285285TRL_PIN" cla2./N, , ,  285   16 na>162href="+285285TRL_PIN" cla2./N, ,  286630" id16 na>163nref="+28663>2866RL_PIN" cla2./N, , ,  286   16 na>163href="+286286TRL_PIN" cla0./N, ,  286   16 na>162href="+286286TRL_PIN" cla<./N, , ,  286   16 na>162href="+286286TRL_P};l-tegra20.c#L628" id="L628" c1579s="line15 na2864L599"> 286   16 na>16 href="+2862864RL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2865L599"> 286   16 na>162href="+2862865RL_Pstatic int, , ,  286   16 na>162href=};286286TRL_P{l-tegra20.c#L628" id="L628" c1579s="line15 na2867L599"> 286   16 na>162href=s/286286TRL_PIN" cla2return, , ,  286   16 na>162href=st286286TRL_P}l-tegra20.c#L628" id="L628" c1579s="line15 na2869L599"> 286   16 na>162href="+286286TRL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na287"L599"> 287630" id16 na>163nref="+28763>2876RL_Pstatic struct, ,  287   16 na>163href="+287287TRL_PIN" cla0{<./N,    16 string">"nvidia,="line1-" cmux", }rl-tegra20.c#L628" id="L628" c1579s="line15 na2872L599"> 287   16 na>162href="+287287TRL_PIN" cla<{ }rl-tegra20.c#L628" id="L628" c1579s="line15 na2873L599"> 287   16 na>162href="+287287TRL_P};l-tegra20.c#L628" id="L628" c1579s="line15 na2874L599"> 287   16 na>16 href="+2872874RL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2875L599"> 287   16 na>162href="+2872875RL_Pstatic struct, ,  287   16 na>162href=};287287TRL_PIN" cla<./N,  287   16 na>162href=s/287287TRL_PIN" cla2IN" cla<./N,    16 string">"="line1-" c1579",l-tegra20.c#L628" id="L628" c1579s="line15 na2878L599"> 287   16 na>162href=st287287TRL_PIN" cla2IN" cla<./N, ,  287   16 na>162href="+287287TRL_PIN" cla2IN" cla<./N, ,  288630" id16 na>163nref="+28863>2886RL_PIN" cla2}rl-tegra20.c#L628" id="L628" c1579s="line15 na2881L599"> 288   16 na>163href="+288288TRL_PIN" cla0./N, ,  288   16 na>162href="+288288TRL_PIN" cla<./N, ,  288   16 na>162href="+288288TRL_P};l-tegra20.c#L628" id="L628" c1579s="line15 na2884L599"> 288   16 na>16 href="+2882884RL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2885L599"> 288   16 na>162href="+2882885RL_Pstatic int, ,  288   16 na>162href=};288288TRL_P{l-tegra20.c#L628" id="L628" c1579s="line15 na2887L599"> 288   16 na>162href=s/288288TRL_PIN" cla2return, ,  288   16 na>162href=st288288TRL_P}l-tegra20.c#L628" id="L628" c1579s="line15 na2889L599"> 288   16 na>162href="+288288TRL_P/N, ,  289630" id16 na>163nref="+28963>2896RL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2891L599"> 289   16 na>163href="+289289TRL_Pstatic void, ,  289   16 na>162href="+289289TRL_P{l-tegra20.c#L628" id="L628" c1579s="line15 na2893L599"> 289   16 na>162href="+289289TRL_PIN" cla24N, ,  289   16 na>16 href="+2892894RL_P}l-tegra20.c#L628" id="L628" c1579s="line15 na2895L599"> 289   16 na>162href="+2892895RL_P/N, ,  289   16 na>162href=};289289TRL_Pl-tegra20.c#L628" id="L628" c1579s="line15 na2897L599"> 289   16 na>162href=s/289289TRL_P_N,    16 string">"Stephen Warren <swarren@nvidia.com>");l-tegra20.c#L628" id="L628" c1579s="line15 na2898L599"> 289   16 na>162href=st289289TRL_P_N,    16 string">"NVIDIA T"line1 " c1579 c#L628");l-tegra20.c#L628" id="L628" c1579s="line15 na2899L599"> 289   16 na>162href="+289289TRL_P/N,    16 string">"GPL v2");l-tegra20.c#L628" id="L628" c1579s="line15 na290"L599"> 290"L5>   16 na>162href="+290"L>290"RL_P_N, , ,  290   16 na>163href="+290290TRL_P


16 foot28i> The original LXR software by the -tegra20.http://sourceforge.net/projects/lx8i>LXR communityRL_P,rthis experimental 628"ion by -tegra20.mailto:lx8@na>ux.no">lx8@na>ux.noRL_P.
16 subfoot28i> lx8.na>ux.no kindly host2d by -tegra20.http://www.redpill-na>pro.no">Redpill La>pro ASRL_P,rprovider of La>ux consulting and opera5iocs servicfs s c1e 1995.