linux/drivers/pinctrl/pinctrl-rockchip.c
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   1/*
   2 * Pinctrl driver for Rockchip SoCs
   3 *
   4 * Copyright (c) 2013 MundoReader S.L.
   5 * Author: Heiko Stuebner <heiko@sntech.de>
   6 *
   7 * With some ideas taken from pinctrl-samsung:
   8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9 *              http://www.samsung.com
  10 * Copyright (c) 2012 Linaro Ltd
  11 *              http://www.linaro.org
  12 *
  13 * and pinctrl-at91:
  14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15 *
  16 * This program is free software; you can redistribute it and/or modify
  17 * it under the terms of the GNU General Public License version 2 as published
  18 * by the Free Software Foundation.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 */
  25
  26#include <linux/module.h>
  27#include <linux/platform_device.h>
  28#include <linux/io.h>
  29#include <linux/bitops.h>
  30#include <linux/gpio.h>
  31#include <linux/of_address.h>
  32#include <linux/of_irq.h>
  33#include <linux/pinctrl/machine.h>
  34#include <linux/pinctrl/pinconf.h>
  35#include <linux/pinctrl/pinctrl.h>
  36#include <linux/pinctrl/pinmux.h>
  37#include <linux/pinctrl/pinconf-generic.h>
  38#include <linux/irqchip/chained_irq.h>
  39#include <linux/clk.h>
  40#include <dt-bindings/pinctrl/rockchip.h>
  41
  42#include "core.h"
  43#include "pinconf.h"
  44
  45/* GPIO control registers */
  46#define GPIO_SWPORT_DR          0x00
  47#define GPIO_SWPORT_DDR         0x04
  48#define GPIO_INTEN              0x30
  49#define GPIO_INTMASK            0x34
  50#define GPIO_INTTYPE_LEVEL      0x38
  51#define GPIO_INT_POLARITY       0x3c
  52#define GPIO_INT_STATUS         0x40
  53#define GPIO_INT_RAWSTATUS      0x44
  54#define GPIO_DEBOUNCE           0x48
  55#define GPIO_PORTS_EOI          0x4c
  56#define GPIO_EXT_PORT           0x50
  57#define GPIO_LS_SYNC            0x60
  58
  59/**
  60 * @reg_base: register base of the gpio bank
  61 * @clk: clock of the gpio bank
  62 * @irq: interrupt of the gpio bank
  63 * @pin_base: first pin number
  64 * @nr_pins: number of pins in this bank
  65 * @name: name of the bank
  66 * @bank_num: number of the bank, to account for holes
  67 * @valid: are all necessary informations present
  68 * @of_node: dt node of this bank
  69 * @drvdata: common pinctrl basedata
  70 * @domain: irqdomain of the gpio bank
  71 * @gpio_chip: gpiolib chip
  72 * @grange: gpio range
  73 * @slock: spinlock for the gpio bank
  74 */
  75struct rockchip_pin_bank {
  76        void __iomem                    *reg_base;
  77        struct clk                      *clk;
  78        int                             irq;
  79        u32                             pin_base;
  80        u8                              nr_pins;
  81        char                            *name;
  82        u8                              bank_num;
  83        bool                            valid;
  84        struct device_node              *of_node;
  85        struct rockchip_pinctrl         *drvdata;
  86        struct irq_domain               *domain;
  87        struct gpio_chip                gpio_chip;
  88        struct pinctrl_gpio_range       grange;
  89        spinlock_t                      slock;
  90
  91};
  92
  93#define PIN_BANK(id, pins, label)                       \
  94        {                                               \
  95                .bank_num       = id,                   \
  96                .nr_pins        = pins,                 \
  97                .name           = label,                \
  98        }
  99
 100/**
 101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
 102 *             instead decide this automatically based on the pad-type.
 103 */
 104struct rockchip_pin_ctrl {
 105        struct rockchip_pin_bank        *pin_banks;
 106        u32                             nr_banks;
 107        u32                             nr_pins;
 108        char                            *label;
 109        int                             mux_offset;
 110        int                             pull_offset;
 111        bool                            pull_auto;
 112        int                             pull_bank_stride;
 113};
 114
 115struct rockchip_pin_config {
 116        unsigned int            func;
 117        unsigned long           *configs;
 118        unsigned int            nconfigs;
 119};
 120
 121/**
 122 * struct rockchip_pin_group: represent group of pins of a pinmux function.
 123 * @name: name of the pin group, used to lookup the group.
 124 * @pins: the pins included in this group.
 125 * @npins: number of pins included in this group.
 126 * @func: the mux function number to be programmed when selected.
 127 * @configs: the config values to be set for each pin
 128 * @nconfigs: number of configs for each pin
 129 */
 130struct rockchip_pin_group {
 131        const char                      *name;
 132        unsigned int                    npins;
 133        unsigned int                    *pins;
 134        struct rockchip_pin_config      *data;
 135};
 136
 137/**
 138 * struct rockchip_pmx_func: represent a pin function.
 139 * @name: name of the pin function, used to lookup the function.
 140 * @groups: one or more names of pin groups that provide this function.
 141 * @num_groups: number of groups included in @groups.
 142 */
 143struct rockchip_pmx_func {
 144        const char              *name;
 145        const char              **groups;
 146        u8                      ngroups;
 147};
 148
 149struct rockchip_pinctrl {
 150        void __iomem                    *reg_base;
 151        struct device                   *dev;
 152        struct rockchip_pin_ctrl        *ctrl;
 153        struct pinctrl_desc             pctl;
 154        struct pinctrl_dev              *pctl_dev;
 155        struct rockchip_pin_group       *groups;
 156        unsigned int                    ngroups;
 157        struct rockchip_pmx_func        *functions;
 158        unsigned int                    nfunctions;
 159};
 160
 161static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 162{
 163        return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 164}
 165
 166static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 167                                        const struct rockchip_pinctrl *info,
 168                                        const char *name)
 169{
 170        int i;
 171
 172        for (i = 0; i < info->ngroups; i++) {
 173                if (!strcmp(info->groups[i].name, name))
 174                        return &info->groups[i];
 175        }
 176
 177        return NULL;
 178}
 179
 180/*
 181 * given a pin number that is local to a pin controller, find out the pin bank
 182 * and the register base of the pin bank.
 183 */
 184static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 185                                                                unsigned pin)
 186{
 187        struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 188
 189        while (pin >= (b->pin_base + b->nr_pins))
 190                b++;
 191
 192        return b;
 193}
 194
 195static struct rockchip_pin_bank *bank_num_to_bank(
 196                                        struct rockchip_pinctrl *info,
 197                                        unsigned num)
 198{
 199        struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 200        int i;
 201
 202        for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 203                if (b->bank_num == num)
 204                        return b;
 205        }
 206
 207        return ERR_PTR(-EINVAL);
 208}
 209
 210/*
 211 * Pinctrl_ops handling
 212 */
 213
 214static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 215{
 216        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 217
 218        return info->ngroups;
 219}
 220
 221static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 222                                                        unsigned selector)
 223{
 224        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 225
 226        return info->groups[selector].name;
 227}
 228
 229static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 230                                      unsigned selector, const unsigned **pins,
 231                                      unsigned *npins)
 232{
 233        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 234
 235        if (selector >= info->ngroups)
 236                return -EINVAL;
 237
 238        *pins = info->groups[selector].pins;
 239        *npins = info->groups[selector].npins;
 240
 241        return 0;
 242}
 243
 244static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 245                                 struct device_node *np,
 246                                 struct pinctrl_map **map, unsigned *num_maps)
 247{
 248        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 249        const struct rockchip_pin_group *grp;
 250        struct pinctrl_map *new_map;
 251        struct device_node *parent;
 252        int map_num = 1;
 253        int i;
 254
 255        /*
 256         * first find the group of this node and check if we need to create
 257         * config maps for pins
 258         */
 259        grp = pinctrl_name_to_group(info, np->name);
 260        if (!grp) {
 261                dev_err(info->dev, "unable to find group for node %s\n",
 262                        np->name);
 263                return -EINVAL;
 264        }
 265
 266        map_num += grp->npins;
 267        new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 268                                                                GFP_KERNEL);
 269        if (!new_map)
 270                return -ENOMEM;
 271
 272        *map = new_map;
 273        *num_maps = map_num;
 274
 275        /* create mux map */
 276        parent = of_get_parent(np);
 277        if (!parent) {
 278                devm_kfree(pctldev->dev, new_map);
 279                return -EINVAL;
 280        }
 281        new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 282        new_map[0].data.mux.function = parent->name;
 283        new_map[0].data.mux.group = np->name;
 284        of_node_put(parent);
 285
 286        /* create config map */
 287        new_map++;
 288        for (i = 0; i < grp->npins; i++) {
 289                new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 290                new_map[i].data.configs.group_or_pin =
 291                                pin_get_name(pctldev, grp->pins[i]);
 292                new_map[i].data.configs.configs = grp->data[i].configs;
 293                new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 294        }
 295
 296        dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 297                (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 298
 299        return 0;
 300}
 301
 302static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 303                                    struct pinctrl_map *map, unsigned num_maps)
 304{
 305}
 306
 307static const struct pinctrl_ops rockchip_pctrl_ops = {
 308        .get_groups_count       = rockchip_get_groups_count,
 309        .get_group_name         = rockchip_get_group_name,
 310        .get_group_pins         = rockchip_get_group_pins,
 311        .dt_node_to_map         = rockchip_dt_node_to_map,
 312        .dt_free_map            = rockchip_dt_free_map,
 313};
 314
 315/*
 316 * Hardware access
 317 */
 318
 319/*
 320 * Set a new mux function for a pin.
 321 *
 322 * The register is divided into the upper and lower 16 bit. When changing
 323 * a value, the previous register value is not read and changed. Instead
 324 * it seems the changed bits are marked in the upper 16 bit, while the
 325 * changed value gets set in the same offset in the lower 16 bit.
 326 * All pin settings seem to be 2 bit wide in both the upper and lower
 327 * parts.
 328 * @bank: pin bank to change
 329 * @pin: pin to change
 330 * @mux: new mux function to set
 331 */
 332static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 333{
 334        struct rockchip_pinctrl *info = bank->drvdata;
 335        void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 336        unsigned long flags;
 337        u8 bit;
 338        u32 data;
 339
 340        dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 341                                                bank->bank_num, pin, mux);
 342
 343        /* get basic quadrupel of mux registers and the correct reg inside */
 344        reg += bank->bank_num * 0x10;
 345        reg += (pin / 8) * 4;
 346        bit = (pin % 8) * 2;
 347
 348        spin_lock_irqsave(&bank->slock, flags);
 349
 350        data = (3 << (bit + 16));
 351        data |= (mux & 3) << bit;
 352        writel(data, reg);
 353
 354        spin_unlock_irqrestore(&bank->slock, flags);
 355}
 356
 357static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 358{
 359        struct rockchip_pinctrl *info = bank->drvdata;
 360        struct rockchip_pin_ctrl *ctrl = info->ctrl;
 361        void __iomem *reg;
 362        u8 bit;
 363
 364        /* rk3066b does support any pulls */
 365        if (!ctrl->pull_offset)
 366                return PIN_CONFIG_BIAS_DISABLE;
 367
 368        reg = info->reg_base + ctrl->pull_offset;
 369
 370        if (ctrl->pull_auto) {
 371                reg += bank->bank_num * ctrl->pull_bank_stride;
 372                reg += (pin_num / 16) * 4;
 373                bit = pin_num % 16;
 374
 375                return !(readl_relaxed(reg) & BIT(bit))
 376                                ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 377                                : PIN_CONFIG_BIAS_DISABLE;
 378        } else {
 379                dev_err(info->dev, "pull support for rk31xx not implemented\n");
 380                return -EIO;
 381        }
 382}
 383
 384static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 385                                        int pin_num, int pull)
 386{
 387        struct rockchip_pinctrl *info = bank->drvdata;
 388        struct rockchip_pin_ctrl *ctrl = info->ctrl;
 389        void __iomem *reg;
 390        unsigned long flags;
 391        u8 bit;
 392        u32 data;
 393
 394        dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 395                 bank->bank_num, pin_num, pull);
 396
 397        /* rk3066b does support any pulls */
 398        if (!ctrl->pull_offset)
 399                return pull ? -EINVAL : 0;
 400
 401        reg = info->reg_base + ctrl->pull_offset;
 402
 403        if (ctrl->pull_auto) {
 404                if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 405                                        pull != PIN_CONFIG_BIAS_DISABLE) {
 406                        dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
 407                        return -EINVAL;
 408                }
 409
 410                reg += bank->bank_num * ctrl->pull_bank_stride;
 411                reg += (pin_num / 16) * 4;
 412                bit = pin_num % 16;
 413
 414                spin_lock_irqsave(&bank->slock, flags);
 415
 416                data = BIT(bit + 16);
 417                if (pull == PIN_CONFIG_BIAS_DISABLE)
 418                        data |= BIT(bit);
 419                writel(data, reg);
 420
 421                spin_unlock_irqrestore(&bank->slock, flags);
 422        } else {
 423                if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) {
 424                        dev_err(info->dev, "pull direction (up/down) needs to be specified\n");
 425                        return -EINVAL;
 426                }
 427
 428                dev_err(info->dev, "pull support for rk31xx not implemented\n");
 429                return -EIO;
 430        }
 431
 432        return 0;
 433}
 434
 435/*
 436 * Pinmux_ops handling
 437 */
 438
 439static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 440{
 441        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 442
 443        return info->nfunctions;
 444}
 445
 446static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 447                                          unsigned selector)
 448{
 449        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 450
 451        return info->functions[selector].name;
 452}
 453
 454static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 455                                unsigned selector, const char * const **groups,
 456                                unsigned * const num_groups)
 457{
 458        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 459
 460        *groups = info->functions[selector].groups;
 461        *num_groups = info->functions[selector].ngroups;
 462
 463        return 0;
 464}
 465
 466static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 467                                                            unsigned group)
 468{
 469        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 470        const unsigned int *pins = info->groups[group].pins;
 471        const struct rockchip_pin_config *data = info->groups[group].data;
 472        struct rockchip_pin_bank *bank;
 473        int cnt;
 474
 475        dev_dbg(info->dev, "enable function %s group %s\n",
 476                info->functions[selector].name, info->groups[group].name);
 477
 478        /*
 479         * for each pin in the pin group selected, program the correspoding pin
 480         * pin function number in the config register.
 481         */
 482        for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 483                bank = pin_to_bank(info, pins[cnt]);
 484                rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 485                                 data[cnt].func);
 486        }
 487
 488        return 0;
 489}
 490
 491static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 492                                        unsigned selector, unsigned group)
 493{
 494        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 495        const unsigned int *pins = info->groups[group].pins;
 496        struct rockchip_pin_bank *bank;
 497        int cnt;
 498
 499        dev_dbg(info->dev, "disable function %s group %s\n",
 500                info->functions[selector].name, info->groups[group].name);
 501
 502        for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 503                bank = pin_to_bank(info, pins[cnt]);
 504                rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 505        }
 506}
 507
 508/*
 509 * The calls to gpio_direction_output() and gpio_direction_input()
 510 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 511 * function called from the gpiolib interface).
 512 */
 513static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 514                                              struct pinctrl_gpio_range *range,
 515                                              unsigned offset, bool input)
 516{
 517        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 518        struct rockchip_pin_bank *bank;
 519        struct gpio_chip *chip;
 520        int pin;
 521        u32 data;
 522
 523        chip = range->gc;
 524        bank = gc_to_pin_bank(chip);
 525        pin = offset - chip->base;
 526
 527        dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 528                 offset, range->name, pin, input ? "input" : "output");
 529
 530        rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 531
 532        data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 533        /* set bit to 1 for output, 0 for input */
 534        if (!input)
 535                data |= BIT(pin);
 536        else
 537                data &= ~BIT(pin);
 538        writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 539
 540        return 0;
 541}
 542
 543static const struct pinmux_ops rockchip_pmx_ops = {
 544        .get_functions_count    = rockchip_pmx_get_funcs_count,
 545        .get_function_name      = rockchip_pmx_get_func_name,
 546        .get_function_groups    = rockchip_pmx_get_groups,
 547        .enable                 = rockchip_pmx_enable,
 548        .disable                = rockchip_pmx_disable,
 549        .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 550};
 551
 552/*
 553 * Pinconf_ops handling
 554 */
 555
 556static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 557                                        enum pin_config_param pull)
 558{
 559        /* rk3066b does support any pulls */
 560        if (!ctrl->pull_offset)
 561                return pull ? false : true;
 562
 563        if (ctrl->pull_auto) {
 564                if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 565                                        pull != PIN_CONFIG_BIAS_DISABLE)
 566                        return false;
 567        } else {
 568                if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
 569                        return false;
 570        }
 571
 572        return true;
 573}
 574
 575/* set the pin config settings for a specified pin */
 576static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 577                                unsigned long *configs, unsigned num_configs)
 578{
 579        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 580        struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 581        enum pin_config_param param;
 582        u16 arg;
 583        int i;
 584        int rc;
 585
 586        for (i = 0; i < num_configs; i++) {
 587                param = pinconf_to_config_param(configs[i]);
 588                arg = pinconf_to_config_argument(configs[i]);
 589
 590                switch (param) {
 591                case PIN_CONFIG_BIAS_DISABLE:
 592                        rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 593                                param);
 594                        if (rc)
 595                                return rc;
 596                        break;
 597                case PIN_CONFIG_BIAS_PULL_UP:
 598                case PIN_CONFIG_BIAS_PULL_DOWN:
 599                case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 600                        if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 601                                return -ENOTSUPP;
 602
 603                        if (!arg)
 604                                return -EINVAL;
 605
 606                        rc = rockchip_set_pull(bank, pin - bank->pin_base,
 607                                param);
 608                        if (rc)
 609                                return rc;
 610                        break;
 611                default:
 612                        return -ENOTSUPP;
 613                        break;
 614                }
 615        } /* for each config */
 616
 617        return 0;
 618}
 619
 620/* get the pin config settings for a specified pin */
 621static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 622                                                        unsigned long *config)
 623{
 624        struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 625        struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 626        enum pin_config_param param = pinconf_to_config_param(*config);
 627
 628        switch (param) {
 629        case PIN_CONFIG_BIAS_DISABLE:
 630                if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 631                        return -EINVAL;
 632
 633                *config = 0;
 634                break;
 635        case PIN_CONFIG_BIAS_PULL_UP:
 636        case PIN_CONFIG_BIAS_PULL_DOWN:
 637        case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 638                if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 639                        return -ENOTSUPP;
 640
 641                if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 642                        return -EINVAL;
 643
 644                *config = 1;
 645                break;
 646        default:
 647                return -ENOTSUPP;
 648                break;
 649        }
 650
 651        return 0;
 652}
 653
 654static const struct pinconf_ops rockchip_pinconf_ops = {
 655        .pin_config_get                 = rockchip_pinconf_get,
 656        .pin_config_set                 = rockchip_pinconf_set,
 657};
 658
 659static const char *gpio_compat = "rockchip,gpio-bank";
 660
 661static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 662                                                struct device_node *np)
 663{
 664        struct device_node *child;
 665
 666        for_each_child_of_node(np, child) {
 667                if (of_device_is_compatible(child, gpio_compat))
 668                        continue;
 669
 670                info->nfunctions++;
 671                info->ngroups += of_get_child_count(child);
 672        }
 673}
 674
 675static int rockchip_pinctrl_parse_groups(struct device_node *np,
 676                                              struct rockchip_pin_group *grp,
 677                                              struct rockchip_pinctrl *info,
 678                                              u32 index)
 679{
 680        struct rockchip_pin_bank *bank;
 681        int size;
 682        const __be32 *list;
 683        int num;
 684        int i, j;
 685        int ret;
 686
 687        dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 688
 689        /* Initialise group */
 690        grp->name = np->name;
 691
 692        /*
 693         * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 694         * do sanity check and calculate pins number
 695         */
 696        list = of_get_property(np, "rockchip,pins", &size);
 697        /* we do not check return since it's safe node passed down */
 698        size /= sizeof(*list);
 699        if (!size || size % 4) {
 700                dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 701                return -EINVAL;
 702        }
 703
 704        grp->npins = size / 4;
 705
 706        grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 707                                                GFP_KERNEL);
 708        grp->data = devm_kzalloc(info->dev, grp->npins *
 709                                          sizeof(struct rockchip_pin_config),
 710                                        GFP_KERNEL);
 711        if (!grp->pins || !grp->data)
 712                return -ENOMEM;
 713
 714        for (i = 0, j = 0; i < size; i += 4, j++) {
 715                const __be32 *phandle;
 716                struct device_node *np_config;
 717
 718                num = be32_to_cpu(*list++);
 719                bank = bank_num_to_bank(info, num);
 720                if (IS_ERR(bank))
 721                        return PTR_ERR(bank);
 722
 723                grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 724                grp->data[j].func = be32_to_cpu(*list++);
 725
 726                phandle = list++;
 727                if (!phandle)
 728                        return -EINVAL;
 729
 730                np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 731                ret = pinconf_generic_parse_dt_config(np_config,
 732                                &grp->data[j].configs, &grp->data[j].nconfigs);
 733                if (ret)
 734                        return ret;
 735        }
 736
 737        return 0;
 738}
 739
 740static int rockchip_pinctrl_parse_functions(struct device_node *np,
 741                                                struct rockchip_pinctrl *info,
 742                                                u32 index)
 743{
 744        struct device_node *child;
 745        struct rockchip_pmx_func *func;
 746        struct rockchip_pin_group *grp;
 747        int ret;
 748        static u32 grp_index;
 749        u32 i = 0;
 750
 751        dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 752
 753        func = &info->functions[index];
 754
 755        /* Initialise function */
 756        func->name = np->name;
 757        func->ngroups = of_get_child_count(np);
 758        if (func->ngroups <= 0)
 759                return 0;
 760
 761        func->groups = devm_kzalloc(info->dev,
 762                        func->ngroups * sizeof(char *), GFP_KERNEL);
 763        if (!func->groups)
 764                return -ENOMEM;
 765
 766        for_each_child_of_node(np, child) {
 767                func->groups[i] = child->name;
 768                grp = &info->groups[grp_index++];
 769                ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 770                if (ret)
 771                        return ret;
 772        }
 773
 774        return 0;
 775}
 776
 777static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 778                                              struct rockchip_pinctrl *info)
 779{
 780        struct device *dev = &pdev->dev;
 781        struct device_node *np = dev->of_node;
 782        struct device_node *child;
 783        int ret;
 784        int i;
 785
 786        rockchip_pinctrl_child_count(info, np);
 787
 788        dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 789        dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 790
 791        info->functions = devm_kzalloc(dev, info->nfunctions *
 792                                              sizeof(struct rockchip_pmx_func),
 793                                              GFP_KERNEL);
 794        if (!info->functions) {
 795                dev_err(dev, "failed to allocate memory for function list\n");
 796                return -EINVAL;
 797        }
 798
 799        info->groups = devm_kzalloc(dev, info->ngroups *
 800                                            sizeof(struct rockchip_pin_group),
 801                                            GFP_KERNEL);
 802        if (!info->groups) {
 803                dev_err(dev, "failed allocate memory for ping group list\n");
 804                return -EINVAL;
 805        }
 806
 807        i = 0;
 808
 809        for_each_child_of_node(np, child) {
 810                if (of_device_is_compatible(child, gpio_compat))
 811                        continue;
 812                ret = rockchip_pinctrl_parse_functions(child, info, i++);
 813                if (ret) {
 814                        dev_err(&pdev->dev, "failed to parse function\n");
 815                        return ret;
 816                }
 817        }
 818
 819        return 0;
 820}
 821
 822static int rockchip_pinctrl_register(struct platform_device *pdev,
 823                                        struct rockchip_pinctrl *info)
 824{
 825        struct pinctrl_desc *ctrldesc = &info->pctl;
 826        struct pinctrl_pin_desc *pindesc, *pdesc;
 827        struct rockchip_pin_bank *pin_bank;
 828        int pin, bank, ret;
 829        int k;
 830
 831        ctrldesc->name = "rockchip-pinctrl";
 832        ctrldesc->owner = THIS_MODULE;
 833        ctrldesc->pctlops = &rockchip_pctrl_ops;
 834        ctrldesc->pmxops = &rockchip_pmx_ops;
 835        ctrldesc->confops = &rockchip_pinconf_ops;
 836
 837        pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 838                        info->ctrl->nr_pins, GFP_KERNEL);
 839        if (!pindesc) {
 840                dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 841                return -ENOMEM;
 842        }
 843        ctrldesc->pins = pindesc;
 844        ctrldesc->npins = info->ctrl->nr_pins;
 845
 846        pdesc = pindesc;
 847        for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 848                pin_bank = &info->ctrl->pin_banks[bank];
 849                for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 850                        pdesc->number = k;
 851                        pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 852                                                pin_bank->name, pin);
 853                        pdesc++;
 854                }
 855        }
 856
 857        info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 858        if (!info->pctl_dev) {
 859                dev_err(&pdev->dev, "could not register pinctrl driver\n");
 860                return -EINVAL;
 861        }
 862
 863        for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 864                pin_bank = &info->ctrl->pin_banks[bank];
 865                pin_bank->grange.name = pin_bank->name;
 866                pin_bank->grange.id = bank;
 867                pin_bank->grange.pin_base = pin_bank->pin_base;
 868                pin_bank->grange.base = pin_bank->gpio_chip.base;
 869                pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 870                pin_bank->grange.gc = &pin_bank->gpio_chip;
 871                pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 872        }
 873
 874        ret = rockchip_pinctrl_parse_dt(pdev, info);
 875        if (ret) {
 876                pinctrl_unregister(info->pctl_dev);
 877                return ret;
 878        }
 879
 880        return 0;
 881}
 882
 883/*
 884 * GPIO handling
 885 */
 886
 887static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
 888{
 889        return pinctrl_request_gpio(chip->base + offset);
 890}
 891
 892static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
 893{
 894        pinctrl_free_gpio(chip->base + offset);
 895}
 896
 897static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 898{
 899        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 900        void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 901        unsigned long flags;
 902        u32 data;
 903
 904        spin_lock_irqsave(&bank->slock, flags);
 905
 906        data = readl(reg);
 907        data &= ~BIT(offset);
 908        if (value)
 909                data |= BIT(offset);
 910        writel(data, reg);
 911
 912        spin_unlock_irqrestore(&bank->slock, flags);
 913}
 914
 915/*
 916 * Returns the level of the pin for input direction and setting of the DR
 917 * register for output gpios.
 918 */
 919static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 920{
 921        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 922        u32 data;
 923
 924        data = readl(bank->reg_base + GPIO_EXT_PORT);
 925        data >>= offset;
 926        data &= 1;
 927        return data;
 928}
 929
 930/*
 931 * gpiolib gpio_direction_input callback function. The setting of the pin
 932 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
 933 * interface.
 934 */
 935static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 936{
 937        return pinctrl_gpio_direction_input(gc->base + offset);
 938}
 939
 940/*
 941 * gpiolib gpio_direction_output callback function. The setting of the pin
 942 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
 943 * interface.
 944 */
 945static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 946                                          unsigned offset, int value)
 947{
 948        rockchip_gpio_set(gc, offset, value);
 949        return pinctrl_gpio_direction_output(gc->base + offset);
 950}
 951
 952/*
 953 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
 954 * and a virtual IRQ, if not already present.
 955 */
 956static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 957{
 958        struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 959        unsigned int virq;
 960
 961        if (!bank->domain)
 962                return -ENXIO;
 963
 964        virq = irq_create_mapping(bank->domain, offset);
 965
 966        return (virq) ? : -ENXIO;
 967}
 968
 969static const struct gpio_chip rockchip_gpiolib_chip = {
 970        .request = rockchip_gpio_request,
 971        .free = rockchip_gpio_free,
 972        .set = rockchip_gpio_set,
 973        .get = rockchip_gpio_get,
 974        .direction_input = rockchip_gpio_direction_input,
 975        .direction_output = rockchip_gpio_direction_output,
 976        .to_irq = rockchip_gpio_to_irq,
 977        .owner = THIS_MODULE,
 978};
 979
 980/*
 981 * Interrupt handling
 982 */
 983
 984static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 985{
 986        struct irq_chip *chip = irq_get_chip(irq);
 987        struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
 988        u32 pend;
 989
 990        dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
 991
 992        chained_irq_enter(chip, desc);
 993
 994        pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
 995
 996        while (pend) {
 997                unsigned int virq;
 998
 999                irq = __ffs(pend);
1000                pend &= ~BIT(irq);
1001                virq = irq_linear_revmap(bank->domain, irq);
1002
1003                if (!virq) {
1004                        dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1005                        continue;
1006                }
1007
1008                dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1009
1010                generic_handle_irq(virq);
1011        }
1012
1013        chained_irq_exit(chip, desc);
1014}
1015
1016static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1017{
1018        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1019        struct rockchip_pin_bank *bank = gc->private;
1020        u32 mask = BIT(d->hwirq);
1021        u32 polarity;
1022        u32 level;
1023        u32 data;
1024
1025        if (type & IRQ_TYPE_EDGE_BOTH)
1026                __irq_set_handler_locked(d->irq, handle_edge_irq);
1027        else
1028                __irq_set_handler_locked(d->irq, handle_level_irq);
1029
1030        irq_gc_lock(gc);
1031
1032        level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1033        polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1034
1035        switch (type) {
1036        case IRQ_TYPE_EDGE_RISING:
1037                level |= mask;
1038                polarity |= mask;
1039                break;
1040        case IRQ_TYPE_EDGE_FALLING:
1041                level |= mask;
1042                polarity &= ~mask;
1043                break;
1044        case IRQ_TYPE_LEVEL_HIGH:
1045                level &= ~mask;
1046                polarity |= mask;
1047                break;
1048        case IRQ_TYPE_LEVEL_LOW:
1049                level &= ~mask;
1050                polarity &= ~mask;
1051                break;
1052        default:
1053                irq_gc_unlock(gc);
1054                return -EINVAL;
1055        }
1056
1057        writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1058        writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1059
1060        irq_gc_unlock(gc);
1061
1062        /* make sure the pin is configured as gpio input */
1063        rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1064        data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1065        data &= ~mask;
1066        writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1067
1068        return 0;
1069}
1070
1071static int rockchip_interrupts_register(struct platform_device *pdev,
1072                                                struct rockchip_pinctrl *info)
1073{
1074        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1075        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1076        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1077        struct irq_chip_generic *gc;
1078        int ret;
1079        int i;
1080
1081        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1082                if (!bank->valid) {
1083                        dev_warn(&pdev->dev, "bank %s is not valid\n",
1084                                 bank->name);
1085                        continue;
1086                }
1087
1088                bank->domain = irq_domain_add_linear(bank->of_node, 32,
1089                                                &irq_generic_chip_ops, NULL);
1090                if (!bank->domain) {
1091                        dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1092                                 bank->name);
1093                        continue;
1094                }
1095
1096                ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1097                                         "rockchip_gpio_irq", handle_level_irq,
1098                                         clr, 0, IRQ_GC_INIT_MASK_CACHE);
1099                if (ret) {
1100                        dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1101                                bank->name);
1102                        irq_domain_remove(bank->domain);
1103                        continue;
1104                }
1105
1106                gc = irq_get_domain_generic_chip(bank->domain, 0);
1107                gc->reg_base = bank->reg_base;
1108                gc->private = bank;
1109                gc->chip_types[0].regs.mask = GPIO_INTEN;
1110                gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1111                gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1112                gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1113                gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1114                gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1115                gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1116
1117                irq_set_handler_data(bank->irq, bank);
1118                irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1119        }
1120
1121        return 0;
1122}
1123
1124static int rockchip_gpiolib_register(struct platform_device *pdev,
1125                                                struct rockchip_pinctrl *info)
1126{
1127        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1128        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1129        struct gpio_chip *gc;
1130        int ret;
1131        int i;
1132
1133        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1134                if (!bank->valid) {
1135                        dev_warn(&pdev->dev, "bank %s is not valid\n",
1136                                 bank->name);
1137                        continue;
1138                }
1139
1140                bank->gpio_chip = rockchip_gpiolib_chip;
1141
1142                gc = &bank->gpio_chip;
1143                gc->base = bank->pin_base;
1144                gc->ngpio = bank->nr_pins;
1145                gc->dev = &pdev->dev;
1146                gc->of_node = bank->of_node;
1147                gc->label = bank->name;
1148
1149                ret = gpiochip_add(gc);
1150                if (ret) {
1151                        dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1152                                                        gc->label, ret);
1153                        goto fail;
1154                }
1155        }
1156
1157        rockchip_interrupts_register(pdev, info);
1158
1159        return 0;
1160
1161fail:
1162        for (--i, --bank; i >= 0; --i, --bank) {
1163                if (!bank->valid)
1164                        continue;
1165
1166                if (gpiochip_remove(&bank->gpio_chip))
1167                        dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1168                                                        bank->gpio_chip.label);
1169        }
1170        return ret;
1171}
1172
1173static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1174                                                struct rockchip_pinctrl *info)
1175{
1176        struct rockchip_pin_ctrl *ctrl = info->ctrl;
1177        struct rockchip_pin_bank *bank = ctrl->pin_banks;
1178        int ret = 0;
1179        int i;
1180
1181        for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1182                if (!bank->valid)
1183                        continue;
1184
1185                ret = gpiochip_remove(&bank->gpio_chip);
1186        }
1187
1188        if (ret)
1189                dev_err(&pdev->dev, "gpio chip remove failed\n");
1190
1191        return ret;
1192}
1193
1194static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1195                                  struct device *dev)
1196{
1197        struct resource res;
1198
1199        if (of_address_to_resource(bank->of_node, 0, &res)) {
1200                dev_err(dev, "cannot find IO resource for bank\n");
1201                return -ENOENT;
1202        }
1203
1204        bank->reg_base = devm_ioremap_resource(dev, &res);
1205        if (IS_ERR(bank->reg_base))
1206                return PTR_ERR(bank->reg_base);
1207
1208        bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1209
1210        bank->clk = of_clk_get(bank->of_node, 0);
1211        if (IS_ERR(bank->clk))
1212                return PTR_ERR(bank->clk);
1213
1214        return clk_prepare_enable(bank->clk);
1215}
1216
1217static const struct of_device_id rockchip_pinctrl_dt_match[];
1218
1219/* retrieve the soc specific data */
1220static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1221                                                struct rockchip_pinctrl *d,
1222                                                struct platform_device *pdev)
1223{
1224        const struct of_device_id *match;
1225        struct device_node *node = pdev->dev.of_node;
1226        struct device_node *np;
1227        struct rockchip_pin_ctrl *ctrl;
1228        struct rockchip_pin_bank *bank;
1229        int i;
1230
1231        match = of_match_node(rockchip_pinctrl_dt_match, node);
1232        ctrl = (struct rockchip_pin_ctrl *)match->data;
1233
1234        for_each_child_of_node(node, np) {
1235                if (!of_find_property(np, "gpio-controller", NULL))
1236                        continue;
1237
1238                bank = ctrl->pin_banks;
1239                for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1240                        if (!strcmp(bank->name, np->name)) {
1241                                bank->of_node = np;
1242
1243                                if (!rockchip_get_bank_data(bank, &pdev->dev))
1244                                        bank->valid = true;
1245
1246                                break;
1247                        }
1248                }
1249        }
1250
1251        bank = ctrl->pin_banks;
1252        for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1253                spin_lock_init(&bank->slock);
1254                bank->drvdata = d;
1255                bank->pin_base = ctrl->nr_pins;
1256                ctrl->nr_pins += bank->nr_pins;
1257        }
1258
1259        return ctrl;
1260}
1261
1262static int rockchip_pinctrl_probe(struct platform_device *pdev)
1263{
1264        struct rockchip_pinctrl *info;
1265        struct device *dev = &pdev->dev;
1266        struct rockchip_pin_ctrl *ctrl;
1267        struct resource *res;
1268        int ret;
1269
1270        if (!dev->of_node) {
1271                dev_err(dev, "device tree node not found\n");
1272                return -ENODEV;
1273        }
1274
1275        info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1276        if (!info)
1277                return -ENOMEM;
1278
1279        ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1280        if (!ctrl) {
1281                dev_err(dev, "driver data not available\n");
1282                return -EINVAL;
1283        }
1284        info->ctrl = ctrl;
1285        info->dev = dev;
1286
1287        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1288        info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1289        if (IS_ERR(info->reg_base))
1290                return PTR_ERR(info->reg_base);
1291
1292        ret = rockchip_gpiolib_register(pdev, info);
1293        if (ret)
1294                return ret;
1295
1296        ret = rockchip_pinctrl_register(pdev, info);
1297        if (ret) {
1298                rockchip_gpiolib_unregister(pdev, info);
1299                return ret;
1300        }
1301
1302        platform_set_drvdata(pdev, info);
1303
1304        return 0;
1305}
1306
1307static struct rockchip_pin_bank rk2928_pin_banks[] = {
1308        PIN_BANK(0, 32, "gpio0"),
1309        PIN_BANK(1, 32, "gpio1"),
1310        PIN_BANK(2, 32, "gpio2"),
1311        PIN_BANK(3, 32, "gpio3"),
1312};
1313
1314static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1315                .pin_banks              = rk2928_pin_banks,
1316                .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1317                .label                  = "RK2928-GPIO",
1318                .mux_offset             = 0xa8,
1319                .pull_offset            = 0x118,
1320                .pull_auto              = 1,
1321                .pull_bank_stride       = 8,
1322};
1323
1324static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1325        PIN_BANK(0, 32, "gpio0"),
1326        PIN_BANK(1, 32, "gpio1"),
1327        PIN_BANK(2, 32, "gpio2"),
1328        PIN_BANK(3, 32, "gpio3"),
1329        PIN_BANK(4, 32, "gpio4"),
1330        PIN_BANK(6, 16, "gpio6"),
1331};
1332
1333static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1334                .pin_banks              = rk3066a_pin_banks,
1335                .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1336                .label                  = "RK3066a-GPIO",
1337                .mux_offset             = 0xa8,
1338                .pull_offset            = 0x118,
1339                .pull_auto              = 1,
1340                .pull_bank_stride       = 8,
1341};
1342
1343static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1344        PIN_BANK(0, 32, "gpio0"),
1345        PIN_BANK(1, 32, "gpio1"),
1346        PIN_BANK(2, 32, "gpio2"),
1347        PIN_BANK(3, 32, "gpio3"),
1348};
1349
1350static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1351                .pin_banks      = rk3066b_pin_banks,
1352                .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1353                .label          = "RK3066b-GPIO",
1354                .mux_offset     = 0x60,
1355                .pull_offset    = -EINVAL,
1356};
1357
1358static struct rockchip_pin_bank rk3188_pin_banks[] = {
1359        PIN_BANK(0, 32, "gpio0"),
1360        PIN_BANK(1, 32, "gpio1"),
1361        PIN_BANK(2, 32, "gpio2"),
1362        PIN_BANK(3, 32, "gpio3"),
1363};
1364
1365static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1366                .pin_banks              = rk3188_pin_banks,
1367                .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1368                .label                  = "RK3188-GPIO",
1369                .mux_offset             = 0x68,
1370                .pull_offset            = 0x164,
1371                .pull_bank_stride       = 16,
1372};
1373
1374static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1375        { .compatible = "rockchip,rk2928-pinctrl",
1376                .data = (void *)&rk2928_pin_ctrl },
1377        { .compatible = "rockchip,rk3066a-pinctrl",
1378                .data = (void *)&rk3066a_pin_ctrl },
1379        { .compatible = "rockchip,rk3066b-pinctrl",
1380                .data = (void *)&rk3066b_pin_ctrl },
1381        { .compatible = "rockchip,rk3188-pinctrl",
1382                .data = (void *)&rk3188_pin_ctrl },
1383        {},
1384};
1385MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1386
1387static struct platform_driver rockchip_pinctrl_driver = {
1388        .probe          = rockchip_pinctrl_probe,
1389        .driver = {
1390                .name   = "rockchip-pinctrl",
1391                .owner  = THIS_MODULE,
1392                .of_match_table = rockchip_pinctrl_dt_match,
1393        },
1394};
1395
1396static int __init rockchip_pinctrl_drv_register(void)
1397{
1398        return platform_driver_register(&rockchip_pinctrl_driver);
1399}
1400postcore_initcall(rockchip_pinctrl_drv_register);
1401
1402MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1403MODULE_DESCRIPTION("Rockchip pinctrl driver");
1404MODULE_LICENSE("GPL v2");
1405
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